inverter

Abstract

Inverter (1), comprising: - a first input terminal (2) to which a positive intermediate circuit potential (VDC+) is applied during operation of the inverter (1), - a second input terminal (3) to which a center potential (N) is applied during operation of the inverter (1), - a third input terminal (4) to which a negative intermediate circuit potential (VDC-) is applied during operation of the inverter (1), - an output terminal (5) at which an output potential (UA) is output during operation of the inverter (1), - a throttle (6), - a first switching device (T1), a second switching device (TP), a third switching device (TN) and a fourth switching device (T4), wherein the first switching device (T1), the second switching device (TP), the third switching device (TN) and the fourth switching device (T4) are connected in series between the first input terminal (2) and the third input terminal (4), and wherein a connection node (N1) of the second switching device (TP) and the third switching device (TN) is electrically connected to the second input terminal (3), - a fifth switching device (T2) and a sixth switching device (T3), wherein the fifth switching device (T2) and the sixth switching device (T3) are connected in series between a connection node (N3) of the first switching device (T1) and the second switching device (TP) and a connection node (N4) of the third switching device (TN) and the fourth switching device (T4), wherein the choke (5) is connected in series between a connection node (N5) of the fifth switching device (T2) and the sixth switching device (T3) and the output terminal (5), and - a control unit (7) designed to control the switching devices (T1, T2, T3, T4, TP, TN), - wherein the control unit (7) is configured to control the switching devices (T1, T2, T3, T4, TP, TN) before switching on the fourth switching device (T4) in such a way that the fifth switching device (T2) is supplied with a voltage in the off state, the magnitude of which does not exceed half the potential difference between the positive DC link potential (VDC+) and the negative DC link potential (VDC-), and that during a first predetermined time interval (ZI_1) a potential at the connection node (N4) of the third switching device (TN) and the fourth switching device (T4) corresponds to the center potential (N), and / or - wherein the control unit (7) is configured to control the switching devices (T1, T2, T3, T4, TP, TN) before the first switching device (T1) is switched on, such that the sixth switching device (T3) is supplied with a voltage in the switched-off state, the magnitude of which does not exceed half the potential difference between the positive DC link potential (VDC+) and the negative DC link potential (VDC-), and that during a predetermined second time interval (ZI_2) a potential at the connection node (N3) of the second switching device (TP) and the first switching device (T1) corresponds to the center potential (N), characterized in that - the control unit (7) is designed to generate a control signal (ST1) for the first switching device (T1), a control signal (STP) for the second switching device (TP), a control signal (STN) for the third switching device (TN), a control signal (ST4) for the fourth switching device (T4), a control signal (ST2) for the fifth switching device (T2) and a control signal (ST3) for the sixth switching device (T3), - wherein the control unit (7) comprises a signal processor (8) and a logic unit (9), - wherein the signal processor (8) is configured to generate the control signal (ST2) for the fifth switching device (T2) and the control signal (ST3) for the sixth switching device (T3), and to generate a first basic control signal (GN) and a second basic control signal (GP), - wherein the logic unit (9) is configured to generate the control signal (ST1) for the first switching device (T1) and the control signal (STN) for the third switching device (TN) from the first basic control signal (GN) and to generate the control signal (STP) for the second switching device (TP) and the control signal (ST4) for the fourth switching device (T4) from the second basic control signal (GP).

Description

[0001] The invention relates to an inverter.

[0002] The publication by Qing-Xin Guan et al, “An Extremely High Efficient Three-Level Active Neutral-Point-Clamped Converter Comprising SiC and Si Hybrid Power Stages” in IEEE TRANSACTIONS ON POWER ELECTRÖNICS, VOL. 33, NO. 10, OCTOBER 2018, pages 8341-8352, describes an inverter in the form of a multi-stage converter.

[0003] US 2017 / 0 373 586 A1, US 2011 / 0 115 532 A1 and ZHANG, Di [et al.]: “Three-level two-stage decoupled active NPC converter with Si IGBT and SiC MOSFET” in: 2017 IEEE Energy Conversion Congress and Exposition (ECCE), 2017, Conference Paper, pp. (3) 5671-5678, reveal further inverter topologies and switching methods for their operation.

[0004] The invention is based on the objective of providing an inverter that advantageously further develops the multi-stage inverter described in the publication by Qing-Xin Guan et al.

[0005] The invention solves this problem by means of an inverter according to claim 1.

[0006] The inverter or multi-stage inverter is specifically designed as a PV inverter and comprises: a first input terminal to which a positive DC link potential is to be applied, a second input terminal to which a center potential is to be applied, a third input terminal to which a negative DC link potential is to be applied, an output terminal at which an output potential is present during operation of the inverter, a choke, a first switching element, a second switching element, a third switching element, and a fourth switching element, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element are connected in series between the first input terminal and the third input terminal.and wherein a connecting node of the second switching means and the third switching means is electrically connected to the second input terminal, a fifth switching means and a sixth switching means, wherein the fifth switching means and the sixth switching means are connected in series between a connecting node of the first switching means and the second switching means and a connecting node of the third switching means and the fourth switching means, wherein the choke is connected between a connecting node of the fifth switching means and the sixth switching means and the output terminal, and a control unit configured to control the switching means. In this respect, the inverter according to the invention corresponds topologically to that in , Fig. 2a of the publication by Qing-Xin Guan et al. inverter or multi-stage inverter shown.

[0007] According to the invention, the control unit is configured to actuate the switching means before the fourth switching means is switched on, such that the fifth switching means is supplied with a voltage in the switched-off state, the magnitude of which does not exceed half the potential difference between the positive DC link potential and the negative DC link potential, and / or the control unit is configured to actuate the switching means before the first switching means is switched on, such that the sixth switching means is supplied with a voltage in the switched-off state, the magnitude of which does not exceed half the potential difference between the positive DC link potential and the negative DC link potential.

[0008] According to one embodiment, the control unit is configured to actuate the switching devices before the fourth switching device is activated, such that during a predetermined first time interval, the potential at the connection node of the third and fourth switching devices corresponds to the center potential. Similarly, the control unit is configured to actuate the switching devices before the first switching device is activated, such that during a predetermined second time interval, the potential at the connection node of the second and first switching devices corresponds to the center potential. This ensures that the fifth and sixth switching devices are not subjected to the full DC link voltage, but only to a maximum of half the DC link voltage.

[0009] According to one embodiment, the control unit is configured to generate a control signal for the first switching device, a control signal for the second switching device, a control signal for the third switching device, a control signal for the fourth switching device, a control signal for the fifth switching device, and a control signal for the sixth switching device. In this case, the control unit comprises a signal processor and a logic unit, wherein the signal processor is configured to directly generate the control signal for the fifth switching device and the control signal for the sixth switching device, and to directly generate a first basic control signal and a second basic control signal.The logic unit is designed to generate the control signal for the first switching device and the control signal for the third switching device from the first basic control signal, and to generate the control signal for the second switching device and the control signal for the fourth switching device from the second basic control signal.

[0010] According to one embodiment, the logic unit is configured to generate, simultaneously with a falling edge of the first basic control signal, a falling edge of the control signal for the first switching device and, with a time delay, a falling edge of the control signal for the third switching device; with a rising edge of the first basic control signal, a rising edge of the control signal for the first switching device and, simultaneously, a rising edge of the control signal for the third switching device; with a falling edge of the second basic control signal, a falling edge of the control signal for the fourth switching device and, with a time delay, a falling edge of the control signal for the second switching device; and with a rising edge of the second basic control signal, a rising edge of the control signal for the fourth switching device.to generate and simultaneously generate a rising edge of the control signal for the second switching device.

[0011] The control of the switching devices according to the invention requires six PWM control signals per phase. For 3-phase interleaved inverters, i.e., two inverters operating on the same phase but with a phase shift relative to each other, 36 PWM outputs of a digital signal processor (DSP) are therefore required. However, conventional DSPs only provide a maximum of 24 PWM outputs. To offer a solution in this respect, i.e., to continue using standard DSPs, the logic unit generates the necessary additional control signals.

[0012] According to one embodiment, freewheeling diodes are connected in parallel to the respective switching elements.

[0013] According to one embodiment, the first switching device, the second switching device, the third switching device and the fourth switching device are each IGBTs, and the fifth switching device and the sixth switching device are each SiC switching devices.

[0014] The invention is described in detail below with reference to the drawings. These show: Fig. 1 a circuit diagram of part of a PV inverter according to the invention, Fig. 2 a block diagram of a control unit of the in Fig. 1 of the inverter shown and Fig. 3 a temporal profile of control signals, which are generated using the in Fig. The control unit shown in section 3 will be generated.

[0015] Fig. Figure 1 shows a circuit diagram of a part of a photovoltaic (PV) inverter 1 according to the invention. The PV inverter comprises: a first input terminal 2, to which a positive DC link potential VDC+ is applied during operation of the inverter 1; a second input terminal 3, to which a center potential N is applied during operation of the inverter 1; a third input terminal 4, to which a negative DC link potential VDC- is applied during operation of the inverter 1; an output terminal 5, at which an output potential UA is output during operation of the inverter 1; an inductor 6; a first semiconductor switching element T1; a second semiconductor switching element TP; a third semiconductor switching element TN; and a fourth semiconductor switching element T4, wherein the first switching element T1 and the second switching element TP are connected.the third switching device TN and the fourth switching device T4 are connected in series between the first input terminal 2 and the third input terminal 4, and wherein a connection node N1 of the second switching device TP and the third switching device TN is electrically connected to the second input terminal 3, a fifth semiconductor switching device T2 and a sixth semiconductor switching device T3, wherein the fifth switching device T2 and the sixth switching device T3 are connected in series between a connection node N3 of the first switching device T1 and the second switching device TP and a connection node N4 of the third switching device TN and the fourth switching device T4, wherein the choke 5 is connected in series between a connection node N5 of the fifth switching device T2 and the sixth switching device T3 and the output terminal 5, and a control unit 7, see , Fig. 2, which is trained to control the switching devices T1, T2, T3, T4, TP, TN.

[0016] The switching elements T1, T2, T3, T4, TP, TN are connected in parallel with respective freewheeling diodes 10, 11, 12, 13 in the switching direction shown.

[0017] The first switching element T1, the second switching element TP, the third switching element TN and the fourth switching element T4 are all IGBTs. The fifth switching element T2 and the sixth switching element T3 are all SiC switching elements.

[0018] The in Fig. The topology shown corresponds to the one in Fig. 2a of the publication by Qing-Xin Guan et al. The switching devices T1, T2, T3, T4, TP, TN are, however, represented differently than in that publication. Fig. 2b is controlled, as described in detail below.

[0019] Fig. Figure 2 shows the control unit 7, which is designed to generate a control signal ST1 for the first switching device T1, a control signal STP for the second switching device TP, a control signal STN for the third switching device TN, a control signal ST4 for the fourth switching device T4, a control signal ST2 for the fifth switching device T2 and a control signal ST3 for the sixth switching device T3.

[0020] The control unit 7 has a conventional signal processor 8 and a logic unit 9, wherein the signal processor 8 is configured to generate the control signal ST2 for the fifth switching device T2 and the control signal S73 for the sixth switching device T3, and to generate a first basic control signal GN and a second basic control signal GP.

[0021] The logic unit 9 is designed to generate the control signal ST1 for the first switching device T1 and the control signal STN for the third switching device TN from the first basic control signal GN, and to generate the control signal STP for the second switching device TP and the control signal ST4 for the fourth switching device T4 from the second basic control signal GP.

[0022] Fig. Figure 3 now shows a time course of the above-mentioned control signals.

[0023] During the time intervals designated as PWM, the switching devices T2 and T3 are controlled according to a PWM scheme, as described, for example, in the publication by Qing-Xin Guan et al.

[0024] During the time intervals designated as Transition, all switching devices T1, T2, T3, T4, TP, TN are controlled in such a way that the fifth switching device T2, when switched off, is supplied with a voltage whose magnitude does not exceed half the potential difference between the positive DC link potential VDC+ and the negative DC link potential VDC-, and that the sixth switching device T3, when switched off, is supplied with a voltage whose magnitude does not exceed half the potential difference between the positive DC link potential VDC+ and the negative DC link potential VDC-.

[0025] The control signals are generated such that, before the fourth switching device T4 is switched on, the switching devices T1, T2, T3, T4, TP, and TN are in a switching state such that, during a first predetermined time interval ZI_1, the potential at the connection node N4 of the third switching device TN and the fourth switching device T4 corresponds to the center potential N. Similarly, before the first switching device T1 is switched on, the control signals are generated such that the switching devices T1, T2, T3, T4, TP, and TN are in a switching state such that, during a predetermined second time interval ZI_2, the potential at the connection node N3 of the second switching device TP and the first switching device T1 corresponds to the center potential N.

[0026] The logic unit 9 is designed to generate, simultaneously with a falling edge of the first basic control signal GN, a falling edge of the control signal ST1 for the first switching device T1 and, with a time delay of t1, a falling edge of the control signal STN for the third switching device TN, and, with a rising edge of the first basic control signal GN, a rising edge of the control signal ST1 for the first switching device T1 with a time delay of t1 and, simultaneously, a rising edge of the control signal STN for the third switching device TN.

[0027] The logic unit 9 is further configured to simultaneously generate a falling edge of the control signal ST4 for the fourth switching device T4 when the second basic control signal GP falls, and to generate a falling edge of the control signal STP for the second switching device TP with a time delay of 11, and to generate a rising edge of the control signal ST4 for the fourth switching device T4 with a time delay of t1 when the second basic control signal GP rises, and to generate a rising edge of the control signal STP for the second switching device TP simultaneously.

[0028] The control signals ST1 and STN for switching devices T1 and TN, respectively, are based on the first basic control signal GN, and the control signals ST4 and STP for switching devices T4 and TP, respectively, are based on the second basic control signal GP. However, the control signal ST1 for switching device T1 is switched on with a delay and switched off without delay. The control signal STN for switching device TN is switched on without delay and switched off with a delay. The delay must correspond to at least twice the dead time t2. This ensures that during the switching process, switching devices TP and TN are switched on together for at least one dead time t2.

[0029] According to the publication by Qing-Xin Guan et al., switching devices T1 and Tn are supplied with the same control signal, and switching devices T4 and Tp are supplied with the same control signal (see Table 1). However, this inevitably leads to switching devices T2 and T3 being supplied with the entire DC link voltage during certain switching sequences. This necessitates increasing the blocking voltage of the switching devices to such an extent that they can block the entire DC link voltage. This, in turn, requires semiconductors with a correspondingly higher blocking voltage. However, these semiconductors have a larger area for the same conduction losses. A larger area, in turn, means higher costs. Furthermore, such semiconductors have poorer dynamic properties, which leads to higher switching losses.

[0030] According to the invention, during the switching from positive to negative output voltage, node TN / T3 to T4 is temporarily held or clamped at the DC link center N. Similarly, during the switching from negative to positive output voltage, node TP / T2 to T1 is temporarily held or clamped at the DC link center N. This ensures that switching elements T2 and T3 are not subjected to the full DC link voltage, but only to a maximum of half the DC link voltage. Therefore, semiconductors with a correspondingly lower reverse voltage can be used as switching elements.

[0031] There can be several, especially two, of which in Fig. The inverters shown are connected in parallel and are then interleaved or operated with a phase shift.

[0032] The intermediate circuit voltage can be conventionally generated by a suitable DC source, for example, one or more solar modules. The output potential or output voltage UA can conventionally be used for grid feed-in.

Claims

[1] Inverter (1) comprising: - a first input terminal (2) to which a positive intermediate circuit potential (VDC+) is applied during operation of the inverter (1), - a second input terminal (3) to which a center potential (N) is applied during operation of the inverter (1), - a third input terminal (4) to which a negative intermediate circuit potential (VDC-) is applied during operation of the inverter (1), - an output terminal (5) at which an output potential (UA) is output during operation of the inverter (1), - a throttle (6), - a first switching device (T1), a second switching device (TP), a third switching device (TN) and a fourth switching device (T4), wherein the first switching device (T1), the second switching device (TP), the third switching device (TN) and the fourth switching device (T4) are connected in series between the first input terminal (2) and the third input terminal (4), and wherein a connection node (N1) of the second switching device (TP) and the third switching device (TN) is electrically connected to the second input terminal (3), - a fifth switching device (T2) and a sixth switching device (T3), wherein the fifth switching device (T2) and the sixth switching device (T3) are connected in series between a connection node (N3) of the first switching device (T1) and the second switching device (TP) and a connection node (N4) of the third switching device (TN) and the fourth switching device (T4), wherein the choke (5) is connected in series between a connection node (N5) of the fifth switching device (T2) and the sixth switching device (T3) and the output terminal (5), and - a control unit (7) designed to control the switching devices (T1, T2, T3, T4, TP, TN), - wherein the control unit (7) is configured to control the switching devices (T1, T2, T3, T4, TP, TN) before the fourth switching device (T4) is switched on, such that the fifth switching device (T2) is supplied with a voltage in the switched-off state, the magnitude of which does not exceed half the potential difference between the positive DC link potential (VDC+) and the negative DC link potential (VDC-), and that during a first predetermined time interval (ZI_1) a potential at the connection node (N4) of the third switching device (TN) and the fourth switching device (T4) corresponds to the center potential (N), and / or - wherein the control unit (7) is configured to control the switching devices (T1, T2, T3, T4, TP, TN) before the first switching device (T1) is switched on, such that the sixth switching device (T3) is supplied with a voltage in the switched-off state, the magnitude of which does not exceed half the potential difference between the positive DC link potential (VDC+) and the negative DC link potential (VDC-), and that during a specified second time interval (ZI_2) a potential at the connection node (N3) of the second switching device (TP) and the first switching device (T1) corresponds to the center potential (N), characterized by , that - the control unit (7) is designed to generate a control signal (ST1) for the first switching device (T1), a control signal (STP) for the second switching device (TP), a control signal (STN) for the third switching device (TN), a control signal (ST4) for the fourth switching device (T4), a control signal (ST2) for the fifth switching device (T2) and a control signal (ST3) for the sixth switching device (T3), - wherein the control unit (7) comprises a signal processor (8) and a logic unit (9), - wherein the signal processor (8) is configured to generate the control signal (ST2) for the fifth switching device (T2) and the control signal (ST3) for the sixth switching device (T3), and to generate a first basic control signal (GN) and a second basic control signal (GP), - wherein the logic unit (9) is configured to generate the control signal (ST1) for the first switching device (T1) and the control signal (STN) for the third switching device (TN) from the first basic control signal (GN) and to generate the control signal (STP) for the second switching device (TP) and the control signal (ST4) for the fourth switching device (T4) from the second basic control signal (GP). [2] Inverter (1) according to claim 1, characterized by , that - the logic unit (9) is designed to - to simultaneously generate a falling edge of the control signal (ST1) for the first switching device (T1) on a falling edge of the first basic control signal (GN) and to generate a falling edge of the control signal (STN) for the third switching device (TN) with a time delay, - to generate a rising edge of the control signal (ST1) for the first switching device (T1) with a time delay on a rising edge of the first basic control signal (GN) and simultaneously to generate a rising edge of the control signal (STN) for the third switching device (TN), - to simultaneously generate a falling edge of the control signal (ST4) for the fourth switching device (T4) on a falling edge of the second basic control signal (GP) and to generate a falling edge of the control signal (STP) for the second switching device (TP) with a time delay, and - to generate a rising edge of the control signal (ST4) for the fourth switching device (T4) with a time delay on a rising edge of the second basic control signal (GP) and to generate a rising edge of the control signal (STP) for the second switching device (TP) at the same time. [3] Inverter (1) according to any of the preceding claims, characterized by , that - the respective freewheeling diodes (10, 11, 12, 13) are connected in parallel to the switching devices (T1, T2, T3, T4, TP, TN). [4] Inverter (1) according to any of the preceding claims, characterized by , that - the first switching device (T1), the second switching device (TP), the third switching device (TN) and the fourth switching device (T4) are each IGBTs, and - the fifth switching device (T2) and the sixth switching device (T3) are each SiC switching devices.

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