Semiconductor device having a porous region, wafer composite structure, and method for producing a semiconductor device

Abstract

A method of manufacturing a semiconductor device, comprising: Providing a semiconductor substrate (700) having a base region (705), an additional layer (710) on the base region (705) and a surface layer (720) on the additional layer (710), wherein the surface layer (720) is in contact with a first main surface (701) of the semiconductor substrate (700) and wherein the additional layer (710) has a different electrochemical dissolution efficiency than the base region (705) and the surface layer (720); Forming a mask (410) on the first main surface (701), wherein mask openings (415) in the mask (410) expose first portions (721) of the surface layer (720); Converting at least one horizontal layer region of the additional layer (710) and the first sections (721) of the surface layer (720) into a porous structure (820), wherein the horizontal layer region of the additional layer (710) directly adjoins the surface layer (720) and wherein non-porosified sections are located laterally between the porosified first sections (721); and Forming, after converting, an epitaxial layer (730) on the first main surface (701).

Description

TECHNICAL FIELD

[0001] Examples of the present disclosure relate to a method for manufacturing semiconductor devices, the method comprising forming a porous structure in a semiconductor substrate. Further examples relate to a wafer composite structure having a porous structure and to a semiconductor device including a porous region. BACKGROUND

[0002] The production of semiconductor wafers typically involves forming crystal ingots by vertical zone melting or by pulling a seed crystal rod from a crucible filled with molten semiconductor material. The crystal ingots are then sliced, for example, by sawing. Meanwhile, several techniques obtain epitaxial silicon wafers by forming a thin separation layer on top of a reusable silicon seed wafer, epitaxially growing a silicon layer on the separation layer, and then mechanically detaching the epitaxially grown silicon layer from the seed wafer. Other methods cleave an epitaxially grown semiconductor wafer from a single-crystal base substrate along a cleavage layer, which can be formed using laser irradiation.

[0003] Document US 2016 / 0 104 780 A1 describes the epitaxial growth of single-crystal semiconductor layers on porous semiconductor layers in the manufacture of semiconductor components. The porous semiconductor layers are layers with a uniform layer thickness and reduce mechanical stress in structures formed in the epitaxial semiconductor layer. Document US 2002 / 0 153 595 A1 describes the manufacture of single-crystal photovoltaic cells based on Si, Ge, GaAs, GaN, or GaP. By anodic oxidation, a highly porous layer is formed on a single-crystal auxiliary substrate and a weakly porous layer is formed on the highly porous layer. An epitaxial layer is grown on the weakly porous layer. The epitaxial layer is separated from the single-crystal auxiliary substrate by cleaving the highly porous layer.The method described in US 2005 / 0 142 687 A1 for producing a micromechanical diaphragm uses a porous double layer with a slightly porous sublayer and a highly porous sublayer. US 2010 / 0 289 123 A1 relates to an SOI technique in which a silicon layer grows epitaxially on a SiGe layer interspersed with porous Si columns. WO 2013 / 117 155 A1 also relates to an SOI technique. A first monocrystalline semiconductor layer is grown on a layer intended for porosification. Trenches are then formed that extend through the first monocrystalline semiconductor layer and into the layer intended for porosification. The layer intended for porosification is porosified by electrochemical etching using HF as the etchant. The porosified layer is oxidized or nitrided.Starting from the sidewalls of the trenches, a second epitaxial layer is grown, laterally overgrowing the first epitaxial layer. US Pat. No. 6,143,628 A describes the transfer of an epitaxial layer grown on a weakly porous layer of a donor substrate to a carrier substrate with an overlying insulator layer. After bonding the epitaxial layer to the insulator layer, the donor substrate is cleaved from the epitaxial layer and the carrier substrate along a highly porous layer.

[0004] There is a need for processes to economically provide semiconductor wafers. SUMMARY

[0005] The invention is defined in the independent claims. Further developments are the subject of the dependent claims. One example of the present disclosure relates to a method for manufacturing a semiconductor device. The method comprises providing a semiconductor substrate comprising a base region, an auxiliary or supplementary layer, and a surface layer. The supplementary layer is formed on the base region. The surface layer is formed on the supplementary layer. The surface layer is formed in contact with a first main surface of the semiconductor substrate. The supplementary layer may have a different electrochemical dissolution efficiency than the base region and the surface layer. At least a region of the supplementary layer and a region of the surface layer are converted into a porous structure.After converting at least the region of the additional layer and at least the region of the surface layer into the porous structure, an epitaxial layer is formed on the first main surface.

[0006] Another example of the present disclosure relates to another method for manufacturing a semiconductor device. A semiconductor substrate is provided comprising a base region and an additional layer formed on the base region. The additional layer is in contact with a first main surface of the semiconductor substrate. Pits are formed in the first main surface. At least a portion of the additional layer is converted into a porous structure, wherein the porous structure includes a layered region spaced from the first main surface and further includes laterally separated columnar regions extending from the pits to the layered region.

[0007] Another example of the present disclosure relates to a wafer composite structure comprising a base region, a porous structure, and an epitaxial layer. The porous structure includes a coarsely porous layered region formed on the base region and a finely porous region formed on the layered region. The epitaxial layer is formed on the finely porous region.

[0008] Another example of the present disclosure relates to a semiconductor device including a semiconductor body. The semiconductor body comprises a drift structure, a fine pore region, and a coarse pore layered region. The fine pore region is formed between a first surface of the semiconductor body and the layered region. The layered region is in direct contact with a second surface of the semiconductor body opposite the first surface.

[0009] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of the specification. The drawings illustrate examples of a semiconductor device, a wafer composite structure, and a method of fabricating a semiconductor device, and together with the description serve to explain principles of the examples. Further examples are described in the following detailed description and claims. Fig. 1A-1D show schematic vertical cross-sectional views of portions of a semiconductor substrate and a wafer composite structure to illustrate a method of manufacturing a semiconductor device including forming a porous structure, according to an example. Fig. 2A-2C show schematic vertical cross-sectional views of portions of a semiconductor substrate and a wafer composite structure to illustrate a method of manufacturing a semiconductor device according to an example using laterally separated, finely porous columnar structures. Fig. 3A-3C show schematic vertical cross-sectional views of portions of a semiconductor substrate and a wafer composite structure to illustrate a method of manufacturing a semiconductor device according to an example using pits to form laterally separated, finely porous columnar structures. Fig. 4A-4C show schematic vertical cross-sectional views of portions of a semiconductor substrate and a wafer composite structure to illustrate a method of fabricating a semiconductor device according to an example using masked implantation of dopants to form laterally separated, finely porous columnar structures. Fig. 5A-5C show schematic vertical cross-sectional views of portions of a semiconductor substrate and a wafer composite structure to illustrate a method of manufacturing a semiconductor device according to an example using pits to form laterally separated, finely porous columnar structures. Fig. 6 shows a schematic vertical cross-sectional view of a wafer composite structure according to an example with an epitaxial layer on a fine porous layer. Fig. 7 shows a schematic vertical cross-sectional view of a wafer composite structure according to an example with laterally separated, finely porous columnar regions. Fig. 8A-8B show schematic vertical and horizontal cross-sectional views of a semiconductor diode having a porous region according to an example. Fig. 9A-9B show vertical and horizontal cross-sectional views of a semiconductor device having transistor cells and a porous region according to an example. DETAILED DESCRIPTION

[0011] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, for purposes of illustration, specific embodiments in which a semiconductor device, a wafer composite structure, and a method of fabricating a semiconductor device may be practiced. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used on or in connection with other examples to arrive at yet another example. It is intended that the present disclosure encompass such modifications and changes.The examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals throughout the various drawings unless otherwise noted.

[0012] The terms "have," "contain," "comprise," "have," and similar terms are open-ended terms. These terms indicate the presence of the identified structures, elements, or characteristics, but do not preclude the presence of additional elements or characteristics. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0013] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" implies that one or more intermediate elements suitable for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. An ohmic contact is a non-rectifying electrical junction with a linear or nearly linear current-voltage characteristic.

[0014] The figures illustrate relative doping concentrations by indicating “ -" or " + ” next to the doping type “n” or “p”. For example, “n - ” a doping concentration that is lower than the doping concentration of an “n” doping region, while an “n + "-doping region has a higher doping concentration than an "n"-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doping regions can have the same or different absolute doping concentrations.

[0015] Two adjacent doping regions of the same conductivity type and with different dopant concentrations form a unipolar junction, e.g., an (n / n+) junction or (p / p+) junction, along an interface between the two doping regions. In a unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may exhibit a step or inflection point at which the dopant concentration profile changes from concave to convex or vice versa.

[0016] Ranges specified for physical dimensions include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a boundary value such as "at most" and "at least."

[0017] The main components of a layer or structure made of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy. For example, nickel and silicon are the main components of a nickel silicide layer, and copper and aluminum are the main components of a copper-aluminum alloy.

[0018] The term "on" should not be construed as meaning only "directly on." Rather, if an element is positioned "on" another element (e.g., a layer is "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0019] According to one example, a method of manufacturing a semiconductor device may include providing a semiconductor substrate comprising a base region, an additional layer, and a surface layer.

[0020] The semiconductor substrate may be a single-crystal semiconductor, wherein the semiconductor may be a single-element semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor, for example, a III / V compound semiconductor such as gallium arsenide (GaAs) or gallium nitride (GaN), or a IV / IV compound semiconductor such as silicon germanium (SiGe) or silicon carbide (SiC). The semiconductor substrate may have two parallel, flat major surfaces of the same shape and size and a lateral surface connecting the edges of the two major surfaces. For example, the semiconductor substrate may be a polygonal (e.g., a rectangular or hexagonal) prism with or without rounded edges, or a right cylinder with or without one or more flats or notches.

[0021] Directions parallel to principal surfaces are horizontal or lateral directions. A surface normal on a principal surface is parallel to a vertical direction.

[0022] The additional layer can be formed directly on the base region. The surface layer can be formed directly on the additional layer. In other words, the base region, the additional layer, and the surface layer can be vertically stacked directly on top of one another. The surface layer can be the uppermost layer, and the exposed surface of the surface layer can form a first of the two main surfaces of the semiconductor substrate. The surface layer can have a first main surface of the semiconductor substrate. That is, the surface layer can be formed in direct contact with the first main surface. For example, an outer surface of the surface layer can form and / or represent the first main surface.

[0023] The base region and the additional layer can form a horizontal first interface, e.g., a horizontal unipolar junction or a pn junction. The base region and the surface layer can form a horizontal second interface, e.g., a horizontal unipolar junction or a pn junction. Here and in the following, a layer can be understood as a horizontal structure of substantially uniform thickness and a laterally substantially uniform dopant distribution.

[0024] The additional layer may have a different electrochemical dissolution efficiency (in particular, a higher dissolution efficiency) than the base region and / or the surface layer. Anodic dissolution occurs during electrochemical etching, whereby a metal or semiconductor dissolves from an anodic workpiece into a cathodic electrolyte. The electrochemical dissolution efficiency may correspond to the amount of material that can be removed with an electrochemical etch under the same conditions, for example, keeping either the current or the voltage constant. A higher electrochemical dissolution efficiency may result in a coarser pore structure with larger pores.

[0025] The electrochemical dissolution efficiency may correspond to the electrochemical dissolution rate, in particular the anodic dissolution rate. Alternatively, the electrochemical dissolution efficiency may correspond to the time during which the electrochemical etching acts on the respective region and / or layer to be etched. The electrochemical dissolution rate may be the amount of atoms removed during a given period of time. For example, the additional layer may have a higher electrochemical dissolution efficiency than the base region and / or the surface layer.

[0026] In some examples, the electrochemical dissolution rate of the additional layer may be higher than the electrochemical dissolution rate of the base region and / or the surface layer. This may be the case, for example, for so-called voltage-controlled electrochemical etching (i.e., when a constant voltage is applied). The electrochemical dissolution rate is the rate at which a particular material dissolves in an electrolyte. In the voltage-controlled case, a more conductive region of a semiconductor material may exhibit a higher electrochemical dissolution rate than a less conductive region of the same semiconductor material with the same conductivity type. For example, in the voltage-controlled case, a more highly doped region of a semiconductor material may exhibit a higher electrochemical dissolution rate than a less doped region of the same semiconductor material with the same conductivity type.

[0027] In other examples, the electrochemical dissolution rate of the additional layer may be equal to or higher than the electrochemical dissolution rate of the base region and / or the surface layer. This may be the case, for example, for so-called current-controlled electrochemical etching. In this case, the electrochemical etching may act on the additional layer for a longer time than on the surface layer and / or the base region. It may be possible that the electrochemical etching for the base region and / or the surface layer will stop (in particular automatically) due to, for example, different electrical properties of these layers (or, respectively, this layer) compared to the additional layer. In this way, more material can be removed from the additional layer compared to the base region and / or the surface layer.

[0028] There are examples where the electrochemical dissolution rate of the additional layer may be even lower than the electrochemical dissolution rate of the base region and / or the surface layer.

[0029] During electrochemical etching of a substrate with a uniform dissolution rate, the electrical resistance of the semiconductor substrate may be locally reduced at locations where etching begins to progress due to natural fluctuations. The lower electrical resistance results in higher local current density and current filaments, so that etching progresses predominantly at locations where etching first began due to natural fluctuations. The embodiments can improve the control of the etching medium's access to the additional layer and, to a certain extent, replace a purely stochastic process.

[0030] At least a portion of the additional layer and a portion of the surface layer can be rendered porous, i.e., converted into a porous structure, electrochemically, e.g., by electrochemical etching that induces anodic dissolution of the semiconductor material. For example, the semiconductor substrate can be contacted with an electrolyte containing fluorine, e.g., hydrofluoric acid (HF), and ethanol. Alternatively, the electrolyte can be an aqueous HF solution. A cathode electrode can be immersed in the electrolyte, and an electrical potential can be applied between the cathode electrode and the semiconductor substrate, which forms the anode electrode.

[0031] Instead of completely dissolving the crystal structure of the semiconductor substrate, anodic dissolution locally excavates groups of lattice atoms from the crystal lattice, forming pores within the semiconductor crystal. The remaining, undissolved lattice atoms form a single-crystal lattice skeleton.

[0032] The anodic dissolution can convert at least a region of the additional layer and at least a region of the surface layer into a porous region. The higher dissolution efficiency of the additional layer can cause the anodic dissolution to convert the additional layer into a coarse-porous region with comparatively large pores and a high total porosity of at least 30% and at most 80%, e.g., in a range from 40% to 60%. For example, in the coarse-porous region, the pores can have an average diameter greater than 50 nm, e.g., in a range from 50 nm to 200 nm.

[0033] The low anodic dissolution efficiency of the surface layer can cause the anodic dissolution to transform the surface layer into a fine-pored region with comparatively small pores and a low total porosity of at least 5% and at most 50%, e.g., in a range of 10% to 35%. For example, in the fine-pored region, the pores can have an average diameter of at most 50 nm, e.g., less than 40 nm.

[0034] The porosity of the coarse-porous region can generally be greater than the porosity of the fine-porous region. The porosity of a region (e.g., a layer or a body) can be the fraction of the void (i.e., "empty") volume in the region over the total volume of the region.

[0035] The additional layer can be made porous across its entire vertical extent. Furthermore, the horizontal layer region of the base region can be made porous, with the porous horizontal layer region of the base region being in direct contact with the porous additional layer. Alternatively, only a horizontal layer region of the additional layer can be made porous, with the porous horizontal layer region directly bordering the porous surface layer.

[0036] After forming the porous structure via a conversion, an epitaxial layer can be formed directly on the first major surface of the surface layer (with or without in-situ hydrogen surface etching prior to epitaxial growth). The deposited atoms can infiltrate into the porous, but still crystalline (especially single-crystalline) lattice of the porous structure. The epitaxial layer can be formed from the same semiconductor as the surface layer or from a different semiconductor that forms a crystal lattice that approximately matches the crystal lattice of the surface layer.

[0037] The quality of the epitaxial layer can be described by its lattice defect density. An epitaxial layer grown on a coarse-porous (also called "large-porous") structure can exhibit a comparatively high lattice defect density. In some semiconductor materials, anodic dissolution can form a thin surface layer (a so-called skin layer) with self-ordered columnar pores and a comparatively fine-porous structure. Such a natural skin layer may be too thin to form a sufficiently rough seed layer for epitaxy. For example, a cleaning or etching process, e.g., an etching process in a hydrogen-containing atmosphere, can precede the epitaxial process and can partially or completely convert the natural skin layer into a porous structure with larger and / or more pores.

[0038] The presence of the surface layer facilitates control of the thickness of a sufficiently rough seed layer for epitaxy, wherein the seed layer has a finely porous structure along the first main surface and wherein the seed layer comprises the surface layer or at least a region of the surface layer.

[0039] In particular, selecting a suitable thickness for the surface layer facilitates the formation of a finely porous seed layer of defined thickness along the first main surface and the formation of a coarsely porous layer at a distance from the first main surface. The seed layer can provide a suitable base for an epitaxial layer with a comparatively high crystal quality. The thickness of the seed layer can be sufficient so that it is not completely consumed or otherwise damaged during or immediately before the epitaxial process. At the same time, the method provides a highly porous structure beneath the finely porous seed layer. The highly porous structure can, for example, facilitate a reliable separation process that separates the epitaxial layer from the base region.

[0040] For example, the wafer may additionally undergo a high-temperature treatment (e.g., an activating anneal after epitaxial growth). The high-temperature treatment may be performed at a temperature above 1300°C. During such a high-temperature treatment, the pores in the porous structure within the semiconductor material may be rearranged. In particular, the pores may be combined and / or rearranged into larger pores. The porosity of the porous structure may remain unchanged or may change by only ± 10% at most. After the high-temperature treatment, for example, the porous structure may have larger pores; but the number of pores may have been reduced. The morphology of the porous structure may thus change during a high-temperature treatment. This could facilitate separation of the epitaxial layer from the base region.

[0041] According to one example, the epitaxial layer can be separated from the base region along the porous structure at any stage of processing. For example, the epitaxial layer can be separated from the base region after forming semiconducting regions of semiconductor devices in the epitaxial layer. The separation process can include separating (e.g., cleaving) the porous structure along an approximately horizontal plane through the coarsely porous layered region.

[0042] The process makes it possible to obtain semiconductor devices exclusively from a single epitaxial layer (e.g., multiple epitaxial layers with different doping). The base region can be reused for another cycle after removing remnants of the porous structure from the base region. Since the additional layer can be thinner than a typical saw blade or even a wire used to saw semiconductor wafers from a crystal ingot, it is possible to reduce the loss of expensive single-crystal semiconductor material.

[0043] According to one example, the epitaxial layer and the semiconductor substrate may differ in at least one major component. For example, the epitaxial layer may be a layer of gallium arsenide (GaAs) or gallium nitride (GaN), and the semiconductor substrate may be a silicon carbide (SiC) substrate. A more expensive semiconductor material may be obtained through epitaxial growth at the expense of a loss of less expensive semiconductor material.

[0044] According to one example, an average net dopant concentration in the additional layer may be at least 100 times an average net dopant concentration in the surface layer. For example, the surface layer and the additional layer are based on n-type 4H-SiC, and the dopant concentration may be greater than 10 19 cm -3 , for example at least 10 20 cm -3The dopant concentration in the surface layer can be less than 10 18 cm -3 , for example a maximum of 10 17 cm -3 , be.

[0045] Furthermore, the average net dopant concentration in the base region can be equal to the average net dopant concentration in the additional layer or can be at most 50%, for example, at most 10%, of this. In this way, the vertical growth of the porous structure toward the second main surface can be controlled.

[0046] According to one example, the surface layer and the additional layer may have the same conductivity type; for example, both layers may be either n-type or p-type. The surface layer may thus be formed in a cost-effective manner. For example, formation of the surface layer may include in-situ doping during epitaxial growth of the surface layer on the additional layer. Alternatively or additionally, formation of the surface layer may include counter-doping a surface region of a precursor layer with the dopant concentration of the additional layer, wherein the counter-doped region of the precursor layer forms the surface layer and the remainder of the precursor layer forms the additional layer.

[0047] According to one example, the semiconductor substrate may be a silicon carbide substrate. Forming porosity in a silicon carbide substrate without forming an additional layer and a surface layer may result in a relatively thin natural skin layer in which self-ordered nano-columnar pores form. The natural skin layer may exhibit a sufficiently smooth surface for epitaxial growth. Providing the combination of the surface layer and the additional layer according to some embodiments of the present method may result in the surface layer or a region of the surface layer forming a seed layer with a greater thickness than the natural skin layer after the formation of porosity, wherein the seed layer is more robust and is not consumed or severely damaged during the epitaxial growth of the epitaxial layer.

[0048] According to one example, the first main surface can be completely exposed during formation of the porous structure. A sufficiently thick surface layer can be formed economically without any further masking steps.

[0049] According to one example, a mask may be formed on the main surface layer prior to forming the porous structure via the conversion. Mask openings in the mask may expose first portions of the surface layer. The mask openings may be strip-shaped with a width of no more than 200 nm, for example, at most 100 nm, or may be approximately circular or approximately regularly polygonal with a diameter or edge length of no more than 200 nm, for example, at most 100 nm. The mask openings may be arranged in a regular pattern, wherein a center-to-center distance between adjacent mask openings may be in the range of a few micrometers. The mask may be formed from a material with sufficient etch resistance to the electrolyte.

[0050] During electrochemical etching, the electric field may be concentrated in areas of the surface layer below the mask openings (i.e., it may be largest and / or dominant there). In other words, in the lightly doped surface layer, porosity formation will concentrate along the electric field lines below the mask openings, so that no or only a few pores are formed in areas of the surface layer covered by the mask. The non-porous areas of the surface layer can form defect-free regions of a seed layer for a high-quality epitaxial layer.

[0051] The dopant concentrations in the surface layer and the additional layer, the thickness of the surface layer, the dimensions of the mask openings and the center-to-center distance between the mask openings enable precise control of the thickness of a rough seed layer for the epitaxial process.

[0052] According to another example, the first portions exposed by the mask openings may be recessed prior to forming the porous structure via the conversion. The recess may form pits in the first main surface. The pits may have a vertical extension in a range from 0.1 µm to 5 µm, for example, from 0.5 µm to 1 µm.

[0053] The mask can be removed before porosity (i.e., before the porous structure) forms. During anodic etching, the electric field lines can concentrate below the pits. Anodic dissolution can concentrate and spread along current filaments that form parallel to the electric field lines below the pits, so that pores are formed in the surface layer predominantly or exclusively below the pits. Non-porous areas of the surface layer can form areas of a rough seed layer for epitaxial growth.

[0054] According to another example, dopants can be selectively implanted into the first sections prior to forming the porous structure via the conversion. The dopants can locally increase the electrochemical dissolution efficiency, e.g., the dissolution rate of the surface layer, so that in the lightly doped surface layer, the formation of porosity occurs predominantly in the areas exposed by the mask openings. Areas of the surface layer that have not been rendered porous can form regions of a rough seed layer for epitaxial growth.

[0055] According to another example, the method for manufacturing a semiconductor device comprises providing a semiconductor substrate comprising a base region and an additional layer formed on the base region. Pits may be formed in the additional layer. For example, an etch mask may be formed on the additional layer, wherein mask openings in the etch mask expose first portions of the additional layer, and wherein the pits are formed in the first portions. The pits may have a vertical extent in a range from 0.1 µm to 5 µm, for example from 0.5 µm to 1 µm. A first vertical extent v1 of the additional layer may be in a range from 0.5 µm to 10 µm.

[0056] At least one region of the additional layer can be converted into a porous structure, for example, by anodic dissolution. The porous structure comprises a layered region at a distance from the main surface and laterally separated columnar regions extending from the pits to the layered region. Non-porous regions of the additional layer between the columnar regions form non-porous regions. The non-porous regions may be completely devoid of pores or may contain pores to a significantly lesser extent than the columnar regions of the porous structure. For example, the porosity of the non-porous region is at most 10% of the porosity of the columnar regions.

[0057] The pits enable the formation of a sufficiently thick, low-porosity seed layer with sufficient crystal quality with little effort.

[0058] According to one example, after converting at least a portion of the additional layer and at least a portion of the surface layer into the porous structure, an epitaxial layer may be formed on the first main surface. The epitaxial layer may be separated from the base region along the layered region of the porous structure. For example, the layered region may be separated horizontally.

[0059] According to another example, a wafer composite structure may include a base region, a porous structure, and an epitaxial layer. The porous structure may include a coarsely porous layered region and a finely porous region. The coarsely porous layered region is formed on the base region. The finely porous region is formed on the coarsely porous layered region. The epitaxial layer may be homogeneously doped, may exhibit a non-uniform vertical dopant gradient, may comprise two or more differently doped sublayers, or may contain semiconducting regions of semiconductor devices at any stage of processing.

[0060] The wafer composite structure enables the fabrication of semiconductor devices in an epitaxial layer with high crystal quality, with the porous structure facilitating effective separation of the epitaxial layer from the base region.

[0061] According to one example, the finely porous region may include laterally separated columnar regions protruding from the layered region. Non-porous regions may be formed laterally between the columnar regions.

[0062] According to another example, the layered region may include a compound semiconductor.

[0063] According to another example, a semiconductor device may include a semiconductor body comprising a drift structure, a fine pore region, and a coarse pore layered region.

[0064] The semiconductor device and / or wafer described above can be manufactured using at least some of the method steps described in connection with the above or following examples. This means that all features disclosed in connection with embodiments of the method are also disclosed for the semiconductor device and / or wafer, and vice versa. In particular, the fine-pored region can have the characteristics of the fine-pored region described above. Furthermore, the coarse-pored region can have the characteristics of the coarse-pored region described above, and a layered region of the coarse-pored region can have the characteristics of the layered region of the coarse-pored region described above.

[0065] The fine-pored region can be formed between the first surface and the layered region of the coarse-pored region. The coarse-pored layered region can be in direct contact with the second surface. The drift structure can contain a lightly doped drift zone between the first surface and the porous region. The drift zone can be formed outside the porous region or can overlap with the porous region, e.g., with the fine-pored region. The fine-pored region can be in direct contact with the layered region.

[0066] The semiconductor device can be cost-effectively formed exclusively in an epitaxial material that can be separated from a donor substrate along a porous structure, wherein the fine-pore region and the layer region of the semiconductor device can be formed from regions of the porous structure. The fine-pore region and the coarse-pore layer region can reduce mechanical stress between a semiconductor body and a backside metallization formed on the second surface. Alternatively or additionally, the fine-pore region and the layer region can provide getter sites for impurities, e.g., metal atoms, and / or can be used to tune device parameters such as short-circuit robustness.Alternatively or additionally, the fine pore region and the coarse pore region may increase a charge carrier recombination rate to improve switching characteristics of a semiconductor device and / or may improve adhesion between the semiconductor body and a non-semiconductor material on the second surface.

[0067] According to one example, the fine-pored region may include laterally separated columnar regions protruding from the layered region. For example, the columnar regions may be strip-shaped with a horizontal longitudinal axis parallel to the first main surface. Alternatively, the columnar regions may have two orthogonal horizontal dimensions within the same order of magnitude. For example, the horizontal cross-sections of the columnar regions may be circular or polygonal, with or without rounded corners. The fine-pored columnar regions may locally increase the charge carrier recombination rate to improve switching characteristics of a semiconductor device.

[0068] According to one example, the semiconductor device includes a backside metallization that is in direct contact with the layer region. The coarse-pored layer region can reduce thermomechanical stress between the semiconductor body and the backside metallization. Furthermore, the coarse-pored layer region can reduce the contact resistance between the backside metallization and the backside surface of the semiconductor.

[0069] According to one example, the layer region may contain a compound semiconductor, for example a IV / IV compound semiconductor, e.g. SiC.

[0070] Fig. 1A - 1D illustrate a formation of an epitaxial wafer that is separable from a donor wafer by horizontally separating (e.g., cleaving) a porous structure.

[0071] Fig. 1A shows a semiconductor substrate 700, which may be a wafer of a non-porous single-crystal semiconductor crystal. The semiconductor substrate 700 may be obtained from a single-crystal ingot, for example, by sawing, or may be obtained by epitaxy.

[0072] A first main surface 701 on the front side of the semiconductor substrate 700 and a second main surface 702 on the back side are parallel to each other and may have the same shape, which may be circular, circular with a notch, circular with a flat surface, polygonal with rounded corners, or polygonal without rounded corners. A lateral surface 703 connects the edges of the first main surface 701 and the second main surface 702.

[0073] The semiconductor of the semiconductor substrate 700 may be an elemental semiconductor such as silicon or germanium, or may be a compound semiconductor, for example, a IV / IV compound semiconductor such as 15R-SiC, 2H-SiC, 6H-SiC, or 4H-SiC. In addition to the main components of silicon and carbon, the semiconductor substrate 700 may contain dopant atoms, for example, nitrogen (N), phosphorus (P), beryllium (Be), aluminum (Al), and / or gallium (Ga). The semiconductor substrate 700 may contain further impurities such as hydrogen (H), fluorine (F), and / or oxygen (O).

[0074] A surface normal 704 of the first main surface 701 defines a vertical direction. Directions orthogonal to the surface normal 704 are lateral and horizontal directions.

[0075] The semiconductor substrate 700 may include at least a base region 705, an additional layer 710, and a surface layer 720 stacked vertically on top of one another, wherein the additional layer 710 may separate the surface layer 720 and the base region 705. An exposed upper surface of the surface layer 720 forms the first main surface 701 of the semiconductor substrate 700. The semiconductor substrate 700 may include further layers between the base region 705 and the second main surface 702. The surface layer 720, the additional layer 710, and the base region 705 may have the same conductivity type. For example, the surface layer 720, the additional layer 710, and the base region 705 may be n-doped. The additional layer 710 may contain, for example, arsenic (As), phosphorus (P), nitrogen (N), and / or antimony (Sb) atoms.The additional layer 710 may be homogeneously doped or may exhibit a non-uniform vertical dopant profile. The additional layer 710 may exhibit a lateral, substantially uniform dopant distribution. A minimum dopant concentration in the additional layer 710 is at least 10. 18 cm -3 , for example at least 10 19 cm -3 . The additional layer 710 may have a first vertical extent v1 in a range from 0.5 µm to 10 µm, for example in a range from 5 µm to 8 µm.

[0076] An average net dopant concentration in the base region 705 may be equal to or lower than in the additional layer 710, for example at most 50% or at most 10% of the average dopant concentration in the additional layer 710.

[0077] A second vertical extension v2 of the surface layer 720 may be in a range from 50 nm to 2 µm, for example in a range from 100 nm to 500 nm. An average net dopant concentration in the surface layer 720 may be at most 5 × 10 17 cm -3 or a maximum of 10 17 cm -3 The surface layer 720 may contain the same dopant elements as the additional layer 710 at the same concentration, wherein the surface layer 720 may further contain p-type dopants and / or deep dopant-forming atoms, for example, vanadium (V) and / or titanium (Ti). At least a portion of the additional layer 710 and a portion of the surface layer 720 are rendered porous by anodic dissolution and converted into a porous structure 820.

[0078] For example, the semiconductor substrate is electrochemically etched in hydrofluoric acid (HF) under conditions that lead to local anisotropic dissolution of the semiconductor material by anodic dissolution. After an initial formation of pits at the side of surface defects, pores can propagate from the pits along crystal axes and / or current filaments. The formation of porosity occurs predominantly at an interface between the continuously formed porous layer and the underlying semiconductor material. In this way, a porous layer is formed, originating from the first main surface 701, which increases in thickness as the etching progresses.

[0079] Fig. Figure 1B shows the porous structure 820 resulting from the additional layer 710 and the surface layer 720 of Fig. 1A porous. The porous structure 820 comprises a layer formed from the additional layer 710 of Fig. 1A formed, coarse-porous layered region 821 and one from the surface layer 720 of Fig. 1A. Due to the lower dopant concentration in the surface layer 720, the anodic dissolution forms fewer and / or smaller pores in the surface layer 720 than in the additional layer 710. The total porosity of the coarsely porous layered region 821 is significantly larger than the total porosity of the finely porous region 824.

[0080] The formation of porosity does not necessarily stop at a junction between the additional layer 710 and the base region 705. For example, only a horizontal layer region of the additional layer 710 may be made porous, whereby the porosity formation process does not reach the base region 705. Alternatively, in addition to the additional layer 710, a horizontal layer region of the base region 705 may be made porous, whereby the porous horizontal layer region of the base region 705 is in direct contact with the porous additional layer 710. An epitaxial layer 730 is formed on the porous structure 820. Forming the epitaxial layer 730 may include CVD (chemical vapor deposition).

[0081] Fig. Figure 1C shows a wafer composite structure 900 comprising epitaxial layer 730, porous structure 820, and base region 705. Epitaxial layer 730 is formed directly on fine-pored region 824. Due to the small cross-sectional area and / or low density of pores in fine-pored region 824, epitaxial layer 730 can grow with high crystal quality and a comparatively low lattice defect density. Fine-pored region 824 is sufficiently thick to form a continuous, thermally stable, and solid seed layer during epitaxy.

[0082] Semiconducting regions of semiconductor devices can be formed in the epitaxial layer 730. For example, doped regions of a power semiconductor diode or a power semiconductor switch can be formed in the epitaxial layer 730. In this context, a power semiconductor device or a power switch is an electronic device that can continuously conduct a load current of at least 0.5 A (e.g., at least 5 A) and can permanently block voltages of at least 100 V, in particular at least 600 V.

[0083] The porous structure 820 can then be separated horizontally, for example by applying a shear force, whereby the epitaxial layer 700 is separated from the base region 705.

[0084] Fig. 1D shows a separation from the base region 705 of Fig. 1C. The epitaxial wafer 910 comprises the epitaxial layer 730 and porous residues 829 of the porous structure 820 of Fig. 1C. The porous residues 829 may be completely or partially removed or may become part of semiconductor dies obtained from the epitaxial wafer 910 by dicing.

[0085] The surface of the base area 805 of Fig. 1C can be polished, lapped, and / or ground after separation to partially or completely remove remnants of the porous structure 820. New additional and surface layers can be formed in the base region 805, whereby the base region 805 can be used multiple times as a donor substrate.

[0086] Fig. 2A to 5C illustrate various masks 410 for laterally restricting the formation of porosity of a portion of a semiconductor substrate 700 in a region directly below a first main surface 701.

[0087] Fig. Figure 2A shows a semiconductor substrate 700 with a lightly doped surface layer 720 between the first main surface 701 and a more heavily doped additional layer 710 as described above. The semiconductor substrate 700 may be a silicon carbide substrate.

[0088] A mask 410 with mask openings 415 covers regions of the first main surface 701. The mask openings 415 may be stripes with a horizontal longitudinal axis orthogonal to the cross-sectional plane or may be point-shaped with an approximately circular or approximately polygonal horizontal cross-section. A width w0 or a diameter of the mask openings 415 may be in a range from 50 nm to 200 nm, for example, approximately 100 nm. A center-to-center distance p0 between adjacent mask openings 415 may be in a range from 0.2 µm to 10 µm, for example, from 2 µm to 6 µm.

[0089] The mask openings 415 may be evenly distributed across the main surface 701. Alternatively, the mask openings may be formed predominantly or exclusively in a kerf region, wherein the kerf region laterally separates productive chip regions from which semiconductor dies can be obtained by wafer dicing. The mask material may be, for example, silicon nitride.

[0090] The additional layer 710 and regions of the surface layer 720 are made porous by anodic dissolution in hydrofluoric acid, wherein the mask 410 covers regions of the first main surface 701 during electrochemical etching.

[0091] Fig. Figure 2B shows that the porous additional layer 710 forms a coarsely porous layered region 821 and that the porous regions of the surface layer 720 of Fig. 2A form finely porous columnar regions 825 extending between the first main surface 701 and the coarsely porous layered region 821 below the mask openings 415. The mask 410 shields regions of the surface layer 720 covered by the mask 410 from the electrolyte such that non-porous regions of the surface layer 720 are Fig. 2A form non-porous regions 830 between the finely porous columnar regions 825.

[0092] The mask 410 can be removed, and a CVD process can form an epitaxial layer 730 on the first main surface 701. At the beginning of the deposition process, the non-porous regions 830 and the finely porous columnar regions 824 form a sufficiently thick and stable seed layer, enabling the growth of an epitaxial layer 730 with a low defect density.

[0093] Fig. Figure 2C shows a wafer composite structure 900 comprising the epitaxial layer 730, the porous structure 820, and the base region 805. The porous structure 820 includes a coarsely porous layered region 821 and finely porous columnar regions 825 extending from the layered region 821 to the epitaxial layer 730. Non-porous regions 830 lie laterally between the columnar regions 825. The coarsely porous lateral regions 821 and the finely porous columnar regions 825 have different net dopant concentrations.

[0094] In a later phase, the epitaxial layer 730 may be separated from the base region 705 along the porous structure 820, for example by separating along a horizontal separation plane through the coarsely porous layered region 821.

[0095] Fig. 3A to 3C show a method for controlling a position and a lateral extent of the finely porous columnar regions 825 in a lightly doped surface layer 720 by forming pits 724 in the first main surface 701.

[0096] Fig. 3A shows a mask formed on the first main surface 701. Mask openings 415 in the mask 410 may have the same width and center-to-center spacing as in the mask 410 of Fig. 2A. The material of the mask 410 in Fig. 3A is not necessarily selected so that it is not consumed during an anodic etching. For example, the mask 410 of Fig. 3A may be based on a resist material. The mask 410 masks an etching of the semiconductor substrate 700. The etching may be a wet etch or an anisotropic etch, e.g., RIE (reactive ion etching). The etching forms pits 724 in the first main surface 701. A third vertical extension v3 of the pits 724 may be in a range from 0.1 µm to 5 µm, for example, from 0.5 µm to 1 µm.

[0097] The mask 410 can be removed. The additional layer 710 and regions of the surface layer 720 can be made porous by anodic dissolution. Since the electrical resistance of the surface layer 720 is lower in sections below the pits 724 than between the pits 724, an electric field and current density below the pits 724 are higher. The formation of porosity in the surface layer 720 begins predominantly at the bottom of the pits 724 and progresses from the pits 724 toward the second main surface 702.

[0098] As in Fig. 3B, the resulting porous structure 820 comprises a coarsely porous layered region 821 consisting of the additional layer 710 of Fig. 3A, and includes finely porous columnar regions 825 extending from the pits 724 to the coarsely porous layered region 821. Non-porous regions 830 are formed laterally between the columnar regions 825. A CVD process may form an epitaxial layer 730 on the first main surface 701.

[0099] Fig. 3C shows a wafer composite structure 900 with a porous structure 820 of Fig. 3B. Later, the epitaxial layer 730 can be separated from the base region 705 along a horizontal separation plane through the porous structure 820.

[0100] In Fig. 4A to 4C, a mask 410 exposes first portions 711 of the first main surface 701. Mask openings 415 in the mask 410 may have the same width and center-to-center spacing as in the mask 410 of Fig. 2A. Dopants are implanted through the mask openings 415.

[0101] The implanted dopants may form additional regions 725 directly below the mask openings 415. A fourth vertical extent v4 of the additional regions 725 may be smaller than, equal to, or larger than the second vertical extent v2 of the surface layer 720. The additional regions 725 may have a higher electrochemical dissolution efficiency than masked regions 726 of the surface layer 720 and a lower electrochemical dissolution efficiency than the additional layer 710. For example, the net dopant concentration in the additional regions 725 may be higher than, e.g., at least twice as high as, in the masked regions 726 and lower than in the additional layer 710.

[0102] The mask 410 may be removed, and the additional layer 710 and the additional regions 725 may be made porous by anodic dissolution.

[0103] Fig. Figure 4B shows a porous structure 820 comprising a coarsely porous layered region 821 consisting of the additional layer 710 of Fig. 4A, and comprises columnar areas 825, which consist mainly of the additional areas 725 of Fig. 4A. A CVD process may form an epitaxial layer 730 on the first main surface 701.

[0104] Fig. 4C shows a wafer composite structure 900 with the porous structure 820 of Fig. 4B. Later, the epitaxial layer 730 can be separated from the base region 705 along a horizontal separation plane through the porous structure 820.

[0105] Fig. 5A to 5C refer to an embodiment with an additional layer 710 extending from the first main surface 701 to the base region 705.

[0106] Fig. 5A shows a mask 410 as described above for forming pits 724 in the first main surface 701. The mask 410 is removed, and the additional layer 710 is rendered porous by anodic dissolution.

[0107] According to Fig. 5B, the additional layer 710 of Fig. 5A into a porous structure 820 having a coarsely porous layered region 821 and finely porous columnar regions 825 extending from the pits 724 to the layered region 821. An epitaxial layer 730 is formed on the first main surface 701.

[0108] Fig. 5C shows a wafer composite structure 900 with the porous structure 820 of Fig. 5B. The columnar regions 825 and the non-porous regions 830 formed between the columnar regions 825 may have the same dopant concentration as the layered region 821.

[0109] The method can be used on semiconductor substrates 700 made of semiconductor materials that form self-ordered nanopores in a thin skin layer along the first main surface 701 during electrochemical dissolution, for example for a silicon carbide-based semiconductor substrate 700.

[0110] Fig. 6 and Fig. 7 show wafer composite structures 900 with porous structures 820 extending horizontally through a complete cross section of the wafer composite structure 900.

[0111] Each wafer composite structure 900 includes a base region 705, a porous structure 820 formed on the base region 705, and an epitaxial layer 730 formed on the porous structure 820.

[0112] The material of the base region 705 may be a first semiconducting material, for example, an elemental semiconductor or a compound semiconductor, for example, a IV / IV compound semiconductor material. A fifth vertical extension v5 of the base region 705 may be in the range of several hundred µm to several mm.

[0113] The porous structure 820 may comprise a fine-porous region 824 and a coarse-porous layered region 821. A sixth vertical extent v6 of the porous structure 820 may be in the same range as the sum of the first vertical extent v1 and the second vertical extent v2 in Fig. 1A.

[0114] At least the layered region 821 extends laterally over the entire horizontal cross-sectional area of ​​the wafer composite structure 900. The porosity in the coarsely porous layered region 821 can be in a range from 30% to 80%, for example from 40% to 60%.

[0115] Apart from the pores, the crystal lattice of the semiconductor material in the layered region 821 forms a single-crystalline lattice skeleton.

[0116] For example, the porous structure 820 is based on silicon carbide, and a minimum dopant concentration in the coarsely porous layered region 821 is greater than 5 × 10 18 cm -3 , for example at least 5 × 10 19 cm -3 , for example about 10 20 cm -3 or higher. A vertical dimension of the coarse-porous layered region 821 can, for example, be in a range of 1 µm to 10 µm.

[0117] The fine-porous region 824 has a porosity of at most 50%, for example, a porosity of at most 20%, of the coarse-porous layered region 821. For example, in the fine-porous region 824, the pores can have an average diameter of at most 50 nm, e.g., less than 40 nm. The porosity of the fine-porous region 824 is, for example, less than 20%, for example, less than 10%. A vertical extent of the fine-porous region 824 can, for example, be in a range from 100 nm to 500 nm.

[0118] A dopant concentration in the fine-porous region 824 may be equal to or lower than that in the layered region 821. For example, an average net dopant concentration in the layered region 821 is at least 100 times the average net dopant concentration in the fine-porous region 824. For example, the porous structure 820 is based on silicon carbide, and the dopant concentration in the fine-porous region 824 may be at most 5 × 10 17 cm -3 be.

[0119] The epitaxial layer 730 may have a seventh vertical extent v7 in a range from 5 µm to several hundred µm. The epitaxial layer 730 may be uniformly doped or may contain semiconducting regions for a variety of semiconductor devices.

[0120] The epitaxial layer 730 may be made of the same material as the base region 705 or of a different material with a similar lattice constant. For example, the base region 705 may be a SiC crystal, and the epitaxial layer 730 may contain, for example, silicon carbide or gallium nitride. In some embodiments, the base region 705 may be a silicon crystal, and the epitaxial layer 730 may be a gallium nitride layer.

[0121] In Fig. 6, the finely porous region 824 is a horizontal layer extending with a uniform thickness through a complete horizontal cross-section of the wafer composite structure 900. The pores may be distributed more or less evenly.

[0122] In Fig. 7, the finely porous region 824 includes a plurality of laterally separated columnar regions 825, with non-porous regions 830 formed laterally between the columnar regions 825.

[0123] The procedure as it is with any of the Fig. 1A-1D, 2A-2C, 3A-3C, 4A-4C and 5A-5C may be used to form any of the wafer composite structures 900 as described with reference to Fig. 6 and Fig. 7. Each of the methods described with reference to Fig. 6 and Fig. 7 may be formed during any of the processes described with reference to Fig. 1A - 1D, 2A - 2C, 3A - 3C, 4A - 4C and 5A - 5C.

[0124] Fig. 8A to 9B illustrate semiconductor devices 500 that include porous regions 180 near the back surface.

[0125] The semiconductor may be single-crystal silicon carbide, e.g., 4H-SiC (4H-polytype SiC), 2H-SiC, or 6H-SiC. The silicon carbide crystal may contain undesirable impurities such as hydrogen, oxygen, and / or fluorine, and may also contain intended impurities, e.g., dopant atoms. A first surface 101 of the semiconductor body 100 on the front side is parallel to an opposite second surface 102 on the back side.

[0126] A drift structure 130 directly adjoins the second surface 102. The drift structure 130 may comprise a lightly doped drift zone 131 and a highly doped contact region 139 (e.g., a drain layer) between the drift zone 131 and the second surface 102. The contact region 139 may have the same conductivity type as the drift zone 131, the opposite conductivity type, or may contain doped regions of both conductivity types. The doped contact region 139 (e.g., embodied as a drain layer therein) may have a vertical extent of at least 3 µm (e.g., at least 10 µm) to at most 100 µm (e.g., at most 50 µm). The doped contact region 139 may mechanically stabilize the separated wafer.

[0127] The drift structure 130 may be electrically connected or coupled to a backside metallization 320. For example, a dopant concentration in the contact region 139 along the second surface 102 is sufficiently high to form a low-resistance ohmic contact between the backside metallization 320 and the drift structure 130. If the porous structure on the wafer backside is not completely removed, a lower doping concentration (which may result in good backside contact between a contact region and a metallization) may be enabled.

[0128] The drift structure 130 may include further doped regions between the drift zone 131 and the second surface 102, for example, a buffer or field stop layer 138 between the drift zone 131 and the contact region 139. A termination structure may be formed between a central region of the semiconductor body 100 and a lateral surface 103 of the semiconductor body 100.

[0129] In Fig. 8A and Fig. 8B, the semiconductor device 500 is a power semiconductor diode having an anode region 122 formed in the central region at the front side of the semiconductor body 100. The anode region 122 and the drift structure 130, e.g., the anode region 122 and the drift zone 131, form a main pn junction pnx. The main pn junction pnx may include a main portion substantially parallel to the first surface 101. A front-side electrode 310 and the anode region 122 may form a low-resistance ohmic contact. The front-side electrode 310 may form an anode terminal A or may be electrically connected or coupled to such an anode terminal. A dielectric layer 210 may cover sidewalls of the front-side metallization 310. A rear metallization 320 may form a cathode terminal K of the semiconductor diode or is electrically connected or coupled to such a terminal.

[0130] Fig. 9A and Fig. 9B show a semiconductor device 500 containing transistor cells TC in the central region. The semiconductor device 500 may be, for example, an IGFET (insulated gate field effect transistor), for example a MOSFET (metal oxide semiconductor FET) in the usual sense, including FETs with metal gates as well as FETs with gates made of highly doped semiconductor material, an MCD (MOS controlled diode), or an IGBT (insulated gate bipolar transistor). In each transistor cell TC, a body region 125 separates a source region from the drift structure 130. The body regions 125 and the drift structure 130, e.g., the body regions 125 and the drift zone 131, form first transistor pn junctions pn1. The body regions 125 and source regions of the transistor cells TC form second transistor pn junctions.

[0131] A front-side electrode 310, which is electrically connected to the body regions 125 and the source regions, may form a first load terminal L1, or may be electrically connected or coupled to one that may be an anode terminal of an MCD, a source terminal of an IGFET, or an emitter terminal of an IGBT. The back-side metallization 320 forms a second load electrode electrically connected to the contact region 139, wherein the second load electrode may form a second load terminal L2, or may be electrically connected or coupled to one that may be a cathode terminal of an MCD, a drain terminal of an IGFET, or a collector terminal of an IGBT.

[0132] The transistor cells TC may be transistor cells with gate electrodes 155 electrically connected to a gate terminal G. The gate electrodes 155 may be planar gate electrodes or trench gate electrodes, where trench gate electrodes may control a lateral channel or a vertical channel. According to one embodiment, the transistor cells TC are n-channel FET cells with p-doped body regions 125, n-doped source zones, and an n-doped drift zone 131.

[0133] In the semiconductor devices 500 of the Fig. 8A to 9B, the semiconductor body 100 includes a porous region 180 that may be in contact with (e.g., comprise or be part of) the second surface 102. The porous region 180 comprises a coarse-pored layer region 181 and a fine-pored region 184. The fine-pored region 184 may be a layer of uniform thickness or may comprise a plurality of laterally separated pillar regions 185 extending from the layer region 181 toward the first surface 101. The porous region 180 may overlap exclusively with the contact region 139, may further overlap with the buffer or field stop layer 138 or with a drain layer, or may even overlap with the drift zone 131.

[0134] An eighth vertical extension v8 of the layer region 181 can be in a range from 100 nm to 10 µm, for example, from 500 nm to 5 µm. A ninth vertical extension v9 of the column regions 185 can be in a range from 100 nm to 500 nm. An average center-to-center distance p9 between adjacent column regions 185 can be in a range from 200 nm to 5 µm. A horizontal width w9 of the column regions 185 can be in a range from 100 nm to 2 µm. Non-porous sections 190, which can be strip-shaped or form a lattice, can laterally separate the column regions 185.

[0135] The porosity of the column regions 185 may differ from the porosity of the layer region 181. For example, the total porosity and / or the average pore size in the column regions 185 are / is lower than in the layer region 181. The column regions 185 may be finely porous. The layer region 181 may be coarsely porous.

[0136] The porous region 180 can reduce mechanical stress between the backside metallization 320 and the drift zone 131, can reduce the contact resistance between a contact zone and the backside metallization, and / or can provide getter sites for impurities, e.g., metal atoms, and / or can be used to tune device parameters such as short-circuit robustness. Alternatively or additionally, the pillar regions 185 can locally increase a charge carrier recombination rate to improve switching characteristics of the semiconductor device 500.

[0137] The procedure as it is with any of the Fig. 1A-1D, 2A-2C, 3A-3C, 4A-4C and 5A-5C may be used to form any of the semiconductor devices 500 as described with reference to Fig. 8A - 8B and 9A - 9B. Each of the embodiments described with reference to Fig. 8A - 8B and 9A - 9B can be obtained by any of the methods described with reference to the Fig. 1A - 1D, 2A - 2C, 3A - 3C, 4A - 4C and 5A - 5C.

Claims

[1] A method of manufacturing a semiconductor device, comprising: Providing a semiconductor substrate (700) having a base region (705), an additional layer (710) on the base region (705) and a surface layer (720) on the additional layer (710), wherein the surface layer (720) is in contact with a first main surface (701) of the semiconductor substrate (700) and wherein the additional layer (710) has a different electrochemical dissolution efficiency than the base region (705) and the surface layer (720); Forming a mask (410) on the first main surface (701), wherein mask openings (415) in the mask (410) expose first portions (721) of the surface layer (720); Converting at least one horizontal layer region of the additional layer (710) and the first sections (721) of the surface layer (720) into a porous structure (820), wherein the horizontal layer region of the additional layer (710) directly adjoins the surface layer (720) and wherein non-porosified sections are located laterally between the porosified first sections (721); and Forming, after converting, an epitaxial layer (730) on the first main surface (701). [2] Method according to the preceding claim, further comprising: Separating the epitaxial layer (730) from the base region (705) along the porous structure (820). [3] Method according to one of the two preceding claims, wherein the epitaxial layer (730) and the semiconductor substrate (700) differ in at least one main component. [4] Method according to one of the three preceding claims, wherein the semiconductor substrate (700) is a silicon carbide substrate. [5] Method according to one of the four preceding claims, further comprising: Deepening, prior to converting, the first sections (721) to form pits (724) in the first main surface (701). [6] Method according to one of the five preceding claims, further comprising: Implanting, before converting the additional layer (710), dopants into the first sections (721). [7] A method of manufacturing a semiconductor device, comprising: Providing a semiconductor substrate (700) having a first surface (701), wherein the semiconductor substrate (700) has a base region (705) and an additional layer (710) formed on the base region (705) between the first surface (701) and the base region (705); Forming pits (724) extending from the first surface into the additional layer (710); Converting at least a portion of the additional layer (710) into a porous structure (820), wherein the porous structure (820) has a layered portion (821) and laterally separated columnar portions (825), wherein the layered portion (821) is formed at a distance from the first main surface (701), wherein the columnar portions (825) extend from the pits (724) to the layered portion (821), and wherein non-porosified portions of the additional layer (710) are formed laterally between the columnar portions (825). [8] Method according to the preceding claim, further comprising: Forming, after converting, an epitaxial layer (730) on the first main surface (701); and Separating the epitaxial layer (730) along the layered region (821) from the base region (705). [9] Wafer composite structure, comprising: a base area (705); a porous structure (820) having a coarse-porous layered region (821) formed on the base region (705) and a fine-porous region (824) formed on the coarse-porous layered region (821); and an epitaxial layer (730) formed on the finely porous region (824), wherein the fine porous region (824) has laterally separated columnar regions (825) projecting from the coarse porous layered region (821), and wherein non-porous regions (830) are formed laterally between the columnar regions (825). [10] A wafer composite structure according to the preceding claim, wherein the coarsely porous layered region (821) comprises a compound semiconductor. [11] A semiconductor device comprising: a semiconductor body (100) having a drift structure (130), a fine-pored region (184) and a coarse-pored layer region (181), wherein the fine-pored region (184) is formed between a first surface (101) of the semiconductor body (100) and the coarse-pored layer region (181), and wherein the coarse-pored layer region (181) is in direct contact with a second surface (102) of the semiconductor body (100) opposite the first surface (101), wherein the fine-pored region (184) has laterally separated columnar regions (185) projecting from the coarse-pored layer region (181), and wherein non-porous regions (190) are formed laterally between the columnar regions (185). [12] A semiconductor device according to the preceding claim, further comprising: a backside metallization (320) in direct contact with the coarse-pored layer area (181). [13] A semiconductor device according to any one of the two preceding claims, wherein the coarse-pore layer region (181) comprises a compound semiconductor.

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