Semiconductor device including a distributed writer arrangement and method for operating the same.

Abstract

Semiconductor memory device comprising: an LWF leadership (234(j), 234(j+n), 334(j), 434(j), 534(j)); a LWB_bar line (336(j), 436(j), 536(j)) ; a GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)); a GWB bar line (322(j), 332(j), 432(j), 532(j)); a column (207(j), 207(j+n), 307(j), 407(j), 507A(j), 507B(j), 507C(j)) of segments (202A, 202B, 302A, 402A, 502A, 502A''), each segment (202A, 202B, 302A, 402A, 502A, 502A'') bit cells (212A(i,j), 212A(i+m,j+n), 212B(i,j), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)); wherein each of the bit cells (212A(i,j), 212A(i+m,j+n), 212B(ij), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)) comprises a latch circuit (311, 315) and a first and second pass gate (N03, N04; N09, N10) which connect the corresponding LWB and LWB_bar line (234(j), 234(j+n), 334(j), 434(j), 5340); 336(j), 436(j), 536(j)) to the latch circuit (311, 315); and a distributed write driver arrangement comprising a global write driver (224(j), 224(j+n)) and a local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)): where the global write driver (224(j), 224(j+n)) has: a first inverter (340, 440, 540) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)); and a second inverter (342, 442, 542) connected between the GWB_bar line (3220, 3320), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and wherein the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is included in each segment (202A, 202B, 302A, 402A, 502A, 502A''), wherein each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is located in an interior of the corresponding segment (202A, 202B, 302A, 402A, 502A, 502A''), wherein each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) comprises: a third inverter (344, 444, 544) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 4340), 534(j); and a fourth inverter (346, 446, 546) connected between the GWB_bar line (322(j), 332(j), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)).

Description

GENERAL STATE OF THE ART

[0001] In a typical memory system, memory cells are arranged in an array. Each memory cell (also called a cell) stores a piece of data representing a bit. Each cell is located at the intersection of a row and a column. Accordingly, a particular cell is accessed by selecting the row and column that intersect at the particular cell. Each of the cells in a column is connected to a bit line. An input / output (I / O) circuit uses the bit line to read or write information to a selected one of the bit cells in the column. Semiconductor memory devices are known from US 2007 / 0237020 A1, US 5,729,501, and US 5,570,319.

[0002] Typically, there are many cells in a column. Due to varying physical distances between the I / O circuitry and the cells, the bit line presents a different resistive and / or capacitive load for each of the cells in the column. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which elements having the same reference numerals represent like elements throughout. The drawings are not to scale unless otherwise stated. Fig. 1 is a block diagram of a semiconductor device according to some embodiments. Fig. 2 is a block diagram of an array and column driver portion including a distributed write driver arrangement, according to at least one embodiment of the present disclosure. Fig. 3 is a circuit diagram of an array and column driver portion including a distributed write driver arrangement, according to at least one embodiment of the present disclosure. Fig. 4A-4C are respective circuit diagrams of an array and column driver portion including a distributed write driver arrangement, in accordance with at least one embodiment of the present disclosure. Fig. 5A-5C are respective circuit diagrams of array and column driver regions, each including a distributed write driver arrangement, according to respective embodiments of the present disclosure. Fig. 6 is a cross-section of an array and column driver region 600 including a distributed write driver arrangement, according to at least one embodiment of the present disclosure. Fig. 7 is a flowchart of a method 700 for write driving a column in an array and column driver portion of an SRAM macro on a distributed basis, according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are contemplated. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Additionally, the present disclosure may repeat reference numerals and / or letters throughout the various examples. This repetition is for simplicity and clarity and does not, in itself, imply any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially related terms such as "underlying," "beneath," "lower," "above," "upper," and the like may be used herein for convenience in describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or with other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0006] In some embodiments, a distributed write driver arrangement is provided for SRAM bit cells having separate write and read ports. More specifically, such a distributed write driver arrangement comprises: a global write driver; and, in each segment of bit cells, a local write driver. The global write driver comprises: a first inverter connected between a global write bit (GWB) line and a local write bit (LWB) line; and a second inverter connected between a global write bit_bar (GWB_bar) line and a local write bit_bar (LWB_bar) line. Each local write driver comprises: a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar_line.In some embodiments, a distributed write driver arrangement having each local write driver located in the corresponding segment of bit cells has the advantage of mitigating a problem of resistive and / or capacitive loading of the LWB line and the LWB_bar line. In some embodiments, each local write driver is located in a first device layer and the global write driver is located in a second device layer above the first device layer, which provides the advantage that the global write driver is more easily configured for high speed and a large footprint than a circumstance in which the global write driver is located in the first device layer.

[0007] Fig. 1 is a block diagram of a semiconductor device 100 according to at least one embodiment of the present disclosure.

[0008] In Fig. 1, the semiconductor device 100 includes, among other things, a circuit macro (hereinafter macro) 102. In some embodiments, the macro 102 is an SRAM macro. In some embodiments, the macro 102 is a macro other than an SRAM macro. The macro 102 includes, among other things, one or more array and column driver regions 104, each comprising a distributed write driver arrangement. An example of region 104 is the array and column driver region 200 of Fig. 2.

[0009] Fig. 2 is a block diagram of the array and column driver portion 200, which includes a distributed write driver arrangement, according to at least one embodiment of the present disclosure. The portion 200 of Fig. 2 is an example of the area 104 of Fig. 1.

[0010] In Fig. 2, the area 200 is organized in columns, with columns 207(j) to 207(j+n) in Fig. 2, where j and n are integers, j ≥ 0, n ≥ 1, and j indicates a column number. Area 200 includes segments 202A and 202B, a global driver (g-drv) block 204, and a control block 206.

[0011] Segment 202A includes a block 210A; a segment driver (s-drv) block 218A; and a block 214A. Segment 202B includes a block 210B; an s-drv block 218B; and a block 214B.

[0012] Block 210A is organized as a two-dimensional array of rows and columns, the array comprising bit cells 212A(i,j) through 212A(i+m,j+n), where i and m are integers, i ≥ 0, m ≥ 1, and i indicates a row number. The bit cells, e.g., bit cell 212A(i,j), are described in more detail in Fig. 3 (discussed below). For example, bit cells 212A(i,j) through 212A(i+m,j) are located in column 207(j). Block 214A is organized as a two-dimensional array including bit cells 216A(i,j) through 216A(i+m,j+n). Block 210B is organized as a two-dimensional array including bit cells 212B(i,j) through 212B(i+m,j+n). Block 214B is organized as a two-dimensional array including bit cells 216B(i,j) through 216B(i+m,j+n).

[0013] The s-drv block 218A includes the local write drivers 220A(j) through 220A(j+n), referred to as segment column (s-col) drivers 220A(j) through 220A(j+n). The s-col drivers, e.g., the s-col driver 220A(j), are described in more detail in Fig. 3 (discussed below). For example, the s-col driver 220A(j) is located in column 207(j). The s-drv block 218B includes the local write drivers 220B(j) through 220B(j+n), referred to as s-col drivers 220B(j) through 220B(j+n).

[0014] The global driver (g-drv) block 204 includes the global write drivers 224(j) through 224(j+n), referred to as global column (g-col) drivers 224(j) through 224(j+n). The g-col drivers, e.g., the g-col driver 224(j), are described in more detail in Fig. 3 (discussed below). For example, the g-col driver 224(j) is located in column 2070.

[0015] In Fig. 2, the region 200 is considered to comprise a distributed write driver arrangement since the region 200 comprises the global driver (g-drv) block 204 and the s-drv blocks 218A-218B (the latter being included in the segments 202A-202B, respectively).

[0016] The control block 206 includes column driver (c-drv) controllers 226(j) through 226(j+n). The controllers, e.g., the c-drv controller 226(j), are described in more detail in Fig. 3 (discussed below). For example, c-drv control unit 226(j) is located in column 207(j). The c-drv control units 226(j)-226(j+n) provide corresponding write control signals (see Fig. 3, (discussed below).

[0017] The area 200 further includes: global write bit (GWB) lines 230(j) to 230(j+n); corresponding global write bit_bar (GWB_bar) lines (not shown, but see Fig. 3, as discussed below); local write bit (LWB) lines 234(j) to 234(j+n); and corresponding local write bit_bar (LWB_bar) lines (not shown, but see Fig. 3, discussed below).

[0018] In the area 200 of Fig. 2, the GWB line 230(j) is connected to each of the s-col driver 220A(j), the s-col driver 220B(j), and the g-col driver 224(j). The GWB line 230(j+n) is connected to each of the s-col driver 220A(j+n), the s-col driver 220B(j+n), the g-col driver 224(j+n), and the like. The LWB line 234(j) is connected to the bit cells 212A(ij)-212A(i+mj), the s-col driver 220A(j), the bit cells 216A(i,j)-216A(i+m,j), the bit cells 212B(i,j)-212B(i+m,j), the s-col driver 220B(j), the bit cells 216B(i,j)-216B(i+m,j), and the g-col driver 224(j), respectively. The LWB line 234(j+n) is connected to the bit cells 212A(i,j+n)-212A(i+m,+j+n), the s-col driver 220A(j+n), the bit cells 216A(i,j+n)-216A(i+m,j+n), the bit cells 212B(i,+j+n)-212B(i+m,j+n), the s-col driver 220B(j+n), the bit cells 216B(i,j+n)-216B(i+m,j+n), and the g-col driver 224(j+n), and the like, respectively.

[0019] For the sake of simplicity, the range 200 of Fig. 2 with two segments, 202A-202B. In some embodiments, additional segments are included in the region 200. Also for ease of illustration, each of the segments 202A-202B has been shown with an s-drv block, namely the corresponding s-drv blocks 218A-218B, such that an intra-segment ratio of the blocks of cells (bcell) to the s-drv blocks (bsdrv) is bcell:bsdrv = 2:1. Other ratios are within the scope of the disclosure. In some embodiments, intra-segment ratios bcell_bsdrv have values ​​other than bcell:bsdrv = 2:1.

[0020] Fig. 3 is a circuit diagram 300 of an array and column driver portion including a distributed write driver arrangement, according to at least one embodiment of the present disclosure.

[0021] The circuit diagram 300 is an exemplary implementation of the array and column driver section 200 of Fig. 2. Therefore, the circuit diagram 300 is an example of the area 104 of Fig. 1.

[0022] Although the circuit diagram 300 of Fig. 3 in some respects more detailed than the block diagram of area 200 of Fig. 2, e.g., because the circuit diagram depicts transistors, inverters, NOR gates, a GWB_bar line 322(j); an LWB_bar line 336(j), or the like, the circuit diagram also depicts a simplification of the block diagram of region 300. For ease of illustration, the simplifications in circuit diagram 300 include: one column 307(j) instead of multiple columns corresponding to all columns 207(j)-207(j+n) of region 200; one segment 302A instead of two segments corresponding to segments 202A-202B in region 200; one bit cell 312A(i,j) in block 310A instead of multiple bit cells corresponding to all bit cells 212A(i,j)-212A(i+m,j+n) in block 210A of segment 202A of region 200; one s-col driver 320A(j) instead of multiple s-col drivers corresponding to s-col drivers 220A(j)-220A(j+n) in s-drv block 218A in region 200;a bit cell 316A(i+m,j) in block 310B instead of a plurality of bit cells corresponding to all bit cells 216A(i,j)-216A(i+m,j+n) in block 214A of segment 202A of region 200; a g-col driver 324(j) instead of a plurality of g-col drivers corresponding to g-col drivers 224(j)-224(j+n) in region 200; a c-drv controller 326(j) instead of a plurality of c-drv controllers corresponding to c-drv controllers 226(j)-226(j+n) in region 200; the GWB line 330(j) instead of a plurality of GWB lines corresponding to the GWB lines 230(j)-230(j+n) in the area 200; and the LWB line 334(j) instead of a plurality of LWB lines corresponding to the LWB lines 234(j)-234(j+n) in the area 200.

[0023] In Fig. 3, bitcells 312A(i,j) and 316A(i+m,j) are 8-transistor (8T) dual-port SRAM bitcells, where one port represents a write port and one port represents a read port. Other bitcell configurations are within the scope of the disclosure. In some embodiments, bitcells 312A(i,j) and 316A(i+m,j) are multi-port SRAM bitcells, which are different from dual-port SRAM bitcells. In some embodiments, bitcells 312A(i,j) and 316A(i+m,j) are implemented with a number of transistors other than 8 transistors.

[0024] In circuit diagram 300, bit cell 312A(i,j) includes PMOS transistors P01-P02 and NMOS transistors N01-N06. Transistors P01-P02 and N01-N02 are configured as an SRAM latch 311. Transistors N03 and N04 represent switches (referred to as pass gates) that selectively connect node 303A and node_bar 303B of latch 311 to the corresponding LWB line 334(j) and LWB_bar line 336(j). The gate electrodes of transistors N03 and N04 are connected to an i-th word write (WRD) line A (AWRD(i)). A signal on the AWRD(i) is used to select when transistors N03 and N04 are off / on, and thereby select when node 303A and node_bar303B of latch 311 are connected to the corresponding LWB line 334(j) and LWB_bar line 336(j).

[0025] Specifically, with respect to latch 311, transistors P01 and N01 are connected in series between a first reference voltage and a second reference voltage. In some embodiments, the first reference voltage is VDD. In some embodiments, the second reference voltage is VSS. The source and drain of transistor P01 are connected to VDD and node 303A, respectively. The drain and source of transistor N01 are connected to node 303A and VSS, respectively. Transistors P02 and N02 are connected in series between VDD and VSS. The source and drain of transistor P02 are connected to VDD and node_bar 303B, respectively. The drain and source of transistor N02 are connected to node_bar 303B and VSS, respectively. The gates of each of transistors P01 and N01 are connected to node_bar 303B.The gate electrodes of each of the transistors P02 and N02 are connected to the node 303A.

[0026] In circuit diagram 300, bit cell 316A(i+m,j) includes PMOS transistors P03-P04 and NMOS transistors N07-N012. Bit cell 316A(i+m,j) is similar to bit cell 312A(i,j). For brevity, the discussion of bit cell 316A(i+m,j) will focus on the differences from bit cell 312A(i,j).

[0027] In bit cell 316A(i+m,j), transistors P03-P04 and N07-N08 are configured as an SRAM latch 315. Transistors N09 and N10 represent switches (referred to as pass gates) that selectively connect nodes 305A and 305B of latch 315 to the corresponding LWB line 334(j) and LWB_bar line 336(j) under the control of a signal on line AWRD(i+m).

[0028] In Fig. 3, the g-col driver 324(j) includes inverters 340 and 342 and an equalizer 325. The inverter 340 is connected between the GWB line 330(j) at a node 360A and the LWB line 334(j) at a node 360B. The inverter 342 is connected between the GWB_bar line 332(j) at a node 362A and the LWB_bar line 336(j) at a node 362B.

[0029] Equalizer 325 is connected between LWB line 334(j) at node 360B and LWB_bar line 336(j) at node 362B. Equalizer 325 includes PMOS transistors P11 and P12 connected in series between LWB line 334(j) at node 360B and LWB_bar line 336(j) at node 362B. The source / drain electrodes of transistor P11 are connected to node 360B and a node 363. The source / drain electrodes of transistor P12 are connected to node 363 and node 362B. The gate electrodes of transistors P11 and P12 are connected to nodes 360A and 362A, respectively.

[0030] In Fig. 3, the s-col driver 320A(j) includes inverters 344 and 346 and an equalizer 321. The inverter 344 is connected between the GWB line 330(j) at a node 364A and the LWB line 334(j) at a node 364B. The inverter 346 is connected between the GWB_bar line 332(j) at a node 366A and the LWB_bar line 336(j) at a node 366B. The inverters 344 and 346 included in the s-col driver 320A(j) are accordingly physically located inside the segment 302A.

[0031] Equalizer 321 is connected between LWB line 334(j) at node 364B and LWB_bar line 336(j) at node 366B. Equalizer 321 includes PMOS transistors P13 and P14 connected in series between LWB line 334(j) at node 364B and LWB_bar line 336(j) at node 366B. The source / drain electrodes of transistor P13 are connected to node 364B and a node 365. The source / drain electrodes of transistor P14 are connected to node 365 and node 366B. The gate electrodes of transistors P13 and P14 are connected to nodes 364A and 366A, respectively.

[0032] In Fig. 3, the c-drv controller 426(i) includes a NOR gate 448 and a NOR gate 450. The outputs of the NOR gates 448-450 are connected to the corresponding nodes 360B and 362B. A first input of each of the NOR gates 448-450 is connected to a column select_bar (CS_bar) line. A second input of the NOR gate 448 is connected to a write_data (WD) line. A second input of the NOR gate 450 is connected to a write_data_bar (WD) line. By using the NOR gates 448-450, the c-drv controller 426(i) reflects an active-low configuration. In some embodiments, the c-drv controller 426(i) reflects an active-high configuration. In some embodiments in which the c-drv controller 426(i) reflects an active-high configuration, the c-drv controller 426(i) includes corresponding NAND gates instead of the NOR gates 448-450.

[0033] In the context of an array and column driver region in an SRAM device according to another approach, and particularly in the context of a column thereof, it should be noted that the other approach does not use a distributed driver arrangement, but instead uses a consolidated driver arrangement. As such, the other approach does not include a local write driver in each corresponding segment of bit cells, nor a GWB line, nor a GWB_bar line, and has a consolidated driver (not shown) instead of the g-col driver 324(j) and the c-drv controller 326(j). The problem of resistive and / or capacitive loading of the LWB line and the LWB_bar line significantly impairs the operation of the arrangement according to the other approach.

[0034] For example, according to the other approach, during a write process in which a column is selected and a segment is selected, the LWB line is precharged to a logic high value (H value). After precharging, the consolidated driver drives the LWB line with either an H value or a logic low value (L value). In a write scenario according to the other approach, in which the latch (bitcell) node initially stores the value H, so that the NMOS transistor connected to the node is turned off because the node_bar stores a corresponding L value, the latch (bitcell) node is selected to be connected to the LWB line, and the consolidated driver attempts to drive / write the LWB line with an L value. In the write scenario according to the other approach, the NMOS transistor will be turned on and attempt to pull the LWB line down from the precharge value H to the L value.The resistive and / or capacitive loading of the LWB line significantly impairs the ability of the corresponding NMOS transistor in the latch of the other approach to pull the WRB line down from the precharge value H to the value L.

[0035] In some embodiments, the distributed write driver arrangement of region 200 has the advantage of mitigating a problem of resistive and / or capacitive loading of LWB line 334(j) and LWB_bar line 336(j). In particular, inverters 344 and 346 are included in s-col driver 320A(j) and are accordingly located inside segment 302A. Inverters 344 and 346 complement the drive capability of inverters 340 and 342 of g-col driver 324(j), mitigating the problem of resistive and / or capacitive loading of LWB line 334(j) and LWB_bar line 336(j). The operation of the c-drv controller 326(j), the g-col driver 324(j), and the s-col driver 320A(j) is described below in the context of Fig. 4A-4C discussed.

[0036] The circuit diagram 300 of Fig. 3 further includes a local read bit (LRB) line 337(j), a segment read (s-read) circuit 368(j), a global read (g-read) circuit 370(j), and a global read bit (GRB) line 339(j). Also connected in bit cell 312A(i,j), transistors N05 and N06 form cell read (c-read) circuit 313.

[0037] Regarding the c-read circuit 313, transistors N05 and N06 are connected in series between a local read bit (LRB) line 337(j) and the VSS. The first and second source / drain electrodes of transistor N05 are connected to the LRB line 337(j) and a node 303C. The first and second source / drain electrodes of transistor N06 are connected to the node 303C and the VSS. The gate electrode of transistor N05 is connected to an i-th word read bit (WRB) B (BWRD(i)). A signal on the BWRD(i) is used to select when transistor N05 is off / on, and thereby select when node 303C of latch 311 is connected to the LRB line 337(j). The gate electrode of transistor N06 is connected to the node_bar 303B of the latch 311.

[0038] In some embodiments, during a read process in which column 307(j) is selected and segment 302A is selected, LRB line 337(j) is precharged to a logic high value (H value). After precharging, LRB line 337(j) is connected to GRB line 339(j) through s-read circuit 368(j) and g-read circuit 370(j). Also after precharging, the signal on BWRD(i) line is used to turn on transistor N05. In a first read scenario, in which node 303A of latch 311 stores a logic low value (L value) and node_bar 303B of latch 311 correspondingly stores a H value, the H value on node_bar 303B will turn on transistor N06.Accordingly, in the first read scenario, transistors N05 and N06 together connect LRB line 337(j) to VSS, causing LRB line 337(j) to assume a value of L, which reflects the value L stored at node 303A of latch 311. In a second read scenario, in which node 303A of latch 311 stores a value of H and node_bar 303B of latch 311 correspondingly stores a value of L, the value L on node_bar 303B will turn off transistor N06. Accordingly, in the second read scenario, transistor N06 prevents LRB line 337(j) from being connected to VSS, resulting in LRB line 337(j) maintaining the value H, which reflects the value H stored at node 303A of latch 311.

[0039] Also in bit cell 316A(i+m,j), transistors N11 and N12 are connected as c-read circuit 317. C-read circuit 317 is similar to c-read circuit 313. For brevity, the discussion of c-read circuit 317 will focus on the differences with respect to c-read circuit 313.

[0040] Regarding the c-read circuit 313, the first and second source / drain electrodes of transistor N11 are connected to the LRB line 337(j) and a node 305C. The first and second source / drain electrodes of transistor N12 are connected to the node 305C and the VSS. Transistor N11 selectively connects the LRB line 337(j) to the node 305C under the control of a signal on the BWRD(i+m) line. Transistor N12 selectively connects the node 305C to the VSS under the control of a logic value (L or H) stored at the node 305B of the latch 315.

[0041] Fig. 4A-4C are corresponding circuit diagrams 400A-400C of an array and column driver region including a distributed write driver arrangement, according to at least one embodiment of the present disclosure. More specifically, each of the circuit diagrams 400A-400C shows the same circuit, albeit in different control phases of column 407(i) of the array and column driver region.

[0042] Each of the circuit diagrams 400A-400C is an example implementation of the array and column driver section 200 of Fig. 2. Therefore, each of the circuit diagrams 400A-400C is an example of the area 104 of Fig. 1.

[0043] In some respects, each of the circuit diagrams 400A-400C is a more detailed version of the circuit diagram 300. For example, each of the circuit diagrams 400A-400C shows the following: the inverter 440 having the connected PMOS transistor P05 and the NMOS transistor N13, with the source / drain of the transistor P05 connected between VDD and a node 460B and the source / drain of the transistor N13 connected between the node 460B and the VSS; and inverter 442 having connected PMOS transistor P06 and NMOS transistor N14, with the source / drain of transistor P06 connected between VDD and a node 462B and the source / drain of transistor N14 connected between node 462B and VSS. In some respects, for ease of illustration, each of circuit diagrams 400A-400C is a less detailed version of circuit diagram 300.While each of the circuit diagrams 400A-400C shows cells 412A(i,j) and 416A(i,j), none of the circuit diagrams 400A-400C shows components included in each of the cells 412A(i,j) and 416A(i,j).

[0044] Fig. 4A assumes a scenario in which column 407(j) is not selected. Fig. Figure 4B assumes a scenario in which column 407(i) is selected and in which column 407(j) is preloaded before a write operation. Fig. 4C assumes a scenario in which column 407(j) is selected and in which data is written to column 407(j) after column 407(j) has been preloaded.

[0045] With reference to Fig. 4A (which again assumes a scenario in which column 407(j) is not selected), because the inclusion of NOR gates 448-450 in c-drv control unit 426(i) reflects an "active-low" configuration, column 407(j) is not selected when a signal on line CS_BAR is set to the value H. When the signal on line CS_BAR is set to the value H, the output of each of NOR gates 448-450 is the value L. As long as the signal on line CS_BAR is set to the value H, the output of NOR gate 448 at node 460A will be the value H regardless of whether the signal on line WD is set to the value L or the value H. Accordingly, in Fig. 4A, the value of the signal on line WD is shown as L / H. Similarly, if the signal on line CS_BAR is set to the value H, the output of NOR gate 450 at node 462A will be the value H regardless of whether the signal on line WD_bar is set to the value L or the value H. Accordingly, in Fig. 4A the value of the signal on the line WD_bar is shown as L / H.

[0046] Regarding the g-col driver 424(j), when the output of NAND gate 448 at node 460A (which is also the input of inverter 440) is L, then the output of inverter 440 at node 460B is H. More specifically, when the input of inverter 440 at node 460A is L, transistor P05 is turned on and transistor N13 is turned off, so that, respectively, VDD is connected to node 460A and VSS is disconnected / blocked from node 460A. Similarly, when the output of NAND gate 450 at node 462A (which is also the input of inverter 442) is L, then the output of inverter 442 at node 462B is H.

[0047] Also, regarding the g-col driver 424(j), when the outputs of each of the NAND gates 448-450 at the corresponding nodes 460A and 462A are low, then the equalizer 425 is turned on. More specifically, when the inputs of the inverters 440-442 at the corresponding nodes 460A and 462A are low, then the corresponding transistors P11-P12 are turned on, connecting the LWB line 434(j) to the LWB_bar line 436(j), which facilitates the equalization of voltage levels on the LWB line 434(j) and the LWB_bar line 436(j).

[0048] With respect to the s-col driver 420(j), if the output of the NAND gate 448 at node 460A (which is also the input at node 464A of the inverter 444 of the s-col driver 420A(j)) is L, then the output of the inverter 444 at node 464B is H. Similarly, if the output of the NAND gate 450 at node 462A (which is also the input at node 466A of the inverter 446 of the s-col driver 420A(j)) is L, then the output of the inverter 442 at node 462B is H.

[0049] Also, with respect to the s-col driver 420(j), when the inputs of inverters 444-446 at the corresponding nodes 464A-466A are low, the equalizer 421 is turned on. More specifically, when the inputs of inverters 444-446 at the corresponding nodes 464A-466A are low, the corresponding transistors P13-P14 are turned on, connecting the LWB line 434(j) to the LWB_bar line 436(j), which facilitates the equalization of voltage levels on the LWB line 434(j) and the LWB_bar line 436(j).

[0050] The discussion now turns Fig. 4B (which again assumes a scenario in which column 407(i) is selected and in which column 407(j) is preloaded before a write operation). In Fig. 4B, a signal on the CS_BAR line is set to the value L. When the signal on the CS_BAR line is set to the value L, the output of each of the NOR gates 448-450 depends on the values ​​on the corresponding WD and WD_bar lines. In Fig. 4B, each of the lines WD and WD_bar has the value H. Accordingly, the output of each of the NOR gates 448-450 at the corresponding nodes 460A and 462A is the value L.

[0051] In Fig. 4B, with respect to the g-col driver 424(j), if the output of the NAND gate 448 at the node 460A (which is also the input of the inverter 440) has the value L, then the signal propagation is similar to that of Fig. 4A (discussed previously). This is because each of the lines WD and WD_bar has the value H in Fig. 4B, while the line CS_bar has the value L, while in Fig. 4A the line CS_bar has the value H (so it does not matter whether the signals on the lines WD and WD_bar have the value L or the value H in Fig. 4A are set). Accordingly, in Fig. 4B, column 407(j) is selected and the LWB line 434(j) and the LWB_bar line 436(j) are precharged to the value H before a write operation occurs.

[0052] The discussion now turns Fig. 4C (which again assumes a scenario in which column 407(j) is selected and in which data is written to column 407(j) after column 407(j) has been preloaded). Recall that a bit cell, e.g., 412A(i,j) (but see 312A(i,j) for more details), stores a pair of opposite logic values ​​(L and H or H and L) at the corresponding pair of nodes, e.g., node 303A and node 303B. Accordingly, the values ​​that c-drv controller 426(i) outputs to the corresponding nodes 460A and 462A are a pair of opposite logic values, either L and H or H and L, to write data to one of the cells in column 407(i,j), e.g., cell 412A(i,j).

[0053] Fig. 4C is similar to Fig. 4B with the exception that Fig. 4C, the value on line WD differs from the value on line WD_bar, with the result that the value output by c-drv control unit 426(i) at node 460A is the logical opposite of the value output by c-drv control unit 426(i) at node 462A. Accordingly, in Fig. 4C, the line WD is shown as having the value L / H, and the line WD_bar is shown as having the value H / L, and the values ​​that the c-drv controller 426(i) outputs to the corresponding nodes 460A and 462A are shown as H / L and L / H.

[0054] More specifically, regarding the c-drv control unit 426(i) in Fig. 4C, a signal on the CS_BAR line is set to the value L. When the signal on the CS_BAR line is set to the value L, the output of each of the NOR gates 448-450 depends on the values ​​on the corresponding WD and WD_bar lines. In Fig. 4C, the WD line has the value L / H, so the output of the NOR gate 448 at node 460A is H / L. The WD_bar line has the value H / L, so the output of the NOR gate 448 at node 462A is L / H.

[0055] Regarding the g-col driver 4240) in Fig. 4C, when the output of NAND gate 448 at node 460A (which is also the input of inverter 440) is H / L, then the output of inverter 440 at node 460B is L / H. More specifically, when the input of inverter 440 at node 460A is H, transistor P05 is turned off and transistor N13 is turned on, so that, accordingly, VDD is disconnected / blocked from node 460A and VSS is connected to node 460A. Alternatively, when the input of inverter 440 at node 460A is L, transistor P05 is turned on and transistor N13 is turned off, so that, accordingly, VDD is connected to node 460A and VSS is disconnected / blocked from node 460A. Similarly, if the output of NAND gate 450 at node 462A (which is also the input of inverter 442) has the value L / H, then the output of inverter 442 at node 462B has the value H / L.

[0056] Also, regarding the g-col driver 424(j), if the output of NAND gate 448 at node 460A and the output of NAND gate 450 at node 462A have different logic values, then the equalizer 425 is turned off. More specifically, because transistors P11 and P12 are both PMOS transistors, one of P11 and P12 is turned off when the corresponding nodes 460A and 462A have different logic values. If the output of NAND gate 448 at node 460A has the value H / L, then transistor P11 is turned on / off. If the output of NAND gate 450 at node 462A has the value L / H, then transistor P12 is turned off / on.With equalizer 425 disabled, LWB line 434(j) is disconnected / blocked from LWB_bar line 436(j), preventing matching of the voltage levels on LWB line 434(j) and LWB_bar line 436(j), thereby facilitating writing of a pair of opposite logic values ​​(L and H or H and L) in a bit cell of column 407(j), e.g., 412A(i,j).

[0057] With respect to s-col driver 420(j), if the output of NAND gate 448 at node 460A (which is also the input at node 464A of inverter 444 of s-col driver 420A(j)) is H / L, then the output of inverter 444 at node 464B is L / H. Similarly, if the output of NAND gate 450 at node 462A (which is also the input at node 466A of inverter 446 of s-col driver 420A(j)) is L / H, then the output of inverter 442 at node 462B is H / L.

[0058] The equalizer 421 of the s-col driver 420(j) is similar to the equalizer 425. Accordingly, when the inputs of the inverters 444 and 446 at the corresponding nodes 464A and 466A have the corresponding values ​​H / L and L / H, then the equalizer 421 is turned off.

[0059] A circuit configuration can be described, e.g., in terms of the relative optimization levels of various parameter combinations representing the circuit configuration. For example, speed is a parameter representing the operating speed of a corresponding circuit. In some embodiments, the relative speed optimization levels are referred to as low, moderate, and high, such that the corresponding circuit is configured to have a low speed, moderate speed, or high speed, where low < moderate < high. As another example, footprint is a parameter representing an area consumed / occupied by a corresponding circuit.In some embodiments, the relative footprint optimization levels are referred to as small, medium, and large, such that the corresponding circuit is configured to have a small footprint, a medium footprint, or a large footprint, where small < medium < large.

[0060] In some embodiments, certain relative optimizations of speed and footprint are referred to as types.

[0061] In some embodiments, the maximum speed is a parameter that represents the maximum operating speed (Max Speed) of a corresponding circuit. In some embodiments, the footprint is a parameter that represents an area consumed by a corresponding circuit. In some embodiments, and as summarized in the following table (Table 1), a Type 1 configuration is configured for a moderate level of max speed and a medium footprint, a Type 2 configuration is configured for a low level of max speed and a small footprint, and a Type 3 configuration is configured for a high level of max speed and a large footprint. In some embodiments, the moderate level of max speed is approximately halfway between the low level of max speed and the high level of max speed.In some embodiments, a difference between the low maximum speed measure and the high maximum speed measure is less than about 30%. In some embodiments, a difference between the small footprint and the large footprint is less than about 30%. In some embodiments, each of the difference between the low maximum speed measure and the high maximum speed measure and the difference between the small footprint and the large footprint is less than about 30%. Table 1 Typ Max. Geschwindigkeit Footprint Typ-1 gemäßigt mittel Typ-2 niedrig klein Typ-3 hoch groß

[0062] In Fig. 3 and 4A-4C, each of the s-col driver 320A(j), the g-col driver 324(j), the s-col driver 420A(j), and the g-col driver 424(j) is shown as having the same internal configuration. More specifically, each of the s-col driver 320A(j), the g-col driver 324(j), the s-col driver 420A(j), and the g-col driver 424(j) is shown as having the Type 1 configuration. Accordingly, each of the s-col driver 320A(j), the g-col driver 324(j), the s-col driver 420A(j), and the g-col driver 424(j) is configured for a moderate speed and a medium footprint. In some embodiments, the configuration of one or more of the s-col driver 320A(j), the g-col driver 324(j), the s-col driver 420A(j), and the g-col driver 424(j) differs from what is described in Fig. 3 and 4A-4C. See for example Fig. 5A-5C (discussed below).

[0063] Fig. 5A-5C are respective circuit diagrams 500A-500C of array and column driver regions, each including a distributed write driver arrangement, according to respective embodiments of the present disclosure.

[0064] Each of the circuit diagrams 500A-500C is an example implementation of the array and column driver section 200 of Fig. 2. Therefore, each of the circuit diagrams 500A-500C is an example of the area 104 of Fig. 1.

[0065] Each of the circuit diagrams 500A-500C of the corresponding Fig. 5A-5C is an exemplary variant of the circuit diagrams 400A-400C of Fig. 4A-4C. Recall that each of the circuit diagrams 400A-400C shows the same circuit in different control phases of column 407(i) of the array and column driver section. For brevity, the discussion of the circuits 500A-500C will be based on differences with respect to the circuit diagrams 400A-400C of Fig. Focus 4A-4C.

[0066] In Fig. 5A, the s-col driver 520A(j)'' and the g-col driver 524(j)''' differ from the corresponding s-col driver 420A(j) and the g-col driver 424(j) of Fig. 4A-4C.

[0067] In circuit diagram 500A, the s-col driver 520A(j)" does not include an equalizer, which would otherwise correspond to the equalizer 421 of the s-col driver 420A(j). Instead, a gap 578A is present between nodes 564B and 566B in the s-col driver 420A(j). In terms of type, the s-col driver 520A(j)" is shown as having the Type-2 configuration, with the double apostrophe (") at reference numeral 520A(j)" indicating Type-2. Accordingly, the s-col driver 520A(j) is configured for low speed and a small footprint.

[0068] Also in circuit diagram 500A, g-col driver 524(j)''' includes equalizer 572A instead of equalizer 425 of g-col driver 424(j).

[0069] Equalizer 572A is connected between LWB line 534(j) at node 560B and LWB_bar line 536(j) at node 562B. Equalizer 572A includes a PMOS transistor P51, a NOR gate 574A, and an inverter 576A. PMOS transistor P51 is connected between LWB line 534(j) at node 560B and LWB_bar line 536(j) at node 562B. The gate of transistor P51 is connected to the output of inverter 576A. The input of inverter 576A is connected to the output of NOR gate 574A. The first and second inputs of NOR gate 574A are connected to nodes 560A and 562A, respectively. In terms of type, g-col driver 524A(j)''' is shown as having the Type-3 configuration, where the triple apostrophe (''') at reference numeral 524A(j)''' indicates Type-3. Accordingly, g-col driver 525A(j)''' is configured for high speed and a large footprint.

[0070] With regard to how the values ​​on the respective nodes 560A and 562A turn the equalizer 572 on / off, the equalizer 527 operates in the same way as the equalizer 425 of Fig. 4A-4C. Since the recording of NOR gate 574A reflects an "active-low" configuration, if each of nodes 560A and 562A has the value L, then the output of NOR gate 574A has the value H and the gate electrode of transistor P51 has the value L, which turns transistor P51 on. Any other combination of values ​​on nodes 560A and 562A produces results in the output of NOR gate 574A having the value L and the gate electrode of transistor P51 having the value H, which turns transistor P51 off. Accordingly, in Fig. 5A, the values ​​on nodes 560A and 562A are shown as L / H / X / X and L / H / X / X, respectively.

[0071] Fig. 5B is in some respects similar to Fig. 4A-4C and is in some respects similar to Fig. 5A. In Fig. 5B, the s-col driver 520A(j) is the same as the s-col driver 420A(j) in Fig. 4A-4C. Also in Fig. 5B, the g-col driver 524(j)''' is the same as the g-col driver 524(j)''' in Fig. 5A.

[0072] Fig. 5C is in some ways similar to Fig. 4A-4C and is in some respects similar to Fig. 5A. In Fig. 5C, the s-col driver 520A(j)'' is the same as the s-col driver 520A(j)'' in Fig. 5A. Also in Fig. 5C, the g-col driver 524(j) is the same as the g-col driver 424(j) in Fig. 4A-4C.

[0073] Regarding the types summarized in Table 1, the combinations of the types listed in Fig. 3, 4A-4C and 5A-5C are summarized in the following table (Table 2).

[0074] In some embodiments, certain relative optimizations of speed and footprint are summarized in the following table (Table 3).

[0075] Regarding Table 3, in Fig. FIGS. 3 and 4A - 4C, each of the s - col drivers 320A(j), the g - col driver 324(j), the s - col driver 420A(j), and the g - col driver 424(j) is configured for substantially the same maximum speed, and each of the s - col drivers 320A(j), the g - col driver 324(j), the s - col driver 420A(j), and the g - col driver 424(j) is configured with substantially the same footprint. In Fig. FIG. 5A, the s - col driver 520A(j)'' is configured for a lower maximum speed compared to the g - col driver 524(j)''', and the s - col driver 520A(j)'' is configured with a smaller footprint compared to the g - col driver 524(j)'''. In Fig. 5B, the s-col driver 520A(j) is configured for a lower maximum speed compared to the g-col driver 524(j)'', and the s-col driver 520A(j)'' is configured with a smaller footprint compared to the g-col driver 524(j)'''. In Fig. 5C, the s-col driver 520A(j)'' is configured for a lower maximum speed compared to the g-col driver 524(j) and the s-col driver 520A(j)'' is configured with a smaller footprint compared to the g-col driver 524(j)'''.

[0076] Fig. 6 is a cross-section of an array and column driver region 600 including a distributed write driver arrangement, according to at least one embodiment of the present disclosure. Therefore, the region 600 of Fig. 6 an example of the area 104 of Fig. 1. In some embodiments, each of the circuit diagrams 300, 400A-400C and 500A-500C has cross sections corresponding to Fig. 6 on.

[0077] Fig. 6 includes layers 671 and 673. Layer 673 lies on top of layer 671. Layer 671 is a p-th layer (layer(p)) of devices (not shown), where p is an integer and p ≥ 0. Layer 673 is a (p+1)-th layer (layer(p(i+1)) of devices (not shown).

[0078] Examples of devices included in device layer(p) 671 include: segments 202A and 202B of Fig. 2, which have the corresponding s-col drivers 220A(j)-220(j+n) and 220B(j)-220B(j+n); the segment 302A of Fig. 3, which has the s-col driver 320A(j); the segment 402A of Fig. 4A-4C, which includes the s-col driver 420A(j); the segments 502A'' of Fig. 5A and Fig. 5C, which include the s-col driver 520A(j)''; and the segment 502A of Fig. 5B, which includes the s-col driver 520A(j).

[0079] Examples of devices included in the device layer(p+1) 673 include: the g-col drivers 224(j)-224(j+n) and the c-drv controllers 226(j)-226(j+1) of Fig. 2; the g-col driver 324(j) and the c-drv control unit 326(j) of Fig. 3; the g-col driver 424(j) and the c-drv control unit 426(j) of Fig. 4A-4C; the g-col driver 524(j)''' from Fig. 5A-5B; the g-col driver 524(j) of Fig. 5C; and the c-drv control unit 526(j) of Fig. 5A-5C.

[0080] Device layer(p) 671 includes sublayers 675-679. Sublayer 677 is located on sublayer 675. Sublayer 679 is located on sublayer 677. Device layer(p+1) 673 includes sublayers 681-687. Sublayer 683 is located on sublayer 681. Sublayer 685 is located on sublayer 683. Sublayer 687 is located on sublayer 685.

[0081] Sublayer 679 is a q-th metallization sublayer (sublayer(q)), where q is an integer and q ≥ 0. In some embodiments, the q-th sublayer is the first metallization sublayer, in which case q = 0 or q = 1 depending on the numbering convention of the corresponding design rules. Sublayer 685 is a (q+1)-th metallization sublayer (sublayer(q+1)). In some embodiments, metallization sublayer (q) 679 also comprises one or more interconnects (not shown), e.g., one or more vias. In some embodiments, metallization sublayer (q+1) 683 also comprises one or more interconnects (not shown), e.g., one or more vias.

[0082] Sublayer 675 includes semiconductor structures (not shown), e.g., active regions or the like. Sublayer 677 is an interconnect sublayer including interconnects (not shown), e.g., vias. The vias of interconnect sublayer 677 connect semiconductor structures of sublayer 675 to corresponding conductors (not shown) in metallization sublayer(q) 679. At least some of the devices of layer(p) 671 include one or more semiconductor structures of sublayer 675, one or more vias of interconnect sublayer 677, and one or more conductors of metallization sublayer(q) 679.

[0083] Sublayer 687 includes semiconductor structures (not shown), e.g., active regions or the like. Sublayers 681 and 685 are interconnect sublayers, each of which includes interconnects (not shown), e.g., vias. The vias of interconnect sublayer 681 connect conductors (not shown) in metallization sublayer (q+1) to corresponding conductors (not shown) in metallization sublayer (q) 683. The vias of interconnect sublayer 685 connect semiconductor structures of sublayer 687 to corresponding conductors (not shown) in metallization sublayer (q+1) 683. At least some of the devices of layer (p+1) 681 include one or more semiconductor structures of sublayer 687, one or more vias of interconnect sublayer 685, and one or more conductors of metallization sublayer (q) 683.

[0084] In the array and column driver area 600 of Fig. 6, device layer(p+1) 673 is less densely populated than device layer(p) 671. Accordingly, compared to device layer(p) 671, device layer(p+1) 673 more easily accommodates circuits with Type 1 configurations (moderate speed and medium footprint) than does device layer(p) 671, and even more easily accommodates circuits with Type 3 configurations (high speed and large footprint) than does device layer(p) 671.

[0085] In some embodiments, device layer(p+1) 673 includes Type 1 and / or Type 3, but no Type 2, configurations of circuits, while layer(p) 671 includes Type 1 and / or Type 2, but no Type 3, configurations of circuits. In some embodiments, device layer(p+1) 673 includes Type 3, but no Type 1 and / or Type 2, configurations of circuits, while layer(p) 671 includes Type 2, but no Type 1 and / or Type 3, configurations of circuits. In some embodiments, device layer(p+1) 673 includes Type 1, but no Type 2 and / or Type 3, configurations of circuits, while layer(p) 671 includes Type 1, but no Type 2 and / or Type 3, configurations of circuits. Other configurations are within the scope of the disclosure.

[0086] Fig. 7 is a flowchart of a method 700 for write driving a column in an array and column driver portion of an SRAM macro on a distributed basis, according to some embodiments.

[0087] According to some embodiments, the method 700 may be implemented using an EDA system 900, for example.

[0088] With respect to method 700, an example of the SRAM macro is SRAM macro 102. Examples of the column and corresponding array and column driver range include: columns 207(j)-207(j+n) in range 200 of Fig. 2; column 307(j) in the circuit diagram 300 of Fig. 3; column 407(j) in circuit diagrams 400A-400C of Fig. 4A-4C; and columns 507A(j)-507C(j) in the corresponding circuit diagrams 400A-400C of the corresponding Fig. 5A-5C.

[0089] In Fig. 7, method 700 includes blocks 702-714. At block 702, a GWB line is driven with a first signal having a first logic value. An example of the GWB line is GWB line 430(j) in Fig. 4A-4C. An example of the first signal having the first state is the signal on node 460A in Fig. 4A-4B, which has the value L. An example of the first signal having the first state is the signal on node 460A in Fig. 4C, which has the value L / H (see Fig. 4C, discussed previously). From block 702, the flow continues to block 704.

[0090] At block 704, a GWB_bar line is driven with a second signal having either the first logical value or a second logical value that is the opposite of the first logical value. An example of the GWB_bar line is the GWB_bar line 432(j) in Fig. 4A-4C. An example of the second signal having the first state is the signal on node 462A in Fig. 4A-4B, which has the value L. Another example of the first signal having the second state is the signal on node 462A in Fig. 4C, which has the value H / L (see Fig. 4C, discussed previously). From block 704, the flow continues to block 706.

[0091] At block 706, using a first inverter in a global write driver and a third inverter in a local write driver, the first signal is inverted to form a first_bar signal having the second logical value. An example of the first inverter in the global write driver is inverter 440 in Fig. 4A-4C. An example of the third inverter in the local write driver is inverter 444 in Fig. 4A-4C. An example of the first_bar signal having the second logical value is the signal on node 460B in Fig. 4A-4B, which has the value H. Another example of the first signal having the second state is the signal on node 460B in Fig. 4C, which has the value L / H (see Fig. 4C, discussed previously). From block 706, the flow continues to block 708.

[0092] At block 708, using each of a second inverter in a global write driver and a fourth inverter in a local write driver, the second signal is inverted to form a second_bar signal having a logical value that is the opposite of the logical value of the second signal. An example of the second inverter in the global write driver is inverter 442 in Fig. 4A-4C. An example of the fourth inverter in the local write driver is inverter 446 in Fig. 4A-4C. An example of the second_bar signal is the signal on node 462B in Fig. 4A-4B, which has the value H. Another example of the second_bar signal is the signal on node 462B in Fig. 4C, which has the value H / L (see Fig. 4C, previously discussed). From block 708, the flow continues to block 710.

[0093] At block 710, the first_bar signal is provided to a first pass gate of each of the bit cells. Examples of the bit cells are bit cells 420A(i,j) and 416A(i,j) in Fig. 4A-4C. An example of the first_bar signal provided to the first pass gate of a bit cell is the signal on nodes 405A and 403A in Fig. 4A-4C. From block 710, the flow continues to block 712.

[0094] At block 712, the second_bar signal is provided to a second pass gate of each of the bit cells. Again, examples of the bit cells are bit cells 420A(i,j) and 416A(i,j) in Fig. 4A-4C. An example of the second_bar signal provided to the second pass gate of a bit cell is the signal on nodes 405B and 403B in Fig. 4A-4C. From block 712, the flow continues to block 714.

[0095] At block 714, each of the first and second equalizers is controlled by the first and second signals. Examples of the first and second equalizers are the corresponding equalizers 425 and 423 in Fig. 4A-4C.

[0096] In some embodiments, block 714 comprises: turning off each of the first equalizer circuit and the second equalizer circuit when the first and second signals have different logic values, an example of which is shown in Fig. 4C is shown.

[0097] In some embodiments, block 714 includes providing the first signal to gates of a first and third transistor; and providing the second signal to gates of a second and fourth transistor. Examples of the first to fourth transistors are the respective transistors P11-P14 of Fig. 4A-4C, the gates of which are connected to the corresponding nodes 460A, 462A, 464A and 466A.

[0098] In some embodiments, block 714 includes: logically combining the first and second signals to form a third signal; and providing the third signal to a gate of a first transistor. An example of the transistor is transistor P51 in Fig.5A. An example of logically combining the first and second signals to form a third signal is providing the signals at nodes 560A and 562A to NOR gate 547A and inverting the output of NOR gate 574A with inverter 576A, with the third signal formed at the output of inverter 576A. An example of providing the third signal to a gate of a first transistor is providing the signal at the output of inverter 576A to the gate of transistor P51.

[0099] In one embodiment, a semiconductor memory device comprises: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWB_bar) line; and a column of segments. Each segment comprises bit cells, each of the bit cells comprising a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit. The device further comprises a distributed write driver arrangement. The distributed write driver arrangement comprises: a global write driver and a local write driver. The global write driver comprises: a first inverter connected between the GWB line and the LWB line; and a second inverter connected between the GWB_bar line and the LWB_bar line.The local write driver is included in each segment, each local write driver being located in an interior of the corresponding segment, each local write driver comprising: a third inverter coupled between the GWB line and the LWB line; and a fourth inverter coupled between the GWB_bar line and the LWB_bar line. In some embodiments, the first inverter is coupled between the GWB line and the LWB line by being coupled between a corresponding first and second node; the second inverter is coupled between the GWB_bar line by being coupled between a corresponding third and fourth node; and the global write driver further comprises: a first equalizer circuit coupled between the LWB line and the LWB_bar line and configured to be controlled by signals on the corresponding first and third nodes.In some embodiments, the first equalizer circuit of the global write driver comprises: first and second transistors connected in series between the LWB line and the LWB_bar line; and signals on the first and third nodes are connected to corresponding gate electrodes of the first and second transistors. In some embodiments, the first equalizer circuit of the global write driver comprises: a transistor connected in series between the LWB line and the LWB_bar line; and a logic circuit connected between a gate electrode of the transistor and each of the first and second nodes. In some embodiments, the logic circuit is configured to apply a logical OR function to signals on the corresponding first and third nodes.In some embodiments, the first equalizer circuit of the global write driver is configured to turn off when signals on the corresponding first and third nodes have different logic states. In some embodiments, the third inverter is connected between the GWB line and the LWB line by being connected between a corresponding fifth and sixth node; the fourth inverter is connected between the GWB_bar line and the LWB line by being connected between a corresponding seventh and eighth node; and the local write driver further comprises: a second equalizer circuit connected between the LWB line and the LWB_bar line and configured to be controlled by signals on the corresponding fifth and seventh nodes.In some embodiments, the second equalizer circuit of each local write driver comprises: first and second transistors connected in series between the LWB line and the LWB_bar line; and signals on the fifth and seventh nodes are connected to corresponding gate electrodes of the first and second transistors. In some embodiments, the second equalizer circuit of each local write driver comprises: a transistor connected in series between the LWB line and the LWB_bar line; and logic circuitry connected between a gate electrode of the second transistor and each of the fifth and seventh nodes. In some embodiments, the logic circuitry is configured to apply a logical OR function to signals on the corresponding fifth and seventh nodes.In some embodiments, the second equalizer circuit of each local write driver is configured to turn off when signals on the corresponding fifth and seventh nodes have different logic states.In some embodiments, the maximum speed is a parameter representing the maximum operating speed of a corresponding circuit; the footprint is a parameter representing an area consumed by a corresponding circuit; and the local write driver and the global write driver are configured to have one of the following descriptions, respectively: the local write driver is configured for substantially the same maximum speed compared to the global write driver, and the local write driver is configured with substantially the same footprint compared to the global write driver; or the local write driver is configured for a lower maximum speed compared to the global write driver, and the local write driver is configured with a smaller footprint compared to the global write driver.

[0100] In another embodiment, a semiconductor memory device comprises: a column of segments, each segment comprising bit cells; a local write bit (LWB) line; a local write bit_bar (LWBL_bar) line; a global write bit (GWB) line; a global write bit_bar (GWB_bar) line; wherein each of the bit cells comprises: a latch circuit; and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driver arrangement comprising: a global write driver and a local write driver. The global write driver is coupled between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.The local write driver is included in each segment, wherein each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: each local write driver is located in a first device layer; and the global write driver is located in a second device layer above the first device layer.In some embodiments, each local write driver is located at an internal location in the corresponding segment; the bit cells are located in the first device layer; the LWB line and the LWB_bar line are located in a first metallization layer of the first device layer, the first metallization layer being between a semiconductor structure sublayer of the first device layer and the second device layer; and the GWB line and the GWB_bar line are located in a second metallization layer of the second device layer, the second metallization layer being between the first metallization layer and a semiconductor structure sublayer of the second device layer.In some embodiments, the maximum speed is a parameter representing the maximum operating speed of a corresponding circuit; the footprint is a parameter representing an area consumed by a corresponding circuit; and the local write driver and the global write driver are configured to have one of the following descriptions, respectively: the local write driver is configured for substantially the same maximum speed compared to the global write driver, and the local write driver is configured with substantially the same footprint compared to the global write driver; or the local write driver is configured for a lower maximum speed compared to the global write driver, and the local write driver is configured with a smaller footprint compared to the global write driver.

[0101] Another embodiment relates to a method for driving a column in an SRAM macro with a distributed write driver arrangement, wherein the column comprises a global write bit (GWB) line, a global write bit_bar (GWB_bar) line, a local write bit (LWB) line, a local write bit_bar (LWB_bar) line, bit cells, and at least one local write driver, each of the bit cells comprising a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines, wherein the global write driver comprises a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line, and the local write driver comprises a third inverter connected between the GWB line and the LWB line, and a fourth inverter connected between the GWB line and the LWB_bar line is switched,and the local write driver is located on an inner portion of the column; the method comprising: driving the GWB line with a first signal having a first logic value; driving the GWB_bar line with a second signal having either the first logic value or a second logic value that is the opposite of the first logic value; inverting the first signal with each of the first inverter in the global write driver and the third inverter in the local write driver to form a first_bar signal having the second logic value; inverting the second signal with each of the second inverter in the global write driver and the fourth inverter in the local write driver to form a second_bar signal having a logic value that is the opposite of the second signal; driving the LWB line with the first_bar signal,to provide the first_bar signal to the first pass gate of each of the bit cells; and driving the LWB_bar line with the second_bar signal to provide the second_bar signal to the second pass gate of each of the bit cells. In some embodiments, the global write driver comprises a first equalizer circuit coupled between the LWB line and the LWB_bar line; the local write driver comprises a second equalizer circuit coupled between the LWB line and the LWB_bar line; and the method further comprises: controlling the first equalizer circuit with the first and second signals; and controlling the second equalizer circuit with the first and second signals. In some embodiments, controlling the first equalizer circuit comprises: turning off the first equalizer circuit,when the first and second signals have different logic values; and controlling the second equalizer circuit comprises: turning off the second equalizer circuit when the first and second signals have different logic values. In some embodiments, the first equalizer circuit comprises first and second transistors connected in series between the LWB line and the LWB_bar line; the local write driver further comprises third and fourth transistors,connected in series between the LWB line and the LWB_bar line; and controlling the first equalizer circuit comprises: providing the first signal to a gate of the first transistor; and providing the second signal to a gate of the second transistor; and controlling the second equalizer circuit comprises: providing the first signal to a gate of the first transistor; and providing the second signal to a gate of the fourth transistor. In some embodiments, the first equalizer comprises a transistor connected in series between the LWB line and the LWB_bar line; and controlling the first equalizer circuit comprises: logically combining the first and second signals to form a third signal; and providing the third signal to a gate of the transistor.

Claims

[1] A semiconductor memory device comprising: an LWF leadership (234(j), 234(j+n), 334(j), 434(j), 534(j)); a LWB_bar line (336(j), 436(j), 536(j)) ; a GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)); a GWB bar line (322(j), 332(j), 432(j), 532(j)); a column (207(j), 207(j+n), 307(j), 407(j), 507A(j), 507B(j), 507C(j)) of segments (202A, 202B, 302A, 402A, 502A, 502A''), each segment (202A, 202B, 302A, 402A, 502A, 502A'') bit cells (212A(i,j), 212A(i+m,j+n), 212B(i,j), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)); wherein each of the bit cells (212A(i,j), 212A(i+m,j+n), 212B(ij), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)) comprises a latch circuit (311, 315) and a first and second pass gate (N03, N04; N09, N10) which connect the corresponding LWB and LWB_bar line (234(j), 234(j+n), 334(j), 434(j), 5340); 336(j), 436(j), 536(j)) to the latch circuit (311, 315); and a distributed write driver arrangement comprising a global write driver (224(j), 224(j+n)) and a local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)): where the global write driver (224(j), 224(j+n)) has the following: a first inverter (340, 440, 540) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)); and a second inverter (342, 442, 542) connected between the GWB_bar line (3220, 3320), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and wherein the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is included in each segment (202A, 202B, 302A, 402A, 502A, 502A''), wherein each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is located in an interior of the corresponding segment (202A, 202B, 302A, 402A, 502A, 502A''), wherein each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) comprises: a third inverter (344, 444, 544) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 4340), 534(j); and a fourth inverter (346, 446, 546) connected between the GWB_bar line (322(j), 332(j), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)). [2] A semiconductor memory device according to claim 1, wherein: the first inverter (340, 440, 540) is connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(J)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) by being connected between a corresponding first and second node (360A, 360B; 460A, 460B; 560A; 560B); the second inverter (342, 442, 542) is connected between the GWB_bar line (322(j), 332(j), 432(j), 532(j)) by being connected between a corresponding third and fourth node (362A, 362B; 462A, 462B; 562A, 562B); and the global write driver (224(j), 224(j+n)) further comprises: a first equalizer circuit (325, 425, 572A) connected between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)) and configured to be controlled by signals on the respective first and third nodes (360A, 362A; 460A, 462A; 560A, 562A). [3] A semiconductor memory device according to claim 2, wherein: the first equalizer circuit (325, 425, 572A) of the global write driver (224(j), 224(j+n)) comprises: a first and second transistor (P11, P12) connected in series between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and the first and third nodes (360A, 362A; 460A, 462A; 560A, 562A) are connected to corresponding gate electrodes of the first and second transistors (P11, P12). [4] A semiconductor memory device according to claim 2 or 3, wherein: the first equalizer circuit (325, 425, 572A) of the global write driver (224(j), 224(j+n)) comprises: a transistor (P51) connected in series between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and a logic circuit (574A, 576A) connected between a gate electrode of the transistor (P51) and each of the first and second nodes. [5] A semiconductor memory device according to any one of the preceding claims 2 to 4, wherein: the logic circuit (574A, 57'6A) is configured to apply a logical OR function to signals on the corresponding first and third nodes. [6] A semiconductor memory device according to any one of the preceding claims 2 to 5, wherein: the first equalizer circuit (325, 425, 572A) of the global write driver (224(j), 224(j+n)) is configured to turn off in response to signals on the corresponding first and third nodes having different logic states. [7] A semiconductor memory device according to any one of the preceding claims 2 to 6, wherein: the third inverter (344, 444, 544) is connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(J)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) by being connected between a corresponding fifth and sixth node; the fourth inverter (346, 446, 546) is connected between the GWB_bar line (322(j), 332(j), 432(j), 532(j)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) by being connected between a corresponding seventh and eighth node; the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) further comprises: a second equalizer circuit (321, 421, 521) connected between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)) and configured to be controlled by signals on the corresponding fifth and seventh nodes (364A, 366A; 464A, 466A, 564A; 566A). [8] A semiconductor memory device according to claim 7, wherein: the second equalizer circuit (321'' 421, 521) of each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) comprises: a first and second transistor (P13, P14) connected in series between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and Signals on the fifth and seventh nodes are connected to corresponding gate electrodes of the first and second transistors (P13, P14). [9] A semiconductor memory device according to claim 7 or 8, wherein: the second equalizer circuit (321'' 421, 521) of each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) comprises: a transistor connected in series between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and a logic circuit connected between a gate electrode of the second transistor and each of the fifth and seventh nodes. [10] A semiconductor memory device according to claim 9, wherein: the logic circuit is configured to apply a logical OR function to signals on the corresponding fifth and seventh nodes. [11] A semiconductor memory device according to any one of the preceding claims 7 to 10, wherein: the second equalizer circuit (321'' 421, 521) of each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured to turn off when signals on the corresponding fifth and seventh nodes have different logic states. [12] A semiconductor memory device according to any preceding claim, wherein: the maximum speed is a parameter representing the maximum operating speed of a corresponding circuit; the footprint is a parameter representing an area (104, 200, 300, 600) consumed by a corresponding circuit; and the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) and the global write driver (224(j), 224(j+n)) are configured to have one of the following descriptions, respectively: the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured for substantially the same maximum speed as the global write driver (224(j), 224(j+n)) and the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured with substantially the same footprint as the global write driver (224(j), 224(j+n)); or the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured for a lower maximum speed compared to the global write driver (224(j), 224(j+n)) and the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured with a smaller footprint compared to the global write driver (224(j), 224(j+n)). [13] A semiconductor memory device comprising: a column (207(j), 207(j+n), 307(j), 407(j), 507A(j), 507B(j), 507C(j)) of segments (202A, 202B, 302A, 402A, 502A, 502A''), each segment (202A, 202B, 302A, 402A, 502A, 502A'') bit cells (212A(i,j), 212A(i+m,j+n), 212B(i,j), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)); an LWF leadership (234(j), 234(j+n), 334(j), 434(j), 534(j)); a LWB_bar line (336(j), 436(j), 536(j)); a GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)); a GWB bar line (322(j), 332(j), 432(j), 532(j)); where each of the bit cells (212A(i,j), 212A(i+m,j+n), 212B(ij), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)) has the following: a latch circuit (311, 315); and a first and second pass gate (N03, N04; N09, N10) connecting the corresponding LWB and LWB_bar line (234(j), 234(j+n), 334(j), 4340), 5340; 336(j), 436(j), 536(j)) to the latch circuit (311, 315); and a distributed write driver arrangement comprising: a global write driver (224(j), 224(j+n)) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 4340), 534(j)) and between the GWB_bar line (322(j), 332(j), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)); a local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) included in each segment (202A, 202B, 302A, 402A, 502A, 502A''), wherein each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and between the GWB_bar line (322(j), 332(j), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and where: each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is located in a first device layer (671); and the global write driver (224(j), 224(j+n)) is located in a second device layer (673) above the first device layer (671). [14] A semiconductor memory device according to claim 13, wherein: each local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is located at an inner location in the corresponding segment (202A, 202B, 302A, 402A, 502A, 502A''); the bit cells (212A(i,j), 212A(i+m,j+n), 212B(i,j), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)) are located in the first device layer; the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)) are located in a first metallization layer (679) of the first device layer (671), wherein the first metallization layer (679) is located between a semiconductor structure sublayer (675) of the first device layer (671) and the second device layer (673); and the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the GWB_bar line (322(j), 332(j), 432(j), 532(j)) are located in a second metallization layer (683) of the second device layer (673), wherein the second metallization layer (683) is located between the first metallization layer (679) and a semiconductor structure sublayer (687) of the second device layer (673). [15] A semiconductor memory device according to claim 13 or 14, wherein: the maximum speed is a parameter representing the maximum operating speed of a corresponding circuit; the footprint is a parameter representing an area (104, 200, 300, 600) consumed by a corresponding circuit; and the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) and the global write driver (224(j), 224(j+n)) are configured to have one of the following descriptions, respectively: the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured for substantially the same maximum speed as the global write driver (224(j), 224(j+n)) and the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured with substantially the same footprint as the global write driver (224(j), 224(j+n)); or the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured for a lower maximum speed compared to the global write driver (224(j), 224(j+n)) and the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is configured with a smaller footprint compared to the global write driver (224(j), 224(j+n)). [16] A method (700) for driving a column (207(j), 207(j+n), 307(j), 407(j), 507A(j), 507B(j), 507C(j)) in an SRAM macro (102) with a distributed write driver arrangement, wherein the column (207(j), 207(j+n), 307(j), 407(j), 507A(j), 507B(j), 507C(j)) has a GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)), a GWB_bar line (322(j), 332(j), 432(j), 532(j)), an LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)), an LWB_bar line (336(j), 436(j), 536(j)), bit cells (212A(i,j), 212A(i+m,j+n), 212B(i,j), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)) and at least one local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)), wherein each of the bit cells (212A(i,j), 212A(i+m,j+n), 212B(ij), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(i,j), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)) comprises a latch circuit (311, 315) and a first and second pass gate (N03, N04; N09, N10) which connect the corresponding LWB and LWB_bar line (234(j), 234(j+n), 334(j), 434(j), 5340); 336(j), 436(j), 536(j)), wherein the global write driver (224(j), 224(j+n)) comprises a first inverter (340, 440, 540) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)), and a second inverter (342, 442, 542) connected between the GWB_bar line (322(j), 332(j), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)), and the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) a third inverter (344, 444, 544) connected between the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(j)) and the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)), and a fourth inverter (346, 446, 546) connected between the GWB_bar line (322(j), 322(j), 432(j), 532(j)) and the LWB_bar line (336(j), 436(j), 536(j)) is switched on, and the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) is located at an inner portion of the column (207(j), 207(j+n), 307(j), 407(j), 507A(j), 507B(j), 507C(j)); wherein the method (700) comprises: Driving the GWB line (230(j), 230(j+n), 330(j), 430(j), 530(J)) with a first signal having a first logic value; Driving the GWB_bar line (322(j), 332(j), 432(j), 532(j)) with a second signal having either the first logical value or a second logical value that is the opposite of the first logical value; Inverting the first signal with each of the first inverter (340, 440, 540) at the global write driver (224(j), 224(j+n)) and the third inverter (344, 444, 544) at the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) to form a first_bar signal having the second logic value; Inverting the second signal with each of the second inverter (342, 442, 542) in the global write driver (224(j), 224(j+n)) and the fourth inverter (346, 446, 546) in the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) to form a second_bar signal having a logical value that is the opposite of the second signal; Driving the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) with the first_bar signal to provide the first_bar signal to the first pass gate of each of the bit cells (212A(i,j), 212A(i+m,j+n), 212B(i,j), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(ij), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)); and Driving the LWB_bar line (336(j), 436(j), 536(j)) with the second_bar signal to provide the second_bar signal to the second pass gate of each of the bit cells (212A(i,j), 212A(i+m,j+n), 212B(i,j), 212B(i+m,j+n), 216A(i,j), 216A(i+n,j+m), 216B(ij), 216B(i+n,j+m), 312A(i,j), 316A(i+m,j), 412A(i,j), 420A(i,j), 512A(i,j), 516A(i,j)). [17] The method (700) of claim 16, wherein: the global write driver (224(j), 224(j+n)) comprises a first equalizer circuit (325, 425, 572A) connected between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j); the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) has a second equalizer circuit (321'' 421, 521) connected between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and the method (700) further comprises: Controlling the first equalizer circuit (325, 425, 572A) with the first and second signals; and Controlling the second equalizer circuit (321, 421, 521) with the first and second signals. [18] The method (700) of claim 17, wherein: controlling the first equalizer circuit (325, 425, 572A) comprises: Switching off the first equalizer circuit (325, 425, 572A) when the first and second signals have different logic values; and controlling the second equalizer circuit (321, 421, 521) comprises: Switching off the second equalizer circuit (321, 421, 521) when the first and second signals have different logical values. [19] Method (700) according to claim 17 or 18, wherein: the first equalizer circuit (325, 425, 572A) comprises first and second transistors (P11, P12) connected in series between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)); the local write driver (220A(j), 220A(j+n), 220B(j), 220B(j+n)) further comprises a third and fourth transistor (P13, P14) connected in series between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and controlling the first equalizer circuit (325, 425, 572A) comprises: Providing the first signal to a gate of the first transistor; and Providing the second signal to a gate of the second transistor; and controlling the second equalizer circuit (321, 421, 521) comprises: Providing the first signal to a gate of the first transistor; and Providing the second signal to a gate of the fourth transistor. [20] Method (700) according to one of the preceding claims 17 to 19, wherein: the first equalizer circuit (325, 425, 572A) comprises a transistor (P51) connected in series between the LWB line (234(j), 234(j+n), 334(j), 434(j), 534(j)) and the LWB_bar line (336(j), 436(j), 536(j)); and controlling the first equalizer circuit (325, 425, 572A) comprises: logically combining the first and second signals to form a third signal; and Providing the third signal to a gate of the transistor.

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