Unrestricted approach to forming contact pins

Abstract

Method comprising: etching a dielectric layer (46, 48) of a substrate (10) to form an opening (60) in the dielectric layer; forming a metal layer (62) extending into the opening (60); performing an annealing process such that a lower section of the metal layer (62) reacts with a semiconductor region (42) located below the metal layer (62) to form a source / drain region (64); performing a plasma treatment process on the substrate (10) using a process gas comprising hydrogen gas and a nitrogen-containing gas to form a silicon- and nitrogen-containing layer (72); and applying a metallic material (73) to the silicon- and nitrogen-containing layer (72).

Description

BACKGROUNDIn the fabrication of integrated circuits, contact pins are used for connection to the source and drain regions as well as to the gates of transistors. The source / drain contact pins are typically connected to source / drain silicide regions formed by forming contact openings to expose source / drain regions, depositing a metal layer, depositing a barrier layer over the metal layer, performing anneals to place the metal layer in reaction with the source / drain regions, filling a metal such as tungsten or cobalt into the remaining contact opening, and performing a chemical mechanical polishing (CMP) process to remove excess metal.With regard to the prior art, reference is made to the publications DE 199 60 503 B4, US 2010 / 0 171 169 A1 and U.S. Pat. No. 5,918,118 A.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description when read with the accompanying figures. It should be appreciated that, in accordance with standard practices in the industry, various features are not drawn to scale. In fact, for clarity, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1-8, 9A, 9B, 9C, 10-18, and 24 are perspective and cross-sectional views of intermediate stages in forming a transistor and the respective contact pins, in accordance with some embodiments. FIGS. 19 through 23 are cross-sectional views of intermediate stages in forming a transistor and the respective contact pins, in accordance with some embodiments. FIG. 25 illustrates a process flow for forming a transistor, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Hereinafter, concrete examples of the components and arrangements will be described in order to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. The formation of a first element over or on a second element in the description that follows may include, for example, embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "underlying", "under", "lower", "overlying", "upper", and the like may be used herein to facilitate the description to describe the relationship of an element or feature to one or more other element(s) or feature(s) as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein may also be interpreted accordingly.A fin field effect transistor (FinFET)) and the method of forming the same are provided according to various embodiments. The intermediates in forming the FinFET are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, like reference numerals are used to designate like elements. According to some embodiments of the present disclosure, a FinFET and the corresponding contact pins are formed. The formation of the contact pins includes etching one or more dielectric layer(s) to form an opening and performing a thermal soak process using a silicon-containing process gas to add silicon to the exposed surfaces of the dielectric layer(s). The impregnation process may be skipped if the exposed surfaces of the dielectric layer(s) already contain enough silicon. Then, plasma treatment is performed on the surface using hydrogen (H 2) and nitrogen (N 2) as process gases so that nitrogen atoms are bonded to the silicon atoms. Then, an application process is performed to apply metal into the opening so that ultra-thin Si-N covalent metal bonds are formed. In the resulting contact pin, no barrier layer (such as a TiN barrier layer) is formed. Accordingly, the widths of the resulting contact pins are increased. By forming the ultra-thin Si-N metal bonds and thus eliminating the barrier layer, the resistance of the contact pins is reduced.Embodiments are described with respect to a specific context, namely the formation of contact pins. The concept of the discussed embodiments may also be applied to the structure and processing of other structures, including, and not limited to, the formation of metal lines, metal vias, etc. Embodiments discussed herein are intended to provide examples for facilitating the manufacture or use of the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that may be made while remaining within the contemplated scope of the various embodiments. Like reference numerals and characters in the figures below refer to like components. Although method embodiments are discussed as being performed in a particular order, other method embodiments may be performed in any logical order.FIGS. 1-8, 9A, 9B, 10-18, and 24 illustrate perspective and cross-sectional views of the intermediate stages in forming a FinFET, in accordance with some embodiments of the present disclosure. The respective processes are also schematically illustrated in the process flow shown in FIG. 25.FIG. 1 illustrates a perspective view of an initial structure formed on wafer 10. Wafer 10 includes substrate 20. substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed from other semiconductor materials. Substrate 20 may be doped with a p-type or an n-type impurity. Isolation regions 22, such as shallow trench isolation (STI) regions, may be formed to extend from a top surface of substrate 20 into substrate 20. The respective process is illustrated as process 202 in process flow 200 shown in FIG. 25. The portions of the substrate 20 between adjacent STI regions 22 are referred to as semiconductor strips 24. The top surfaces of the semiconductor strips 24 and the top surfaces of the STI regions 22 may be substantially planar with respect to each other, in accordance with some embodiments. According to some embodiments of the present disclosure, semiconductor strips 24 are portions of the original substrate 20, and thus the material of the semiconductor strips 24 is the same as that of the substrate 20. Accordingly, semiconductor stripes 24 are formed of a semiconductor material different from that of the substrate 20. In some embodiments, semiconductor strips 24 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.STI regions 22 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be an deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), or the like. STI regions 22 may also include a dielectric material over the liner oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like.Referring to FIG. 2, the STI regions 22 are recessed such that the top portions of the semiconductor strips 24 protrude higher than the top surfaces 22A of the remaining portions of the STI regions 22 to form protruding fins 24'. The respective process is illustrated as process 204 in the process flow 200 shown in FIG. 25. The etching may be performed using a dry etching method using HF 3 and NH 3 as the etching gases. Plasma may be generated during the etching process. Argon may also be present. According to alternative embodiments of the present disclosure, the recess of the STI regions 22 is performed using a wet etching process. The etching chemical may include, for example, HF.In the embodiments illustrated above, the fins may be patterned by any suitable method. The fins may be patterned using, for example, one or more photolithography processes, including dual pattern or multi-pattern processes. In general, dual pattern or multi-pattern processes combine photolithography and self-aligning processes, which allows patterns to be generated that have, for example, smaller pitches than otherwise achieved using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to pattern the fins.Referring to FIG. 3, dummy gate stack 30 is formed to extend on the top surfaces and sidewalls of (protruding) fins 24'. The respective process is illustrated as process 206 in the process flow 200 shown in FIG. 25. Dummy gate stacks 30 may include dummy gate dielectrics 32 and dummy gate electrodes 34 over the respective dummy gate dielectrics 32. Dummy gate electrodes 34 may be formed using polysilicon, for example, and other materials may also be used. Each of the dummy gate stacks 30 may also include a (or a plurality of) hard mask layer(s) 36 over dummy gate electrodes 34. Hard mask layers 36 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or multiple layers thereof. Dummy gate stacks 30 may traverse a single or a plurality of protruding fins 24' and / or STI regions 22. Dummy gate stacks 30 also have longitudinal directions perpendicular to the longitudinal directions of protruding fins 24'.Next, gate spacers 38 are formed on the sidewalls of the dummy gate stacks 30. According to some embodiments of the present disclosure, gate spacers 38 are formed of one or more dielectric material(s), such as silicon nitride, silicon carbon nitride, or the like, and may have a single layer structure or a multilayer structure including a plurality of dielectric layers.An etching step is then performed to etch the portions of protruding fins 24' not covered by dummy gate stack 30 and gate spacers 38, resulting in the structure shown in FIG. 4. The respective process is illustrated as process 208 in process flow 200 shown in FIG. 25. The recess may be anisotropic and thus the portions of the fins 24' immediately below dummy gate stacks 30 and gate spacers 38 are protected and are not etched. The top surfaces of the recessed semiconductor strips 24 may be lower than the top surfaces 22A of the STI regions 22, in accordance with some embodiments. Recesses 40 are located on the opposite sides of the dummy gate stacks 30.Next, as shown in FIG. 5, epitaxial regions (source / drain regions) 42 are formed by selectively growing (by epitaxy) a semiconductor material in recesses 40. The respective process is illustrated as process 210 in the process flow 200 shown in FIG. 25. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or an n-type impurity may be doped in situ with the process of epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown. According to alternative embodiments of the present disclosure, epitaxy regions 42 include III-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After recesses 40 are filled with epitaxy regions 42, the further epitaxial growth of epitaxy regions 42 causes epitaxy regions 42 to extend horizontally and facilities may form facilities. The further growth of the epitaxy regions 42 may also cause adjacent epitaxy regions 42 to merge with each other. Cavities (air gaps) 44 may be created. According to some embodiments of the present disclosure, the formation of epitaxy regions 42 may be completed when the upper surface of the epitaxy regions 42 is still wavy or when the upper surface of the merged epitaxy regions 42 has become planar, which is achieved by further growth on the epitaxy regions 42 as shown in FIG. 6.According to alternative embodiments, plating source / drain regions are formed instead of etching protruding fins 24' and then epitaxially growing source / drain regions. According to these embodiments, as shown in FIG. 3, the protruding fins 24' are not recessed and epitaxial regions are grown on protruding fins 24' to form source / drain regions. The material of epitaxial regions may be similar to the material of epitaxial semiconductor material 42 as shown in FIG. 5, depending on whether the resulting FinFET is a p-type or an n-Tp FinFET. Accordingly, the resulting source / drain regions 42 include protruding fins 24' and the epitaxial regions grown on the sidewalls and top surfaces of the protruding fins 24'. Implantation may be performed (or may not be) to implant an n-type impurity or a p-type impurity. The adjacent plating source / drain regions may also merge with or remain separated from each other.After the epitaxy step, epitaxy regions 42 may be further implanted with a p-type or an n-type impurity to form source and drain regions also indicated using reference number 42. According to alternative embodiments of the present disclosure, the implantation step is skipped when epitaxy regions 42 are in situ doped with the p-type or n-type impurity during epitaxy.FIG. 7 illustrates a perspective view of the structure after formation of contact etch stop layer (CESL)) 46 and inter-layer dielectric (ILD)) 48, which is illustrated as process 212 in the process flow 200 shown in FIG. 25. CESL 46 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 48 may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition process. ILD 48 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based dielectric material, such as silicon oxide (formed using, for example, tetra ethyl ortho silicate (TEOS) as the process gas), phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), or the like. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, may be performed to smooth the top surfaces of the ILD 48, dummy gate stacks 30, and gate spacers 38 together.Next, dummy gate stacks 30 including hard mask layers 36, dummy gate electrodes 34, and dummy gate dielectrics 32 are replaced with replacement gate stacks 56 including metal gate electrodes 54 and gate dielectrics 52, as shown in FIG. 8. The respective process is illustrated as process 214 in the process flow 200 shown in FIG. 25. In the formation of replacement gate stacks 56, hard mask layers 36, dummy gate electrodes 34, and dummy gate dielectrics 32 are first removed in one or a plurality of etching processes as shown in FIG. 7, resulting in formation of trenches / openings between gate spacers 38. The top surfaces and the sidewalls of the protruding semiconductor fins 24' are exposed to the resulting trenches.Next, (replacement) gate dielectric layers 52 are formed that extend into the trenches between gate spacers 38. According to some embodiments of the present disclosure, each of the gate dielectric layers 52 includes an intermediate layer (IL)) as its lower part that is in contact with the exposed surfaces of the corresponding protruding fins 24'. The IL may include an oxide layer, such as a silicon oxide layer formed by thermal oxidation of the protruding fins 24', a chemical oxidation process, or a deposition process. Gate dielectric layer 52 may also include a high-k dielectric layer formed over the IL. The high-k dielectric layer may include a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9 and may be higher than about 7.0. the high-k dielectric layer is formed as a conformal layer and extends on the sidewalls of protruding fins 24' and the sidewalls of gate spacers 38.With continued reference to FIG. 8, gate electrodes 54 are formed over gate dielectrics 52, where gate electrodes 54 include conductive sub-layers. The sub-layers are not shown separately, although the sub-layers are distinguishable from each other. The deposition of the sub-layers may be performed using one or more conformal deposition method(s), such as ALD or CVD.The stacked conductive layers may include a diffusion barrier layer and a work function layer(s) (or more) over the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layer determines the work function of the gate and includes at least one layer or a plurality of layers formed of different materials. The material of the work function layer is selected according to whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, if the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiA1) layer over the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer, a TiN layer over the TaN layer, and a TiA1 layer over the TiN layer. After the work function layer(s) are applied, a barrier layer, which may be another TiN layer, is formed.The deposited gate dielectric layers and conductive layers are formed as conformal layers that extend into the trenches and include some portions over ILD 48. Next, a metallic material is deposited to fill the remaining trenches between gate spacers 38. The metallic material may be formed of tungsten or cobalt, for example. A planarization process, such as a CMP process or a mechanical grinding process, is then performed so that the portions of the gate dielectric layers, conductive sub-layers, and the metallic material over ILD 48 are removed. This forms metal gate electrodes 54 and gate dielectrics 52. Gate electrodes 54 and gate dielectrics 52 are referred to in combination as replacement gate stacks 56. The top surfaces of replacement gate stacks 56, gate spacers 38, CESL 46, and ILD 48 may be substantially coplanar at this time.FIG. 8 illustrates the formation of the (self-aligning) hard masks 58, in accordance with some embodiments. The respective process is illustrated as process 216 in the process flow 200 shown in FIG. 25. The formation of the hard mask 58 may include performing an etching process to recess gate stacks 56 such that recesses are formed between gate spacers 38, filling the recesses with a dielectric material, and then performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the dielectric material. Hard masks 58 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbon nitride, or the like.FIG. 9A illustrates the formation of source / drain contact openings 60. The formation of contact openings 60 includes etching ILD 48 to expose the underlying portions of CESL 46 and then etching the exposed portions of CESL 46 to uncover epitaxial regions 42. According to some embodiments of the present disclosure, as illustrated in FIG. 9A, gate spacers 38 are spaced apart from the nearest contact openings 60 by some remaining portions of the ILD 48. According to other embodiments, the sidewalls of the contact openings 60 are exposed towards the contact openings 60.FIG. 9B illustrates a cross-sectional view showing the reference cross-section 9B- 9B in FIG. 9A. FIG. 9C illustrates a cross-sectional view showing the reference cross-section 9C- 9C in FIG. 9A. In FIG. 9C, the levels of the top surfaces 22A and bottom surfaces 22B of STI regions 22 are illustrated and semiconductor fins 24' overlie top surfaces 22A. The subsequently illustrated FIGS. 10 to 18 illustrate subsequent processes, and the illustrated cross sections in FIGS. 10 to 18 are the same as the reference cross section 9C- 9C in FIG. 9A.Referring to FIG. 10, metal layer 62 (such as a titanium or cobalt layer) is deposited, for example, using physical vapor deposition (PVD)) or similar process. The respective process is illustrated as process 220 in the process flow 200 shown in FIG. 25. Metal layer 62 is a conformal layer and extends onto the top surface of source / drain regions 42 and the sidewalls of ILD 48 and CESL 46, the sidewalls of which are exposed to openings 60. Then, an annealing process is performed to form source / drain silicide regions as shown in FIG. 11. The respective process is illustrated as process 222 in the process flow 200 shown in FIG. 25. The annealing process may include a rapid thermal anneal (RTA) annealing process, a furnace annealing process, or the like. Accordingly, the lower portion of metal layer 62 reacts with source / drain region 42 to form silicide regions 64. The sidewall portions of the metal layer 62 are retained after the silicide process. In some embodiments, the bottom portion of metal layer 62 is fully silicided and the resulting silicide regions 63 are exposed to openings 60. In some embodiments, a portion of metal layer 62 may remain overlapping and in contact with silicide regions 64.FIG. 12 illustrates a thermal soak process 66 performed using a silicon-containing process gas, such as silane (SiH 4), disilane (Si 2 H 6), dichlorosilane (DCS, H 2 SiCl 2) or the like. The respective process is illustrated as process 224 in the process flow 200 shown in FIG. 25. Carrier gases such as argon may be added. The thermal impregnation process can be carried out without plasma. According to some embodiments of the present disclosure, the pressure of the thermal soak process is in the range between about 1.33 kPa and about 133 Pa (about 10 Torr and about 100 Torr). The temperature of the wafer 10 may be higher than about 200° C. and may be in the range between about 250° C. and about 350° C. The thermal soak time may be in the range between about 30 seconds and about 120 seconds.The elevated temperature in the thermal soak results in dissociation of the silicon-containing process gas, resulting in a monosilicon layer 68 (or multiple monolayers such as 2, 3, 4, or 5 monosilicon layers) that adhere to the exposed surfaces of the wafer 10. The thickness T 1 of the silicon layer 68 may be less than about 1 nm. As shown in FIG. 12, silicon layer 68 may be formed on the top surface of source / drain silicon regions 64 and metal layer 62.FIG. 13 illustrates plasma treatment process 70. According to some embodiments, the plasma treatment process 70 is performed using process gases comprising hydrogen (H 2) and a nitrogen-containing gas. The nitrogen-containing gas may comprise N 2. Other types of nitrogen-containing gases may also be used, such as ammonia (NH 3). The treatment is carried out with the plasma turned on. Direct plasma may also be used, wherein the plasma is generated in the same process chamber in which wafer 10 is also placed for the plasma treatment process. According to some embodiments of the present disclosure, the flow rate of hydrogen is in the range between about 10 sccm and about 50 sccm, and the flow rate of the nitrogen-containing gas is in the range between about 10 sccm and about 50 sccm. The treatment time may be in the range between about 100 seconds and about 150 seconds. The temperature of the wafer 10 during the plasma treatment may be room temperature (such as about 21° C.) or it may be elevated and in the range between about 400° C. and about 450° C.In the plasma treatment process, the hydrogen has a function of performing a reduction reaction on silicon atoms and thus generating Baumel bonds for the silicon atoms of the silicon layer 68. It is thereby easier for the nitrogen atoms in the nitrogen-containing gas to be bonded to the Baunel bonds of the silicon atoms. Accordingly, Si-N bonds are formed. This results in the formation of the SiN layer 72, which may be a mono-layer of Si-N, or may include multiple (such as two, three, four, or five) layers of SiN. The Si-N has good adhesion to the underlying metal layer 62 and also good adhesion to the metal region 73 (FIG. 14 ) formed later. The thickness T 2 of the SiN layer 72 may be less than about 1 nm. SiN layer 72 is also a conformal layer, where the horizontal portions and vertical portions have a thickness variation of less than about 20 percent, for example.FIG. 14 illustrates the formation of metallic material 73 including a metal seed layer and the overlying metal region. The respective process is illustrated as process 228 in the process flow 200 shown in FIG. 25. According to some embodiments, the metal seed layer is a cobalt layer or comprises cobalt. According to other embodiments, tungsten, copper, molybdenum, or the like may be used. The formation method may include physical vapor deposition (PVD)), ALD, or a PVD process followed by an ALD process. According to some embodiments, electrical-chemical plating (ECP) is performed to plate a metal region on the metal seed layer and fill the remaining contact openings 60. The material of the metal portion may be the same as or different from that of the metal seed layer, and may be selected from cobalt, tungsten, copper, molybdenum or the like, composite layers thereof, or alloys thereof.The metal seed layer forms covalent bonds with the previously formed Si-N bonds and thus Si-N metal bonds are formed which are conductive due to the small thickness of the Si-N bonds / layers. For example, when the metal seed layer includes or is formed from cobalt, Si-N-Co bonds (in the form of a thin layer) may be formed. Si-N-Co has good adhesion to the underlying metal layer 62, and thus the bonding of the contact pins 74 to metal layer 62 is excellent.According to some embodiments, in order to effectively form Si-N bonds and then bond the metal to the Si-N bonds, the processes shown in FIGS. 13 and 14 including the plasma treatment process (FIG. 13 ) and the formation of the metal seed layer (FIG. 14 ) are performed in situ in the same process chamber and without vacuum fracture therebetween. The plasma treatment performed in situ and the formation of the metal seed layer ensure that the Si-N bonds are not bonded to other elements, such as oxygen (e.g., to form Si-N-O bonds), so that Baumel bonds of Si-N are available for metal atoms to bond thereto. According to some embodiments, the thermal soak process (FIG. 12 ) is also performed in situ with the plasma treatment process (FIG. 13 ) and the formation of the metal seed layer (FIG. 14 ) such that a clean silicon layer is formed.In a subsequent process, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the metal layer 62 and metallic material 73, thereby leaving contact pins 74 as shown in FIG. 15. The respective process is illustrated as process 230 in process flow 200 shown in FIG. 25. A perspective view of the bottom portion of the structure shown in FIG. 15 is also shown in FIG. 24, except that etch stop layer 76 and ILD 78 are not shown in FIG. 24.With continued reference to FIG. 15, etch stop layer 76 is formed, in accordance with some embodiments of the present disclosure. Etch stop layer 76 may be formed of a silicon-containing material, such as SiN, SiCN, SiC, SiOCN, or the like. The formation method may include PECVD, ALD, CVD, or the like. Next, ILD 78 is formed over etch stop layer 76. The formation of etch stop layer 76 and ILD 78 is illustrated as process 232 in process flow 200 shown in FIG. 25. The material of ILD 78 may be selected from the same candidate material (and method) for forming ILD 481. ILD 798 may include, for example, silicon oxide, PSG, BSG, BPSG, or the like, including silicon therein. In some embodiments, ILD 78 is formed using PECVD, FCVD, spin-on coating, or the like.FIG. 16 illustrates the etching of ILD 78 and etch stop layer 76 to form upper source / drain contact openings 80A. The respective process is illustrated as process 234 in process flow 200 shown in FIG. 25. Moreover, ILD 78, etch stop layer 76, and hard masks 58 may be etched to form contact gate openings 80B. Gate openings 80A and source / drain contact openings 80B are collectively referred to as contact openings 80. Gate electrodes 54 and source / drain contact pins 74 are thus exposed to gate openings 80A and source / drain contact openings 80B, respectively.Next, another plasma treatment process 70' similar to the plasma treatment process shown in FIG. 13 is performed to form SiN layer 72'. The respective process is illustrated as process 236 in the process flow 200 shown in FIG. 25. According to some embodiments of the present disclosure, the plasma treatment process 70' is performed using a process gas comprising hydrogen (H 2) and nitrogen-containing gas. The nitrogen-containing gas may include N 2, ammonia (NH 3) or the like. The treatment is carried out with the plasma turned on. Direct plasma may also be used, wherein the plasma is generated in the same process chamber in which wafer 10 is also placed for the plasma treatment process. According to some embodiments of the present disclosure, the flow rate of hydrogen is in the range between about 10 sccm and about 50 sccm, and the flow rate of the nitrogen-containing gas is in the range between about 10 sccm and about 50 sccm. The treatment time may be in the range between about 100 seconds and about 150 seconds. The temperature of the wafer 10 during the plasma treatment may be room temperature (such as about 21° C.) or it may be elevated and in the range between about 400° C. and about 450° C.In some embodiments, no thermal soak process is performed using one or more silicon-containing processes between the formation of the openings 80 and the plasma treatment process 70'. Since ILD 78, etch stop layer 76, and hard masks 58 may be formed of silicon-containing materials, the silicon atoms in ILD 78, etch stop layer 76, and hard masks 58 are reduced by the hydrogen gas (in a reduction reaction) to form Baumel bonds for silicon atoms, and the Baumel bonds are then bonded to nitrogen atoms. Accordingly, Si-N bonds are formed. In these embodiments, the silicon atoms in the Si-N bonds are portions of the ILD 78, the etch stop layer 76, and the hard masks 58.According to alternative embodiments in which ILD 78, etch stop layer 76, and / or hard masks 58 do not contain silicon, or contain silicon, but the silicon atomic percentages are negligible, the thermal soak process is performed prior to plasma treatment process 70'. The respective process is illustrated as process 235 in the process flow 200 shown in FIG. 25. Process 235 is shown using a dashed box to indicate that it may be performed or skipped. The process conditions may be similar to those of the thermal soak process 66 in FIG. 12 and are therefore not repeated herein. The resulting structure is similar to that shown in FIG. 16, except that a silicon layer forms between SiN layer 72' and the dielectric layers including ILD 78, etch stop layer 76, and hard masks 58, silicon layer 68, as shown in FIG. 12. Due to the diffusion, the silicon layer is in the form of silicon compounds with adjacent layers such as ILD 78, etch stop layer 76, and hard masks 58. the portions of the silicon layer may be visible when the silicon atom percentage of the compounds of the respective portions is higher than any one of ILD 78, etch stop layer 76, and / or hard masks 58. the silicon layer may not be visible when the silicon atom percentage is high in SiN layer 72' and in ILD 78, etch stop layer 76, and hard masks 58. According to some embodiments of the present disclosure, the deposited silicon layer is converted to SiN layer 72' after the plasma treatment. SiN layer 72' according to these embodiments may extend on the top surfaces of contact pins 74 and gate electrodes 54.FIG. 17 illustrates the deposition of metallic material 82, which may be deposited using PVD, CVD, plating, combinations thereof, or the like, forming Si-N metal bonds with SiN layer 72'. The respective process is illustrated as process 238 in the process flow 200 shown in FIG. 25. Metallic material 82 may include cobalt, tungsten, molybdenum, copper, or alloys thereof. According to some embodiments of the present disclosure, at least the bottom portion (e.g., a seed layer) of metallic material 82 is formed in situ with the plasma treatment process 70' (FIG. 16 ) to ensure the effective formation of Si-N metal bonds. In a subsequent process, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of metallic material 82 and SiN layer 72' and thus form top contact pins 84. The resulting structure is shown in Fig. 18.As shown in FIG. 18, metal layer 62 forms a ring (in a plan view) surrounding metal region 73. Metal layer 62 and metal region 73 may be formed of the same metal or different metals. Si- and N-containing layers 72 are interposed between metal region 73 and metal layer 62, both of which are free of silicon therein when formed. Accordingly, in the final structure, Si- and N-containing layer 72 is considered to be a silicon- and nitrogen-rich layer, wherein both silicon and nitrogen have higher atomic percentages than in metal layer 62 and metal region 73, regardless of whether or not silicon and nitrogen diffuse in metal layer 62 and metal region 73 in subsequent processes. Due to the presence of the lower portion of layer 72 immediately above and in contact with silicide region 64, the percentage nitrogen atom content in layer 72 may be higher than that of the overlying metal region 73 and the underlying silicide region 64. In the illustrated embodiments, contact pins 74 do not include a deposited barrier layer (e.g., a TiN layer).In the embodiments shown in FIGS. 1-8, 9A, 9B, and 10-18, the metal layer 62 remains unremoved after the anneal process to form the silicide regions 64. Because the remaining metal layer 62 prevents the silicon atoms (if present) in ILD 48 and CESL 46 from being exposed to the plasma treatment process, the thermal soak process (FIG. 12 ) is formed to form a silicon layer 68. FIGS. 19 through 23 illustrate cross-sectional views of intermediate stages in the formation of a FinFET and the corresponding contact pins in accordance with some embodiments of the present invention, in which the exposed layer comprises silicon and thus the thermal soak process may be skipped. Unless otherwise indicated, the materials and the formation processes of the components in these embodiments are substantially the same as the same components indicated by the same reference numerals in the previous embodiments shown in FIGS. 1-8, 9A, 9B, and 10-18. The details regarding the forming process and the materials of the components shown in Figs. 19 to 23 will be therefore found in the explanation of the above embodiments.The initial process is substantially the same as that shown in FIGS. 1-8, 9A, 9B, 10 and 11 in which an annealing process for forming silicide regions 64 is performed. Next, the unreacted portions of the metal layer 62 are removed in an etching process, resulting in the structure shown in FIG. 19. Silicide regions 64 are not etched. The top surface and sidewalls of ILD 48 (and possibly the sidewalls of CESL 46) are thus exposed.Next, as shown in FIG. 20, plasma treatment process 70 is performed to form the SiN layer 72 (a silicon- and nitrogen-containing layer) formed by adhering nitrogen atoms to a surface layer of ILD and possibly CESL 46. In some embodiments, ILD 48 (and possibly CESL 46) is formed from a silicon-containing compound and therefore contains silicon. Accordingly, the plasma treatment process 70 is performed without a prior thermal impregnation process using a silicon-containing process gas. Since the silicon atoms in the Si-N bonds are portions of ILD 48 and perhaps CESL 46, the bonding of the SiN layer 72 to ILD 48 and CESL 46 is strong. The process conditions of the plasma treatment process 70 may be substantially the same as explained with reference to FIG. 13, and will not be repeated herein.According to other embodiments, the thermal soak process (using silicon-containing process gas) is also performed to add silicon atoms, followed by the plasma treatment process 70 in FIG. 13. The thermal soak process may be substantially the same as process 66 in FIG. 12. The thermal soak process may be performed when ILD 48 and CESL 46 do not contain silicon or when the percentage silicon atom content in ILD 48 and CESL 46 is low.FIG. 21 illustrates the formation of metallic material 73 that includes metallic material that may include cobalt, tungsten, molybdenum, copper, or the like. The metal atoms in the metallic material 73 are bonded with the Si-N bonds in the SiN layer 72 to form the Si-N metal covalent bonds. Since at least some of the silicon atoms in the Si-N metal bonds may be portions of the ILD 48 and CESL 46, the bonding of the metallic material 73 to the ILD 48 and CESL 46 is strong. No barrier layer (e.g., TiN layer) is formed before metal material 73 is deposited. FIG. 22 illustrates a planarization process for forming source / drain contact plugs 74.FIG. 23 illustrates the formation of etch stop layer 76, ILD 78, SiN layer 72', and contact pins 84.Experimental results have shown that the Ni-N metal (such as Si-N cobalt) covalent bonds have good thermal stability. In the thirty-minute endurance test at 400° C., no separation and no extrusion could be observed with the contact pins formed according to the embodiments. Also, no Co-N dissociation or delamination was observed. The resulting contact pins are free of barrier layers (formed of TiN, for example). Eliminating the barrier layers leads to the lateral dimension of the low resistance parts of the contact pins being increased, for example by 2 nm or more. The overall resistance of the contact pins is reduced.The embodiments of the present disclosure have some advantageous features. The plasma treatment and possibly the thermal impregnation process do not require any barrier layers. This leads to an increase in the lateral sizes of the contact pins and a reduction in the resistance. The adhesion of the contact pins to the ILD and CESL is good due to the excellent adhesion of the Si-N metal bonds to dielectric layers and metals.According to some embodiments of the present disclosure, a method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer; forming a metal layer extending into the opening; performing an annealing process such that a lower portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source / drain region; performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon and nitrogen-containing layer; and depositing a metallic material on the silicon and nitrogen-containing layer. In an embodiment, the method further includes, prior to the plasma treatment process, performing a thermal soak process on the substrate using a silicon-containing process gas. In one embodiment, the thermal impregnation process is performed using silane as a portion of the process gas. In an embodiment, the dielectric layer comprises silicon, and wherein when the plasma treatment process is performed, a sidewall of the dielectric layer is exposed to the opening and exposed to the hydrogen gas and the nitrogen-containing gas. In an embodiment, the plasma treatment process and at least a portion of the applying of the metallic material are performed in situ without vacuum fracture therebetween. In an embodiment, the applying of the metallic material comprises applying a metal seed layer and the applying of the metal seed layer and the plasma treatment process are performed in situ without vacuum fracture therebetween. In one embodiment, the nitrogen-containing gas comprises nitrogen (N 2) gas. In one embodiment, the plasma treatment process results in a monolayer of Si-N bonds to be formed.According to some embodiments of the present disclosure, a method includes performing a thermal soak process using a silicon-containing gas to deposit a silicon layer on a surface of an underlying layer; performing a plasma treatment process on the silicon layer to form a silicon- and nitrogen-containing layer; and depositing a metallic layer on the silicon- and nitrogen-containing layer to form Si-N metal bonds, wherein the plasma treatment process and the depositing of the metallic layer are performed in situ in a same process chamber without vacuum fracture therebetween. In one embodiment, the silicon layer is deposited as a monolayer. In one embodiment, the Si-N metal bonds are formed as a monolayer. In one embodiment, the thermal impregnation process is performed using silane as a portion of the silicon-containing gas. In an embodiment, the plasma treatment process is performed using hydrogen (H 2) and nitrogen (N 2) as process gases. In one embodiment, no vacuum fracture occurs between the thermal impregnation process and the application of the metallic layer. In one embodiment, applying the metallic layer comprises applying a cobalt layer.According to some embodiments of the present disclosure, an integrated circuit structure includes a dielectric layer; a metal ring contacting sidewalls of the dielectric layer; a metal region surrounded by the metal ring; and a silicon- and nitrogen-rich layer between the metal ring and the metal region, wherein a silicon atom percentage in the silicon- and nitrogen-rich layer is higher than silicon atom percentages in the metal ring and the metal region, and a first nitrogen atom percentage in the silicon- and nitrogen-rich layer is higher than second nitrogen atom percentages in the metal ring and the metal region. In an embodiment, the integrated circuit structure includes a semiconductor region underlying the dielectric layer; a metal silicide region atop the semiconductor region, the metal silicide region being overlapped by the metal region; and a nitrogen-rich layer overlapping and contacting the metal silicide region, wherein a third nitrogen atom percentage in the nitrogen-rich layer is higher than a fourth nitrogen atom percentage in the metal silicide region and the second nitrogen atom percentage in the metal region. In one embodiment, the metal ring and the metal region are formed from different metals. In one embodiment, the metal ring comprises titanium and the metal portion comprises cobalt. In an embodiment, the dielectric layer comprises a silicon-based dielectric material.

Claims

A method comprising: etching a dielectric layer (46, 48) of a substrate (10) to form an opening (60) in the dielectric layer; forming a metal layer (62) extending into the opening (60); performing an annealing process such that a lower portion of the metal layer (62) reacts with a semiconductor region (42) underlying the metal layer (62) to form a source / drain region (64); performing a plasma treatment process on the substrate (10) using a process gas comprising hydrogen gas and a nitrogen-containing gas to form a silicon and nitrogen-containing layer (72); and depositing a metallic material (73) on the silicon and nitrogen-containing layer (72).The method of claim 1, further comprising: prior to the plasma treatment process, performing a thermal soak process on the substrate using a silicon-containing process gas.The method of claim 2, wherein the thermal impregnation process is performed using silane as a portion of the process gas.The method of any preceding claim, wherein the dielectric layer (46, 48) comprises silicon, and wherein when the plasma treatment process is performed, a sidewall of the dielectric layer is exposed to the opening (60) and exposed to the hydrogen gas and the nitrogen-containing gas.The method of any preceding claim, wherein the plasma treatment process and at least a portion of the applying of the metallic material (73) are performed in situ without vacuum fracture therebetween.The method of claim 5, wherein the applying of the metallic material (73) comprises applying a metal seed layer, and the applying of the metal seed layer and the plasma treatment process are performed in situ without vacuum fracture therebetween.The method of any preceding claim, wherein the nitrogen-containing gas comprises nitrogen (N 2)- gas.The method of any preceding claim, wherein the plasma treatment process results in a monolayer (72) of Si-N bonds to be formed.A method comprising: performing a thermal soak process (66) using a silicon-containing gas to deposit a silicon layer (68) on a surface of an underlying layer (42, 48); performing a plasma treatment process on the silicon layer 68 to form a silicon and nitrogen-containing layer (72); and depositing a metallic layer (73) on the silicon and nitrogen-containing layer (72), wherein the plasma treatment process and the depositing of the metallic layer (73) are performed in situ in a same process chamber without vacuum fracture therebetween.The method of claim 9, wherein the silicon layer (68) is deposited as a monolayer.The method of claim 9 or 10, wherein the metallic layer (73) and the silicon and nitrogen containing layer (72) form Si-N metal bonds.The method of any of claims 9 to 11, wherein the thermal soak process (66) is performed using silane as a portion of the silicon-containing gas.The method according to any one of claims 9 to 12, wherein the plasma treatment process is performed using hydrogen (H 2) and nitrogen (N 2) as process gases.Method according to one of Claims 9 to 13, wherein no vacuum fracture occurs between the thermal impregnation process (66) and the application of the metallic layer (73).The method of any of claims 9 to 14, wherein applying the metallic layer (73) comprises applying a cobalt layer.An integrated circuit structure comprising: a dielectric layer (46, 48); a metal ring (62) contacting side walls of the dielectric layer (46, 48); a metal region (73) surrounded by the metal ring (62); and a silicon and nitrogen rich layer (72) between the metal ring (62) and the metal region (73), wherein a silicon atom percentage in the silicon and nitrogen rich layer (72) is higher than silicon atom percentages in the metal ring (62) and the metal region (73), and a first nitrogen atom percentage in the silicon and nitrogen rich layer (72) is higher than second nitrogen atom percentages in the metal ring (62) and the metal region (73), wherein no barrier layer, in particular no TiN layer, is provided between the metal region (73) and the metal ring (62).The integrated circuit structure of claim 16, further comprising: a semiconductor region (42) underlying the dielectric layer (46, 48); a metal silicide region atop the semiconductor region (42), the metal silicide region being overlapped by the metal region; and a nitrogen-rich layer overlapping and contacting the metal silicide region, wherein a third nitrogen atom percentage in the nitrogen-rich layer is higher than a fourth nitrogen atom percentage in the metal silicide region and the second nitrogen atom percentage in the metal region.The integrated circuit structure according to claim 16 or 17, wherein the metal ring (62) and the metal region (73) are formed of different metals.The integrated circuit structure of claim 16 or 17, wherein the metal ring (62) comprises titanium and the metal region (73) comprises cobalt.The integrated circuit structure of any of claims 16 to 19, wherein the dielectric layer (46, 48) comprises a silicon-based dielectric material.

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