Semiconductor device with improved heat dissipation and method for manufacturing the same

Abstract

Method comprising: forming a solder layer (45, 80, 85) on a surface of one or more chips (15); positioning a lid (65) over the solder layer (45, 80, 85) on each of the one or more chips (15); applying heat and pressure (75) to melt the solder layer (45, 80, 85) and attaching each lid (65) over the solder layer (45, 80, 85) to a corresponding chip (15), wherein the solder layer (45, 80, 85) has a thermal conductivity of ≥ 50 W / mK;Prior to forming the solder layer (45, 80, 85) on the surface of the one or more chips (15), forming an integrated fan-out wafer on a frame (30), wherein the integrated fan-out wafer has the one or more chips (15), forming several bond pads (40) on the surface of the one or more chips (15), and forming a metal column (90) on each of the several bond pads (40), wherein the solder layer (45, 80, 85) comprises solder beads formed on each of the metal columns (90).

Description

BACKGROUNDHeat dissipation in an advanced package becomes more and more difficult, especially in high performance and artificial intelligence applications, when the power consumption exceeds 500 W. The conventional approach is to use a thermal interface material (TIM) material between a chip and the lid to improve heat dissipation. The thermal conductivity of a conventional thermal conductive material is usually less than 10 W / mK, which may limit the operating performance of a package to less than 500 W. The publication US 2003 / 0 080 411 A1 relates to a semiconductor package comprising a chip having an active surface and a rear side and also a substrate. The chip is electrically connected to the top surface of the substrate. A lid is thermally coupled to the back side of the chip.In the document US 2018 / 0 166 356 A1, an IC package is disclosed comprising a carrier with a recess, IC chips coupled to the carrier within the recess, and a thermally conductive material between the IC chips and the carrier within the recess.JP 2001-298 131 A relates to a chip package structure for forming a direct heat path of the welded joint from a chip surface to a cover. U.S. Pat. No. 9,064,879 B2 describes packaging methods and structures for semiconductor components which use a die attach film. In particular, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) including a polymer over the carrier wafer. A plurality of chips are attached to the DAF, and the plurality of chips are packaged. At least the carrier wafer is removed from the packaged chips and the packaged chips are singulated.In U.S. Pat. No. 9,337,098 B1, semiconductor chips are singulated from a semiconductor wafer having a rear-side metal layer by placing the semiconductor wafer on a carrier strip, the rear-side metal layer adjoining the carrier strip. Dicing lines are formed through the semiconductor wafer to expose the back side metal layer within the dicing lines, and portions of the back side metal layer are separated using a fluid.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure may best be understood from the following detailed description read in conjunction with the accompanying drawings. It is emphasized that, in accordance with the practice common in the industry, various features are not drawn to scale and are used for purposes of illustration only. Indeed, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIGS. 3A and 3B illustrate a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 4 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 5 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 6 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 7 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 8 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 9 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 10 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 11 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 12 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 13 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 14 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 15 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 16 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 17 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 18 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 19 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 20 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 21 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 22 shows a detailed view of a column according to an embodiment of the present disclosure. FIG. 23 shows a view of an array of columns according to an embodiment of the present disclosure. FIG. 24 shows a detailed view of a column according to an embodiment of the present disclosure. FIG. 25 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 26 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 27 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 28 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 29 illustrates a sequential step of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 30 shows a diagram in which the thermal conductivity of a material is plotted against a normalized temperature.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the submitted subject matter. Specific examples of components and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and should not be considered limiting. For example, the formation of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Moreover, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not dictate a relationship between the various embodiments and / or configurations in itself.Further, spatially relative terms such as "bottom," "below," "lower," "top," "above," "upper," and the like may be used herein to facilitate the description to describe the relationship of an element or feature to another element(s) or feature(s) illustrated in the figures. The spatially relative terms are intended to include other orientations of the device being used or operated in addition to the orientation depicted in the figures. The device may be otherwise (rotated 90 degrees or oriented in other orientations) oriented and the spatially relative descriptors used herein may likewise be interpreted accordingly. Moreover, the term "made of" may mean either "comprising" or "consisting of.". In the present disclosure, an expression "one of A, B, and C" means "A, B, and / or C" (A, B, C, A, and B, A and C, Federal C, or A, B, and C), and does not mean an element of A, an element of B, and an element of C, unless otherwise described.It is desirable to increase the thermal conductivity of the thermal conductive material to more than 10 W / mK to operate packages of semiconductor devices of more than 500 W. Embodiments of the present disclosure use materials containing high thermal conductivity metals, e.g., -Cu (K Cu ~400 W / mK) and Sn (K Sn ~65 W / mK), to provide a thermal conductive material having thermal conductivities superior to a conventional thermal conductive material (<10 W / mK). By using materials with high thermal conductivity between chip and cover, the operating performance and the operating behavior can be significantly improved.FIGS. 1-9 illustrate a sequential step method 10 of manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 1, a semiconductor device such as a fan-out (Integrated Fan Out, InFO) integrated wafer is provided on a frame. The InFO wafer includes a plurality of chips 15, such as systems on a chip (SOC), disposed on a redistribution layer 20 and embedded in a molding 25, e.g., a thermosetting resin. The InFO wafer is placed on a frame 30 via metal pillars or solder bumps 35. In some embodiments, the chip 15 is a fan-out integrated chip, a system on a chip, a wafer level chip scale package, or a chip on wafer on substrate.In some embodiments, redistribution layer 20 is formed with one or more metal layers and one or more dielectric intermetallic layers. The dielectric intermetallic layers are disposed between the metal layers. The dielectric intermetallic layers have conductive features, such as vias, disposed in a dielectric material and connected to conductive features, such as conductive traces in the metal layers. In some embodiments, the dielectric material of the metal layers and the dielectric intermetallic layers are, for example, a silicon oxide, nitride, carbide, polymer, or other insulating or dielectric material and may be formed by a chemical vapor deposition (CVD), spin-on, or other deposition process. The conductive features may be formed using a damascene or dual damascene process, in which openings are etched into the dielectric layer of redistribution layer 20, and a conductive material such as copper, aluminum, or the like is deposited in the opening and subsequently planarized. The redistribution layer is constructed by forming multiple metal layers and intermetallic dielectric layers, where the conductive traces and vias branch electrical connections from structures on the substrate 50 on which the chip 15 is subsequently placed (see FIG. 5 ) to the top of the redistribution layer 20.A pattern of bond pads 40 is formed on the die surface as shown in FIG. 2. In some embodiments, bond pads 40 are formed as a pattern of spaced apart regions. In some embodiments, bond pads 40 are formed on the surface of the die 15, as shown in FIGS. 3A and 3B. FIG. 3A shows a plan view of the device 15 and FIG. 3B shows a cross-sectional view of the device 15 along the line A-A of FIG. 3A. In some embodiments, bond pads 40 are formed on the surface of chip 15 in an array. In some embodiments, bond pads 40 are formed from a suitable conductive metal, for example, aluminum, copper, silver, gold, nickel, tungsten, titanium, alloys thereof, and / or multilayers thereof. Bond pads 40 are formed by a suitable metal deposition process, such as electroplating or electroless plating, physical vapor deposition (PVD) with sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, or electron beam evaporation.A solder layer 45 is then formed over each of the bond pads 40, as shown in FIG. 4. In this embodiment, the solder layer 45 is formed in the form of solder bumps. In some embodiments, the solder layer 45 is made of a tin-containing alloy, such as PbSn, AgSn, SnAgCu, CuSnNi, AgCuSnSn, AuSn, or CuSn. In some embodiments, the PbSn solder has a thermal conductivity of about 50 W / mK, the AgSn solder has a thermal conductivity of about 78 W / mK, the SnAgCu solder has a thermal conductivity of about 60 W / mK, the CuSnNi has a thermal conductivity of about 64 W / mK, the AgCuSnSn solder has a thermal conductivity of about 57 W / mK, the AuSn solder has a thermal conductivity of about 57 W / mK, and the CuSn solder has a thermal conductivity of about 65 W / mK. In some embodiments, individual chips 15 are separated by a dicing process before or after forming the solder layer 45.Next, individual chips 15 are removed from the frame 30 and attached to a substrate 50 such as a ball grid array substrate as shown in FIG. 5. The ball grid array substrate 50 has a first main surface 50A to which the chip 15 is attached via the solder bumps 35 on the redistribution layer 20, and a second main surface 50B including an array of solder bumps 55. In some embodiments, conductive vias or wiring layers are formed in the substrate that electrically connect the solder bumps 35 on the redistribution layer to solder bumps on the second major surface 50B of the substrate 50.In some embodiments, an underfill material 60 is formed between the die 15 and the substrate 50, as shown in FIG. 6. The underfill material 60 fills the area between the solder bumps 35 on the redistribution layer 20. In some embodiments, the underfill material 60 is an epoxy, such as a silica filled epoxy, a polyimide, or other suitable insulating material. The underfill material 60 increases mechanical reliability by distributing stress across the top of the ball grid array substrate 50, rather than concentrating in the solder bumps 35. Moreover, the underfill material 60 provides encapsulation against moisture and contaminants in the external environment.Subsequently, as shown in FIG. 7, a lid 65 is positioned over the solder layer 45. The lid 65 functions as a heat sink to remove heat generated by the chip 15. The lid 65 is made of a thermally conductive material. In some embodiments, the lid is made of aluminum, copper, nickel, cobalt, and alloys thereof, or other thermally conductive materials. In some embodiments, the lid is made of a composite material, for example, silicon carbide, aluminum nitride, graphite, and the like.Then, the lid 65 is heated and pressed into close contact with the chip 15 via the solder layer 45 by, for example, a thermal pressure bonding head 145 as shown in FIG. 8, thereby forming a semiconductor device in which the lid 65 is bonded to the chip 15 as shown in FIG. 9. During application of the heat and pressure 75 to the lid 65, the solder layer 45 flows to form a continuous solder layer 70 between the lid 65 and the chip 15. In some embodiments, the thermal pressure bonding head 145 heats the solder layer 45 to a temperature of about 150° C. to about 400° C. In some embodiments, the solder layer 45 is heated to a temperature of about 200° C. to about 300° C. In one embodiment, the solder layer 45 is heated to a temperature of about 250° C. In some embodiments, the pressure applied while the lid 65 is pressed into contact with the chip 15 is in the range of about 50 kPa to about 20 MPa. In some embodiments, the pressure applied is in the range of about 300 kPa to about 3 MPa. In some embodiments, the pressure applied is in the range of about 500 kPa to about 2 MPa. During application of the heat and pressure, the solder layer 45 flows to surround and encapsulate the bond pads 40. The continuous solder layer 70 acts as an improved thermal interface material (TIM) layer that has a higher thermal conductivity than conventional thermal conductive materials. Heat from the chip 15 is transferred to the lid 65 via the continuous solder layer 70. The lid 65 dissipates the heat of the chip 15 so that the chip 15 can operate at higher speeds and lower thermal stress.FIGS. 10-17 illustrate a method 155 including sequential steps for fabricating a semiconductor device, according to an embodiment of the present disclosure. As shown in FIG. 10, a semiconductor device such as a fan out (InFO) integrated wafer is provided on a frame. The process shown in FIG. 10 is the same as in FIG. 1. The InFO wafer includes a plurality of chips 15 such as systems on a chip (SOC) disposed on a redistribution layer 20 and embedded in a molding 25, e.g., a thermosetting resin. The InFO wafer is placed on a frame 35 via metal pillars or solder bumps 35. In some embodiments, the chip 15 is a fan-out integrated chip, a system on a chip, a wafer level chip scale package, or a chip on wafer on substrate.A continuous solder layer 80 is formed directly on the chips as shown in Figure 11. In contrast to the previously disclosed method, a plurality of bond pads are not formed on the top side of the chips 15. In some embodiments, the solder layer 45 is made of a tin-containing alloy, such as PbSn, AgSn, SnAgCu, CuSnNi, AgCuSnSn, AuSn, or CuSn. In some embodiments, the PbSn solder has a thermal conductivity of about 50 W / mK, the AgSn solder has a thermal conductivity of about 78 W / mK, the SnAgCu solder has a thermal conductivity of about 60 W / mK, the CuSnNi has a thermal conductivity of about 64 W / mK, the AgCuSnSn solder has a thermal conductivity of about 57 W / mK, the AuSn solder has a thermal conductivity of about 57 W / mK, and the CuSn solder has a thermal conductivity of about 65 W / mK. Subsequently, the individual chips 15 are separated by a dicing process as shown in FIG. 12.Next, individual chips 15 are removed from the frame 30 and attached to a substrate 50 such as a ball grid array substrate as shown in FIG. 13. The ball grid array substrate 50 has a first main surface 50A to which the chip 15 is attached via the solder bumps 35 on the redistribution layer 20, and a second main surface including an array of solder bumps 55. In some embodiments, conductive vias or wiring layers are formed in the substrate that electrically connect the solder bumps 35 on the redistribution layer to solder bumps on the second major surface 50B of the substrate 50.In some embodiments, an underfill material 60 is formed between the die 15 and the substrate 50, as shown in FIG. 14. The underfill material 60 fills the area between the solder bumps 35 on the redistribution layer 20. In some embodiments, the underfill material 60 is an epoxy, such as a silica filled epoxy, a polyimide, or other suitable insulating material. In some embodiments, the underfill material 60 encapsulates the chip.Next, as shown in FIG. 15, a lid 65 is positioned over the solder layer 80. The lid 65 functions as a heat sink to remove heat generated by the chip 15. The lid 65 is made of a thermally conductive material. In some embodiments, the lid is made of aluminum, copper, nickel, cobalt, and alloys thereof, or other thermally conductive materials.Subsequently, the lid 65 is heated, for example, by a thermal pressure bonding head 145 as shown in FIG. 16, and is pressed into close contact with the chip 15 via the solder layer 80, thereby forming a semiconductor device in which the lid 65 is bonded to the chip 15 as shown in FIG. 17. In some embodiments, the thermal pressure bonding head 14 heats the solder layer 80 to a temperature of about 150° C. to about 400° C. In some embodiments, the solder layer 80 is heated to a temperature of about 200° C. to about 300° C. In one embodiment, the solder layer 80 is heated to a temperature of about 250° C. During application of the heat and pressure 75 to the lid 65, the solder layer 80 flows and the solder layer 80 subsequently cures and bonds the lid 65 firmly to the chip 15 upon cooling. Heat from the chip 15 is transferred to the lid 65 via the solder layer 80 so that the chip 15 can operate at higher speeds and lower thermal stress. In some embodiments, a continuous bond pad layer is formed on the die 15 prior to forming the solder layer 80.FIGS. 18-28 illustrate a method 160 including sequential steps for fabricating a semiconductor device, according to an embodiment of the present disclosure. As shown in FIG. 18, a semiconductor device such as a fan out (InFO) integrated wafer is provided on a frame. The process shown in FIG. 18 is the same as in FIGS. 1 and 10. The InFO wafer includes a plurality of chips 15 such as on-chip systems (SOC) disposed on a redistribution layer 20 and embedded in a molding 25, e.g., a thermosetting resin. The InFO wafer is placed on a frame 30 via metal pillars or solder bumps 35. In some embodiments, the chip 15 is a fan-out integrated chip, a system on a chip, a wafer level chip scale package, or a chip on wafer on substrate.A pattern of bond pads 40 is formed on the die surface as shown in FIG. 19. In some embodiments, bond pads 40 are formed as a pattern of spaced apart regions. In some embodiments, bond pads 40 are formed on the surface of the die 15, as shown in FIGS. 3A and 3B. In some embodiments, bond pads 40 are formed from a suitable conductive metal, for example, aluminum, copper, silver, gold, nickel, tungsten, titanium, alloys thereof, and / or multilayers thereof. Bond pads 40 are formed by a suitable metal deposition process, such as electroplating or electroless plating, physical vapor deposition (PVD) with sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, or electron beam evaporation.Subsequently, spaced-apart conductive pillars 90 are formed over bond pads 40 as shown in FIG. 20. In some embodiments, the conductive pillars are formed by a suitable metal deposition process, such as electroplating or electroless plating, physical vapor deposition (PVD) with sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, and electron beam evaporation.Then, a solder layer 85 is formed over the conductive pillars 90, as shown in FIG. 20. In some embodiments, the solder layer 85 includes solder bumps or bumps formed over each conductive pillar 90. In some embodiments, the solder layer 85 is made of a tin-containing alloy such as PbSn, AgSn, SnAgCu, CuSnNi, AgCuSnSn, AuSn, or CuSn. In some embodiments, the PbSn solder has a thermal conductivity of about 50 W / mK, the AgSn solder has a thermal conductivity of about 78 W / mK, the SnAgCu solder has a thermal conductivity of about 60 W / mK, the CuSnNi has a thermal conductivity of about 64 W / mK, the AgCuSnSn solder has a thermal conductivity of about 57 W / mK, the AuSn solder has a thermal conductivity of about 57 W / mK, and the CuSn solder has a thermal conductivity of about 65 W / mK. In some embodiments, prior to or after forming the solder layer 80 or the conductive pillars 90, individual chips 15 are separated by a dicing process, as shown in FIG. 20.Next, individual chips 15 are removed from the frame 30 and attached to a substrate 50 such as a ball grid array substrate as shown in FIG. 21. The ball grid array substrate 50 has a first main surface 50A to which the chip 15 is attached via the solder bumps 35 on the redistribution layer 20, and a second main surface including an array of solder bumps 55. In some embodiments, conductive vias or wiring layers are formed in the substrate that electrically connect the solder bumps 35 on the redistribution layer to solder bumps on the second major surface 50B of the substrate 50.Referring now to FIG. 22, a detailed schematic view of the conductive column is shown in accordance with an embodiment of the disclosure. As shown, a bond pad 40 is disposed on a die 15. In some embodiments, the conductive pillar 90 is mainly made of a metal selected from the group consisting of aluminum, copper, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc, and alloys thereof. In some embodiments, the conductive pillar is made of copper, copper base material, or a copper alloy. In other embodiments, the conductive pillar 90 is made of nickel, nickel base material, or a nickel alloy. Copper-based or nickel-based materials contain copper or nickel, respectively, in an amount of 50 mol % or more. A conductive column mainly made of a metal is made of this metal by 50 mol % or more. In some embodiments, the conductive pillar 90 includes only a copper-based material layer or a nickel-based layer. In other embodiments, the conductive pillar 90 includes a first layer 90A mainly made of a metal selected from the group consisting of aluminum, copper, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc, and alloys thereof, and a second metal layer 90B made of another of the metal mainly made of a metal selected from the group consisting of aluminum, copper, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc, and alloys thereof.In some embodiments, a sub bump metallization 100 is disposed on bond pad 40 between conductive pillar 90 and die 15. In some embodiments, the under bump metallization is formed by a suitable metal deposition process, such as electroplating or electroless plating, physical vapor deposition (PVD) with sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, and electron beam evaporation. In some embodiments, a seed layer (not shown) is deposited on the bond pad before the under bump metallization is formed. In some embodiments, the sub bump metallization 100 extends over the insulating layer 105, and the excess sub bump metallization is removed by a suitable process, such as chemical mechanical polishing (CMP).In one embodiment, under bump metallization 100 includes a titanium-based layer disposed on bond pad 20 and a copper-based layer disposed on the titanium-based layer by sputtering. A titanium-based material contains titanium and titanium alloys and titanium compounds containing 50 mol % or more of titanium. A copper-based material includes copper and copper alloys and copper compounds including 50 mol % or more of copper. In one embodiment, the titanium-based layer is a sputtered layer of Ti or TiW having a thickness in the range of 20 nm to 70 nm.In some embodiments, an insulating layer 105 is formed over the chip 15 surrounding the sub bump metallization 100 in some embodiments. In some embodiments, the insulating layer 105 is made of a nitride, an oxide, an oxynitride, a carbide such as silicon carbide, or other material, and is formed by a deposition, masking, and etching process or by a masking and deposition process. In some embodiments, the insulating layer 105 is made of a polymer, such as polybenzoxazole (PBO), or an epoxy, polyimide, or other material 106.In some embodiments, the solder layer 85 is in direct physical contact with a top surface of the conductive pillar 90.In some embodiments, the conductive pillar 90 has a height D 1 in the range of about 1 μm to about 1 mm. In some embodiments, the height D 1 of the conductive pillar is in the range of 10 μm to about 100 μm. In some embodiments, the height of a second conductive pillar metal layer 90A is in the range of 0 mm to about 50 μm.In some embodiments, the conductive pillar 90 has a diameter in the range of about 5 μm to about 50 μm. In some embodiments, the conductive pillar 90 has a diameter in the range of about 10 μm to about 25 μm. In an embodiment, the semiconductor device 10 includes, between an upper layer 90A of the conductive layer 90B and the top surface of the under bump metallization 100, one of a copper base material layer or a nickel base material layer 90A having a height D 2 of about 0 μm to about 50 μm. In some embodiments, the height D 1 of the upper metal layer 90B of the conductive pillar 90 is greater than the height D 2 of the lower layer 90A. In some embodiments, a ratio of the height D 1 of the upper metal layer 90B of the conductive pillar 290 to the height D 2 of the lower metal layer 90A (D 1 / D 2) is in the range of about 1000 / 1 to about 1 / 1. In some embodiments, a ratio of the height D 1 of the upper layer of the conductive pillar 90B to the height D 2 of the lower metal layer 90A (D 1 / D 2) is in the range of about 100 / 1 to about 5 / 1.FIG. 23 is a plan view showing a row-column arrangement of the conductive pillars with the solder layer 85 formed thereon on the chip 15. Other arrangements having a fewer or greater number of rows or columns of conductive pillars are included within the scope of this disclosure. For example, the array may be a 10×10 array or an array having a larger number of columns and rows. The arrangement of the conductive pillars is not limited to a rectangular arrangement. In some embodiments, other arrangements include staggered rows and columns, with each conductive column immediately adjacent to six more conductive columns. In further embodiments, the conductive pillars are arranged in a concentric circular array. In further embodiments, the conductive pillars are arranged around the perimeter of the chip or in a central portion of the chip. In further embodiments, the conductive pillars are arranged irregularly. In some embodiments, up to about 1,000 conductive pillars are formed on the substrate.In some embodiments, the conductive pillars 90 have a diameter D 3 in the range of about 5 μm to about 50 μm, as seen in plan view. In some embodiments, the conductive pillars 90 have a diameter D 3 in the range of about 10 μm to about 25 μm. In some embodiments, the plurality of conductive pillars 90 are arranged in a row-column arrangement in the x-direction with a pitch S 1 of about 15 μm to about 60 μm from the center of one conductive pillar 90 to the center of an adjacent conductive pillar 90. In some embodiments, the plurality of conductive pillars 90 have a pitch S 1 from about 25 μm to about 50 μm from the center of one conductive pillar 90 to the center of an adjacent conductive pillar 90 in the x direction. In some embodiments, the plurality of conductive pillars 90 have a pitch S 2 from about 15 μm to about 60 μm from the center of one conductive pillar 90 to the center of an adjacent conductive pillar 90 in the y-direction. In some embodiments, the plurality of conductive pillars 90 have a pitch S 2 from about 25 μm to about 50 μm from the center of one conductive pillar 90 to the center of an adjacent conductive pillar 90 in the y-direction.In some embodiments, a ratio of the diameter D 3 of the conductive column to the pitch S 1 in the x direction is in the range of about 1 / 12 to about 5 / 6. In some embodiments, a ratio of the diameter D 3 of the conductive column to the pitch S 1 in the x direction is in the range of about 1 / 3 to about 2 / 3. In some embodiments, a ratio of the diameter D 3 of the conductive column to the pitch S 2 in the y direction is in the range of about 1 / 12 to about 5 / 6. 2 / 3. In some embodiments, the pitch S 1 in the x-direction is substantially equal to the pitch S 2 in the y-direction. In some embodiments, the pitch S 1 in the x-direction is greater than the pitch S 2 in the y-direction. In some embodiments, the pitch S 1 in the x-direction is less than the pitch S 2 in the y-direction.In some embodiments, a capping layer 110 is formed over the conductive pillar 90, as shown in FIG. 24. After forming the capping layer 110, the solder layer 85 is formed over the capping layer 110. In some embodiments, the capping layer 110 is a metal layer. The capping layer 110 may be formed of nickel, and other metals may be added. In some embodiments, the capping layer 110 is formed of electroless nickel and electroless palladium gold immersion (ENEPIG) including a nickel layer, a palladium layer on the nickel layer, and a gold layer on the palladium layer. The gold layer may be formed by dip coating. In other embodiments, the capping layer 110 is formed from other known capping materials and by other methods, such as, but not limited to, ENIG (Electroless Nickel Immersion Gold), DIG (Direct Immersion Gold), or the like. In some embodiments, the capping layer is substantially copper-free. As used herein, substantially copper-free means that, if any, copper is present in the capping layer, it is present only to the extent of contamination. Methods for forming the capping layer 110 include electroless plating, dipping, and the like. The capping layer 110 forms a large interface with the underlying conductive pillar 90, so bonding between the conductive pillar 90 and the solder layer 85 is improved. In some embodiments, the cap layer 110 has a thickness in the range of about 5 nm to about 100 nm.In some embodiments, an underfill material 60 is formed between the die 15 and the substrate 50, as shown in FIG. 25. The underfill material 60 fills the area between the solder bumps 35 on the redistribution layer 20. In some embodiments, the underfill material 60 is an epoxy, such as a silica filled epoxy, a polyimide, or other suitable insulating material. The underfill material 60 increases mechanical reliability by distributing stress across the top of the ball grid array substrate 50, rather than concentrating in the solder bumps 35. Moreover, the underfill material 60 provides encapsulation against moisture and contaminants in the external environment.Next, a lid 65 is positioned over the solder layer 45 as shown in Fig. 26. The lid 65 functions as a heat sink to remove heat generated by the chip 15. The lid 65 is made of a thermally conductive material. In some embodiments, the lid is made of aluminum, copper, nickel, cobalt, and alloys thereof, or other thermally conductive materials.Subsequently, the lid 65 is heated, for example, by a thermal pressure bonding head 145 as shown in FIG. 27, and is pressed into close contact with the chip 15 via the solder layer 45, thereby forming a semiconductor device in which the lid 65 is bonded to the chip 15 as shown in FIG. 28. In some embodiments, the thermal pressure bonding head 145 heats the solder layer 85 to a temperature of about 150° C. to about 400° C. In some embodiments, the solder layer 85 is heated to a temperature of about 200° C. to about 300° C. In one embodiment, the solder layer 85 is heated to a temperature of about 250° C. During application of the heat and pressure 75 to the lid 65, the solder layer 85 flows and the solder layer 85 subsequently cures and bonds the lid 65 firmly to the chip 15 upon cooling. Heat from the chip 15 is transferred to the lid 65 via the solder layer 85. The lid 65 dissipates the heat of the chip 15 so that the chip 15 can operate at higher speeds and lower thermal stress.In some embodiments, a thermal conductive material (TIM) 175 is interposed between the conductive pillars 90 to promote heat dissipation, as shown in FIG. 29. In some embodiments, the thermal thermal conductive material 175 is based on a thermally conductive gel, paste, pad, grease, or phase change materials having thermal conductivities between about 0.5 W / mK and 10 W / mK. In some embodiments, the thermal grease may be based on ceramic materials or metal, for example beryllium oxide, aluminum nitride, aluminum oxide, zinc oxide, silver, aluminum, or the like suspended in a silicone-based gel. In some embodiments, the thermal thermal thermal conductive material is a liquid metal paste of gallium alloys or a metal alloy pad that is reflowed to attach the thermal thermal thermal conductive material to a surface. In some embodiments, the thermal thermal conductive material is a non-electrically conductive ceramic-based paste filled with ceramic powders such as beryllium oxide, aluminum nitride, aluminum oxide, or zinc oxide.FIG. 30 shows a thermal simulation illustrating the normalized operating temperature of a system on chip (SOC) using a thermal conductive material having a selected thermal conductivity. The simulation is based on a system on a chip performance of 300 W and forced air convection on the lid surface. The thermal simulation shows that increasing the thermal conductivity from K=3 W / mK to 6 W / mK using a conventional thermal conductive material decreases the operating temperature of the SOC only by about 5%. On the other hand, when using a conductive metal according to the embodiments of the present disclosure, such as Sn having a thermal conductivity of about 50 W / mK, the operating temperature of the SOC is reduced to about 88% of its normalized value. Thus, in some embodiments, the methods and apparatuses of the present disclosure provide more than 200% improvement in heat transfer over conventional methods and apparatuses.Embodiments of the present disclosure use materials containing high thermal conductivity metals, e.g., -Cu (K Cu ~400 W / mK) and Sn (K Sn ~65 W / mK), to provide a solder-based thermal conductive material having thermal conductivities superior to a conventional thermal conductive material (<10 W / mK). In some embodiments, the solder has a thermal conductivity of ≥50 W / mK. By using materials with high thermal conductivity between the chip and the lid, the operating performance and the operating behavior can be significantly increased without substantial changes to the construction of the semiconductor device and without adverse effects on the device performance.An embodiment of the disclosure is a method including forming a solder layer on a surface of one or more chips and positioning a lid over the solder layer on the one or each of the plurality of chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding chip via the solder layer. The solder layer has a thermal conductivity of ≥50 W / mK. In an embodiment, prior to forming the solder layer on the surface of the one or more dies, the method includes forming a fan-out integrated wafer on a frame, the fan-out integrated wafer including the one or more dies. In an embodiment, the solder layer is a patterned solder layer. In an embodiment, the patterned solder layer includes a plurality of spaced apart solder regions. In an embodiment, the method includes forming a plurality of bond pads on the surface of the one or more chips prior to forming the solder layer. In an embodiment, prior to forming the solder layer, the method includes forming a metal pillar on each of the plurality of bond pads, the solder layer including solder bumps formed on each of the metal pillars. In one embodiment, the column is formed mainly of a metal selected from the group consisting of aluminum, copper, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc, and alloys thereof. In an embodiment, the method includes forming a thermally conductive material between the lid and the surface of the chip. In one embodiment, the method includes separating the one or more chips prior to positioning the covers. In an embodiment, the method comprises: removing the one or more chips from the frame; and attaching the one or more chips to a substrate, wherein the removing and attaching of the one or more chips is performed prior to positioning the lids. In an embodiment, the method includes forming an underfill layer between the one or more chips and the substrate. In one embodiment, the heat and pressure are applied to each lid. In one embodiment, a thermal pressure bonding head is used to apply the heat and pressure to each lid.Another embodiment of the disclosure is a method including forming a metal pillar on each of a plurality of bond pads disposed on a main surface of a chip and forming a solder layer on each of the metal pillars. A lid is positioned on each of the metal pillars over the solder layer and heat and pressure are applied to melt the solder layer and bond the lid to the chip via the solder layer. In an embodiment, the solder layer includes solder bumps formed on each of the metal pillars. In one embodiment, the column is made primarily of a metal selected from the group consisting of aluminum, copper, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc, and alloys thereof. In an embodiment, the method includes forming a fan-out integrated wafer on a frame prior to forming the metal pillars, the fan-out integrated wafer including the die.Another embodiment of the disclosure is a method of forming a solder bump having a solder on each of a plurality of bond pads disposed on a main surface of a chip. A lid is positioned over solder bumps formed on each of the plurality of bond pads. To melt the solder bumps, heat and pressure are applied, with the result that the solder flows and the solder bumps fuse, so that a solder layer is formed. The lid is firmly attached to the chip via the solder layer. In an embodiment, prior to forming the solder bumps on the main surface of the die, the method includes forming a fan-out integrated wafer on a frame, the fan-out integrated wafer including the die. In one embodiment, the solder comprises a material having a thermal conductivity of ≥50 W / mK.Another embodiment of the disclosure is a semiconductor device including a chip disposed over a substrate. A solder layer is disposed over a surface of the chip, and a lid is attached to the chip via the solder layer. In one embodiment, the chip is a fan-out integrated chip, a system on a chip, a wafer level chip scale package, or a chip-on-wafer-on-substrate. In an embodiment, the device includes an underfill layer between the chip and the substrate. In an embodiment, the solder layer is a patterned solder layer. In an embodiment, the patterned solder layer includes a plurality of spaced apart solder regions. In an embodiment, the semiconductor device includes a plurality of bond pads between the surface of the one or more dies and the solder layer. In an embodiment, the semiconductor device includes a metal pillar disposed between each of the bond pads and the solder layer. In one embodiment, the metal pillars include copper or nickel. In an embodiment, the semiconductor device includes a thermally conductive material between the lid and the chip.Another embodiment of the disclosure is a semiconductor device including a chip disposed over a substrate and a plurality of bond pads disposed on a main surface of a chip. A plurality of metal pillars are disposed on the bond pads, each bond pad having a pillar disposed thereon. A solder layer is disposed over a surface of each metal pillar, and a lid is attached to the chip via the solder layer. In one embodiment, the chip is a fan-out integrated chip, a system on a chip, a wafer level chip scale package, or a chip-on-wafer-on-substrate. In an embodiment, the semiconductor device includes an underfill layer between the chip and the substrate. In an embodiment, the semiconductor device includes a seed layer between each of the plurality of bond pads and each of the plurality of pillars. In one embodiment, the column is formed from a metal selected from the group consisting of aluminum, copper, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc, and alloys thereof. In an embodiment, the semiconductor device includes a thermally conductive material between the lid and the chip.Another embodiment of the disclosure is a semiconductor device including a chip disposed over a first main surface of a substrate. First solder bumps connect the chip to the first major surface of the substrate. Second solder bumps are disposed on a second main surface of the substrate. Conductive vias in the substrate connect the first solder bumps to the second solder bumps. A plurality of bond pads are disposed on a first major surface of the die. A solder layer is disposed over the plurality of bond pads and the first main surface of the chip. A lid is in contact with the substrate and is attached to the chip via the solder layer. In one embodiment, the chip is a fan-out integrated chip, a system on a chip, a wafer level chip scale package, or a chip-on-wafer-on-substrate. In an embodiment, the semiconductor device includes an underfill layer between the chip and the substrate. In one embodiment, the solder includes a material having a thermal conductivity of ≥50 W / mK. In one embodiment, the solder is selected from the group consisting of PbSn, AgSn, SnAgCu, CuSnNi, AgCuSnSn, AuSn, and CuSn.Features of several embodiments or examples are outlined above in order to make an understanding of the aspects of the present disclosure easier for a person skilled in the art. It should be understood by those skilled in the art that the present disclosure may be readily utilized as a basis for designing or altering other processes and structures to achieve the same purposes and / or to achieve the same advantages of the embodiments or examples presented herein.

Claims

A method comprising: forming a solder layer (45, 80, 85) on a surface of one or more chips (15); positioning a lid (65) over the solder layer (45, 80, 85) on each of the one or more chips (15); applying heat and pressure (75) to melt the solder layer (45, 80, 85) and attach each lid (65) to a corresponding chip (15) via the solder layer (45, 80, 85), wherein the solder layer (45, 80, 85) has a thermal conductivity of ≥ 50 W / mK; Prior to forming the solder layer (45, 80, 85) on the surface of the one or more chips (15), forming a fan-out integrated wafer on a frame (30), the fan-out integrated wafer having the one or more chips (15), forming a plurality of bond pads (40) on the surface of the one or more chips (15), and forming a metal pillar (90) on each of the plurality of bond pads (40), the solder layer (45, 80, 85) comprising solder bumps formed on each of the metal pillars (90).The method of claim 1, wherein the solder layer (45, 80, 85) is a patterned solder layer (45, 80, 85).The method of claim 2, wherein the patterned solder layer (45, 80, 85) comprises a plurality of spaced apart solder regions.The method of any preceding claim, wherein the metal pillars (90) are formed of copper.The method of any preceding claim, further comprising forming a thermally conductive material between the lid (65) and the surface of the chip (15).The method of any preceding claim, further comprising separating the one or more chips (15) prior to positioning the lids (65).The method of any preceding claim, further comprising: removing the one or more chips (15) from the frame (30); and attaching the one or more chips (15) to a substrate (50), wherein the removing and attaching of the one or more chips (15) is performed prior to positioning the lids (65).The method of claim 7, further comprising forming an underfill layer (60) between the one or more chips (15) and the substrate (50).The method of any preceding claim, wherein the heat and pressure (75) are applied to each lid (65).The method of claim 9, wherein a thermal pressure bonding head (145) is used to apply the heat and pressure (75) to each lid (65).A method comprising: forming a metal pillar (90) on each of a plurality of bond pads (40) disposed on a major surface of a die (15); forming a solder layer (85) on each of the metal pillars (90), the solder layer (85) comprising solder bumps formed on each of the metal pillars (90); positioning a lid (65) over the solder layer (85) on each of the metal pillars (90); and applying heat and pressure (75) to melt the solder layer (85) and attach the lid (65) to the die (15) via the solder layer (85).The method of claim 11, wherein the metal pillars (90) are formed of copper or nickel.The method of any of claims 11 or 12, further comprising forming a fan-out integrated wafer on a frame (30) prior to forming the metal pillars (90), the fan-out integrated wafer having the die (15).A semiconductor device comprising: a chip (15) disposed over a substrate (50); a solder layer (85) disposed over a surface of the chip (15); a lid (65) attached to the chip (15) via the solder layer (85); a plurality of bonding pads (40) between the surface of the chip (15) and the solder layer (85), wherein a metal pillar (90) is disposed between each of the bonding pads (40) and the solder layer (85), respectively, wherein the metal pillar (90) has a first layer (90A) mainly made of a metal and a second metal layer (90B) made of another metal.The semiconductor device of claim 14, wherein the chip (15) is a fan-out integrated chip, a system on a chip, a wafer level chip scale package, or a chip-on-wafer-on-substrate.The semiconductor device of claim 14 or 15, further comprising an underfill layer (60) between the chip (15) and the substrate (50).

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