Power semiconductor module

Abstract

Power semiconductor module with a substrate (2) comprising an electrically non-conductive insulating layer (3) and metallization load layer regions (MI,MA1,MA2,MZ1,MZ2) arranged thereon, and with power semiconductor switches (T) each comprising a first and second load current connection (C,E) and a control connection (G), wherein the substrate (2) comprises exactly one longitudinally extending inner metallization load layer region (MI), longitudinally extending first and second outer metallization load layer regions (MA1,MA2), and longitudinally extending, electrically conductively connected first and second intermediate metallization load layer regions (MZ1,MZ2), wherein in a transverse direction (Q) extending perpendicular to the longitudinal direction (L),the first intermediate metallization load layer region (MZ1) is arranged between the inner metallization load layer region (MI) and the first outer metallization load layer region (MA1), and the second intermediate metallization load layer region (MZ2) is arranged between the inner metallization load layer region (MI) and the second outer metallization load layer region (MA2), wherein the inner metallization load layer region (MI) is arranged between the first and second outer metallization load layer regions (MA1,MA2), wherein a first and second group (P1,P2) of the power semiconductor switches (T) are provided for realizing a first arm (A1) of a half-bridge circuit (6), wherein a third and fourth group (P3,P4) of the power semiconductor switches (T) are provided for realizing a second arm (A2) of the half-bridge circuit (6), wherein the first and second group (P1,P2) of the power semiconductor switches (T) are arranged on the inner metallization load layer region (MI) and the first load current terminals (C) of the first and second groups (P1,P2) of the power semiconductor switches (T) are electrically conductively contacted with the inner metallization load layer region (MI), wherein the second load current terminals (E) of the power semiconductor switches (T) of the first group (P1) are electrically conductively connected with the first intermediate metallization load layer region (MZ1) and the second load current terminals (E) of the power semiconductor switches (T) of the second group (P2) are electrically conductively connected with the second intermediate metallization load layer region (MZ2),wherein the third group (P3) of the power semiconductor switches (T) is arranged on the first intermediate metallization load layer region (MZ1) and the first load current terminals (C) of the third group (P3) of the power semiconductor switches (T) are electrically conductively contacted with the first intermediate metallization load layer region (MZ1), wherein the second load current terminals (E) of the power semiconductor switches (T) of the third group (P3) are electrically conductively connected with the first outer metallization load layer region (MA1), wherein the fourth group (P4) of the power semiconductor switches (T) is arranged on the second intermediate metallization load layer region (MZ2) and the first load current terminals (C) of the fourth group (P4) of the power semiconductor switches (T) are electrically conductively contacted with the second intermediate metallization load layer region (MZ2),wherein the second load current terminals (E) of the power semiconductor switches (T) of the fourth group (P4) are electrically connected to the second outer metallization load layer region (MA2), wherein the substrate (2) has a first metallization control layer region (MS1) arranged on the insulating layer (3) in the longitudinal direction (L) and arranged in the transverse direction (Q) between the first and second groups (P1,P2) of the power semiconductor switches (T), wherein the control terminals of the power semiconductor switches (T) of the first and second groups (P1,P2) are electrically connected to the first metallization control layer region (MS1), and wherein the inner metallization load layer region (MI) extends around the first metallization control layer region (MS1).

Description

[0001] The invention relates to a power semiconductor module.

[0002] In a power semiconductor module, when its power semiconductor switches, which are electrically connected in a half-bridge circuit, are switched off, parasitic inductances from the lines electrically connected to the power semiconductor switches can cause overvoltages between the load current terminals of the power semiconductor switch. These overvoltages can lead to damage or destruction of the power semiconductor switch. Therefore, to reduce or prevent these overvoltages, it is technically necessary to design the power semiconductor module with the lowest possible inductance.

[0003] From EP 3 246 945 B1, a low-inductance power semiconductor module providing a half-bridge circuit is known, comprising a substrate and power semiconductor switches arranged on the substrate. For reasons of mechanical protection of the power semiconductor switches, it is a disadvantage that some of the power semiconductor switches providing the half-bridge circuit are arranged on outer metallization load layer areas of the substrate.

[0004] From JP 2014-033 118 A, two semiconductor modules arranged next to each other are known, wherein the internal structures of the two semiconductor modules are mirror-symmetric to each other.

[0005] The object of the invention is to create a low-inductance power semiconductor module with a half-bridge circuit in which no power semiconductor switches of the half-bridge circuit are arranged on the outer metallization load layer areas of a substrate of the power semiconductor module.

[0006] This problem is solved by a power semiconductor module with a substrate having an electrically non-conductive insulating layer and metallization load layer regions arranged on it, and with power semiconductor switches, each having a first and second load current connection and a control connection, wherein the substrate has exactly one longitudinally extending inner metallization load layer region, longitudinally extending first and second outer metallization load layer regions, and longitudinally extending, electrically conductively connected, first and second intermediate metallization load layer regions, wherein in a transverse direction perpendicular to the longitudinal direction,the first intermediate metallization load layer region is arranged between the inner metallization load layer region and the first outer metallization load layer region, and the second intermediate metallization load layer region is arranged between the inner metallization load layer region and the second outer metallization load layer region, wherein the inner metallization load layer region is arranged between the first and second outer metallization load layer regions, wherein a first and second group of power semiconductor switches are provided for realizing a first arm of a half-bridge circuit, wherein a third and fourth group of power semiconductor switches are provided for realizing a second arm of the half-bridge circuit,wherein the first and second groups of power semiconductor switches are arranged on the inner metallization load layer region and the first load current terminals of the first and second groups of power semiconductor switches are electrically conductively contacted with the inner metallization load layer region, wherein the second load current terminals of the power semiconductor switches of the first group are electrically conductively connected with the first intermediate metallization load layer region and the second load current terminals of the power semiconductor switches of the second group are electrically conductively connected with the second intermediate metallization load layer region,wherein the third group of power semiconductor switches is arranged on the first intermediate metallization load layer region and the first load current terminals of the third group of power semiconductor switches are electrically conductively contacted with the first intermediate metallization load layer region, wherein the second load current terminals of the power semiconductor switches of the third group are electrically conductively connected to the first outer metallization load layer region, wherein the fourth group of power semiconductor switches is arranged on the second intermediate metallization load layer region and the first load current terminals of the fourth group of power semiconductor switches are electrically conductively contacted with the second intermediate metallization load layer region,wherein the second load current terminals of the power semiconductor switches of the fourth group are electrically connected to the second outer metallization load layer region, wherein the substrate has a longitudinally extending first metallization control layer region arranged on the insulating layer, which is arranged transversely between the first and second groups of power semiconductor switches, wherein the control terminals of the power semiconductor switches of the first and second groups are electrically connected to the first metallization control layer region, and wherein the inner metallization load layer region extends around the first metallization control layer region.

[0007] It proves advantageous if the first and second intermediate metallization load layer regions are electrically connected to each other by means of a first metallization bonding layer region arranged on the insulating layer, wherein the first metallization bonding layer region is formed integrally with the first and second intermediate metallization load layer regions. This results in a low-inductance electrical connection between the first and second intermediate metallization load layer regions.

[0008] Furthermore, it proves advantageous if the first and second outer metallization load layer regions are electrically connected to each other. This means that the first and second outer metallization load layer regions are already electrically connected to each other on the power semiconductor module.

[0009] In this context, it proves advantageous if the first and second outer metallization load layer regions are electrically connected to each other by means of a second metallization bonding layer region arranged on the insulating layer, wherein the second metallization bonding layer region is formed integrally with the first and second outer metallization load layer regions. This results in a low-inductance electrical connection between the first and second outer metallization load layer regions.

[0010] Furthermore, it proves advantageous if the power semiconductor switches of the first group are arranged longitudinally in a row one behind the other, and the power semiconductor switches of the second group are arranged longitudinally in a row one behind the other, with the power semiconductor switches of the second group being spaced apart from the power semiconductor switches of the first group in the transverse direction. This achieves a symmetrical arrangement of the power semiconductor switches of the first and second groups and thus aligns their switching behavior.

[0011] Furthermore, it proves advantageous if the power semiconductor switches of the third group are arranged longitudinally in a row behind one another, and the power semiconductor switches of the fourth group are also arranged longitudinally in a row behind one another. This achieves a symmetrical arrangement of the power semiconductor switches of the third and fourth groups, thus aligning their switching behavior.

[0012] Furthermore, it proves advantageous if the substrate has a longitudinally extending first metallization control layer region arranged on the insulating layer and positioned transversely between the first and second groups of power semiconductor switches, wherein the control terminals of the power semiconductor switches of the first and second groups are electrically connected to the first metallization control layer region. This achieves symmetrical control of the power semiconductor switches of the first and second groups, thus aligning their switching behavior.

[0013] In this context, it proves advantageous if the inner metallization load layer region surrounds the first metallization control layer region, particularly if it is completely enclosed. This achieves a highly symmetrical control of the power semiconductor switches of the first and second groups, thus further aligning the switching behavior of the power semiconductor switches of the first and second groups.

[0014] Furthermore, it proves advantageous if the substrate has a second metallization control layer region arranged on the insulating layer in the longitudinal direction, which is arranged in the transverse direction between the first intermediate metallization load layer region and the inner metallization load layer region, wherein the control terminals of the power semiconductor switches of the third group are electrically connected to the second metallization control layer region, and if the substrate has a third metallization control layer region arranged on the insulating layer in the longitudinal direction, which is arranged in the transverse direction between the second intermediate metallization load layer region and the inner metallization load layer region, wherein the control terminals of the power semiconductor switches of the fourth group are electrically connected to the third metallization control layer region.This achieves a symmetrical control of the power semiconductor switches of the third and fourth groups, thus aligning the switching behavior of the power semiconductor switches of the third and fourth groups.

[0015] Furthermore, it proves advantageous if the inner metallization load layer region, the first outer metallization load layer region to the second outer metallization load layer region, the first intermediate metallization load layer region to the second intermediate metallization load layer region, and the first group of power semiconductor switches to the second group of power semiconductor switches, and the third group of power semiconductor switches to the fourth group of power semiconductor switches are arranged in a mirror-symmetrical manner with respect to a longitudinally extending virtual line of symmetry. This achieves a symmetrical arrangement of the power semiconductor switches of the power semiconductor module, so that the stray inductances of the first and second arms of the half-bridge circuit are matched.

[0016] In this context, it proves advantageous if the substrate, for the electrical connection of the third and fourth group of power semiconductor switches to an external control device for controlling the power semiconductor switches of the third and fourth group, has a first and second control terminal metallization layer area arranged on the insulation layer and on the symmetry line, wherein the inner metallization load layer area extends around the first and second control terminal layer area, in particular closed around, wherein the first control terminal metallization layer area is electrically conductively connected to the first and second outer metallization load layer area and the second control terminal metallization layer area is electrically conductively connected to the second and third metallization control layer area.This enables a particularly symmetrical control of the power semiconductor switches of the third and fourth groups by an external control device, so that the switching behavior of the power semiconductor switches of the third and fourth groups is aligned with each other.

[0017] Furthermore, it proves advantageous if the first and second outer metallization load layer region are designed to have a negative electrical voltage potential during operation of the power semiconductor module, and the inner metallization load layer region is designed to have a positive electrical voltage potential during operation of the power semiconductor module, and the first and second intermediate metallization load layer region is designed to have an alternating electrical voltage potential during operation of the power semiconductor module.

[0018] Furthermore, it proves advantageous if the power semiconductor module has an electrically conductive first load current connection element connected to the inner metallization load layer region, an electrically conductive second load current connection element connected to the first outer metallization load layer region, an electrically conductive third load current connection element connected to the second outer metallization load layer region, and an electrically conductive fourth load current connection element connected to the first and second intermediate metallization load layer regions. This facilitates simple electrical connection of the power semiconductor module to an external device.

[0019] In this context, it proves advantageous if the first load current connection element, the fourth load current connection element, and the second load current connection element are arranged in a mirror-symmetrical manner with respect to a virtual symmetry line running in the longitudinal direction. This achieves a symmetrical arrangement of the load current connection elements of the power semiconductor module, so that the leakage inductances of the first and second arms of the half-bridge circuit are matched.

[0020] An embodiment of the invention is explained below with reference to the figures shown below. These figures show: Fig. 1 an electrical circuit diagram of a power semiconductor module according to the invention, Fig. 2 a top view of a power semiconductor module according to the invention and Fig. 3 a sectional view of a section of a substrate of the power semiconductor module according to the invention with a power semiconductor component of the power semiconductor module according to the invention arranged thereon.

[0021] Identical elements in the figures are marked with the same reference symbols.

[0022] In Fig. Figure 1 shows an electrical circuit diagram of a power semiconductor module 1 according to the invention. The power semiconductor module 1 has a half-bridge circuit 6. The half-bridge circuit 6 has a first arm A1, which is formed by power semiconductor switches T connected electrically in parallel at its load current terminals C and E, and has a second arm A2, which is formed by power semiconductor switches T connected electrically in parallel at its load current terminals C and E. The first and second arms A1 and A2 are connected electrically in series.The power semiconductor module 1 has a first load current connection element DC1+ electrically connected to the first load current terminals C of the power semiconductor switches T of the first arm A1, second and third load current connection elements DC2- and DC3- electrically connected to the second load current terminals E of the power semiconductor switches T of the second arm A2, and a fourth load current connection element AC4 electrically connected to the second load current terminals E of the power semiconductor switches T of the first arm A1 and to the first load current terminals C of the power semiconductor switches T of the second arm A2. During operation of the power semiconductor module 1, a DC link voltage Udc is present between the first load current terminals C of the power semiconductor switches T of the first arm A1 and the second load current terminals E of the power semiconductor switches T of the second arm A2.Half-bridge circuits are used to rectify or convert electrical voltages to alternating current. The power semiconductor switches T of the first arm A1 and the power semiconductor switches T of the second arm A2 are switched on and off alternately via their respective control terminals G. The control terminals G of the power semiconductor switches T of the first arm A1 are preferably electrically connected to each other, and the control terminals G of the power semiconductor switches T of the second arm A2 are preferably electrically connected to each other.

[0023] It should be noted that T diodes can be connected electrically antiparallel to the power semiconductor switches.

[0024] In Fig. Figure 2 shows a top view of the power semiconductor module 1 according to the invention. Fig.Figure 3 shows a sectional view of a section of a substrate 2 of the power semiconductor module 1 according to the invention with a power semiconductor component T of the power semiconductor module 1 according to the invention arranged thereon.

[0025] The power semiconductor module 1 comprises a substrate 2, which has an electrically non-conductive insulating layer 3 and metallization load layer regions MI, MA1, MA2, MZ1, and MZ2 arranged on this layer. Each metallization load layer region MI, MA1, MA2, MZ1, or MZ2 forms a conductor, or, as in the exemplary embodiment, a portion of a conductor, arranged on the insulating layer 3. The substrate 2 can have a metal layer 5 arranged on the side of the insulating layer 3 opposite the metallization load layer regions MI, MA1, MA2, MZ1, and MZ2. The insulating layer 3 can, for example, be a ceramic plate. The substrate 2 can, for example, be a direct copper bonded substrate (DCB substrate), an active metal brazing substrate (AMB substrate), or an insulated metal substrate (IMS).

[0026] The power semiconductor module 1 further comprises several power semiconductor switches T, each having a first and second load current connection C and E and a control connection G. The power semiconductor switches T are preferably in the form of transistors, such as IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In the exemplary embodiment, the power semiconductor switches T are in the form of IGBTs, wherein the first load current connection C is in the form of the collector metallization of the IGBT, the second load current connection E is in the form of the emitter metallization of the IGBT, and the control connection G is in the form of the gate metallization of the IGBT. The load current connections C and E and the control connection G are arranged on a power semiconductor body 20 of the respective power semiconductor switch T.The power semiconductor body 20 forms the semiconductor structure of the respective power semiconductor switch T. The semiconductor material of the power semiconductor body 20 can consist of, for example, silicon or silicon carbide.

[0027] Substrate 2 has an inner metallization load layer region MI extending in a longitudinal direction L, first and second outer metallization load layer regions MA1, MA2 extending in the longitudinal direction L, and first and second intermediate metallization load layer regions MZ1, MZ2 extending in the longitudinal direction L and electrically connected to each other. The first intermediate metallization load layer region MZ1 is arranged in a transverse direction Q perpendicular to the longitudinal direction L between the inner metallization load layer region MI and the first outer metallization load layer region MA1. The second intermediate metallization load layer region MZ2 is arranged in the transverse direction Q between the inner metallization load layer region MI and the second outer metallization load layer region MA2.

[0028] A first and second group P1 and P2 of the power semiconductor switches T are provided for the realization of the first arm A1 of the half-bridge circuit 6. A third and fourth group P3 and P4 of the power semiconductor switches T are provided for the realization of a second arm A2 of the half-bridge circuit 6.

[0029] The first and second groups P1 and P2 of the power semiconductor switches T are arranged on the inner metallization load layer region MI, and the first load current terminals C of the first and second groups P1 and P2 of the power semiconductor switches T are electrically conductively contacted with the inner metallization load layer region P1 and P2 via a bonding layer 4, which can be, for example, a sintered layer or a solder layer. The second load current terminals E of the power semiconductor switches T of the first group P1 are electrically conductively connected to the first intermediate metallization load layer region MZ1, for example, via bond wires 10, and the second load current terminals E of the power semiconductor switches T of the second group P2 are electrically conductively connected to the second intermediate metallization load layer region MZ2, for example, via bond wires 10.

[0030] The third group P3 of the power semiconductor switches T is arranged on the first intermediate metallization load layer region MZ1, and the first load current terminals C of the third group P3 of the power semiconductor switches T are electrically conductively contacted with the first intermediate metallization load layer region MZ1 via a bonding layer 4, which can be, for example, a sintered layer or a solder layer. The second load current terminals E of the power semiconductor switches T of the third group P3 are electrically conductively connected to the first outer metallization load layer region MA1, for example, via bond wires 10. The fourth group P4 of the power semiconductor switches T is arranged on the second intermediate metallization load layer region MZ2, and the first load current terminals C of the fourth group P4 of the power semiconductor switches T are electrically conductively connected to the second intermediate metallization load layer region MZ2, for example, via bond wires 10.The second load current terminals E of the power semiconductor switches T of the fourth group P4 are electrically connected to the second outer metallization load layer area MA2, e.g. via bond wires 10.

[0031] The invention provides a low-inductance power semiconductor module 1 with a half-bridge circuit 6, in which no power semiconductor switches T of the half-bridge circuit 6 are arranged on the outer metallization load layer areas MA1 and MA2 of the substrate 2 of the power semiconductor module 1.

[0032] The first and second intermediate metallization load layer regions MZ1 and MZ2 are preferably electrically connected to each other by means of a first metallization bonding layer region MV1 arranged on the insulating layer 3, wherein the first metallization bonding layer region MV1 is formed integrally with the first and second intermediate metallization load layer regions MZ1 and MZ2. The first and second intermediate metallization load layer regions MZ1 and MZ2 and the first metallization bonding layer region MV1 are thus preferably an integral part of a common conductor track of the substrate 2 arranged on the insulating layer 3. Alternatively or additionally, the first and second intermediate metallization load layer regions MZ1 and MZ2 can also be electrically connected to each other, e.g., by means of at least one bonding wire 10.

[0033] The first and second outer metallization load layer regions MA1 and MA2 are preferably electrically connected to each other. These regions are preferably electrically connected by means of a second metallization bonding layer region MV2 arranged on the insulating layer 3, wherein the second metallization bonding layer region MV2 is integrally formed with the first and second outer metallization load layer regions MA1 and MA2. Thus, the first and second outer metallization load layer regions MA1 and MA2 and the second metallization bonding layer region MV2 are preferably integral components of a common conductor track of the substrate 2 arranged on the insulating layer 3. Alternatively or additionally, the first and second outer metallization load layer regions MA1 and MA2 can, for example, be connected to a single conductor track.also be electrically connected to each other by means of at least one bond wire 10.

[0034] The power semiconductor switches T of the first group P1 are preferably arranged in a row in the longitudinal direction L and the power semiconductor switches T of the second group P2 are preferably arranged in a row in the longitudinal direction L, wherein the power semiconductor switches T of the second group P2 are spaced apart from the power semiconductor switches T of the first group P1 in the transverse direction Q.

[0035] The power semiconductor switches T of the third group P3 are preferably arranged in a row in the longitudinal direction L and the power semiconductor switches T of the fourth group P4 are preferably arranged in a row in the longitudinal direction L.

[0036] The substrate 2 preferably has a first metallization control layer region MS1 ​​arranged on the insulating layer 3, extending longitudinally in the direction L and arranged transversely in the direction Q between the first and second groups P1 and P2 of the power semiconductor switches T, wherein the control terminals G of the power semiconductor switches T of the first and second groups P1 and P2 are electrically connected to the first metallization control layer region MS1, e.g. via bond wires 10. The inner metallization load layer region MI preferably extends around the first metallization control layer region MS1, in particular completely around it.

[0037] The substrate 2 preferably has a second metallization control layer region MS2 arranged on the insulating layer 3, extending longitudinally in the direction L and arranged in the transverse direction Q between the first intermediate metallization load layer region MZ1 and the inner metallization load layer region MI. The control terminals G of the power semiconductor switches T of the third group P3 are electrically connected to the second metallization control layer region MS2, e.g., via bond wires 10. The substrate 2 preferably has a third metallization control layer region MS3 arranged on the insulating layer 3, extending longitudinally in the direction L and arranged in the transverse direction Q between the second intermediate metallization load layer region MZ2 and the inner metallization load layer region MI.The control terminals G of the power semiconductor switches T of the fourth group P4 are electrically connected to the third metallization control layer area MS3, e.g. via bond wires 10.

[0038] The respective metallization control layer regions MS1, MS2, and MS3 form a conductor track, or a portion thereof, as in the exemplary embodiment, which is arranged on the insulation layer 3. The respective metallization control layer regions MS1, MS2, and MS3 electrically connect the control terminals G of the respective groups P1, P2, P3, and P4 of the power semiconductor switches T to each other.

[0039] The inner metallization load layer region MI is preferably arranged in a mirror-symmetrical manner with respect to a virtual symmetry line S extending in the longitudinal direction L. Furthermore, the first outer metallization load layer region MA1 is preferably arranged in a mirror-symmetrical manner with respect to the second outer metallization load layer region MA2, the first intermediate metallization load layer region MZ1 is preferably arranged in a mirror-symmetrical manner with respect to the second group P2 of power semiconductor switches T, and the third group P3 of power semiconductor switches T is preferably arranged in a mirror-symmetrical manner with respect to a virtual symmetry line S extending in the longitudinal direction L.

[0040] The substrate 2 preferably has, for electrical connection of the third and fourth groups P3 and P4 of power semiconductor switches T to an external control device (not shown in the figures) for controlling the power semiconductor switches T of the third and fourth groups P3 and P4, a first and second control terminal metallization layer region SA1 and SA2 arranged on the insulation layer 2 and on the symmetry line S. The inner metallization load layer region MI extends around the first and second control terminal layer regions SA1 and SA2, respectively, in particular in a closed configuration, wherein the first control terminal metallization layer region SA1 is connected to the first and second outer metallization load layer regions MA1 and MA2, e.g.The second control terminal metallization layer area SA2 is electrically connected via bond wires 10 to the second and third metallization control layer areas MS2 and MS3. The electrical connection of the power semiconductor switches T of the third and fourth groups P3 and P4 to the external control device can be achieved, for example, via electrically conductive contact springs, which establish an electrically conductive connection between a printed circuit board on which the external control device is arranged and the control terminal metallization layer areas SA1 and SA2 against which the contact springs press.

[0041] A connection area B1 of the first metallization control layer region MS1, preferably arranged on the symmetry line S, and a connection area B2 of the first metallization compound layer region MV1, preferably arranged on the symmetry line S, serve for the electrical connection of the first and second groups P1 and P2 of power semiconductor switches T to the external control device for controlling the power semiconductor switches T of the first and second groups P1 and P2. The electrical connection of the power semiconductor switches T of the first and second groups P1 and P2 to the external control device can be effected, for example, via electrically conductive contact springs, which establish an electrically conductive connection between the circuit board on which the external control device is arranged and the connection areas B1 and B2 on which the contact springs press.

[0042] The first and second outer metallization load layer regions MA1 and MA2 are preferably designed to have a negative electrical voltage potential during operation of the power semiconductor module 1. The inner metallization load layer region MI is preferably designed to have a positive electrical voltage potential during operation of the power semiconductor module 1. The first and second intermediate metallization load layer regions MZ1 and MZ2 are preferably designed to have an alternating voltage potential during operation of the power semiconductor module 1. During operation of the power semiconductor module 1, the DC link voltage Udc is present between the inner metallization load layer region MI and the first and second outer metallization load layer regions MA1 and MA2.

[0043] The first metallization control layer area MS1 is intended to have a first electrical control potential during operation of the power semiconductor module 1, and the second and third metallization control layer areas MS2 and MS3 are intended to have a second control potential during operation of the power semiconductor module 1.

[0044] The power semiconductor module 1 preferably comprises a first electrically conductive load current connection element DC1+, which is electrically connected to the inner metallization load layer region MI; a second electrically conductive load current connection element DC2-, which is electrically connected to the first outer metallization load layer region MA1; a third electrically conductive load current connection element DC3-, which is electrically connected to the second outer metallization load layer region MA2; and a fourth electrically conductive load current connection element AC4, which is electrically connected to the first and second intermediate metallization load layer regions MZ1 and MZ2. The first load current connection element DC1+ is preferably arranged on the inner metallization load layer region MI and electrically contacted with it.The second load current connection element DC2- is preferably arranged on the first outer metallization load layer region MA1 and electrically contacted with it. The third load current connection element DC3- is preferably arranged on the second outer metallization load layer region MA2 and electrically contacted with it. The fourth load current connection element AC4 is preferably arranged on the first metallization compound layer region MV1 and electrically contacted with it.

[0045] The first load current connection element DC1+ is preferably arranged in a mirror-symmetrical manner with respect to the virtual symmetry line S extending in the longitudinal direction L. The fourth load current connection element AC4 is preferably arranged in a mirror-symmetrical manner with respect to the virtual symmetry line S. The second load current connection element DC2- is preferably arranged in a mirror-symmetrical manner with respect to the third load current connection element DC3- with respect to the virtual symmetry line S.

[0046] It should be noted that the electrically conductive connections, which in the exemplary embodiment are realized by means of the bond wires 10, can also be realized, for example, by means of an electrically conductive foil composite.

Claims

[1] Power semiconductor module with a substrate (2) comprising an electrically non-conductive insulating layer (3) and metallization load layer regions (MI,MA1,MA2,MZ1,MZ2) arranged thereon, and with power semiconductor switches (T) each comprising a first and second load current connection (C,E) and a control connection (G), wherein the substrate (2) comprises exactly one longitudinally extending inner metallization load layer region (MI), longitudinally extending first and second outer metallization load layer regions (MA1,MA2) and longitudinally extending, electrically conductively connected, first and second intermediate metallization load layer regions (MZ1,MZ2), wherein in a transverse direction (Q) extending perpendicular to the longitudinal direction (L),the first intermediate metallization load layer region (MZ1) is arranged between the inner metallization load layer region (MI) and the first outer metallization load layer region (MA1), and the second intermediate metallization load layer region (MZ2) is arranged between the inner metallization load layer region (MI) and the second outer metallization load layer region (MA2), wherein the inner metallization load layer region (MI) is arranged between the first and second outer metallization load layer regions (MA1,MA2), wherein a first and second group (P1,P2) of the power semiconductor switches (T) are provided for realizing a first arm (A1) of a half-bridge circuit (6), wherein a third and fourth group (P3,P4) of the power semiconductor switches (T) are provided for realizing a second arm (A2) of the half-bridge circuit (6), wherein the first and second group (P1,P2) of the power semiconductor switches (T) are arranged on the inner metallization load layer region (MI) and the first load current terminals (C) of the first and second groups (P1,P2) of the power semiconductor switches (T) are electrically conductively contacted with the inner metallization load layer region (MI), wherein the second load current terminals (E) of the power semiconductor switches (T) of the first group (P1) are electrically conductively connected with the first intermediate metallization load layer region (MZ1) and the second load current terminals (E) of the power semiconductor switches (T) of the second group (P2) are electrically conductively connected with the second intermediate metallization load layer region (MZ2),wherein the third group (P3) of the power semiconductor switches (T) is arranged on the first intermediate metallization load layer region (MZ1) and the first load current terminals (C) of the third group (P3) of the power semiconductor switches (T) are electrically conductively contacted with the first intermediate metallization load layer region (MZ1), wherein the second load current terminals (E) of the power semiconductor switches (T) of the third group (P3) are electrically conductively connected with the first outer metallization load layer region (MA1), wherein the fourth group (P4) of the power semiconductor switches (T) is arranged on the second intermediate metallization load layer region (MZ2) and the first load current terminals (C) of the fourth group (P4) of the power semiconductor switches (T) are electrically conductively contacted with the second intermediate metallization load layer region (MZ2),wherein the second load current terminals (E) of the power semiconductor switches (T) of the fourth group (P4) are electrically connected to the second outer metallization load layer region (MA2), wherein the substrate (2) has a first metallization control layer region (MS1) arranged on the insulating layer (3) in the longitudinal direction (L) and arranged in the transverse direction (Q) between the first and second groups (P1,P2) of the power semiconductor switches (T), wherein the control terminals of the power semiconductor switches (T) of the first and second groups (P1,P2) are electrically connected to the first metallization control layer region (MS1), and wherein the inner metallization load layer region (MI) extends around the first metallization control layer region (MS1). [2] Power semiconductor module according to claim 1, characterized by, that the first and second intermediate metallization load layer region (MZ1,MZ2) are electrically connected to each other by means of a first metallization connection layer region (MV1) arranged on the insulating layer (3), wherein the first metallization connection layer region (MV1) is formed integrally with the first and second intermediate metallization load layer region (MZ1,MZ2). [3] Power semiconductor module according to any one of the preceding claims, characterized by that the first and second outer metallization load layer areas (MA1,MA2) are electrically connected to each other. [4] Power semiconductor module according to claim 3, characterized by, that the first and second outer metallization load layer region (MA1,MA2) are electrically connected to each other by means of a second metallization connection layer region (MV2) arranged on the insulating layer (3), wherein the second metallization connection layer region (MV2) is formed integrally with the first and second outer metallization load layer region (MA1,MA2). [5] Power semiconductor module according to any one of the preceding claims, characterized by , that the power semiconductor switches (T) of the first group (P1) are arranged in a row in the longitudinal direction (L) and the power semiconductor switches (T) of the second group (P2) are arranged in a row in the longitudinal direction (L), wherein the power semiconductor switches (T) of the second group (P2) are spaced apart from the power semiconductor switches (T) of the first group (P1) in the transverse direction (Q). [6] Power semiconductor module according to any one of the preceding claims, characterized by , that the power semiconductor switches (T) of the third group (P3) are arranged in a row in the longitudinal direction (L) and the power semiconductor switches (T) of the fourth group (P4) are arranged in a row in the longitudinal direction (L). [7] Power semiconductor module according to any one of the preceding claims, characterized by , that the inner metallization load layer region (MI) runs closed around the first metallization control layer region (MS1). [8] Power semiconductor module according to any one of the preceding claims, characterized by, that the substrate (2) has a second metallization control layer region (MS2) arranged on the insulating layer (3) in the longitudinal direction (L) and arranged in the transverse direction (Q) between the first intermediate metallization load layer region (MZ1) and the inner metallization load layer region (MI), wherein the control terminals (G) of the power semiconductor switches (T) of the third group (P3) are electrically connected to the second metallization control layer region (MS2), and that the substrate (2) has a third metallization control layer region (MS3) arranged on the insulating layer (3) in the longitudinal direction (L) and arranged in the transverse direction (Q) between the second intermediate metallization load layer region (MZ2) and the inner metallization load layer region (MI),wherein the control terminals (G) of the power semiconductor switches (T) of the fourth group (P4) are electrically connected to the third metallization control layer area (MS3). [9] Power semiconductor module according to any one of the preceding claims, characterized by , that the inner metallization load layer region (MI), the first outer metallization load layer region (MA1) to the second outer metallization load layer region (MA2), the first intermediate metallization load layer region (MZ1) to the second intermediate metallization load layer region (MZ2), and the first group (P1) of power semiconductor switches (T) to the second group (P2) of power semiconductor switches (T), and the third group (P3) of power semiconductor switches (T) to the fourth group (P4) of power semiconductor switches (T) are arranged in a mirror-symmetrical manner with respect to a virtual symmetry line (S) extending in the longitudinal direction (L). [10] Power semiconductor module according to claim 9, insofar as it refers back to claim 8, characterized by, that the substrate (2), for electrical connection of the third and fourth group (P3,P4) of power semiconductor switches (T) to an external control device for controlling the power semiconductor switches (T) of the third and fourth group, (P3,P4) has a first and second control terminal metallization layer region (SA1,SA2) arranged on the insulation layer (2) and on the symmetry line (S), wherein the inner metallization load layer region (MI) extends around the first and second control terminal layer region (SA1,SA2), in particular closed around, wherein the first control terminal metallization layer region (SA1) is electrically conductively connected to the first and second outer metallization load layer region (MA1,MA2) and the second control terminal metallization layer region (SA2) is electrically conductively connected to the second and third metallization control layer region (MS2,MS3). [11] Power semiconductor module according to any one of the preceding claims, characterized by , that the first and second outer metallization load layer region (MA1,MA2) are intended to have a negative electrical voltage potential during operation of the power semiconductor module (1), and the inner metallization load layer region (MI) is intended to have a positive electrical voltage potential during operation of the power semiconductor module, and the first and second intermediate metallization load layer region (MZ1,MZ2) is intended to have an alternating electrical voltage potential during operation of the power semiconductor module (1). [12] Power semiconductor module according to any one of the preceding claims, characterized by, that the power semiconductor module (1) has an electrically conductive first load current connection element (DC1+) electrically connected to the inner metallization load layer region (MI), an electrically conductive second load current connection element (DC2-) electrically connected to the first outer metallization load layer region (MA1), an electrically conductive third load current connection element (DC3-) electrically connected to the second outer metallization load layer region (MA2), and an electrically conductive fourth load current connection element (AC4) electrically connected to the first and second intermediate metallization load layer regions (MZ1,MZ2). [13] Power semiconductor module according to claim 12, characterized by, that the first load current connection element (DC1+), the fourth load current connection element (AC4) and the second load current connection element (DC2-) are arranged in a mirror-symmetric manner with respect to the third load current connection element (DC3-) in relation to a virtual symmetry line (S) running in the longitudinal direction (L).

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