METHOD FOR CONDITION END EXTENSION

Abstract

Procedure with the following steps: Creating a structured photoresist (16) on a first region (33) of a hard mask layer (14); and Creating a lead-end extension region (32) in the hard mask layer (14), wherein the lead-end extension region (32) extends laterally outwards from an end of the first region (33) of the hard mask layer (14), wherein creating the lead-end extension region (32) comprises changing a physical property of the hard mask layer (14) in the lead-end extension region (32), the establishment of the line end extension area (32) comprises the following: Implanting ions (20) with an initial concentration into the lead-end extension region (32) of the hard mask layer (14); and Implanting ions (20) with a second concentration into the hard mask layer (14) outside the lead end extension area (32), wherein the second concentration of ions (20) is higher than the first concentration of ions (20), wherein the implantation of ions (20) into the lead end extension area (32) and the implantation of ions (20) into the hard mask layer (14) outside the lead end extension area (32) occur simultaneously.

Description

background

[0001] Advances in the manufacturing of semiconductor integrated circuits (ICs) have led to an increase in functional density (i.e., the number of interconnected devices per chip area) and a decrease in feature size (i.e., the smallest component or line that can be produced using a manufacturing process). Increasing functional density while decreasing feature size generally offers advantages by increasing production output and reducing corresponding costs. However, these advances in the size and density of devices or components are also associated with increased complexity in the design and manufacturing of devices that use these ICs.

[0002] For example, reducing sizes and spacing between IC features defined and fabricated on a semiconductor substrate generally involves using a plurality of different photolithographic masks, and dicing processes are performed to create patterned features used in the ICs.

[0003] German patent application DE 10 2018 122 496 A1 discloses a method for forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end distance between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer. Short description of the drawings

[0004] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1 to 8 are sectional views showing a method of manufacturing an integrated circuit according to some embodiments of the present invention. Fig. Fig. 9 is a sectional view showing a structured structural element obtained by a modification of the method described with reference to Fig. 1 to 8, according to some embodiments. Fig. 10 is a plan view showing a device according to some embodiments. Detailed description

[0005] Throughout this specification, deposition processes for depositing dielectric layers, metals, or other materials include processes such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electroless plating, and the like. Specific embodiments are described herein by way of example of these processes. However, the present invention and reference to specific deposition processes should not be limited to the processes mentioned.

[0006] Throughout this specification, etching processes for selectively removing semiconductor materials, dielectric materials, metals, or other materials include processes such as dry etching, wet chemical etching, reactive ion (plasma) etching (RIE), cleaning, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing (CMP), and the like. Specific embodiments are described herein by way of example of these processes. However, the present invention and reference to specific etching processes should not be limited to the processes mentioned.

[0007] As the sizes or dimensions of features fabricated in integrated circuits decrease, a spacing or gap between ends of adjacent features may be limited by the processing steps used to fabricate the features. For example, photolithography and dicing processes used to fabricate patterned features of an integrated circuit may have lower limits on the spacing between features than can be practically achieved. These lower limits may be defined, for example, by the dimensions of a photomask that can be physically created based on the integrated circuit layout.

[0008] As set forth herein, the present invention provides methods for forming line end extensions for patterned features at the ends of feature lines, thereby enabling a reduction in the spacing or gap that may occur between patterned features of an integrated circuit. In some embodiments, the line end extensions may be formed without additional dicing layers (and corresponding additional masking processes) that may be required in other methods for forming line end extensions.

[0009] In view of the foregoing, various embodiments of the present application are directed to methods in which line-end extension regions are created in a hard mask layer by directed ion beam bombardment. The ion beams may be at least partially blocked from reaching the line-end extension regions of the hard mask layer. The line-end extension regions may be regions that extend laterally outward from ends of a patterned photoresist on the hard mask layer, and the patterned photoresist blocks at least some of the ion beams from reaching the line-end extension regions. The line-end extension regions may, for example, be shadow regions that receive a lower concentration or fewer ions than other regions of the hard mask layer.The ions can change physical properties of the hard mask layer, such as selectivity for an etchant. Therefore, the unblocked areas of the hard mask layer can be readily removed with an etchant, while the line-end extension areas (as well as areas covered by the patterned photoresist) of the hard mask layer can remain and be used to pattern a target layer. Thus, patterned features can be fabricated in a self-aligned manner, with the patterned features having areas corresponding to the line-end extension areas of the hard mask layer. This enables a significant reduction in the gap between patterned features.

[0010] The Fig. Figures 1 to 8 are sectional views illustrating a method for fabricating an integrated circuit according to one or more embodiments of the present invention. Additional steps may be provided before, during, and after the method, and some of the described steps may be substituted or omitted in other embodiments of the method.

[0011] As in Fig. 1, a hard mask 14 is formed on a target layer 12. The hard mask 14 may be any suitable hard mask comprising a masking material used to protect underlying areas (e.g., the target layer 12) during processing. Suitable materials for the hard mask 14 include dielectric materials (e.g., semiconductor oxides, semiconductor nitrides, semiconductor oxide-nitrides, semiconductor carbides, metal oxides, other metal compounds, etc.), metals, metal alloys, polysilicon, and / or other suitable materials. In some embodiments, the hard mask 14 is a silicon nitride layer.

[0012] The hard mask 14 may be formed using any suitable method, such as deposition, anodization, thermal oxidation, or the like. In some embodiments, the hard mask 14 is formed using a deposition method. The deposition method may be any deposition method suitable for depositing a hard mask layer, such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), or the like.

[0013] The target layer 12 is formed on a substrate 10. The substrate 10 may be any suitable substrate, such as any suitable semiconductor substrate. In various embodiments, the substrate 10 may be formed from a crystalline semiconductor material, for example, monocrystalline silicon, polycrystalline silicon, or another type of crystalline semiconductor material. In some embodiments, the substrate 10 is a silicon substrate, but embodiments provided herein are not limited thereto. In various embodiments, the substrate 10 may comprise, for example, gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or another semiconductor material. The substrate 10 may have various doping configurations depending on the design specifications. In some embodiments, the substrate 10 is a p-type substrate having a concentration of p-type dopants.

[0014] In various embodiments, substrate 10 may have a substantially uniform composition or may include various layers. The layers may have similar or different compositions, and in some embodiments, some substrate layers may have non-uniform compositions to induce mechanical device stress and thereby tailor device performance. Examples of multilayer substrates are silicon-on-insulator (SOI) substrates. In some embodiments, a layer of substrate 10 may include an insulating material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxide nitride, a semiconductor carbide, and / or other suitable insulating materials.

[0015] The target layer 12 may be a layer of material to be patterned into one or more features of an integrated circuit. Lead end extensions are formed in or with the target layer 12, as will be explained in more detail later. In some embodiments, the target layer 12 may be a dielectric layer, for example, made of oxide, nitride, silicon oxide (SiO x), silicon oxynitride (SiON), silicon nitride (SiN), or the like. In some embodiments, the target layer 12 may be a semiconductor layer, such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or another semiconductor material. In some embodiments, the target layer 12 may be an electrically conductive layer, such as a layer of copper (Cu) or another metal or other electrically conductive material. The materials to be used for the target layer 12 may, if appropriate, be selected depending, for example, on particular structural elements to be formed by the target layer 12 after its patterning.In various embodiments, the features formed by the target layer 12 may be, for example, semiconductor fins for a FinFET device, gate features, conductive traces or conductive vias, or other features of an integrated circuit.

[0016] The target layer 12 can be formed by any suitable method used, for example, for depositing dielectric layers, metals, or other materials, such as CVD, LPCVD, MOCVD, PECVD, plasma vapor deposition (PVD), ALD, MBE, electroplating, electroless plating, or the like.

[0017] As in Fig. 2, a photoresist 16 is patterned on the hard mask 14, for example, by lithographic exposure, in which a photomask is used to expose selected areas of the photoresist 16. The exposure triggers a chemical reaction in the exposed areas of the photoresist 16. A developer dissolves or otherwise removes the exposed areas in a positive resist development process, or dissolves the unexposed areas in a negative resist development process. Suitable positive developers are tetramethylammonium hydroxide (TMAH), KOH, and NaOH, and suitable negative developers are solvents such as n-butyl acetate, ethanol, hexane, benzene, and toluene. In various embodiments, the patterned photoresist 16 remaining after the development process has a shape that substantially corresponds to a shape of the feature to be defined in the target layer 12. The ends (e.g.,However, the ends (i.e., the line ends) of the structural elements to be defined in the target layer 12 are extended laterally beyond the ends of the patterned photoresist 16.

[0018] Ions 20 are implanted into the hard mask 14, as in Fig. 2. The implantation of the ions 20, e.g., by ion bombardment, causes a change in one or more properties of regions of the hard mask 14 into which the ions 20 are implanted. In some embodiments, the implanted ions 20 change (e.g., increase) a selective etch rate of the hard mask 14 when treated with a suitable etchant. In some embodiments, the ions 20 comprise an element selected from the group consisting of nitrogen (N), tellurium (Te), boron (B), gallium (Ga), phosphorus (P), arsenic (As), argon (Ar), krypton (Kr), and xenon (Xe).

[0019] The ions 20 are implanted into the hard mask 14, and they can be implanted directionally, for example, with ion beams that are emitted at selected angles with respect to the hard mask 14. In some embodiments, the ions 20 are directed to the hard mask 14 using ion beams that are not orthogonal to the hard mask 14. For example, in some embodiments, the ions 20 are emitted to the hard mask 14 with an ion beam angle θ with respect to a direction 22 that is orthogonal to the hard mask 14. In the example shown in Fig. 2, ion beams can be provided with the ion beam angle θ formed by two different directions (e.g., from right to left and from left to right, as shown in Fig. 2 is shown).

[0020] As in Fig. 2, the bombardment or implantation of ions 20 into the hard mask 14 creates a first region 31 with full ion bombardment and second regions 32 with partial ion bombardment. The second regions 32 of the hard mask 14 are only partially bombarded with the ions 20 because the photoresist 16 prevents at least some of the directed ion beams from reaching the second regions 32 of the hard mask 14. That is, the second regions 32 may be shadow regions or regions of the hard mask 14 that are protected from receiving all directed ion beams by the presence of the photoresist 16. In some embodiments, the first region 31 of the hard mask 14 may be completely unprotected or otherwise protected from receiving ion beams, and therefore the first region 31 may be referred to as a region that receives 100% of the bombardment with the ions 20.The second regions 32 may receive a partial bombardment of the ions 20, e.g., 90% or less, 75% or less, 50% or less, or 25% or less, of the bombardment of the ions 20. The amount or percentage of bombardment of the ions 20 received in the second regions 32 should be less than the amount or percentage of bombardment of the ions 20 received in the first region 31, such that one or more properties of the first region 31 are changed relative to the second regions 32, which changes may include a change in selectivity for an etchant, as will be explained in more detail later. By receiving less than full bombardment (e.g., less than 90%, less than 75%, less than 50%, or less than 25%), the second regions 32 are less easily removed with an etchant than the first region 31, which receives 100% of the bombardment with the ions 20.Other factors may also influence the change in etchant selectivity due to reduced or partial bombardment with ions 20, such as the material of the hard mask 14, the type of ions, the etchant used, and the like. In some embodiments, receiving partial bombardment with ions 20, e.g., 90% or less, 75% or less, 50% or less, or 25% or less, creates a significant difference in properties between the second regions 32 and the first region 31 (which receives 100% of the bombardment), such that the first region 31 can be easily removed (e.g., with an etchant) while the second regions 32 remain at least partially intact.

[0021] As in Fig. 2, in some embodiments, the second regions 32 may be referred to as regions that receive 50% of the bombardment with the ions 20, since each of the second regions 32 may receive ions 20 from only one ion beam of a particular direction (e.g., from right to left and from left to right, as shown in Fig. 2), while ions 20 from the other ion beam are blocked by the photoresist 16. The second regions 32 may be referred to herein as lead end extension regions 32, since these regions effectively extend the lead ends of the features fabricated in the target layer 12, as will be explained in more detail later.

[0022] The line end extension portions 32 may have a length L1 (e.g., in a horizontal direction, as shown in Fig. 2) that depends on the ion beam angle θ and a height h of the photoresist 16. In some embodiments, the length L1 of the line end extension regions 32 can be represented by the following equation: L1=h×tanθ.

[0023] Accordingly, the line-end extension regions 32 can be formed with any desired length L1, for example, by forming the photoresist 16 with a height h suitable for forming the line-end extension regions 32 with the desired length L1 and / or by selectively irradiating the hard mask 14 with ion beams having a specific ion beam angle θ suitable for forming the line-end extension regions 32 with the desired length L1. A region under the photoresist 16 can have a length L2 of any desired size, depending on a desired length of a patterned feature to be formed according to the method presented here. A total length of the patterned feature to be formed can be equal to the length L2 plus twice the length L1 of the line-end extension regions 32.

[0024] In some embodiments, the photoresist 16 has a thickness or height h that is less than 100 nm. In some embodiments, the photoresist 16 has a height h that is less than 75 nm. In some embodiments, the photoresist 16 has a height h that is about 20 nm to about 50 nm.

[0025] In some embodiments, the hard mask 14 has a thickness that is less than 100 nm. In some embodiments, the hard mask 14 has a thickness that is less than 50 nm. In some embodiments, the hard mask 14 has a thickness that is about 10 nm to about 20 nm.

[0026] In some embodiments, the target layer 12 has a thickness that is less than 100 nm. In some embodiments, the target layer 12 has a thickness that is less than 50 nm. In some embodiments, the target layer 12 has a thickness that is about 20 nm to about 35 nm.

[0027] In some embodiments, the ion beam angle θ is less than about 85°. In some embodiments, the ion beam angle θ is less than 80°. In some embodiments, the ion beam angle θ is greater than 30°. In some embodiments, the ion beam angle θ is from about 30° to about 85°. In some embodiments, the ion beam angle θ is from about 50° to about 80°. As stated above, the length L1 of the lead-end extension regions 32 depends at least in part on the height h of the photoresist 16 and the ion beam angle θ. By irradiating the ions 20 at an ion beam angle θ of from about 30° to about 85°, the lead-end extension regions 32 can be fabricated to have a suitable length L1 and the ions 20 can be effectively implanted into the hard mask 14.Outside the ranges mentioned here, the ions 20 cannot be effectively implanted into the hard mask 14, which may result in an insufficient change in one or more properties of the first region 31 of the hard mask 14. For example, by irradiating the ions 20 with an ion beam angle θ of less than about 30°, the first region 31 may not receive implanted ions 20 suitable for changing the selectivity of the first region 31 for an etchant. On the other hand, by irradiating the ions 20 with an ion beam angle θ of more than about 85°, the length L1 of the lead-end extension regions 32 may be limited, since the photoresist 16 must have a relatively large height h for the lead-end extension regions 32 to have a desired length L1.

[0028] The implantation of ions 20 into the hard mask 14 changes the physical properties of the hard mask 14. In some embodiments, the implantation of ions 20 into the first region 31 of the hard mask 14 reduces an etch resistance of the first region 31, so that the first region 31 of the hard mask 14 can be more easily removed with an etching process than portions of the hard mask 14 that are not irradiated with ions 20 or that receive a lower percentage of ion 20 bombardment. That is, the first region 31 can be more easily removed by etching than the second regions or lead end extension regions 32.

[0029] In some embodiments, the ions 20 are implanted with a suitable energy such that they penetrate at least halfway into the hard mask 14. In some embodiments, the ions 20 are implanted with an energy of 25 keV to 250 keV. In some embodiments, the ions 20 are implanted in the first region 31 with a concentration of about 10 12 up to 10 15 ions / cm 2implanted into the lead-end extension regions 32 at a lower concentration than in the first region 31. In some embodiments, the ions 20 are implanted into the lead-end extension regions 32 at a concentration that is 25% lower than the concentration of the ions 20 implanted in the first region 31. In some embodiments, the ions 20 are implanted into the lead-end extension regions 32 at a concentration that is 50% lower than the concentration of the ions 20 implanted in the first region 31. In some embodiments, the ions 20 are implanted into the lead-end extension regions 32 at a concentration that is 75% lower than the concentration of the ions 20 implanted in the first region 31.The concentrations of ions 20 implanted into the first region 31 and the lead-end extension regions 32 may be selected depending on various factors, such as a desired change in properties (e.g., etch rate) of the hard mask layer 14 in the lead-end extension regions 32 compared to those in the first region 31.

[0030] A ratio r1 / r2 of etch rates at which the first region 31 or the second regions or line end extension regions 32 of the hard mask 14 are etched may optionally be selected, for example, depending on design considerations. In some embodiments, the ratio of the etch rates may depend at least in part on various factors, such as the type of ions 20, the duration of the ion bombardment, the concentration of the ions 20 during the ion bombardment, the etchant used, or various other factors. In some embodiments, the ratio of the etch rates r1 / r2 may be greater than 1.5, greater than 2.0, greater than 3.0, or greater than 5.0.

[0031] As in Fig. As shown in Figure 3, the photoresist 16 is removed following ion bombardment of the hard mask 14. The photoresist 16 may be removed using any suitable method. In some embodiments, the photoresist 16 is removed using a wet etching process. In some embodiments, the photoresist 16 may be removed using a photoresist stripping process using organic, inorganic, or dry stripping agents.

[0032] After the photoresist 16 has been removed, a non-bombarded region 33 of the hard mask 14 is exposed. The non-bombarded region 33 is a region below the location of the photoresist 16, where the photoresist 16 prevented the ions 20 from reaching the non-bombarded region 33. Thus, the non-bombarded region 33 may have a higher etch resistance than the first region 31 of the hard mask 14. In some embodiments, the non-bombarded region 33 may have a higher etch resistance than the lead end extension regions 32 of the hard mask 14.

[0033] As in Fig. 4, the first region 31 of the hard mask 14 is then removed. The first region 31 of the hard mask 14 may be removed using any suitable method, such as wet etching, dry etching, reactive ion etching (RIE), stripping, or other suitable etching techniques. In some embodiments, the first region 31 of the hard mask 14 is removed using a first etching gas 42 containing an etching chemical with a high etch selectivity for the first region 31. For example, an etching gas may be used that removes the first region 31 at a higher etch rate than the line end extension regions 32 and the non-bombarded region 33 of the hard mask 14. In some embodiments, the first region 31 of the hard mask 14 is removed using an etching gas containing carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), other suitable etchants, or combinations thereof.

[0034] As in Fig. 5, portions of the target layer 12 are exposed at locations where the first region 31 of the hard mask 14 has been removed. The portions of the hard mask 14 forming the lead-end extension regions 32 and the non-bombarded region 33 remain on the target layer 12. During the removal of the first region 31 of the hard mask 14, a thickness of the lead-end extension regions 32 may be reduced. For example, an etching gas used to remove the first region 31 of the hard mask 14 may also remove portions of the lead-end extension regions 32, thereby reducing the thickness or height of the lead-end extension regions 32.However, as stated above, the lead end extension regions 32 are etched at a lower rate than the first region 31 of the hard mask 14 because the lead end extension regions 32 received a lower percentage or fraction of ions 20 during ion bombardment (see . Fig. 2). Accordingly, the lead-end extension regions 32 are etched at a lower speed than the first region 31. Thus, the thickness of the lead-end extension regions 32 can be reduced during etching, but the surface area of ​​the lead-end extension regions 32 can remain substantially the same.

[0035] The non-bombarded region 33 may have substantially the same dimensions after removal of the hard mask 14 as before. Because the non-bombarded region 33 was protected, for example, against bombardment with ions 20, the etch rate of the non-bombarded region 33 of the hard mask 14 was not reduced. Accordingly, the use of an etchant to remove the first region 31 of the hard mask 14 does not significantly affect the non-bombarded region 33. However, it should be understood that in various embodiments, removing the first region 31 of the hard mask 14, for example, with an etching gas, may result in some reduction in the thickness of the non-bombarded region 33.

[0036] As in Fig. 6, the target layer 12 is patterned by transferring the pattern of the remaining hard mask 14 (e.g., the non-bombarded region 33 and the lead end extension regions 32) to the target layer 12. The target layer 12 is patterned, for example, by removing portions of the target layer 12 that are exposed or otherwise not covered by the non-bombarded region 33 or the lead end extension regions 32 of the hard mask 14. The exposed portions of the target layer 12 may be removed using any suitable method, such as wet etching, dry etching, RIE, stripping, or other suitable etching techniques. In some embodiments, the exposed portions of the target layer 12 are removed using a second etching gas 52 containing an etching chemical with a high selectivity for the target region 12.For example, the second etching gas 52 may be used to remove the exposed portions of the target region 12 while leaving the lead end extension regions 32 and the non-bombarded region 33 of the hard mask 14 intact. In some embodiments, the second etching gas 52 is different from the first etching gas 42 used to remove the first region 31 of the hard mask 14 (see FIG. Fig. 4) may be used. The second etching gas 52 may be selected as desired, for example, depending on design considerations. In some embodiments, the second etching gas 52 may be selected depending on a composition of the target layer 12. For example, a different etching gas may be used to remove a target layer made of a dielectric material than to remove a target layer made of an electrically conductive material.

[0037] As in Fig. 7, a structured structural element 112 is produced by structuring the target layer 12. The structured structural element 112 remains on the substrate 10 after the exposed parts of the target layer 12 have been removed, as shown, for example, in Fig. 6 and has been set forth with reference thereto. The structured structural element 112 has substantially the same dimensions as the non-bombarded region 33 and the lead end extension regions 32. For example, the structured structural element 112 may have substantially the same length and width as the non-bombarded region 33 and the lead end extension regions 32.

[0038] As in Fig. 8, the non-bombarded region 33 and the lead-end extension regions 32 of the hard mask 14 may then be removed. The non-bombarded region 33 and the lead-end extension regions 32 of the hard mask 14 may be removed using any suitable method, such as wet etching, dry etching, RIE, stripping, or other suitable etching techniques. In some embodiments, the non-bombarded region 33 and the lead-end extension regions 32 of the hard mask 14 are removed using a third etching gas containing an etching chemical that has high selectivity for the hard mask 14. In some embodiments, the non-bombarded region 33 and the lead end extension regions 32 of the hard mask 14 are removed with an etching gas containing carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), other suitable etchants, or combinations thereof.In some embodiments, the third etching gas is the same as the first etching gas 42.

[0039] The patterned feature 112 may be any feature of an integrated circuit, such as an electrically conductive feature or a semiconductor feature. In some embodiments, the patterned feature 112 may be a semiconductor fin of a FinFET device, a gate feature such as a polysilicon or metal gate, an electrically conductive trace or via, or another feature of an integrated circuit.

[0040] The patterned feature 112 can be fabricated to have any desired shape. While the patterned feature 112 is illustrated as a linear shape having a length along one direction, it should be understood that, in various embodiments, other shapes can be fabricated using the methods described herein. For example, the photoresist can be patterned to have any desired shape using photolithographic methods described herein, and the hardmask layer can be ion implanted as described herein to create lead end extensions at lead ends of the photoresist having the desired shape.

[0041] In some embodiments, multiple patterned features 112 may be fabricated close to one another. The lead end extensions fabricated by ion implantation, as set forth herein, enable a reduction in the gaps between adjacent or opposite lead ends of features of an integrated circuit.

[0042] Fig. 9 is a sectional view showing a structured structural element 212 according to some embodiments of the present invention. The structured structural element 212 can be manufactured using substantially the same method as described in FIGS. Fig. 1 to 8, but with some modifications. The structured structural element 212 can be formed by performing the Fig. 1 to 7, with a modification at Fig. 8, are manufactured.

[0043] As in Fig. 9, in particular, the non-bombarded region 33 and the lead end extension regions 32 of the hard mask 14 may be removed with an etching gas different from the third etching gas described with reference to Fig. 8. Instead of using the third etching gas with an etching chemical with a high selectivity for the hard mask 14, in embodiments described in Fig. 9, the non-bombarded region 33 and the lead end extension regions 32 of the hard mask 14 are removed with a fourth etching gas having a low or slight selectivity between the hard mask 14 and the material of the target layer 12.

[0044] Because the fourth etching gas has a low or slight selectivity between the hard mask 14 and the material of the target layer 12, it may remove respective portions of the hard mask 14 and the target layer 12 at a similar or substantially the same speed. Therefore, thinner portions of the hard mask 14 (e.g., the lead-end extension regions 32) may be completely removed with the etching gas before thicker portions of the hard mask 14 (e.g., the non-bombarded region 33) are completely removed. By removing the lead-end extension regions 32 before completely removing the non-bombarded region 33, portions of the target layer 12 are exposed in the regions where the lead-end extension regions 32 were first removed. Accordingly, the resulting shape of the patterned feature 212 may resemble the shape of the hard mask 14, as shown, for example, in Fig. 7. The structured feature 212 may, for example, have a first portion 201 that is thicker than second portions 202 that extend laterally outward from the first portion 201. The first portion 201 of the structured feature 212 may be referred to as a "natural lead end" because the first portion 201 has dimensions (e.g., a length and a width) that correspond to the dimensions of the photoresist 16 (see Fig. 2) and the non-bombarded region 33 of the hard mask 14. The second parts 202 of the structured structural element 212 may be referred to as "extended line end" parts, since the second parts 202 have dimensions that correspond to the line end extension regions 32 of the hard mask 14.

[0045] Fig. Figure 10 is a plan view showing a component 300 that can be manufactured by the method described here, for example, with reference to Fig. 1 to 9. The component 300 may be an electronic component, for example, an integrated circuit or the like.

[0046] The device 300 comprises a plurality of structured structural elements 312 formed on a substrate 310. The structured structural elements 312 may be formed using the methods described, for example, with reference to Fig. 1 to 9. In various embodiments, the patterned features 312 may be, for example, semiconductor device structures, such as fins for a FinFET device, gate features, conductive traces or conductive vias, or other features of an integrated circuit.

[0047] At least some of the structured structural elements 312 may include natural line end portions 312a and 312b and line end extension portions 332a and 332b. The line end extension portions 332a and 332b may be formed, for example, by ion bombardment, as set forth above. The natural line end portions 312a and 312b represent portions of the structured structural elements 312 that are not bombarded with ions, as set forth above for the non-bombarded region 33, for example. By using methods described herein, such as ion bombardment, the line end extension portions 332a and 332b may be formed in a manner that enables a reduction in the end-to-end gap between the structured structural elements 312.

[0048] In some embodiments, the plurality of patterned features 312 may be formed based on a layout comprising a layout of shapes. The layout may, for example, be a data file stored on a non-transitory machine-readable medium and represented in a design standard such as GDSII, OASIS, or the like. The layout may be a digital representation of the device 300, which may be an integrated circuit. The shapes of the layout may correspond to and define physical features of the device 300. In particular, the shapes of the layout may define physical features, such as portions of the patterned features 312 of the device 300. However, the layout may be limited by dimensional constraints of photolithographic processes for fabricating an integrated circuit based on the layout.For example, gaps (or lead-end-to-lead spacing) between the shapes of the layout may be limited by dimensions of a photomask that can be physically fabricated based on the layout. In particular, a natural lead-end-to-lead gap G1 between opposing shapes of the layout may be limited by photolithographic processes, such as dimensional constraints of the photomask that can be fabricated to create the shapes.

[0049] In some embodiments, a photomask is fabricated based on the shapes of the layout. For example, as described above with reference to Fig. 1 and Fig. 2, a hard mask layer is formed on a target layer, and the photomask may be used to pattern a photoresist formed over the hard mask layer. The patterned photoresist may correspond to the patterned features 312 and the patterned features 312a and 312b shown in Fig. 10, and a minimum distance between the patterned photoresist (e.g., for forming the features 312a and 312b) may be the natural line end-to-end gap G1. The line end extension regions 332a and 332b of the patterned features 312a and 312b are not covered by the photoresist, and the line end extension regions 332a and 332b may be formed as previously described, e.g., by ion bombardment to create line end extension regions in the hard mask and by subsequently patterning a target layer to form the patterned features 312 with the line end extension regions 332a and 332b.

[0050] By using methods described herein, such as ion bombardment to form lead end extension regions, the lead end extension portions 332a and 332b of the patterned features 312 may be formed with a smaller lead end-to-end gap G2 between the patterned features 312 than the natural lead end-to-end gap G1, which is limited by constraints of conventional photolithographic processes.

[0051] In some embodiments, the line end-to-end gap G2 may be less than 25 nm. In some embodiments, the line end-to-end gap G2 may be less than 18 nm. In some embodiments, the line end-to-end gap G2 may be less than 14 nm. In some embodiments, the line end-to-end gap G2 may be less than 10 nm. In some embodiments, the line end-to-end gap G2 may be about 5 nm to about 25 nm. By creating the line end-to-end gap G2 in this range, the line ends of the patterned features 312 can be manufactured very close to each other, thus increasing the number of these features 312 that can be manufactured on a given area, while maintaining a sufficient gap or spacing between the features 312 to electrically isolate the features 312 from each other and to avoid or reduce undesired cross-talk of the features 312.

[0052] The dimension of the line end-to-end gap G2 is not limited by specific dimensional constraints of photolithographic or dicing processes, but the gap G2 can be made to have a considerably smaller width depending on the height h of the photoresist and the ion beam angle θ (which can be determined, for example, with reference to Fig. 2), each of which can be selected as desired to produce the line end extension regions with a desired length and a desired gap G2 between the structured structural elements 312.

[0053] As explained above, the patterned features 312 may be features of an integrated circuit, such as semiconductor device structures such as fins for a FinFET device, gate features, conductive traces or conductive vias, or other features of an integrated circuit.

[0054] It should be well understood that this Fig. 10 may be a part or a portion of an integrated circuit, and in some embodiments, the device 300 may include various other structural elements, such as further patterned structural elements 312, as well as other structural elements of an integrated circuit.

[0055] The present invention provides, in various embodiments, methods for forming line end extensions of patterned features at the ends of patterned lines, thereby enabling a reduction in a distance or gap that may arise between patterned features of an integrated circuit. In some embodiments, the line end extensions may be formed without additional dicing layers (and corresponding additional masking processes) that may be required in other methods for forming line end extensions. This offers a significant advantage in increasing the density of features that can be formed in an integrated circuit.

[0056] According to one embodiment, a method comprises forming a patterned photoresist on a first region of a hard mask layer. A lead end extension region is formed in the hard mask layer. The lead end extension region extends laterally outward from one end of the first region of the hard mask layer. The lead end extension region can be formed by changing a physical property of the hard mask layer in the lead end extension region.

[0057] According to another embodiment, a method is provided that comprises forming a hard mask layer on a target layer. The target layer is disposed between a substrate and the hard mask layer. A patterned photoresist is formed on a plurality of first regions of the hard mask layer. A plurality of line-end extension regions are formed by irradiating the hard mask layer with a plurality of ion beams extending outward from ends of the plurality of first regions. The ion beams each have a non-zero ion beam angle with respect to a direction orthogonal to the hard mask layer, and the patterned photoresist prevents at least a portion of the plurality of ion beams from reaching the plurality of line-end extension regions. The patterned photoresist is then removed.Portions of the target layer are exposed by removing portions of the hard mask layer outside the plurality of first regions and the plurality of line end extension regions. A patterned structural element is formed in the target layer by removing the exposed portions of the target layer.

[0058] According to yet another exemplary embodiment, an integrated circuit comprises a substrate and a plurality of patterned structural elements on the substrate. The patterned structural elements are each made of the same material. A distance between an end of a first patterned structural element of the plurality of patterned structural elements and an end of a second patterned structural element of the plurality of patterned structural elements is less than 25 nm.

Claims

[1] Procedure with the following steps: Producing a patterned photoresist (16) on a first region (33) of a hard mask layer (14); and Producing a line end extension region (32) in the hard mask layer (14), wherein the line end extension region (32) extends laterally outward from one end of the first region (33) of the hard mask layer (14), wherein the production of the line end extension region (32) comprises changing a physical property of the hard mask layer (14) in the line end extension region (32), wherein the production of the cable end extension region (32) comprises: implanting ions (20) having a first concentration into the line end extension region (32) of the hard mask layer (14); and Implanting ions (20) having a second concentration into the hard mask layer (14) outside the line end extension region (32), wherein the second concentration of ions (20) is higher than the first concentration of ions (20), wherein the implantation of ions (20) into the line end extension region (32) and the implantation of ions (20) into the hard mask layer (14) outside the line end extension region (32) take place simultaneously. [2] The method of claim 1, further comprising: Removing the patterned photoresist (16); and Exposing parts of a target layer (12) by removing parts of the hard mask layer (14) outside the first region (33) and the line end extension region (32). [3] The method of claim 2, wherein the physical property of the hard mask layer (14) comprises selectivity for an etching gas, wherein removing the portions of the hard mask layer (14) comprises removing the portions of the hard mask layer (14) by etching the portions of the hard mask layer (14) with the etching gas. [4] The method of claim 2 or 3, further comprising removing the exposed portions of the target layer (12). [5] The method of claim 4, further comprising removing the first region (33) and the lead end extension region (32) of the hard mask layer (14). [6] The method of any preceding claim, wherein forming the lead end extension region (32) in the hard mask layer (14) comprises irradiating the hard mask layer (14) with an ion beam, the ion beam having a non-zero ion beam angle (θ) with respect to a direction orthogonal to the hard mask layer (14). [7] The method of claim 6, wherein the ion beam angle (θ) is less than about 85°. [8] The method of claim 6 or 7, wherein the ion beam angle (θ) is greater than about 30°. [9] The method of claim 6, wherein the ion beam angle (θ) is about 50° to about 80°. [10] Method according to one of claims 6 to 9, wherein the ion beam comprises ions (20) formed by an element from the group nitrogen (N), tellurium (Te), boron (B), gallium (Ga), phosphorus (P), arsenic (As), argon (Ar), krypton (Kr) and xenon (Xe). [11] The method of any preceding claim, wherein a length (L1) of the lead end extension region (32) is based at least in part on a height (h) of the patterned photoresist (16). [12] A method according to any one of the preceding claims, wherein the height (h) of the patterned photoresist (16) is about 20 nm to about 50 nm. [13] The method of any one of claims 1 to 10, wherein the lead end extension region (32) has a length (L1) substantially equal to h × tan θ, where h is a height of the patterned photoresist (16) and θ is the non-zero ion beam angle [14] Procedure with the following steps: Producing a hard mask layer (14) on a target layer (12), wherein the target layer (12) is arranged between a substrate (10) and the hard mask layer (14); Producing a patterned photoresist (16) on a plurality of first regions (33) of the hard mask layer (14); Forming a plurality of line-end extension regions (32) such that they extend outwardly from ends of the plurality of first regions (33) by irradiating the hard mask layer (14) with a plurality of ion beams (20), each having a non-zero ion beam angle (θ) with respect to a direction (22) orthogonal to the hard mask layer (14), wherein the patterned photoresist (16) prevents at least a portion of the plurality of ion beams (20) from reaching the plurality of line-end extension regions (32), wherein forming the plurality of line-end extension regions (32) comprises forming the plurality of line-end extension regions (32) such that they have a length (L1) substantially equal to h × tan θ, where h is a height of the patterned photoresist (16) and θ is the non-zero ion beam angle; Removing the patterned photoresist (16); Exposing parts of the target layer (12) by removing parts (31) of the hard mask layer (14) outside the plurality of first regions (33) and the plurality of line end extension regions (32); and Producing a structured structural element (112) in the target layer (12) by removing the exposed parts of the target layer (12). [15] The method of claim 14, wherein forming the plurality of line end extension regions (32) comprises changing, by irradiating the hard mask layer (14), a selectivity for an etching gas in the plurality of line end extension regions (32) of the hard mask layer (14). [16] The method of claim 14 or 15, wherein removing portions of the hard mask layer (14) outside the plurality of first regions (33) and the plurality of line end extension regions (32) comprises treating the hard mask layer (14) with the etching gas, wherein the etching gas has a lower selectivity for the plurality of line end extension regions (32) than for the portions of the hard mask layer (14) outside the plurality of first regions (33) and the plurality of line end extension regions (32).

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