Semiconductor chip with low-k dielectric layer

Abstract

Semiconductor chip (1), comprising: a component layer (130) on a substrate (110), wherein the component layer (130) comprises several semiconductor components (120); a wiring structure (MS) and a lower inter-wiring dielectric layer (210) each on the device layer (130), wherein the lower inter-wiring dielectric layer (210) surrounds the wiring structure (MS) and has a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer (220-250) on the lower inter-wiring dielectric layer (210), wherein the upper inter-wiring dielectric layer (220-250) has a permittivity that is at least as high as the permittivity of silicon oxide; an insulating recess (SRS) along an edge of the substrate (110), wherein the insulating recess (SRS) is formed on a side face of the lower inter-wiring dielectric layer (210) and a side face of the upper inter-wiring dielectric layer (220-250), wherein the insulating recess (SRS) has a bottom surface at a level that is not higher than the level of a bottom surface of the lower inter-wiring dielectric layer (210); and a dielectric cover layer (290) which covers the side surfaces of the lower inter-wiring dielectric layer (210) and the upper inter-wiring dielectric layer (220-250) and the underside of the insulation recess (SRS), wherein the substrate (110) has four sides which form a rectangular shape in a top view, wherein the dielectric cover layer (290) has a step section (ST) along at least one of the four sides of the substrate (110), and wherein a groove or projection is formed in a bottom side of the step section (ST) along at least one of the four sides of the substrate (110).

Description

BACKGROUND

[0001] The inventive concept relates to a semiconductor chip and in particular to a semiconductor chip comprising a low-k dielectric layer.

[0002] With the rapid development of the electronics industry and evolving user needs, electronic devices and equipment are becoming lighter and more compact than ever before. Consequently, the semiconductor chips and packages used in electronic devices have an ever-increasing integration density, leading to a relaxation of the design rules for semiconductor chip and package components. Therefore, a low-k dielectric layer has been introduced to reduce parasitic capacitance within a semiconductor chip, particularly between wires.

[0003] In US patent application 2017 / 0053902A1, three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure comprises a first chip, a second chip, and at least one through-substrate via (TSV). The first chip is electrically connected to the second chip via a first bonding pad of the first chip and a second bonding pad of the second chip. The TSV extends from a first back surface of the first chip to a metallization element of the first chip. At least one conductive via is electrically connected between the TSV and the first bonding pad, and at least one elongated slot or closed space is located within the at least one conductive via.

[0004] US 2010 / 0072635A1 discloses a method for manufacturing an integrated circuit structure, comprising providing a wafer with a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjacent to the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom that is no higher than the top surface of a semiconductor substrate in the wafer; forming a first insulating film over the wafer, wherein the first insulating film extends into the notch; removing a portion of the first insulating film from the center of the notch, wherein a remaining portion of the first insulating film encompasses an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip.

[0005] CHISCA, Stefan; SAVA, Ion; MUSTEATA, Valentina; BRUMA, Maria: Dielectric and conductive properties of polyimide films. In: Semiconductor Conference (CAS), 2011. Vol. 2, pp. 253-256 concerns polyimide films. SUMMARY

[0006] The inventive concept provides a semiconductor chip that ensures mechanical reliability during the singulation of the semiconductor chip.

[0007] According to one aspect of the inventive concept, a semiconductor chip is provided. The semiconductor chip comprises a component layer on a substrate, wherein the component layer comprises several semiconductor components; a wiring structure and a lower inter-wiring dielectric layer, each on the component layer, wherein the lower inter-wiring dielectric layer surrounds the wiring structure and has a lower permittivity than silicon oxide; and an upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer, wherein the upper inter-wiring dielectric layer has a permittivity at least as high as that of silicon oxide.an insulation recess along an edge of the substrate, wherein the insulation recess is formed on a side face of the lower inter-wiring dielectric layer and a side face of the upper inter-wiring dielectric layer and has a bottom surface at a level that is not higher than a level of a bottom surface of the lower inter-wiring dielectric layer;and a dielectric cover layer covering the side surfaces of the lower inter-wiring dielectric layer and the upper inter-wiring dielectric layer and the underside of the insulating recess, wherein the substrate has four sides forming a rectangular shape in a top view, wherein the dielectric cover layer has a step section along at least one of the four sides of the substrate, and wherein a groove or projection is formed in an underside of the step section along at least one of the four sides of the substrate.

[0008] According to another aspect of the inventive concept, a semiconductor chip is provided comprising: a component layer on a substrate, wherein the component layer comprises several semiconductor components; a wiring structure and a lower inter-wiring dielectric layer, each on the component layer, wherein the lower inter-wiring dielectric layer surrounds the wiring structure; an upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer; an insulating recess arranged along an entire edge of the substrate and extending from a top surface of the upper inter-wiring dielectric layer at least to the same level as a bottom surface of the lower inter-wiring dielectric layer;and an upper dielectric cover layer which fills the insulation recess, covers at least a section of the top surface of the upper inter-wiring dielectric layer, and has a step section along at least a section of the edge of the substrate; and a groove or projection in a bottom surface of the step section, wherein the dielectric cover layer comprises a lower dielectric cover layer which conformally covers the side surface of the lower inter-wiring dielectric layer, a top surface of the upper inter-wiring dielectric layer, and an inner and a bottom surface of the insulation recess.

[0009] According to a further aspect of the inventive concept, a semiconductor chip is provided comprising: a component layer on a substrate having four sides forming a rectangular shape in a plan view, the component layer comprising multiple semiconductor components; a wiring structure and a lower inter-wiring dielectric layer, each on the component layer, the lower inter-wiring dielectric layer surrounding the wiring structure; an upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer; and an insulating recess arranged along an entire edge of the substrate, extending from a top surface of the upper inter-wiring dielectric layer to at least the same level as a bottom surface of the lower inter-wiring dielectric layer.a pad structure on the upper inter-wiring dielectric layer and a pad via extending through the upper inter-wiring dielectric layer, the pad via electrically connecting the pad structure to the wiring structure; and an upper dielectric cover layer filling the insulation recess, covering at least a portion of the top surface of the upper inter-wiring dielectric layer, and having a step section along at least one of the four sides of the substrate at a level higher than a top surface of the lower inter-wiring dielectric layer and lower than the top surface of the upper inter-wiring dielectric layer; and a groove or projection in a bottom surface of the step section along at least one of the four sides of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments of the inventive concept will be better understood with reference to the following detailed description in conjunction with the accompanying drawings. The drawings depict the following. Fig. Figures 1 to 7 are cross-sectional views of stages in a process for manufacturing a semiconductor chip according to embodiments; Fig. 8A and Fig. Figure 8B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments; Fig. Figure 9 is a cross-sectional view of a stage in a process for manufacturing a semiconductor chip according to embodiments; Fig. Figure 10 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments; Fig. Figures 11 to 15 are cross-sectional views of stages in a process for manufacturing a semiconductor chip according to embodiments; Fig. Figure 16 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments; Fig. Figure 17 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments; Fig. 18A and Fig. Figure 18B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments; Fig. 19A and Fig. Figure 19B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments; Fig. Figure 20 is a cross-sectional view of a stage in a process for manufacturing a semiconductor chip according to embodiments; Fig. Figure 21 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments; Fig. Figures 22 to 24 are cross-sectional views showing the main elements of semiconductor chips according to embodiments; Fig. 25 and Fig. Figure 26 shows cross-sectional views of stages in a process for manufacturing a semiconductor chip according to embodiments; Fig. Figure 27 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments; Fig. Figures 28 to 30 are cross-sectional views showing the main elements of semiconductor chips according to embodiments; Fig. 31A and Fig. Figure 31B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments; Fig. Figures 32 to 34 are cross-sectional views showing the main elements of semiconductor chips according to embodiments; Fig. 35 and Fig. Figure 36 shows cross-sectional views of stages in a process for manufacturing a semiconductor chip according to embodiments; Fig. 37A and Fig. Figure 37B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments; Fig. Figure 38 is a cross-sectional view of a stage in a process for manufacturing a semiconductor chip according to embodiments; and Fig. 39A and Fig. Figure 39B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0011] Fig. Figures 1 to 7 are cross-sectional views of stages in a process for manufacturing a semiconductor chip according to embodiments. Fig. 8A and Fig. Figure 8B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments.

[0012] As in Fig. As shown in Figure 1, a component layer 130, comprising several semiconductor components 120, is formed on a substrate 110. The substrate 110 can comprise a component region DR, in which the semiconductor components 120 are arranged, and a scribe lane region SR. The scribe lane region SR can surround each of several component regions DR in a top view. Although in Fig. Figure 1 illustrates only two component regions DR and a single groove region SR between two component regions DR. The substrate 110 can comprise multiple component regions DR in a matrix and a groove region SR positioned between adjacent component regions DR such that, in a plan view, it surrounds each component region DR. The groove region SR can be a region that can be removed from a wafer in which the component regions DR were formed, while preserving the functionality of components (for example, components in integrated circuits) formed within the component regions DR.The scribble region SR between the component regions DR can include areas of the wafer in which no circuits (for example, no transistors) are formed and / or no circuits (for example, no transistors) are formed that are part of the integrated circuits of the components in integrated circuits within the component regions DR.

[0013] The scoring trench region SR can comprise a cutting region BR and a remaining scoring region RR. Within the scoring trench region SR, the remaining scoring region RR can be a section that touches a component region DR, and the cutting region BR can be a section separate from the component region DR, with the remaining scoring region RR located between the cutting region BR and the component region DR.

[0014] To place a semiconductor chip 1 in Fig. 8A and Fig. To obtain 8B by separating the component region DR, which comprises several semiconductor components 120, a splitting process can be carried out such that the substrate 110 is cut along the scribed groove region SR, in which the semiconductor components 120 are not arranged. During the splitting process, the cutting region BR is removed, and the remaining scribed region RR can remain around the component region DR. Accordingly, the component region DR and the remaining scribed region RR, which remains in contact with the component region DR, can form a single semiconductor chip and can therefore be collectively referred to as the chip region CR.

[0015] The cutting region BR and the remaining scribble region RR, contained within the scribble groove region SR, are defined as a result of a splitting process and therefore may not be clearly defined prior to the splitting process. However, since the scribble groove region SR is designed to have a larger area than the cutting region BR to prevent damage to the device region DR during the splitting process, the singulated semiconductor chip 1 includes the device region DR and the remaining scribble region RR, that is, a portion of the scribble groove region SR that touches the device region DR along its edge.

[0016] Substrate 110 can, for example, comprise silicon (Si). Substrate 110 can comprise a semiconductor element, for example, germanium (Ge), or a composite semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Substrate 110 can have a silicon-on-insulator (SOI) structure. For example, substrate 110 can comprise a buried oxide layer (BOX). Substrate 110 can comprise a conductive region, for example, a trough doped with impurities or a structure doped with impurities. Substrate 110 can have various insulation structures, including shallow trench isolation (STI). Substrate 110 can have an active side and an inactive side opposite the active side.The component layer 130, which comprises the semiconductor components 120, can be formed on the active side of the substrate 110. For example, the active side can be a main surface of the substrate 110 on which circuits and the semiconductor components 120 are formed, and the inactive side can be a bottom surface of the substrate 110 opposite the main surface of the substrate 110.

[0017] At least some of the semiconductor devices 120 can be transistors. For example, at least some of the semiconductor devices 120 can be bipolar junction transistors (BJTs) or field-effect transistors (FETs). For example, at least some of the semiconductor devices 120 can be planar transistors or FinFETs. If at least some of the semiconductor devices 120 are FinFETs, then several active regions of the Fin type can protrude from the substrate 110 and extend horizontally parallel to each other.

[0018] The semiconductor devices 120 can form a logic cell. The logic cell can comprise several circuit elements, such as a transistor and a register, in various ways. For example, the logic cell can represent an AND gate, a NAND gate, an OR gate, a NOR gate, an exclusive-OR gate (XOR), an exclusive-NOR gate (XNOR), an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), a multiplexer (MXT / MXIT), an OR / AND / inverter (OAI) gate, an AND / OR (AO) gate, an AND / OR / inverter (AOI) gate, a D flip-flop, a reset flip-flop, a master-slave flip-flop, or a latch. The logic cell can represent a standard cell, such as a counter or a buffer, that performs a desired logical function.

[0019] The semiconductor devices 120 can, for example, include various types of individual devices that represent a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a dynamic random access memory (DRAM) device, a static RAM (SRAM) device, a flash memory device, an electrically erasable and programmable read-only memory (EEPROM) device, a phase-change RAM (PRAM) device, a magnetic RAM (MRAM) device, or a resistive RAM (RRAM) device.

[0020] The component layer 130 can comprise the semiconductor devices 120, a conductive line and a conductive connector that electrically connect the semiconductor devices 120, and an interlayer dielectric layer between the conductive connectors. It can include various types and forms of conductive materials, semiconductor materials, and insulating materials. In some embodiments, the interlayer dielectric layer arranged between the conductive line and the conductive connectors can comprise oxide.

[0021] An auxiliary structure 190 can be arranged in the ridge region SR. The auxiliary structure 190 is irrelevant to the operation of the semiconductor devices 120 and can comprise any structure used as an auxiliary structure in the fabrication of the semiconductor devices 120 or used to evaluate the electrical and / or physical properties of the semiconductor devices 120. The auxiliary structure 190 can, for example, comprise a test element group (TEG) or an alignment key. Although it is illustrated that the auxiliary structure 190 is arranged in the device layer 130, this is only an example, and the auxiliary structure 190 can also be located in the substrate 110, the device layer 130, or a section at a higher level than the device layer 130 in a vertical direction from the substrate 110, as shown in Fig. Figures 2 to 7 illustrate how the SR are formed in the Ritzgraben region.

[0022] In the documentation, the term "level" refers to a height from a main surface, for example, the top, of substrate 110 in the vertical direction. For example, "at the same level" or "at a certain level" refers to "the same height from the main surface of substrate 110 in the vertical direction" or "at a specific position that is a certain distance from the main surface of substrate 110 in the vertical direction," and "at a low / high level" refers to "at a low / high position relative to the main surface of substrate 110 in the vertical direction." For example, the height / level can be a distance from the top of substrate 110 in a perpendicular direction relative to the top of substrate 110.

[0023] As in Fig. As shown in Figure 2, a wiring structure MS and a first inter-wiring dielectric layer 210, which surrounds the wiring structure MS, are formed on the substrate 110, which has the device layer 130. The first inter-wiring dielectric layer 210 can comprise an insulating material having a lower permittivity than silicon dioxide. In some embodiments, the first inter-wiring dielectric layer 210 can comprise an ultra-low-k (ULK) film having an ultra-low permittivity of about 2.2 to about 2.4. The ULK film can comprise a SiOC film or a SiCOH film. The first inter-wiring dielectric layer 210 can be referred to as a low-k dielectric layer. In some embodiments, the level of a top surface of the first inter-wiring dielectric layer 210 can be essentially constant. For example, the top surface of the first inter-wiring dielectric layer 210 can be flat.

[0024] Terms such as "the same," "the identical," "planar," or "coplanar," when used in this text to refer to orientation, layout, position, shapes, sizes, quantities, or other dimensions, do not necessarily mean exactly identical orientations, layouts, positions, shapes, sizes, quantities, or other dimensions. Rather, they also encompass nearly identical orientations, layouts, positions, shapes, sizes, quantities, or other dimensions within acceptable tolerances, which may arise, for example, due to manufacturing processes. The term "essentially" may be used in this text to emphasize this meaning, unless the context or other statements require a different interpretation.For example, things described as “essentially the same”, “essentially identical”, or “essentially planar” may be exactly the same, exactly identical, or planar, or they may be the same, identical, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0025] The wiring structure MS can comprise multiple wiring layers ML and multiple through-hole connectors MV electrically / directly connected to the wiring layers ML. The wiring structure MS can, for example, comprise a metal such as aluminum, copper, or tungsten. In some embodiments, the wiring structure MS can comprise a wiring barrier layer and a wiring metal layer. The wiring barrier layer can comprise a nitride or oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or an alloy such as cobalt-tungsten phosphide (CoWP), cobalt-tungsten-boron (CoWB), or cobalt-tungsten-boron phosphide (CoWBP). The wiring metal layer can comprise at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu.

[0026] It is understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to that other element, or there may be intervening elements. However, when an element is described as "directly connected" or "directly coupled" to another element, or as "touching" or "in contact" with another element, there are no intervening elements. Other words used to describe the relationship between elements are to be interpreted similarly (for example, "between" as opposed to "directly between," "next to" as opposed to "directly beside," etc.). For the purposes of this text, "contact" means a direct connection (that is, a touch), unless the context indicates otherwise.

[0027] The inter-wiring layers ML can have a multilayer structure, with the inter-wiring layers ML being present at different levels. The first inter-wiring dielectric layer 210 can have a multilayer structure in which several low-k dielectric layers are stacked according to the multilayer structure of the inter-wiring layers ML. In some embodiments, the first inter-wiring dielectric layer 210 can have a multilayer structure in which an insulating material having a lower permittivity than silicon oxide and another insulating material having a permittivity at least as high as that of silicon oxide are stacked. For example, the multilayer structure of the first inter-wiring dielectric layer 210 can include at least one oxide or nitride layer.For example, the first inter-wiring dielectric layer 210 may include an etch stop layer comprising nitride, which is used in a process for forming the wiring layers ML, but the proportion of the etch stop layer comprising nitride in the first inter-wiring dielectric layer 210 may be relatively very small. For example, the total thickness of the etch stop layer may be less than one-tenth of the total thickness of the first inter-wiring dielectric layer 210. In certain embodiments, the layers having a lower permittivity and the layers having a higher permittivity than silicon oxide may be stacked alternately in the first inter-wiring dielectric layer 210.

[0028] In some embodiments, an underside of a lower wiring layer ML-L, which is located at the lowest level of the wiring layers ML, can be at the same level as an underside of the first interwiring dielectric layer 210.

[0029] Although in Fig. Figure 2 illustrates that an upper surface of a wiring layer ML, located at the highest level of the wiring layers ML, is at the same level as the upper surface of the first inter-wiring dielectric layer 210. While embodiments are not limited to this, in some embodiments an underside of the wiring layer ML, located at the highest level of the wiring layers ML, may also be at the same level as the upper surface of the first inter-wiring dielectric layer 210.

[0030] A lower via connector MV-L, located at the lowest level of the via connectors MV, can extend from the underside of the lower wiring layer ML-L towards the component layer 130. The wiring structure MS can be electrically connected to the semiconductor components 120. The via connectors MV can extend from the underside of each of the wiring layers ML, which are located at different levels in a multilayer structure of wiring layers ML, towards the substrate 110.

[0031] Some of the MV via connectors can electrically / directly connect the wiring layers ML at different levels, and others of the MV via connectors can electrically connect some of the wiring layers ML to the semiconductor devices 120. For example, the lower MV-L via connector can electrically connect the lower wiring layer ML-L to the semiconductor devices 120.

[0032] A second inter-wiring dielectric layer 220 and a sub-pad via SPV are formed on the wiring structure MS and the first inter-wiring dielectric layer 210. The sub-pad via SPV extends through the second inter-wiring dielectric layer 220 and is electrically connected to the wiring structure MS. A sub-pad SPD is formed on the second inter-wiring dielectric layer 220 to be electrically connected to the sub-pad via SPV.

[0033] In some embodiments, the subpad via SPV and the subpad SPD may comprise a barrier layer and a metal layer. The barrier layer may comprise a nitride or oxide of a metal, such as Ti, Ta, Ru, Mn, Co, or W, or an alloy, such as CoWP, CoWB, or CoWBP. The metal layer may comprise at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu.

[0034] The second inter-wiring dielectric layer 220 can comprise an oxide layer, a carbide layer, a polymer, or a combination thereof. For example, the second inter-wiring dielectric layer 220 can comprise an oxide layer. In some embodiments, the second inter-wiring dielectric layer 220 can comprise tetraethyl orthosilicate (TEOS). In some embodiments, the level of a top surface of the second inter-wiring dielectric layer 220 can be substantially constant. For example, the top surface of the second inter-wiring dielectric layer 220 can be flat.

[0035] A third inter-wiring dielectric layer 230, a dielectric protective layer 240, and a fourth inter-wiring dielectric layer 250 are sequentially formed on the sub-pad SPD and the second inter-wiring dielectric layer 220. The third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250 can comprise an oxide layer, a carbide layer, a polymer, or a combination thereof.

[0036] For example, the third inter-wiring dielectric layer 230 can comprise oxide. In some embodiments, the third inter-wiring dielectric layer 230 can comprise high-density plasma (HDP) oxide. For example, the third inter-wiring dielectric layer 230 can comprise an oxide layer (for example, a silicon dioxide layer), and the oxide layer can be formed by a high-density plasma deposition process. In some embodiments, the level of a top surface of the third inter-wiring dielectric layer 230 can change with a step corresponding to the level of the top surfaces of the sub-pad SPD and the second inter-wiring dielectric layer 220.For example, the sub-pad SPD may protrude from the top of the second inter-wiring dielectric layer 220, and the third inter-wiring dielectric layer 230 may have an uneven top surface corresponding to the top surfaces of the sub-pad SPD and the second inter-wiring dielectric layer 220.

[0037] For example, the dielectric protective layer 240 can comprise nitride. The dielectric protective layer 240 can conformally cover the third inter-wiring dielectric layer 230. In some embodiments, the dielectric protective layer 240 can vary in height according to the level of the top of the third inter-wiring dielectric layer 230.

[0038] For example, the fourth inter-wiring dielectric layer 250 can comprise oxide. In some embodiments, the fourth inter-wiring dielectric layer 250 can comprise TEOS. In some embodiments, the level of the top surface of the fourth inter-wiring dielectric layer 250 can be substantially constant. For example, the top surface of the fourth inter-wiring dielectric layer 250 can be flat.

[0039] A pad via PV, extending through the third inter-wiring dielectric layer 230, the dielectric protection layer 240, and the fourth inter-wiring dielectric layer 250, and a pad structure PD, electrically connected to the pad via PV and located on the fourth inter-wiring dielectric layer 250, are formed. In some embodiments, the pad via PV and the pad structure PD may comprise a barrier layer and a metal layer. The barrier layer may comprise a nitride or oxide of a metal, such as Ti, Ta, Ru, Mn, Co, or W, or an alloy, such as CoWP, CoWB, or CoWBP. The metal layer may comprise at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu. The pad via PV may electrically connect the sub-pad SPD to the pad structure PD.The pad structure PD can comprise a redistribution structure and a chip pad connected to the redistribution structure. For example, the pad structure PD can be electrically connected to the redistribution structure and the chip pad. The pad structure PD can, for example, be directly / integrally connected to the redistribution structure (for example, the pad structure PD and the redistribution structure can be a structure of the same metal layer).

[0040] The second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250 can comprise a material having a higher permittivity than the first inter-wiring dielectric layer 210. For example, each of the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250 can comprise an insulating material having a permittivity at least as high as that of silicon dioxide.

[0041] As in Fig. As shown in Figure 3, a hard mask layer 270 is formed, which covers the fourth inter-wiring dielectric layer 250 and the pad structure PD. In some embodiments, the hard mask layer 270 can comprise a carbon-based layer. For example, the carbon-based layer can comprise an amorphous carbon layer (ACL) or a carbon-based spin-on hard mask (C-SOH). Fig. Figure 3 shows a cross-section of a wafer in which finished semiconductor devices are integrally formed in each of the device regions DR. Although only two device regions DR are shown, it is understood that device regions DR can be formed in rows and columns within the wafer (in a two-dimensional arrangement in a top view of the wafer). The device regions DR can be separated from each other by groove regions SR (for example, by forming a lattice in which the cells of the lattice correspond to the device regions DR).

[0042] As in Fig. As shown in Figure 4, the hard mask layer 270 is partially removed to form an opening OP, which exposes the fourth inter-wiring dielectric layer 250 in the screed region SR. In some embodiments, a portion of the fourth inter-wiring dielectric layer 250 in the screed region SR and a portion of the fourth inter-wiring dielectric layer 250 in a section of the device region DR adjacent to the screed region SR can be exposed through the opening OP. For example, the section of the device region DR in which the portion of the fourth inter-wiring dielectric layer 250 is exposed through the opening OP can have a width of about 5 µm or less from the screed region SR.

[0043] Then the fourth inter-wiring dielectric layer 250, the dielectric protective layer 240, the third inter-wiring dielectric layer 230 and the second inter-wiring dielectric layer 220 are partially removed using the hard mask layer 270 as an etching mask, so that an insulation recess SRS is created which exposes the first inter-wiring dielectric layer 210.

[0044] For example, the fourth inter-wiring dielectric layer 250, the dielectric protective layer 240, the third inter-wiring dielectric layer 230 and the second inter-wiring dielectric layer 220 can be partially removed by means of an etching / ashing process.

[0045] As in Fig. As shown in Figure 5, a section of the first inter-wiring dielectric layer 210, exposed at the bottom of the insulating recess SRS, is removed to expose the component layer 130. The section of the first inter-wiring dielectric layer 210 is removed such that the insulating recess SRS can extend into or within the first inter-wiring dielectric layer 210 and expose the component layer 130 at its bottom. The bottom of the insulating recess SRS can be at the same level as the top of the component layer 130.

[0046] The section of the first interwire dielectric layer 210 can be removed by a dry etching process, such as sputtering or reactive ion etching (RIE).

[0047] In some embodiments, a side face of each of the fourth inter-wiring dielectric layer 250, the dielectric protective layer 240, the third inter-wiring dielectric layer 230, the second inter-wiring dielectric layer 220, and the first inter-wiring dielectric layer 210, exposed in the insulation recess SRS, can be essentially smooth. For example, the insulation recess SRS can be formed on side faces of the first, second, third, and fourth inter-wiring dielectric layers 210, 220, 230, and 250, on the side face of the dielectric protective layer 240, and on the top of the component layer 130. For example, a cross-sectional view of the side walls of the insulation recess SRS can be linear, as shown in Fig. 5 shown.

[0048] After the section of the first inter-wiring dielectric layer 210 has been removed, the remaining hard mask layer 270 (in Fig. 4) be removed.

[0049] As in Fig. As shown in Figure 6, an upper dielectric cover layer 290 is formed to fill at least one section of the insulation recess SRS and to cover the fourth inter-wiring dielectric layer 250 and the pad structure PD. The upper dielectric cover layer 290 can be a single layer comprising a single type of insulating layer, a double layer comprising two types of insulating layers, or a multiple layer comprising a combination of at least three types of insulating layers. For example, the upper dielectric cover layer 290 can comprise oxide. In some embodiments, the upper dielectric cover layer 290 can comprise TEOS. For example, the upper dielectric cover layer 290 can comprise oxide, nitride, or a combination thereof. In some embodiments, the upper dielectric cover layer 290 can comprise an HDP oxide layer, a TEOS layer, a silicon nitride layer, or a combination thereof.In some embodiments, the upper dielectric cover layer 290 can have a multilayer in which a layer formed of HDP, a layer formed of TEOS, and a layer formed of silicon nitride are stacked successively.The upper dielectric cover layer 290 can comprise a material having a higher permittivity than the first inter-wiring dielectric layer 210. The upper dielectric cover layer 290 can cover both an inner surface and the bottom surface of the insulating recess SRS. In some embodiments, the lowest level of the top surface of the upper dielectric cover layer 290 can be higher than the level of the top surface of the first inter-wiring dielectric layer 210. For example, the upper dielectric cover layer 290 can completely fill the space of a section of the insulating recess SRS formed in the first inter-wiring dielectric layer 210.

[0050] The upper dielectric cover layer 290 can include a recess section 290R in which the top surface of the upper dielectric cover layer 290 slopes down according to the insulation recess SRS. For example, the recess section 290R can correspond to the insulation recess SRS.

[0051] As in Fig. As shown in Figure 7, an upper portion of the upper dielectric cover layer 290 is removed such that the level of the top surface of the upper dielectric cover layer 290 is substantially constant in the device region DR. For example, the top surface of the upper dielectric cover layer 290 may be flat in the device region DR. In some embodiments, the level of the top surface of the upper dielectric cover layer 290 in a portion of the remaining scribble region RR may be lower than in the device region DR. For example, if the upper portion of the upper dielectric cover layer 290 is removed, the upper dielectric cover layer 290 may include the recess section 290R, which corresponds to the insulating recess SRS. For example, the upper portion of the upper dielectric cover layer 290 may be removed by means of a chemical-mechanical polishing (CMP) process.

[0052] In some embodiments, the underside of the recess section 290R may be located at a lower level than the top of the fourth inter-wiring dielectric layer 250.

[0053] As in Fig. 7, Fig. 8A and Fig. As shown in Figure 8B, a section of the upper dielectric cover layer 290 on the pad structure PD is removed such that a chip pad section CPD of the pad structure PD can be exposed. At least one section of the pad structure PD covered by the upper dielectric cover layer 290 can be a redistribution structure. For example, the chip pad section CPD can be directly connected to the redistribution structure or formed integrally with it.

[0054] Subsequently, a sectioning process is performed to cut the substrate 110 along the groove region SR, thus isolating the semiconductor chip 1. For example, the sectioning process to obtain the semiconductor chip 1 can be performed by sawing / cutting using a saw or cutting blade. A width of the cutting region BR in Fig. 1 to 7 can be essentially equal to the kerf width of a saw or cutting blade used in the parting process to obtain the semiconductor chip 1. The kerf width of a saw or cutting blade can be smaller than the width of the scoring region SR (in Fig. 1 to 7), which is defined between two adjacent component regions DR.

[0055] The semiconductor chip 1 comprises the component layer 130, which includes the semiconductor components 120, on the substrate 110. The substrate 110 can comprise the component region DR, in which the semiconductor components 120 are arranged, and the remaining scribble region RR, which surrounds the component region DR along the edge of the semiconductor chip 1. The remaining scribble region RR can include the scribble groove region SR in Fig. 1 to 7, with the exception of the cutting region BR, which is removed by sawing / cutting using a saw or cutting blade.

[0056] The wiring structure MS and the first inter-wiring dielectric layer 210, which surrounds the wiring structure MS, are arranged on the substrate 110 with the device layer 130. The first inter-wiring dielectric layer 210 can comprise an insulating material having a lower permittivity than silicon oxide. The first inter-wiring dielectric layer 210 can be referred to as a low-k dielectric layer. In some embodiments, the surface level of the first inter-wiring dielectric layer 210 can be essentially constant.

[0057] The wiring structure MS can comprise the wiring layers ML and the via connectors MV electrically connected to the wiring layers ML. The wiring structure MS can be electrically connected to the semiconductor devices 120. The wiring layers ML can have a multilayer structure, with the wiring layers ML located at different levels. The via connectors MV can extend from the underside of each of the wiring layers ML, which are located in a multilayer structure of the wiring layers ML at different levels, towards the substrate 110. Some of the via connectors MV can electrically / directly connect the wiring layers ML at different levels to each other, and others of the via connectors MV can electrically connect some of the wiring layers ML to the semiconductor devices 120.

[0058] In some embodiments, the underside of the lower wiring layer ML-L, located at the lowest level of the wiring layers ML, can be at the same level as the underside of the first inter-wiring dielectric layer 210. The lower via connector MV-L, located at the lowest level of the via connectors MV, can extend from the underside of the lower wiring layer ML-L toward the component layer 130. For example, the lower via connector MV-L can electrically connect the lower wiring layer ML-L to the semiconductor components 120.

[0059] The second inter-wiring dielectric layer 220 and the sub-pad via SPV are arranged on the wiring structure MS and the first inter-wiring dielectric layer 210. The sub-pad via SPV extends through the second inter-wiring dielectric layer 220 and is electrically connected to the wiring structure MS. A sub-pad SPD is arranged on the second inter-wiring dielectric layer 220 to be electrically connected to the sub-pad via SPV. In some embodiments, the level of the top surface of the second inter-wiring dielectric layer 220 can be essentially constant. In some embodiments, the sub-pad via SPV and the sub-pad SPD can be omitted.

[0060] The third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250 are stacked sequentially on the sub-pad SPD and the second inter-wiring dielectric layer 220. In some embodiments, the level of the top surface of the third inter-wiring dielectric layer 230 can change by a step corresponding to the level of the top surfaces of the sub-pad SPD and the second inter-wiring dielectric layer 220. The dielectric protective layer 240 can conformally cover the third inter-wiring dielectric layer 230. In some embodiments, the level of the top surface of the dielectric protective layer 240 can change, for example, by a step corresponding to the level of the top surface of the third inter-wiring dielectric layer 230. The dielectric protective layer 240 can serve as a passivation layer that protects the semiconductor chip 1.In some embodiments, the level of the top of the fourth inter-wiring dielectric layer 250 can be essentially constant.

[0061] The pad structure PD can be arranged on the fourth inter-wiring dielectric layer 250, and the pad via PV can pass through the third inter-wiring dielectric layer 230, the dielectric protective layer 240 and the fourth inter-wiring dielectric layer 250 to electrically connect the sub-pad SPD to the pad structure PD.

[0062] For the sake of a simpler description, the first inter-wiring dielectric layer 210 can be referred to as a lower inter-wiring dielectric layer 210, and the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 240 and the fourth inter-wiring dielectric layer 250 can be referred to together as an upper inter-wiring dielectric layer.For example, the semiconductor chip 1 can comprise the substrate 110, the component layer 130, which includes the semiconductor components 120, on the substrate 110, the wiring structure MS on the component layer 130, the lower inter-wiring dielectric layer 210, which surrounds the wiring structure MS, the upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer 210, the pad structure PD, which includes a chip pad, on the upper inter-wiring dielectric layer, and the pad via PV, which electrically connects the pad structure PD to the wiring structure MS.

[0063] The upper dielectric cover layer 290 can cover a portion of the pad structure PD and the fourth inter-wiring dielectric layer 250. A portion of the pad structure PD not covered by the upper dielectric cover layer 290 can be the chip pad section CPD, and the portion of the pad structure PD covered by the upper dielectric cover layer 290 can be at least partially a redistribution structure. For example, the pad structure PD can include the chip pad section CPD and the redistribution structure.

[0064] The upper dielectric cover layer 290 can cover the side faces of the first inter-wiring dielectric layer 210, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250 in the insulation recess SRS. The upper dielectric cover layer 290 can cover the top surface of the component layer 130 at the bottom of the insulation recess SRS. For example, the upper dielectric cover layer 290 can cover the top surface of an inter-layer dielectric of the component layer 130.

[0065] The upper dielectric cover layer 290 can have a step section ST in an edge of the semiconductor chip 1. For example, the step section ST can be a stepped region of the upper dielectric cover layer 290 extending from the highest flat surface of the upper dielectric cover layer 290. For example, the step section ST can comprise a step formed in the upper dielectric cover layer 290. In certain embodiments, the step section can refer to the step itself. In some embodiments, the step section ST of the upper dielectric cover layer 290 can be formed in the remaining scribble region RR. In some embodiments, the step section ST of the upper dielectric cover layer 290 can be formed across the remaining scribble region RR and a portion of the device region DR adjacent to the remaining scribble region RR.For example, the remaining scribble region RR can be an edge section of the semiconductor chip 1. For example, no semiconductor devices need to be arranged in the edge section of the semiconductor chip 1. For example, the section of the device region DR with which the step section ST overlaps in the vertical direction can overlap a semiconductor device that is formed in the device region DR in the vertical direction.

[0066] The stepped section ST can surround the component region DR along the edge of the semiconductor chip 1. For example, if the semiconductor chip 1 has four sides that form a rectangular shape in a top view, the stepped section ST can be arranged to surround the component region DR along the four sides of the semiconductor chip 1. In some embodiments, the stepped section ST can extend along the four sides of the semiconductor chip 1 with a substantially uniform horizontal width. For example, the stepped section ST can extend along the four sides of the semiconductor chip 1 with a horizontal width of about 5 µm or less. The isolation recess SRS can be arranged along the edge of the semiconductor chip 1. The isolation recess SRS can, for example, extend along the four sides of the semiconductor chip 1.

[0067] The edge or four sides of the semiconductor chip 1 can be referred to as the edge or four sides of the substrate 110.

[0068] The step section ST, for example, the top surface of step section ST, can be located at a lower level than the top surface of the fourth inter-wiring dielectric layer 250. The step section ST, for example, the top surface of step section ST, can be located at a higher level than the top surface of the first inter-wiring dielectric layer 210. The side surface of the upper dielectric cover layer 290 can extend substantially vertically below the step section ST. For example, the side surface of the upper dielectric cover layer 290 can extend substantially vertically with respect to the main surface of the substrate 110 in a section around the first inter-wiring dielectric layer 210, that is, between the levels of the top and bottom surfaces of the first inter-wiring dielectric layer 210.In some embodiments, the side surface of the upper dielectric cover layer 290 above the step section ST can extend at an acute angle with respect to the main surface of the substrate 110.

[0069] According to embodiments, the first interleaving dielectric layer 210, i.e., a low-k dielectric layer, is not chipped by a saw or cutting blade during a severing process for singulating the semiconductor chip 1. For example, during the severing process to obtain the singulated semiconductor chip 1, a cutting process using a saw or cutting blade can be performed through the upper dielectric cover layer 290, the component layer 130, and the substrate 110. Therefore, the saw or cutting blade can pass through the upper dielectric cover layer 290, the component layer 130, and the substrate 110 and does not need to touch the first interleaving dielectric layer 210, which is located in the component region DR of the semiconductor chip 1.Accordingly, chipping of a low-k dielectric layer, which can occur when the low-k dielectric layer is cut using a saw or cutting blade, can be prevented. For example, chipping of the low-k dielectric layer that occurs when the saw or cutting blade touches / penetrates the low-k dielectric layer during the cutting process can be mitigated by the embodiments described above.Therefore, the side surface of the semiconductor chip 1 can be essentially smooth, and accordingly, if an adhesive film such as a non-conductive film (NCF) is applied to the underside of the substrate 110 of the semiconductor chip 1 and a splitting process is performed to separate the semiconductor chip 1, or if an adhesive film such as an NCF is applied to the top or bottom of the semiconductor chip 1 to stack multiple semiconductor chips 1, the adhesive film such as an NCF may not be torn off at the edge of the semiconductor chip 1, which may be caused by flaking of a low-k dielectric layer and / or by flaking of a low-k dielectric layer.

[0070] Fig. Figure 9 is a cross-sectional view of a stage in a process for manufacturing a semiconductor chip according to embodiments. Fig. Figure 10 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments. Fig. 9 is the cross-sectional view of the step, which leads to the step of Fig. 4 follows. Redundant descriptions that resemble or are the same as those already given in relation to Fig. Items 1 to 8B that were given can be omitted. Fig. Numbers 1 to 10 denote identical reference symbols and identical elements.

[0071] As in Fig. As shown in Figure 9, the component layer 130 can be partially removed in a process in which the first inter-wiring dielectric layer 210 is partially removed to expose the component layer 130 such that an insulating recess SRSa can pass through the first inter-wiring dielectric layer 210 and extend into the component layer 130. A bottom surface of the insulating recess SRSa can be located at a lower level than a top surface of the component layer 130.

[0072] As shown in Fig. Fig. As shown in 10, a semiconductor chip 1a is formed by the same processes as those described with reference to Fig. The steps described in sections 6 to 8B will be carried out.

[0073] The semiconductor chip 1a comprises the component layer 130, which includes the semiconductor components 120, on the substrate 110. The substrate 110 can comprise the component region DR, in which the semiconductor components 120 are arranged, and the remaining scribble region RR, which surrounds the component region DR along the edge of the semiconductor chip 1a.

[0074] The upper dielectric cover layer 290 can cover the side faces of the first inter-wiring dielectric layer 210, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250 in the insulating recess SRSa, and cover one side face of an upper section of the component layer 130. The upper dielectric cover layer 290 can extend into the component layer 130 such that the underside of the upper dielectric cover layer 290 is at a lower level than the upper end or top surface of the component layer 130 in the insulating recess SRSa. The upper dielectric cover layer 290 can have a step section ST in an edge of the semiconductor chip 1a.

[0075] Fig. Figures 11 to 15 are cross-sectional views of stages in a process for manufacturing a semiconductor chip according to embodiments. Fig. Figure 16 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments. Fig. 11 is the cross-sectional view of a step, which leads to the step of Fig. 1 follows. Redundant descriptions that resemble or are the same as those already given in relation to Fig. Items 1 to 8B that were given can be omitted. Fig. Numbers 1 to 16 denote identical reference symbols and identical elements.

[0076] As in Fig. As shown in Figure 11, a through-electrode 150 is formed, which extends through the component layer 130 and into the substrate 110. Although the through-electrode 150 extends from the top to the bottom of the substrate 110 and through the substrate 110 into Fig. The passage 11 is just one example. The through-electrode 150 can be formed to extend into the substrate 110, and back-grinding or back-lapping can be performed to partially remove a lower section of the substrate 110 in a subsequent process so that the through-electrode 150 is exposed on the underside of the substrate 110.

[0077] The through-hole electrode 150 can comprise a conductive plug and a conductive barrier layer covering the surface of the conductive plug. The conductive barrier layer can, for example, be arranged on the side face of the conductive plug. For example, the conductive plug can comprise Cu or W. In some embodiments, the conductive plug can comprise, but is not limited to, Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or an alloy of W. In some embodiments, the conductive barrier layer can comprise at least one material selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. In some embodiments, a dielectric via layer can be arranged between the through-hole electrode 150 and the component layer 130 and between the through-hole electrode 150 and the substrate 110.For example, the dielectric through-hole layer can comprise an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination thereof.

[0078] In some embodiments, the conductive barrier layer and the conductive connector can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD), but the embodiments are not limited to these methods. In some embodiments, the dielectric through-hole layer can comprise a high-aspect-ratio process (HARP) oxide film formed by an ozone / tetraethyl orthosilicate (O3 / TEOS)-based subatmospheric CVD process.

[0079] Before or after forming the through-electrode 150, the lower via connector MV-L can be formed such that it extends from the top of the component layer 130 into the component layer 130.

[0080] As in Fig. As shown in Figure 12, a dielectric cover layer 160 is formed such that it covers the component layer 130, the lower via connector MV-L, and the through-electrode 150. The dielectric cover layer 160 can, for example, comprise nitride.

[0081] As in Fig. As shown in Figure 13, the dielectric cover layer 160 is partially removed to expose the lower via connector MV-L and at least a section of the top of the through-hole electrode 150, and then the lower wiring layer ML-L is formed to connect to the lower via connector MV-L and the through-hole electrode 150. Although the dielectric cover layer 160 is not located between the lower wiring layer ML-L and the component layer 130 in Fig. The embodiments are not limited to the location shown in 13. For example, the dielectric cover layer 160 can be located between the lower wiring layer ML-L and the component layer 130, in which the lower via connector MV-L and the through-electrode 150 are not located.

[0082] As in Fig. As shown in Figure 14, a buried dielectric layer 170 is formed such that it covers the side face of the lower wiring layer ML-L. For example, the buried dielectric layer 170 can comprise oxide. In some embodiments, the buried dielectric layer 170 can comprise TEOS. In some embodiments, the level of a top surface of the buried dielectric layer 170 can be essentially constant. For example, the top surfaces of the buried dielectric layer 170 and the lower wiring layer ML-L can be coplanar.

[0083] The dielectric cover layer 160 and the buried dielectric layer 170 can comprise an insulating material having a permittivity at least as high as that of silicon oxide.

[0084] As in Fig. As shown in Figure 15, the wiring structure MS and a first inter-wiring dielectric layer 210a, which surrounds the wiring structure MS, are formed on the substrate 110, which has the lower wiring layer ML-L and the buried dielectric layer 170. The wiring structure MS can comprise several wiring layers ML and several via connectors MV connected to the wiring layers ML. The wiring layers ML comprise the lower wiring layer ML-L, and the via connectors MV comprise the lower via connector MV-L. However, since the lower via connector MV-L and the lower wiring layer ML-L are already, as with reference to Fig. 12 and Fig. As described in 13, the wiring structure MS can be formed by forming the wiring layers ML and the via connectors MV, except for the lower wiring layer ML-L and the lower via connector MV-L, after the buried dielectric layer 170 has been formed.

[0085] The first inter-wiring dielectric layer 210a can comprise an insulating material having a lower permittivity than the dielectric cover layer 160 and the buried dielectric layer 170. The first inter-wiring dielectric layer 210a can comprise an insulating material having a lower permittivity than silicon oxide. In some embodiments, the first inter-wiring dielectric layer 210a can comprise a ULK film having an ultra-low permittivity of about 2.2 to about 2.4. The first inter-wiring dielectric layer 210a can be referred to as a low-k dielectric layer. In some embodiments, the level of a top surface of the first inter-wiring dielectric layer 210a can be substantially constant.

[0086] In some embodiments, an upper surface of the lower wiring layer ML-L, which is located at the lowest level of the wiring layers ML, can be at the same level as an underside of the first inter-wiring dielectric layer 210a.

[0087] As in Fig. As shown in Figure 16, the second inter-wiring dielectric layer 220, the sub-pad via SPV, the sub-pad SPD, the third inter-wiring dielectric layer 230, the dielectric protective layer 240, the fourth inter-wiring dielectric layer 250, the pad via PV and the pad structure PD are formed by carrying out the process described in relation to Fig. 2 was described. After that, the following will be discussed with reference to Fig. The processes described in steps 3 to 8A are carried out, and a lower pad 155 connected to the through-electrode 150 is formed on the underside of the substrate 110, thus forming a semiconductor chip 2. The lower pad 155 can, for example, comprise Ti, Cu, Ni, Au, NiV, NiP, TiNi, TiW, TaN, Al, Pd, CuCr, or a combination thereof.

[0088] Semiconductor chip 2 can move away from semiconductor chip 1. Fig. 8A differ in that the top side of the lower wiring layer ML-L is at the same level as the bottom side of the first inter-wiring dielectric layer 210a, which is at the lowest level of the wiring layers ML. Furthermore, the semiconductor chip 2 can also include the through-electrode 150 and the lower pad 155. Although the through-electrode 150 passes through the component layer 130 and the substrate 110 in Fig. The embodiments are not limited to the path shown in section 16. For example, the through-electrode 150 can be formed such that it extends from the top to the bottom of the substrate 110, passing through the substrate 110, and can be electrically connected to the lower wiring layer ML-L through the lower via connector MV-L or another conductive structure.

[0089] The upper dielectric cover layer 290 can cover the side faces of the first inter-wiring dielectric layer 210a, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250 in an insulating recess SRS. A bottom surface of the insulating recess SRSb, which can correspond to the bottom surface of the upper dielectric cover layer 290, can be at the same level as the top surface of the buried dielectric layer 170. The upper dielectric cover layer 290 can cover the top surface of the buried dielectric layer 170 at the bottom surface of the insulating recess SRSb.

[0090] Fig. Figure 17 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments. Redundant descriptions similar to or identical to those already given in relation to Fig. Numbers 1 to 16 that were given can be omitted. Fig. Numbers 1 to 17 denote identical reference symbols and identical elements.

[0091] As in Fig. As shown in Figure 17, a semiconductor chip 2a comprises an upper dielectric cover layer 290 that fills an insulating recess SRSc. The insulating recess SRSc can extend through the first inter-wiring dielectric layer 210a and into the buried dielectric layer 170. A bottom surface of the insulating recess SRSc can be located at a lower level than the top surface of the buried dielectric layer 170.

[0092] The upper dielectric cover layer 290 can cover the side faces of the first inter-wiring dielectric layer 210a, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250, as well as at least a portion of a side face of the buried dielectric layer 170 in the insulating recess SRSc. The underside of the upper dielectric cover layer 290 can be at a lower level than the top of the buried dielectric layer 170, and the upper dielectric cover layer 290 can extend into the buried dielectric layer 170.

[0093] In some embodiments, the insulating recess SRSc can extend through the buried dielectric layer 170 and the dielectric cover layer 160 and into the component layer 130. The underside of the insulating recess SRSc can be located at a lower level than the upper end of the component layer 130. In this case, the upper dielectric cover layer 290 can cover the side faces of the buried dielectric layer 170 and the dielectric cover layer 160, as well as a side face of an upper section of the component layer 130.

[0094] Fig. 18A and Fig. Figure 18B shows a cross-sectional or top view illustrating the main elements of a semiconductor chip according to embodiments. Redundant descriptions similar to or identical to those already given in relation to Fig. Numbers 1 to 16 that were given can be omitted. Fig. 1 to 18B denote identical reference symbols and identical elements.

[0095] As in Fig. 18A and Fig. As shown in Figure 18B, the upper dielectric cover layer 290 of a semiconductor chip 3 can have a step section ST in an edge region of the semiconductor chip 3. In some embodiments, the step section ST of the upper dielectric cover layer 290 can be formed in the remaining scribble region RR.

[0096] The semiconductor chip 3 only needs the step section ST in a section of its edge. The step section ST can be a section of the underside of the recess section 290R in Fig. 7, the section remaining after a division process to form the semiconductor chip 3. Although the step section ST extends along two sides under the four sides of the semiconductor chip 3, but not along the other two sides in Fig. The embodiments are not limited to those described in 18B. For example, the step section ST need not be arranged along at least one of the four sides of the semiconductor chip 3, but can be arranged along one to three of the other sides.

[0097] In a sectioning process to obtain the semiconductor chip 3, sawing can be performed using a saw blade along the four sides of the semiconductor chip 3. At this point, when the recess section 290R (in Fig. 7) if at least one side of the semiconductor chip 3 is completely cut away in a sawing process using a saw blade, the step section ST is not present on the side of the semiconductor chip 3 and may extend along its other sides. The insulation recess SRS may extend along all four sides of the semiconductor chip 3.

[0098] Fig. 19A and Fig. Figure 19B shows a cross-sectional or top view illustrating the main elements of a semiconductor chip according to embodiments. Redundant descriptions similar to or identical to those already given in relation to Fig. Numbers 1 to 16 that were given can be omitted. Fig. 1 to 19B denote identical reference symbols and identical elements.

[0099] As in Fig. 19A and Fig. As shown in Figure 19B, a semiconductor chip 3a comprises the upper dielectric cover layer 290, which has a groove section STR adjacent to an edge of the semiconductor chip 3a. In some embodiments, the groove section STR of the upper dielectric cover layer 290 can be formed in the remaining scribble region RR. The groove section STR can be arranged in a section of the upper dielectric cover layer 290, the section having a horizontal distance of several µm or less from the edge of the semiconductor chip 3a.

[0100] The semiconductor chip 3a only needs to have the trench section STR in one section of its edge. The trench section STR can be a section of the recess section 290R in Fig. 7, the section remaining after a division process to form the semiconductor chip 3a. Although the trench section STR extends along two sides under the four sides of the semiconductor chip 3a, but not along the other two sides in Fig. The embodiments are not limited to those described in Section 19B. For example, the trench section STR need not be arranged along at least one of the four sides of the semiconductor chip 3a, but may be arranged along one to three of the other sides. In some embodiments, the trench section STR may extend along some of the four sides of the semiconductor chip 3a with a substantially uniform horizontal width. For example, the trench section STR may extend along some of the four sides of the semiconductor chip 3a with a horizontal width of about 5 µm or less. The insulation recess SRS may extend along the four sides of the semiconductor chip 3a. For example, the trench section STR may be formed along one or more of the four sides of the semiconductor chip 3a. In certain embodiments, the trench section STR may be formed along a portion of one side of the semiconductor chip 3a.

[0101] In a sectioning process to obtain the semiconductor chip 3a, sawing can be performed using a saw blade along the four sides of the semiconductor chip 3a. At this point, when the recess section 290R (in Fig. 7) if the trench section STR remains along some of the four sides of the semiconductor chip 3a and is completely cut away along the other sides of the semiconductor chip 3a in a sawing process using a saw blade, the trench section STR may extend along some sides of the semiconductor chip 3a but not along its other sides.

[0102] The ST stage in Fig. 8A, Fig. 8B, Fig. 10, Fig. 16, Fig. 17, Fig. 18A and Fig. 18B and the trench section STR in Fig. 19A and Fig. 19B can collectively be described as a recess structure.

[0103] Fig. Figure 20 is a cross-sectional view of a stage in a process for manufacturing a semiconductor chip according to embodiments. Fig. Figure 21 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments. Fig. 20 is a cross-sectional view of the step, which leads to the step of Fig. 5 follows. Redundant descriptions that resemble or are the same as those already given in relation to Fig. Items 1 to 8B that were given can be omitted. Fig. Numbers 1 to 21 denote identical reference symbols and identical elements.

[0104] As in Fig. As shown in Figure 20, an upper dielectric cover layer 290a is formed to completely fill the insulation recess SRS and to cover the fourth inter-wiring dielectric layer 250 and the pad structure PD. The upper dielectric cover layer 290a can be a single layer comprising a single type of insulating layer, a double layer comprising two types of insulating layers, or a multiple layer comprising a combination of at least three types of insulating layers. For example, the upper dielectric cover layer 290a can comprise oxide. In some embodiments, the upper dielectric cover layer 290a can comprise TEOS. For example, the upper dielectric cover layer 290a can comprise oxide, nitride, or a combination thereof. In some embodiments, the upper dielectric cover layer 290a can comprise an HDP oxide layer, a TEOS layer, a silicon nitride layer, or a combination thereof.In some embodiments, the upper dielectric cover layer 290a can have a multilayer in which a layer formed of HDP, a layer formed of TEOS, and a layer formed of silicon nitride are stacked successively. In some embodiments, the upper dielectric cover layer 290 can have a multilayer in which a layer formed of TEOS, a layer formed of HDP, and a layer formed of silicon nitride are stacked successively. In some embodiments, the upper dielectric cover layer 290 can have a multilayer in which a layer formed of HDP, a layer formed of silicon nitride, and a layer formed of TEOS are stacked successively.The upper dielectric cover layer 290a can comprise a material that has a higher permittivity than the first inter-wiring dielectric layer 210.

[0105] The upper dielectric cover layer 290a can have a flat top surface that is at a substantially constant level.

[0106] As in Fig. As shown in Figure 21, an upper section of the upper dielectric cover layer 290a is partially removed. For example, the upper section of the upper dielectric cover layer 290a can be partially removed using CMP. Subsequently, a section of the upper dielectric cover layer 290a on the pad structure PD can be removed to expose the chip pad section CPD of the pad structure PD. A sectioning process is then performed to cut the substrate 110 along the screed region SR, thereby singulating a semiconductor chip 4.

[0107] The semiconductor chip 4 can comprise the upper dielectric cover layer 290a, which covers the fourth inter-wiring dielectric layer 250 and a section of the pad structure PD. A section of the pad structure PD that is not covered by the upper dielectric cover layer 290a can be the chip pad section CPD, and at least one section of the pad structure PD that is covered by the upper dielectric cover layer 290 can be a redistribution structure.

[0108] The upper dielectric cover layer 290a can cover the side surfaces of the first inter-wiring dielectric layer 210, the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 240, and the fourth inter-wiring dielectric layer 250 in the insulation recess SRS. The upper dielectric cover layer 290a can cover the top surface of the component layer 130 on the bottom surface of the insulation recess SRS.

[0109] The upper dielectric cover layer 290a can have a side surface that extends along an edge of the semiconductor chip 4 substantially in the vertical direction with respect to the substrate 110, for example, with respect to the top surface of the substrate 110. The side surface of the upper dielectric cover layer 290a can extend from the top surface of the component layer 130 to at least a level higher than the top surface of the fourth interleaving dielectric layer 250 in the vertical direction with respect to the substrate 110, for example, with respect to the top surface of the substrate 110. For example, the upper dielectric cover layer 290a does not need to extend the Fig. 8A and Fig. 8B shows the stage section ST.

[0110] Fig. Figures 22 to 24 are cross-sectional views showing the main elements of semiconductor chips according to embodiments. Redundant descriptions similar to or identical to those already given with respect to Fig. Numbers 1 to 20 that were given can be omitted. Fig. Numbers 1 to 24 denote identical reference symbols and identical elements.

[0111] As in Fig. As shown in Figure 22, a semiconductor chip 4a can include an isolation recess SRSa having a bottom surface at a lower level than an upper surface of a component layer 130, which extends from the isolation recess SRS of the semiconductor chip 4. Fig. 21 distinguishes.

[0112] As in Fig. As shown in 23, a semiconductor chip 5 can have an upper dielectric cover layer 290a similar to that of the semiconductor chip 4 of Fig. 21 comprise, which extend from the upper dielectric cover layer 290 with the step section ST in the semiconductor chip 2 of Fig. 16 differs.

[0113] As in Fig. As shown in Figure 24, a semiconductor chip 5a can have an upper dielectric cover layer 290a similar to that of the semiconductor chip 4. Fig. 21 comprise, which extend from the upper dielectric cover layer 290 with the step section ST in the semiconductor chip 2a of Fig. 17 differs.

[0114] Fig. 25 and Fig. Figure 26 shows cross-sectional views of stages in a process for manufacturing a semiconductor chip according to embodiments. Fig. Figure 27 is a cross-sectional view showing the main elements of a semiconductor chip according to embodiments. Fig. 25 is the cross-sectional view of a step, which leads to the step of Fig. 3 follows. Redundant descriptions that resemble or are the same as those already given in relation to Fig. Items 1 to 8B that were given can be omitted. Fig. Numbers 1 to 27 denote identical reference symbols and identical elements.

[0115] As in Fig. As shown in Figure 25, the hard mask layer 270 is partially removed to form the opening OP, which exposes the fourth inter-wiring dielectric layer 250 in the screed region SR, as above with reference to Fig. 4 described. Thereafter, the fourth inter-wiring dielectric layer 250, the dielectric protective layer 240, the third inter-wiring dielectric layer 230, the second inter-wiring dielectric layer 220 and the first inter-wiring dielectric layer 210 are partially removed using the hard mask layer 270 as an etching mask, such that an insulating recess SRSd is formed, which exposes the component layer 130.

[0116] For example, the fourth inter-wiring dielectric layer 250, the dielectric protective layer 240, the third inter-wiring dielectric layer 230, the second inter-wiring dielectric layer 220, and the first inter-wiring dielectric layer 210 can be partially removed by an ashing / etching process. While, for example, the insulation recess SRS in Fig. 5. The insulation recess SRSd can be formed by separately performing a process for removing the fourth inter-wiring dielectric layer 250, the dielectric protective layer 240, the third inter-wiring dielectric layer 230, and the second inter-wiring dielectric layer 220, and a process for removing the first inter-wiring dielectric layer 210. Fig. 25 formed by performing a single process to completely remove the fourth inter-wiring dielectric layer 250, the dielectric protective layer 240, the third inter-wiring dielectric layer 230, the second inter-wiring dielectric layer 220 and the first inter-wiring dielectric layer 210.

[0117] In some embodiments, the side surface of each of the fourth inter-wiring dielectric layer 250, the dielectric protective layer 240, the third inter-wiring dielectric layer 230, and the second inter-wiring dielectric layer 220, which is exposed in the insulating recess SRSd, can be substantially smooth, and the side surface of the first inter-wiring dielectric layer 210, which is exposed in the insulating recess SRSd, can have a coarse section RGN. For example, the coarse section RGN of the first inter-wiring dielectric layer 210 can be rougher than the side surfaces of the second inter-wiring dielectric layer 220, the third inter-wiring dielectric layer 230, the dielectric protective layer 220, and the fourth inter-wiring dielectric layer 250.

[0118] As in Fig. As shown in Figure 26, a lower dielectric cover layer 260 is formed to conformally cover the inner and bottom surfaces of the insulation recess SRSd and the top surfaces of the fourth inter-wiring dielectric layer 250 and the pad structure PD. For example, the lower dielectric cover layer 260 can comprise nitride. The lower dielectric cover layer 260 can cover the coarse section RGN in the side surface of the first inter-wiring dielectric layer 210.

[0119] As in Fig. 27 shows the same processes as those described in relation to Fig. As described in sections 6 to 8B, a section of the lower dielectric cover layer 260 on the pad structure PD is also removed when a section of the upper dielectric cover layer 290 on the pad structure PD is removed to expose the chip pad section CPD of the pad structure PD, thereby forming a semiconductor chip 6. The lower dielectric cover layer 260 and the upper dielectric cover layer 290 can together be referred to as a dielectric cover layer.

[0120] In contrast to the semiconductor chip 1 of Fig. 8A the semiconductor chip 6 can further comprise the coarse section RGN in the side surface of the first inter-wiring dielectric layer 210 and the lower dielectric cover layer 260, which covers the inner and bottom surface of the insulation recess SRSd, the top surface of the fourth inter-wiring dielectric layer 250 and a section of the top and side surface of the pad structure PD, and the upper dielectric cover layer 290 can be arranged on the lower dielectric cover layer 260.

[0121] Since the coarse section RGN in the side surface of the first inter-wiring dielectric layer 210 is covered with the lower dielectric cover layer 260 and the upper dielectric cover layer 290 in the semiconductor chip 6, the coarse section RGN may not cause damage to the upper dielectric cover layer 290 or flaking of an adhesive film, for example an NCF.

[0122] Fig. Figures 28 to 30 are cross-sectional views showing the main elements of semiconductor chips according to embodiments. Redundant descriptions similar to or identical to those already given in relation to Fig. Numbers 1 to 27 that were given can be omitted. Fig. Numbers 1 to 30 denote identical reference symbols and identical elements.

[0123] As in Fig. 28 shows, in contrast to the semiconductor chip 1a of Fig. 10 a semiconductor chip 6a further comprising the coarse section RGN in the side face of the first inter-wiring dielectric layer 210 and the lower dielectric cover layer 260, which covers the inner and bottom of the insulating recess SRSd, the top of the fourth inter-wiring dielectric layer 250 and a section of the top and side face of the pad structure PD, and the upper dielectric cover layer 290 can be arranged on the lower dielectric cover layer 260. Similar to the insulating recess SRSa of the semiconductor chip 1a of Fig. 10. The insulation recess SRSe can extend through the first inter-wiring dielectric layer 210 and into the component layer 130. The underside of the insulation recess SRSc can be located at a lower level than the upper end of the component layer 130.

[0124] As in Fig. As shown in 29, unlike the semiconductor chip 2 of Fig. 16 a semiconductor chip 7 further comprising the coarse section RGN in the side face of the first inter-wiring dielectric layer 210a and the lower dielectric cover layer 260, which covers the inner and bottom of the insulating recess SRSd, the top of the fourth inter-wiring dielectric layer 250 and a section of the top and side face of the pad structure PD, and the upper dielectric cover layer 290 can be arranged on the lower dielectric cover layer 260. Similar to the insulating recess SRSb of the semiconductor chip 2 of Fig. 16. The underside of the insulation recess SRSf of the semiconductor chip 7 can be at the same level as the top side of the buried dielectric layer 170. For example, the underside of the insulation recess SRSf of the semiconductor chip 7 can correspond to the top side of the buried dielectric layer 170 in the insulation recess SRSf.

[0125] As in Fig. 30 shown, unlike the semiconductor chip 2a of Fig. 17 a semiconductor chip 7a further comprising the coarse section RGN in the side face of the first inter-wiring dielectric layer 210a and the lower dielectric cover layer 260, which covers the inner and bottom of the insulating recess SRSd, the top of the fourth inter-wiring dielectric layer 250 and a section of the top and side face of the pad structure PD, and the upper dielectric cover layer 290 can be arranged on the lower dielectric cover layer 260. Similar to the insulating recess SRSc of the semiconductor chip 2a of Fig. 17. The underside of the insulation recess SRSg of the semiconductor chip 7 can be at a lower level than the top of the buried dielectric layer 170.

[0126] Fig. 31A and Fig. Figure 31B shows a cross-sectional or top view illustrating the main elements of a semiconductor chip according to embodiments. Redundant descriptions similar to or identical to those already given in relation to Fig. Numbers 1 to 30 that were given can be omitted. Fig. 1 to 31B denote identical reference symbols and identical elements.

[0127] As in Fig. 31A and Fig. As shown in Figure 31B, a semiconductor chip 8 can comprise an upper dielectric cover layer 295, which differs from the upper dielectric cover layer 290 found in the semiconductor chip 6 of Fig. 27. The upper dielectric cover layer 295 need not fill the insulating recess SRSd and need only be arranged on a section of the lower dielectric cover layer 260, wherein the section of the lower dielectric cover layer 260 covers the top surface of the fourth inter-wiring dielectric layer 250 and the side surface and a section of the top surface of the pad structure PD. For example, the upper dielectric cover layer 295 can comprise photosensitive polyimide (PSPI).

[0128] The isolation recess SRSd can extend along four sides of the semiconductor chip 8.

[0129] Since the coarse RGN section in the side surface of the first inter-wiring dielectric layer 210 is covered with the lower dielectric cover layer 260 in the semiconductor chip 8, flaking of an adhesive film, for example an NCF, may not be caused by the coarse RGN section of the first inter-wiring dielectric layer 210.

[0130] Fig. Figures 32 to 34 are cross-sectional views showing the main elements of semiconductor chips according to embodiments. Redundant descriptions similar to or identical to those already given with respect to Fig. Items 1 to 31B that were given can be omitted. Fig. Numbers 1 to 34 denote identical reference symbols and identical elements.

[0131] As in Fig. As shown in Figure 32, a semiconductor chip 8a can comprise an upper dielectric cover layer 295, which differs from the upper dielectric cover layer 290 found in semiconductor chip 6a. Fig. 28 is included. The upper dielectric cover layer 295 does not need to fill the insulation recess SRSe and only needs to be arranged on a section of the lower dielectric cover layer 260, wherein the section of the lower dielectric cover layer 260 covers the top of the fourth inter-wiring dielectric layer 250 and the side surface and a section of the top of the pad structure PD.

[0132] As in Fig. As shown in Figure 33, a semiconductor chip 9 can comprise an upper dielectric cover layer 295, which differs from the upper dielectric cover layer 290 found in the semiconductor chip 7 of Fig. 29 is included. The upper dielectric cover layer 295 does not need to fill the insulation recess SRSf and only needs to be arranged on a section of the lower dielectric cover layer 260, wherein the section of the lower dielectric cover layer 260 covers the top of the fourth inter-wiring dielectric layer 250 and the side surface and a section of the top of the pad structure PD.

[0133] As in Fig. As shown in Figure 34, a semiconductor chip 9a can comprise an upper dielectric cover layer 295, which differs from the upper dielectric cover layer 290 in the semiconductor chip 7a of Fig. 30 is included. The upper dielectric cover layer 295 does not need to fill the insulation recess SRSg and only needs to be arranged on a section of the lower dielectric cover layer 260, wherein the section of the lower dielectric cover layer 260 covers the top of the fourth inter-wiring dielectric layer 250 and the side surface and a section of the top of the pad structure PD.

[0134] Fig. 35 and Fig. Figure 36 shows cross-sectional views of stages in a process for manufacturing a semiconductor chip according to embodiments. Fig. 37A and Fig. Figure 37B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments. Fig. 35 is the cross-sectional view of a step, which leads to the step of Fig. 5 follows. Redundant descriptions that resemble or are the same as those already given in relation to Fig. Items 1 to 8B that were given can be omitted. Fig. 1 to 37B denote identical reference symbols and identical elements.

[0135] As in Fig. 35 shows, similar to the upper dielectric cover layer 290 in Fig. 6 and Fig. 7. An upper dielectric cover layer 290 is formed to fill at least one section of the insulation recess SRS and to cover a fourth inter-wiring dielectric layer 250 and a pad structure PD, and an upper section of the upper dielectric cover layer 290 is partially removed. The level of the top of the upper dielectric cover layer 290 is essentially constant in the device region DR. The upper dielectric cover layer 290 can include a recess section 290Ra corresponding to the insulation recess SRS.

[0136] In some embodiments, the underside of the recess section 290Ra may be located at a higher level than the top of the fourth inter-wiring dielectric layer 250. In some embodiments, the underside of the recess section 290Ra may be located at a lower level than the top of the pad structure PD.

[0137] As in Fig. As shown in Figure 36, an extended recess section 292R is formed by removing a section of the upper dielectric cover layer 290 adjacent to the recess section 290Ra. The extended recess section 292R can be formed by removing a section of the upper dielectric cover layer 290 adjacent to the recess section 290Ra using a photolithography or etching process. The extended recess section 292R can be formed such that it is connected to and open towards the recess section 290Ra. Although the recess section 290Ra and the extended recess section 292R are formed separately and therefore named individually, the recess section 290Ra can be considered to be extended to the extended recess section 292R, given the result of forming the extended recess section 292R.Therefore, the recess section 290Ra and the extended recess section 292R can be referred to together as one recess section.

[0138] Although one underside of the extended recess section 292R is at a higher level than the underside of the recess section 290Ra in Fig. 36, the embodiments are not limited thereto. For example, the underside of the extended recess section 292R may be at the same level as the underside of the recess section 290Ra or at a lower level than it.

[0139] In a process for removing a section of the upper dielectric cover layer 290 to form the extended recess section 292R, a further section of the upper dielectric cover layer 290 between the recess section 290Ra and the extended recess section 292R, that is, a section of the upper dielectric cover layer 290 in which the recess section 290Ra overlaps the extended recess section 292R, is removed so that a groove section SLP can be formed between the recess section 290Ra and the extended recess section 292R. A lower end of the groove section SLP can be located at a lower level than the bottom of the recess section 290Ra and the bottom of the extended recess section 292R.For example, the groove section SLP can comprise a groove that is an extending narrow channel formed on a surface of the upper dielectric cover layer 290 between the extended recess section 292R and the recess section 290Ra. In certain embodiments, the groove section SLP can refer to the groove itself.

[0140] As in Fig. As shown in Figures 36 to 37B, a section of the upper dielectric cover layer 290 on the pad structure PD can be removed to expose the chip pad section CPD of the pad structure PD.

[0141] Subsequently, a division process is carried out to cut the substrate 110 along the slit region SR, thereby isolating a semiconductor chip 10.

[0142] In contrast to the semiconductor chip 1 of Fig. In embodiment 8A, the semiconductor chip 10 comprises the upper dielectric cover layer 290, which has a step section STa extending over the remaining scribble region RR and a section of the device region DR adjacent to the remaining scribble region RR. In some embodiments, the step section ST can extend along four sides of the semiconductor chip 10 with a substantially uniform horizontal width. For example, the step section ST can extend along the four sides of the semiconductor chip 10 with a horizontal width of about 10 µm or less.

[0143] The step section STa can be located at a higher level than the top of the fourth inter-wiring dielectric layer 250. The step section STa can be located at a lower level than the top of the chip pad section CPD.

[0144] The step section STa can have the slot section SLP on its underside. The slot section SLP can surround the component region DR along an edge of the semiconductor chip 10. For example, if the semiconductor chip 10 has four sides that form a rectangular shape in a top view, the slot section SLP can be arranged to surround the component region DR along the four sides of the semiconductor chip 10.

[0145] Fig. Figure 38 is a cross-sectional view of a stage in a process for manufacturing a semiconductor chip according to embodiments. Fig. 39A and Fig. Figure 39B shows a cross-sectional view or a top view showing the main elements of a semiconductor chip according to embodiments. Fig. 38 is the cross-sectional view of the step, which leads to the step of Fig. 35 follows. Redundant descriptions that resemble or are the same as those already given in relation to Fig. Items 1 to 37B that were given can be omitted. Fig. 1 to 39B denote identical reference symbols and identical elements.

[0146] As in Fig. As shown in Figure 38, an extended recess section 292Ra is formed by removing a section of the upper dielectric cover layer 290 adjacent to the recess section 290Ra. The extended recess section 292Ra can be formed by removing a section of the upper dielectric cover layer 290 adjacent to the recess section 290Ra using a photolithography or etching process. The extended recess section 292Ra can be formed such that it is connected to and open towards the recess section 290Ra. Although the recess section 290Ra and the extended recess section 292Ra are formed separately and therefore named individually, the recess section 290Ra can be considered, given the result of forming the extended recess section 292Ra, as being extended towards the extended recess section 292Ra.Therefore, the recess section 290Ra and the extended recess section 292Ra can be referred to together as one recess section.

[0147] Although one underside of the extended recess section 292Ra is at a higher level than the underside of the recess section 290Ra in Fig. 38, the embodiments are not limited thereto. For example, the underside of the extended recess section 292Ra may be at the same level as the underside of the recess section 290Ra or at a lower level than it.

[0148] In a process for removing a portion of the upper dielectric cover layer 290 to form the extended recess section 292R, a portion of the upper dielectric cover layer 290 between the recess section 290Ra and the extended recess section 292Ra may be removed less, such that a projection section PRP may be formed between the recess section 290Ra and the extended recess section 292Ra. An upper end of the projection section PRP may be located at a higher level than the bottom of the recess section 290Ra and the bottom of the extended recess section 292Ra. For example, the projection section PRP may include a projection extending along and between the recess section 290Ra and the extended recess section 292Ra on a surface of the upper dielectric cover layer 290.In certain embodiments, the projection section SLP can refer to the projection itself.

[0149] As in Fig. As shown in Figures 38 to 39B, a section of the upper dielectric cover layer 290 on the pad structure PD can be removed to expose the chip pad section CPD of the pad structure PD.

[0150] Subsequently, a division process is carried out to cut the substrate 110 along the slit region SR, thereby singulating a semiconductor chip 10a.

[0151] In contrast to the semiconductor chip 10 of Fig. In embodiment 37A, the semiconductor chip 10a comprises the upper dielectric cover layer 290, which has a step section STb extending over the remaining scribble region RR and a section of the device region DR adjacent to the remaining scribble region RR. In some embodiments, the step section STb can extend along four sides of the semiconductor chip 10a with a substantially uniform horizontal width. For example, the step section STb can extend along the four sides of the semiconductor chip 10a with a horizontal width of about 10 µm or less.

[0152] The step section STb can be located at a higher level than the top of the fourth inter-wiring dielectric layer 250. The step section STb can be located at a lower level than the top of the chip pad section CPD.

[0153] The step section STb can have the projection section PRP on its underside. The projection section PRP can surround the device region DR along an edge of the semiconductor chip 10a. For example, if the semiconductor chip 10a has four sides that form a rectangular shape in a top view, the projection section PRP can be arranged to surround the device region DR along the four sides of the semiconductor chip 10a.

[0154] Although not shown, similar to the semiconductor chip 3, they can Fig. 18A and Fig. 18B, the semiconductor chip 10 of the Fig. 37A and Fig. 37B and the semiconductor chip 10a Fig. 39A and Fig. 39B each have the step sections STa and STb, each of which is not arranged along at least one of the four sides of the semiconductor chip 10 or 10a, but along one to three of the other sides. Similar to the semiconductor chip 3a from Fig. 19A and Fig. 19B can be the semiconductor chip 10 Fig. 37A and Fig. 37B and the semiconductor chip 10a from Fig. 39A and Fig. 39B instead of the step section STa or STb have the trench section STR, which is not arranged along at least one of the four sides of the semiconductor chip 10 or 10a, but along the other one to three sides.

[0155] In some embodiments, the slot section SLP of the semiconductor chip requires 10 Fig. 37A and Fig. 37B or the protrusion section PRP of the semiconductor chip 10 from Fig. 39A and Fig. 39B need not be arranged along at least one of the four sides of the semiconductor chip 10 or 10a, but may be arranged along the other one to three sides.

Claims

[1] Semiconductor chip (1), comprising: a component layer (130) on a substrate (110), wherein the component layer (130) comprises several semiconductor components (120); a wiring structure (MS) and a lower inter-wiring dielectric layer (210) each on the device layer (130), wherein the lower inter-wiring dielectric layer (210) surrounds the wiring structure (MS) and has a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer (220-250) on the lower inter-wiring dielectric layer (210), wherein the upper inter-wiring dielectric layer (220-250) has a permittivity that is at least as high as the permittivity of silicon oxide; an insulating recess (SRS) along an edge of the substrate (110), wherein the insulating recess (SRS) is formed on a side face of the lower inter-wiring dielectric layer (210) and a side face of the upper inter-wiring dielectric layer (220-250), wherein the insulating recess (SRS) has a bottom surface at a level that is not higher than the level of a bottom surface of the lower inter-wiring dielectric layer (210); and a dielectric cover layer (290) which covers the side surfaces of the lower inter-wiring dielectric layer (210) and the upper inter-wiring dielectric layer (220-250) and the underside of the insulation recess (SRS), wherein the substrate (110) has four sides which form a rectangular shape in a top view, wherein the dielectric cover layer (290) has a step section (ST) along at least one of the four sides of the substrate (110), and wherein a groove or projection is formed in a bottom side of the step section (ST) along at least one of the four sides of the substrate (110). [2] Semiconductor chip (1) according to claim 1, wherein the step section (ST) of the dielectric cover layer (290) extends along the four sides of the substrate (110). [3] Semiconductor chip (1) according to claim 1, wherein the step section (ST) of the dielectric cover layer (290) is located at a higher level than a top surface of the lower inter-wiring dielectric layer (210) and at a lower level than a top surface of the upper inter-wiring dielectric layer (220-250). [4] Semiconductor chip (1) according to claim 1, wherein the step section (ST) of the dielectric cover layer (290) is located at a higher level than a top surface of the upper inter-wiring dielectric layer (220-250). [5] Semiconductor chip (1) according to claim 1, wherein the dielectric cover layer (290) has a groove along some of the four sides of the substrate (110). [6] Semiconductor chip (1) according to claim 1, wherein the dielectric cover layer comprises a lower dielectric cover layer (260) covering the side surface of the lower inter-wiring dielectric layer (210) and conformally covering a top surface of the upper inter-wiring dielectric layer (220-250) as well as an inner and a bottom surface of the insulation recess (SRS). [7] Semiconductor chip (1) according to claim 6, wherein the dielectric cover layer further comprises an upper dielectric cover layer (290) which fills the insulation recess (SRS) and covers the lower dielectric cover layer (260). [8] Semiconductor chip (1) according to claim 6, wherein the dielectric cover layer further comprises an upper dielectric cover layer (290) covering a section of the lower dielectric cover layer (260) on the top side of the upper inter-wiring dielectric layer (220-250), wherein the upper dielectric cover layer (290) has a multilayer in which a high-density plasma (HDP) layer, a tetraethyl orthosilicate (TEOS) layer and a silicon nitride layer are stacked successively. [9] Semiconductor chip (1) according to claim 1, wherein the wiring structure (MS) comprises several wiring layers (ML), which include a lower wiring layer (ML-L) at the lowest level of the several wiring layers, and a bottom side of the lower wiring layer (ML-L) is at the same level as the bottom side of the lower interwiring dielectric layer (210). [10] Semiconductor chip (1) according to claim 1, wherein the wiring structure (MS) comprises several wiring layers (ML), which include a lower wiring layer (ML-L) at the lowest level of the several wiring layers, and a top surface of the lower wiring layer (ML-L) is at the same level as the bottom surface of the lower interwiring dielectric layer (210). [11] Semiconductor chip (1) according to claim 10, further comprising: a lower pad (155) on a bottom side of the substrate (110); and a through-electrode (150) that passes through the component layer (130) and the substrate (110) and electrically connects the lower wiring layer (ML-L) to the lower pad. [12] Semiconductor chip (1), comprising: a component layer (130) on a substrate (110), wherein the component layer (130) comprises several semiconductor components (120); a wiring structure (MS) and a lower inter-wiring dielectric layer (210) each on the device layer (130), wherein the lower inter-wiring dielectric layer (210) surrounds the wiring structure (MS); an upper inter-wiring dielectric layer (220-250) on the lower inter-wiring dielectric layer (210); an insulation recess (SRS) arranged along an entire edge of the substrate (110) and extending from a top surface of the upper inter-wiring dielectric layer (220-250) at least to the same level as a bottom surface of the lower inter-wiring dielectric layer (210); an upper dielectric cover layer (290) which fills the insulation recess (SRS), covers at least a section of the top surface of the upper inter-wiring dielectric layer (220-250), and has a step section (ST) along at least a section of the edge of the substrate (110); and a groove or projection in a bottom side of the step section (ST), wherein the dielectric cover layer comprises a lower dielectric cover layer (260) conformally covering the side surface of the lower inter-wiring dielectric layer (210), a top surface of the upper inter-wiring dielectric layer (220-250) and an inner and a bottom surface of the insulation recess (SRS). [13] Semiconductor chip (1) according to claim 12, wherein the insulation recess (SRS) further extends below the level of the underside of the lower inter-wiring dielectric layer (210) into the component layer (130). [14] Semiconductor chip (1) according to claim 12, wherein the lower inter-wiring dielectric layer (210) is a dielectric layer (170) with a low k-value, which has a lower permittivity than silicon oxide, and a permittivity of the upper inter-wiring dielectric layer (220-250) is greater than a permittivity of the lower inter-wiring dielectric layer (210). [15] Semiconductor chip (1) according to claim 12, wherein the step section (ST) of the dielectric top layer (290) is located at a higher level than a top surface of the lower inter-wiring dielectric layer (210). [16] Semiconductor chip (1), comprising: a component layer (130) on a substrate (110) having four sides which form a rectangular shape in a top view, wherein the component layer (130) comprises several semiconductor components (120); a wiring structure (MS) and a lower inter-wiring dielectric layer (210) each on the device layer (130), wherein the lower inter-wiring dielectric layer (210) surrounds the wiring structure (MS); an upper inter-wiring dielectric layer (220-250) on the lower inter-wiring dielectric layer (210); an insulation recess (SRS) arranged along an entire edge of the substrate (110) and extending from a top surface of the upper inter-wiring dielectric layer (220-250) at least to the same level as a bottom surface of the lower inter-wiring dielectric layer (210); a pad structure (PD) on the upper inter-wiring dielectric layer (220-250) and a pad via (PV) passing through the upper inter-wiring dielectric layer (220-250), wherein the pad via (PV) electrically connects the pad structure (PD) to the wiring structure (MS); an upper dielectric cover layer (290) which fills the insulation recess (SRS), covers at least a section of the top surface of the upper inter-wiring dielectric layer (220-250), and has a step section (ST) along at least one of the four sides of the substrate (110) at a level that is higher than the top surface of the lower inter-wiring dielectric layer (210) and lower than the top surface of the upper inter-wiring dielectric layer (220-250); and a groove or projection in an underside of the step section along at least one of the four sides of the substrate. [17] Semiconductor chip (1) according to claim 16, wherein the step section (ST) of the upper dielectric cover layer (290) extends along the four sides of the substrate (110). [18] Semiconductor chip (1) according to claim 16, wherein the isolation recess (SRS) extends along the four sides of the substrate (110).

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