PACKAGE AND METHOD FOR ITS MANUFACTURING

Abstract

Integrated circuit package (301, 401, 501, 601) with: a photonic integrated circuit die (50C; 50D), wherein the photonic integrated circuit die (50C; 50D) has an optical coupler (76; 78); an encapsulation material (120) that encapsulates the photonic integrated circuit die (50C; 50D), wherein a first surface of the photonic integrated circuit die (50C; 50D) is at the same level as a first surface of the encapsulation material (120); a first redistribution structure (122) on the photonic integrated circuit die (50C; 50D) and the encapsulation material (120); and an opening (304; 504) that exposes the optical coupler (76; 78), with one side wall of the opening extending through the first redistribution structure (122).

Description

background

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely attributable to the repeated reduction of the smallest feature size, allowing more components to be integrated into a given area. As the demand for miniaturized electronic devices has intensified, a need has arisen for methods to create smaller and more innovative packaging for semiconductor dies. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to achieve a high level of integration and high component density.PoP technology enables the fabrication of semiconductor devices with improved functionalities and small footprints on a printed circuit board (PCB).

[0002] Manufacturing methods for photonic integrated circuits are known, for example, from WO 2019 / 050 477 A1, US 2019 / 0 146 166 A1 and US 2019 / 0 285 804 A1.

[0003] WO 2019 / 050477 A1 discloses a method for fabricating a photonically integrated circuit. The method may include forming a redistribution layer (RDL) over a substrate. The method may also include forming a through-hole or cavity on the redistribution layer. Additionally, the method may include providing a stop ring structure, wherein the stop ring structure comprises a ring of suitable material and defines a cavity above the redistribution layer, such that the cavity is located above the through-hole or cavity.

[0004] US Patent 2019 / 0 146 166 A1 discloses a semiconductor device comprising a photonic integrated circuit, an electronic integrated circuit, and a high-power integrated circuit. The electronic integrated circuit is arranged adjacent to the photonic integrated circuit and electrically connected to it via a first redistribution structure. The high-power integrated circuit is also arranged adjacent to the electronic integrated circuit and electrically connected to it via a second redistribution structure. US Patent 2019 / 0 285 804 A1 discloses a photonic integrated circuit (PIC) fan-out device and associated fabrication methods.The PIC fan-out device comprises an overmold body, a PIC chip containing electro-optical circuitry arranged within the overmold body, a plurality of optical fiber segments functionally coupled to the electro-optical circuitry, a fiber coupling interface on a side face of the overmold body for coupling the plurality of optical fiber segments to external optical fibers by means of a connector, an additional component arranged within the overmold body, an interposer with a redistribution layer (RDL) located adjacent to the overmold body and electrically connected to the PIC chip and the additional component, and a ball grid array (BGA) electrically connected to the PIC chip and the additional component via the RDL interposer, wherein the BGA is configured to electrically couple the PIC chip and the additional component to a printed circuit board (PCB). Brief description of the drawings

[0005] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 shows a sectional view of an integrated circuit die according to some embodiments. Fig. Figure 2 shows a sectional view of an integrated circuit die according to some embodiments. Fig. Figure 3 shows a sectional view of an integrated circuit die according to some embodiments. Fig. Figure 4 shows a sectional view of an integrated circuit die according to some embodiments. The Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 to Fig. Figure 14 shows sectional views of intermediate stages in a manufacturing process for a package according to exemplary embodiments. The Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. Figure 22 shows sectional views of intermediate stages in a manufacturing process for a package according to some embodiments. The Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. Figure 32 shows sectional views of intermediate stages in a manufacturing process for a package according to some embodiments. Fig. Figure 33 shows a sectional view of a package according to some embodiments. The Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. Figure 43 shows sectional views of intermediate stages in a manufacturing process for a package according to some embodiments. Fig. Figure 44 shows a sectional view of a package according to some embodiments. Detailed description

[0006] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe a relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0008] This paper describes embodiments in a specific context, namely for a package and a method for its fabrication. Various embodiments presented here describe the fabrication of an integrated fan-out package (InFO package) used in photonic applications. These embodiments enable a cost-effective photonic InFO package with bandwidth scalability and lower accuracy requirements for the optical waveguide array.

[0009] Fig. Figure 1 shows a sectional view of an integrated circuit die 50A according to some embodiments. The integrated circuit die 50A is capped during subsequent machining to produce an integrated circuit package. The integrated circuit die 50A can be: a logic die, e.g., a main processor (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, or the like; a memory die, e.g., a DRAM die (DRAM: dynamic random-access memory), an SRAM die (SRAM: static random-access memory), and the like; a power management die, e.g., a PMIC die (PMIC: integrated power management circuit); a radio frequency die (RF die); a sensor die; a MEMS die (MEMS: microelectromechanical system); a signal processing die, etc. B. a DSP die (DSP: digital signal processing); a front-end die, e.g.an analog front-end die (AFE die) or the like; or a combination thereof.

[0010] The integrated circuit die 50A can be fabricated on a wafer that may have different fixture areas, which are separated in subsequent steps to produce a plurality of integrated circuit dies. The integrated circuit die 50A can be processed using suitable fabrication processes to produce integrated circuits. For example, the integrated circuit die 50A has a semiconductor substrate 52, such as doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include: other semiconductor materials, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Other substrates, such as multilayer or gradient substrates, can also be used. The semiconductor substrate 52 has an active side (e.g., the side that is in ). Fig. 1 facing upwards), which is occasionally referred to as a front side, and an inactive side (e.g., the side that is in Fig. 1 pointing downwards), which is occasionally referred to as a reverse side.

[0011] Devices 54 can be fabricated on the front face of the semiconductor substrate 52. The devices 54 can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, inductors, or the like, or combinations thereof. An interlayer dielectric (ILD) 56 is fabricated over the front face of the semiconductor substrate 52. The ILD 56 surrounds and can cover the devices 54. The ILD 56 can have one or more dielectric layers made of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and it can be fabricated by spin coating, lamination, atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like.

[0012] Conductive pins 58 extend through the ILD 56 to physically and electrically connect the devices 54. If the devices 54 are, for example, transistors, the conductive pins 58 can connect the gates and source / drain regions of the transistors. The conductive pins 58 can be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or combinations thereof. An interconnection structure 60 is arranged above the ILD 56 and the conductive pins 58. The interconnection structure 60 connects the devices 54 to form an integrated circuit. The interconnection structure 60 can, for example, be formed by metallization structures in dielectric layers on the ILD 56. The metallization structures include metal conductors and vias fabricated in one or more low-k dielectric layers.In some embodiments, the interconnect structure 60 can be made from alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper) with vias connecting the conductive material layers, and it can be fabricated using a suitable process such as deposition, single-damascene process, dual-damascene process, or the like. The metallization structures of the interconnect structure 60 are electrically connected to the devices 54 via the conductive pins 58.

[0013] The integrated circuit die 50A also features pads 62, such as aluminum pads, to which external connections are made. The pads 62 are located on the active side of the integrated circuit die 50A, such as in and / or on the interconnect structure 60. One or more passivation layers 64 are arranged on the active device die 50A, such as on parts of the interconnect structure 60 and the pads 62. Openings extend through the passivation layers 64 to the pads 62. Die interconnects 66, such as conductive pillars (made, for example, of a metal like copper), extend through the openings in the passivation layers 64 and are physically and electrically connected to the respective pads 62. The die interconnects 66 can be manufactured, for example, by plating or the like.The die connecting elements 66 are electrically connected to the respective integrated circuits of the integrated circuit die 50A.

[0014] Optionally, solder pads (e.g., solder balls or solder contact bumps) can be arranged on the die connecting elements 66. The solder pads can be used to perform a chip probe test (CP test) on the integrated circuit die 50A. The CP test can be performed on the integrated circuit die 50A to determine whether the integrated circuit die 50A is a proven good die (KGD). Thus, only integrated circuit dies 50A that are KGDs are further processed and capped, and dies that fail the CP test are not capped. After the CP test, the solder pads can be removed in subsequent processing steps.

[0015] An insulating layer 68 may (or may not) be produced on the front face of the integrated circuit die 50A, such as on the passivation layers 64 and the die connectors 66. The insulating layer 68 encapsulates the die connectors 66 laterally and abuts the integrated circuit die 50A laterally. Initially, the insulating layer 68 may cover the die connectors 66, so that the top surface of the insulating layer 68 is located above the top surfaces of the die connectors 66. In some embodiments where solder pads are arranged on the die connectors 66, the insulating layer 68 may also cover the solder pads. Alternatively, the solder pads may be removed before the insulating layer 68 is produced.

[0016] The insulating layer 68 can be a polymer, such as polybenzoxazole (PBO), a polyimide, benzocyclobutene (BCB), or the like; a nitride, such as silicon nitride or the like; an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; or the like, or a combination thereof. The insulating layer 68 can be produced, for example, by spin coating, lamination, ALD, CVD, or the like. In some embodiments, the die interconnects 66 are exposed by the insulating layer 68 during the fabrication of the integrated circuit die 50A. In other embodiments, the die interconnects 66 remain concealed and are exposed during a subsequent capping process of the integrated circuit die 50A. Exposing the die interconnects 66 allows for the removal of any solder deposits that may be present on the die interconnects 66.

[0017] In some embodiments, the integrated circuit die 50A is a device consisting of stacked chips comprising multiple semiconductor substrates 52. The integrated circuit die 50A can, for example, be a memory device, such as an HMC module (HMC: hybrid memory cube), an HBM module (HBM: high-bandwidth memory), or the like, comprising multiple memory dies. In these embodiments, the integrated circuit die 50A comprises multiple semiconductor substrates 52 interconnected by substrate vias (TSVs). The semiconductor substrates 52 may or may not each have an interconnection structure 60.

[0018] The Fig. Figure 2 shows a sectional view of an integrated circuit die 50B according to some embodiments. The integrated circuit die 50B is capped during subsequent machining to produce an integrated circuit package. The integrated circuit die 50B can be a photonic integrated circuit die (PIC die). In some embodiments, the integrated circuit die 50B is equivalent to the integrated circuit die 50A (see Figure 2). Fig. 1) similar, where similar structural elements are designated by similar reference numerals, and the descriptions of the similar structural elements are not repeated here. In some embodiments, the 50B integrated circuit die can be manufactured using the process steps described above with reference to Fig. 1 have been described, and the description will not be repeated here.

[0019] In some embodiments, the integrated circuit die 50B includes an optical coupler structure configured to couple with an optical waveguide. In some embodiments, the optical coupler structure includes a silicon waveguide 70 coupled to the interconnect structure 60. In some embodiments, the silicon waveguide 70 has a silicon layer fabricated over a silicon oxide layer. In some embodiments, the passivation layers 64 and the insulating layer 68 are patterned to expose the interconnect structure 60 before the silicon waveguide 70 is fabricated. In other embodiments, the passivation layers 64 and the insulating layer 68 are fabricated after the silicon waveguide 70 has been fabricated. Suitable photolithographic and etching techniques can be used for the patterning process.After the silicon waveguide 70 has been fabricated, an insulating layer 72 is produced over the silicon waveguide 70 and the exposed portion of the interconnect structure 60. In some embodiments, the insulating layer 72 comprises a dielectric material, such as silicon oxide or the like. Subsequently, a sacrificial layer 74 is produced over the insulating layers 68 and 72. In some embodiments, the sacrificial layer 74 comprises a polyimide, polyolefin, a combination thereof, or the like, and it can be produced by spin coating or the like.

[0020] Fig. Figure 3 shows a sectional view of an integrated circuit die 50C according to some embodiments. The integrated circuit die 50C is capped during subsequent machining to produce an integrated circuit package. The integrated circuit die 50C can be a photonic integrated circuit die (PIC die). In some embodiments, the integrated circuit die 50C is equivalent to the integrated circuit die 50A (see Figure 3). Fig. 1) similar, where similar structural elements are designated by similar reference numerals, and the descriptions of the similar structural elements are not repeated here. In some embodiments, the 50C integrated circuit die can be manufactured using the process steps described above with reference to Fig. 1 have been described, and the description will not be repeated here.

[0021] In some embodiments, the integrated circuit die 50C has an optical coupler structure configured to couple with an optical waveguide. In some embodiments, the optical coupler structure includes an edge coupler 76 coupled to the interconnect structure 60. The edge coupler 76 enables lateral or in-line coupling of an optical waveguide to the integrated circuit die 50C. In some embodiments, the passivation layers 64 and the insulating layer 68 are patterned to expose the interconnect structure 60 before the edge coupler 76 is fabricated. Suitable photolithographic and etching techniques can be used for the patterning process. Subsequently, a sacrificial layer 74 is fabricated over the insulating layer 68 and the interconnect structure 60. In some embodiments, the sacrificial layer 74 is fabricated as described above with reference to Fig. 2 has been described, and the description will not be repeated here.

[0022] Fig. Figure 4 shows a sectional view of an integrated circuit die 50D according to some embodiments. The integrated circuit die 50D is capped during subsequent machining to produce an integrated circuit package. The integrated circuit die 50D can be a photonic integrated circuit die (PIC die). In some embodiments, the integrated circuit die 50D is equivalent to the integrated circuit die 50A (see Figure 4). Fig. 1) similar, where similar structural elements are designated by similar reference numerals, and the descriptions of the similar structural elements are not repeated here. In some embodiments, the 50D integrated circuit die can be manufactured using the process steps described above with reference to Fig. 1 have been described, and the description will not be repeated here.

[0023] In some embodiments, the integrated circuit die 50D features an optical coupler structure configured to couple with an optical waveguide. In some embodiments, the optical coupler structure includes a grid coupler 78 coupled to the interconnect structure 60. The grid coupler 78 enables vertical coupling of an optical waveguide to the integrated circuit die 50D. In some embodiments, the passivation layers 64 and the insulating layer 68 are patterned to create an opening and expose the interconnect structure 60 before the grid coupler 78 is fabricated. Suitable photolithographic and etching techniques can be used for the patterning process. Subsequently, a sacrificial layer 74 is fabricated over the insulating layer 68 and within the opening that extends through the passivation layers 64 and the insulating layer 68.In some embodiments, the sacrificial layer 74 is produced as described above with reference to . Fig. 2 has been described, and the description will not be repeated here.

[0024] The Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 to Fig. Figure 14 shows sectional views of intermediate stages in a manufacturing process for a package according to exemplary embodiments. A package area 101 of a package component 100 is shown. In some embodiments, the package component 100 has a plurality of package areas, and in each of the package areas, one or more of the integrated circuit dies are encapsulated to form an integrated circuit package. The integrated circuit packages can also be referred to as integrated fan-out (InFo) packages.

[0025] In Fig. Step 5 provides a support substrate 102, and a release layer 104 is produced on the support substrate 102. The support substrate 102 can be a glass support substrate, a ceramic support substrate, or the like. The support substrate 102 can be a wafer, so that multiple packages can be produced simultaneously on the support substrate 102.

[0026] The release layer 104 can be made of a polymer-based material that, together with the support substrate 102, can be removed from overlying structures fabricated in subsequent steps. In some embodiments, the release layer 104 is a heat-removable, epoxy-based material that loses its adhesive properties upon heating, such as an LTHC release coating (LTHC: light-heat conversion). In other embodiments, the release layer 104 can be an ultraviolet (UV) adhesive that loses its adhesive properties when irradiated with UV light. The release layer 104 can be dispersed and cured as a liquid, or it can be a laminate layer with which the support substrate 102 is coated, or the like. The top surface of the release layer 104 can be leveled and may have a high degree of planarity.

[0027] The integrated circuit - The 50A (see Fig. 1) and the integrated circuit die 50B (see Fig. 2) are bonded to the support substrate 102 by means of an adhesive layer 118, which is produced over the release layer 104. The adhesive layer 118 may comprise a suitable adhesive, an epoxy, a die-fixing layer (DAF), or the like.

[0028] In Fig. 6. An encapsulation material 120 is produced on and around the integrated circuit dies 50A and 50B. The encapsulation material 120 can be a molding compound, an epoxy resin, or the like. The encapsulation material 120 can be applied over the support substrate 102 by compression molding, injection molding, or the like, so that the integrated circuit dies 50A and 50B are buried or covered. The encapsulation material 120 is also produced in gaps between the integrated circuit dies 50A and 50B. The encapsulation material 120 can be applied in a liquid or semi-liquid form and subsequently cured.

[0029] In Fig. In addition, a planarization process is performed on the encapsulation material 120 to expose the die connectors 66. The planarization process can also remove portions of the insulating layers 68, the sacrificial layer 74, and / or the die connectors 66 until the die connectors 66 are exposed. After the planarization process, the top surfaces of the die connectors 66, the insulating layers 68, the sacrificial layer 74, and the encapsulation material 120 are essentially coplanar within process variations. The planarization process can be, for example, a chemical-mechanical polishing (CMP) process, a grinding process, or the like. In some embodiments, the planarization can be omitted, for example, if the die connectors 66 are already exposed.

[0030] In Fig. 8 becomes a remaining part of the victim layer 74 (see Fig. 7) removed to expose the silicon waveguide 70 and the insulating layer 72. In some embodiments, the remaining part of the sacrificial layer 74 can be removed by a suitable selective etching process. The selective etching process may comprise one or more suitable wet etching processes, one or more suitable dry etching processes, combinations thereof, or the like. In some embodiments, the wet etching processes may be carried out using suitable solvents. In some embodiments, the dry etching processes may be carried out using gases, such as O2 or Ar, a combination thereof, or the like.

[0031] In Fig. In embodiment 9, a portion of the encapsulation material 120 adjacent to the insulating layer 72 is recessed beneath a sacrificial layer 74 of the insulating layer 72. In some embodiments, a portion of the encapsulation material 120 is recessed beneath a bottom surface of the silicon waveguide 70. Suitable photolithographic and etching processes can be used for the recession process. A suitable etching process can be a dry or wet etching process. The encapsulation material 120 is recessed beneath the top surface of the insulating layer 72 to a depth D1. The depth D1 can be approximately 0.1 µm to approximately 100 µm.

[0032] In Fig. In 10, a polymer waveguide (PWG) 154 is fabricated over the silicon waveguide 70, and a redistribution structure 122 is fabricated over the encapsulation material 120, the integrated circuit dies 50A and 50B, and the PWG 154. In some embodiments, the PWG 154 comprises an organic polymer, such as a polyimide, polyolefin, PBO, a combination thereof, or the like.

[0033] The redistribution structure 122 comprises insulating layers 124, 128, 132, and 136, and metallization structures 126, 130, and 134. The metallization structures can also be referred to as redistribution layers or redistribution lines. Redistribution structure 122 is shown as an example with three layers of metallization structures. However, redistribution structure 122 can be produced with more or fewer insulating layers and metallization structures. If fewer insulating layers and metallization structures are to be produced, the steps and processes described below can be omitted. If more insulating layers and metallization structures are to be produced, the steps and processes described below can be repeated.

[0034] Let's stay with Fig. 10. The insulating layer 124 is deposited on the encapsulation material 120, the die interconnects 66, and the insulating layers 68 and 72. In some embodiments, the insulating layer 124 is made of a photosensitive material, such as PBO, a polyimide, or BCB, or the like, which can be patterned using a lithographic mask. The insulating layer 124 can be produced by spin coating, lamination, CVD, or the like, or a combination thereof. Subsequently, the insulating layer 124 is patterned. The patterning creates openings in the insulating layer 124 that expose portions of the die interconnects 66 and a portion of the insulating layer 72 that is arranged above the silicon waveguide 70.The structuring can be carried out using a suitable method, such as by exposing and developing the insulating layer 124 if the insulating layer 124 is a photosensitive material, or by etching, for example anisotropic etching, if the insulating layer 124 is not a photosensitive material.

[0035] Subsequently, the PWG 154 is produced in the opening of the insulating layer 124, which exposes the insulating layer 72. In some embodiments, a first part of the PWG 154 extends along a top surface of the insulating layer 124, and a second part of the PWG 154 extends along a top surface of the insulating layer 68 of the integrated circuit die 50B. In some embodiments, the organic polymer material of the PWG 154 is deposited in the opening of the insulating layer 124, which exposes the insulating layer 72, by spin coating or the like. Subsequently, the organic polymer material is structured using suitable photolithographic methods.

[0036] The metallization structure 126 is then fabricated. The metallization structure 126 comprises conductive elements extending along the main surface of the insulating layer 124 and through the insulating layer 124 to physically and electrically connect the integrated circuit dies 50A and 50B. As an example of fabricating the metallization structure 126, a seed layer is fabricated over the insulating layer 124 and in the openings extending through the insulating layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer with multiple sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be fabricated, for example, by PVD or the like.A photoresist is then produced on the seed layer and subsequently patterned. The photoresist can be produced by spin coating or similar processes and can be exposed for patterning. The structure of the photoresist corresponds to metallization structure 126. Patterning creates openings through the photoresist to expose the seed layer. A conductive material is then deposited in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be deposited by plating, such as electroplating or electroless plating, or similar processes. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or similar. The combination of the conductive material and the underlying portions of the seed layer forms metallization structure 126.The photoresist and the portions of the seed layer where the conductive material has not been deposited are then removed. The photoresist can be removed using a suitable stripping or removal method, for example, using an oxygen plasma or similar technique. After the photoresist has been removed, any exposed portions of the seed layer are removed, for example, using a suitable etching process such as wet or dry etching.

[0037] After the metallization structure 126 has been produced, the insulating layer 128 is deposited onto the metallization structure 126, the insulating layer 124, and the PWG 154. The insulating layer 128 can be produced in a similar manner and from a similar material as the insulating layer 124.

[0038] Then the metallization structure 130 is fabricated. The metallization structure 130 comprises parts on and along the main surface of the insulating layer 128. The metallization structure 130 also comprises parts that extend through the insulating layer 128 to electrically connect the metallization structure 126. The metallization structure 130 can be fabricated in a similar manner and from a similar material as the metallization structure 126. In some embodiments, the metallization structure 130 has a different size than the metallization structure 126. For example, the conductive traces and / or vias of the metallization structure 130 can be wider or thicker than the conductive traces and / or vias of the metallization structure 126. Furthermore, the metallization structure 130 can be fabricated with a larger pitch than the metallization structure 126.

[0039] After the metallization structure 130 has been produced, the insulating layer 132 is deposited onto the metallization structure 130 and the insulating layer 128. The insulating layer 132 can be produced in a similar manner and from a similar material as the insulating layer 124.

[0040] Then the metallization structure 134 is fabricated. The metallization structure 134 comprises parts on and along the main surface of the insulating layer 132. The metallization structure 134 also includes parts that extend through the insulating layer 132 to physically and electrically connect the metallization structure 130. The metallization structure 134 can be fabricated in a similar manner and from a similar material as the metallization structure 126. The metallization structure 134 is the uppermost metallization structure of the redistribution structure 122. Therefore, all intermediate metallization structures of the redistribution structure 122 (e.g., the metallization structures 126 and 130) are located between the metallization structure 134 and the integrated circuit dies 50A and 50B. In some embodiments, the metallization structure 134 has a different size than the metallization structures 126 and 130.For example, the conductive traces and / or vias of metallization structure 134 can be wider or thicker than the conductive traces and / or vias of metallization structures 126 and 130. Furthermore, metallization structure 134 can be manufactured with a larger pitch than metallization structure 130.

[0041] After the metallization structure 134 is fabricated, the insulating layer 136 is deposited onto the metallization structure 134 and the insulating layer 132. The insulating layer 136 can be fabricated in a similar manner and from a similar material as the insulating layer 124. The insulating layer 136 is the uppermost insulating layer of the redistribution structure 122. Therefore, all metallization structures of the redistribution structure 122 (e.g., metallization structures 126, 130, and 134) are located between the insulating layer 136 and the integrated circuit dies 50A and 50B. Furthermore, all intermediate insulating layers of the redistribution structure 122 (e.g., insulating layers 124, 128, and 132) are located between the insulating layer 136 and the integrated circuit dies 50A and 50B. The redistribution structure 122 can also be described as a front-side redistribution structure.

[0042] Let's stay with Fig. 10. After fabrication of the redistribution structure 122, subsurface metallizations (UBMs) 138 are fabricated to provide an external connection to the redistribution structure 122. The UBMs 138 have contact mound portions on and along the main surface of the insulating layer 136, as well as through-hole portions extending through the insulating layer 136 to physically and electrically connect the metallization structure 134. This electrically connects the UBMs 138 to the integrated circuit dies 50A and 50B via the redistribution structure 122. The UBMs 138 can be fabricated from the same material as the metallization structure 126. In some embodiments, the UBMs 138 can have different dimensions than the metallization structures 126, 130, and 134.

[0043] Following the fabrication of the UBMs 138, conductive interconnects 150 are fabricated on the UBMs 138. The conductive interconnects 150 can be BGA interconnects (BGA: Ball Grid Array), solder balls, metal pillars, C4 contact bumps (C4: Controlled Collapse Chip Interconnect), microbumps, contact bumps fabricated using the ENEPIG process (ENEPIG: Electroless Nickel Electroless Palladium Immersion Gold), or the like. The conductive interconnects 150 can comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive interconnects 150 are fabricated by first producing a layer of solder by vapor deposition, electroplating, printing, solder transfer, bead placement, or the like.After the solder layer has been applied to the structure, a melting process can be performed to shape the material into the desired contact bump forms. In another embodiment, the conductive connecting elements are 150 metal pillars (such as copper pillars) produced by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metallic capping layer is applied to the metal pillars. The metallic capping layer may consist of nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be produced by a plating process.

[0044] In Fig. 11. A carrier substrate detachment is performed to detach the carrier substrate 102 from the package component 100. In some embodiments, the detachment includes projecting light, such as laser light or UV light, onto the detachment layer 104, so that it decomposes due to the heat of the light and the carrier substrate 102 can be removed.

[0045] In Fig. 12 After the carrier substrate 102 is removed, the package component 100 is turned over and placed on a singulation belt 158. Subsequently, a singulation process 160 is carried out by sawing along scoring groove areas, e.g., between adjacent package areas of the package component 100. The package area 101 is separated from the rest of the package component 100 by sawing and forms a package 101.

[0046] In Fig. Figure 13 shows a sectional view and a top view of area 156 of package area 101. Fig. Figure 12 shows the following. In some embodiments, the PWG 154 is spaced laterally from the insulating layer 124, such that the insulating layer 128 is arranged laterally between the PWG 154 and the insulating layer 124. In some embodiments, the width of the silicon waveguide 70 is smaller than the width of the PWG 154. In some embodiments, the width W1 of the PWG 154 is approximately 1.3 µm to approximately 9 µm. In some embodiments, the width W2 of the silicon waveguide 70 is approximately 0.1 µm to approximately 9 µm. In some embodiments, the ratio W1 / W2 is approximately 4.3 to approximately 90.

[0047] In Fig. In section 14, the package 101 is mounted to a package substrate 162 using the conductive connecting elements 150. In some embodiments, the package substrate 162 comprises a substrate core 162A and bond pads 162B over the substrate core 162A. The substrate core 162A can be made of a semiconductor material such as silicon, germanium, or diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide, combinations thereof, and the like can be used. Furthermore, the substrate core 162A can be an SOI substrate. In general, an SOI substrate comprises a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI or SGOI, or a combination thereof.In an alternative embodiment, the substrate core 162A is based on an insulating core, such as a core made of glass fiber-reinforced resin. An example of a core material is glass fiber resin, such as FR4. Alternatives for the core material are bismaleimide triazine (BT) resin or, alternatively, other printed circuit board (PCB) materials or layers. Build-up layers, such as an Ajinomoto build-up layer (ABF), or other laminates can also be used for the substrate core 162A.

[0048] The substrate core 162A can include active and passive devices (not shown). A wide range of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional requirements of the resulting device design. The devices can be fabricated using any suitable method.

[0049] The substrate core 162A can also include metallization layers and vias (not shown), with the bond pads 162B being physically and / or electrically connected to the metallization layers and vias. The metallization layers can be fabricated over the active and passive devices and are configured to connect the various devices to form functional circuits. The metallization layers can be made from alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper) with vias connecting the conductive material layers, and they can be fabricated by any suitable process (such as deposition, single-damascene process, dual-damascene process, or the like).In some embodiments, the substrate core 162A essentially has no active and passive devices.

[0050] In some embodiments, the conductive connecting elements 150 are melted to attach the package 101 to the bond pads 162B. The conductive connecting elements 150 electrically and / or physically connect the package substrate 162, which comprises the metallization layers in the substrate core 162A, to the package 101. In some embodiments, a solder resist 162C is produced on the substrate core 162A. The conductive connecting elements 150 can be arranged in openings in the solder resist 162C to be electrically and mechanically connected to the bond pads 162B. The solder resist 162C can be used to protect areas of the substrate core 162A against external damage.

[0051] In some embodiments, an underfill 164 can be produced between the package 101 and the package substrate 162 and around the conductive connecting elements 150. The underfill 164 can be produced by a capillary flow process after the package 101 has been attached to the package substrate 162, or it can be produced by a suitable deposition process before the package 101 is attached to the package substrate 162.

[0052] In some embodiments, passive devices, e.g., surface-mount devices (SMDs; not shown), can also be attached to the package 101 (e.g., to the UBMs 138) or to the package substrate 162 (e.g., to the bond pads 162B). The passive devices can be attached, for example, to the same surface of the package 101 or the package substrate 162 as the conductive connecting elements 150. The passive devices can be attached to the package 101 before the package 101 is mounted to the package substrate 162, or they can be attached to the package substrate 162 before or after the package 101 is mounted to the package substrate 162.

[0053] In some embodiments, an optical waveguide 168 is attached to the package substrate 162 using an adhesive layer 166 and is connected to the PWG 154 of the package 101. The adhesive layer 166 can be produced using similar materials and methods as the adhesive layer 118 described above with reference to Fig. Section 5 has been described, and the description is not repeated here. In some embodiments, the PWG 154 connects the optical waveguide 168 to the silicon waveguide 70.

[0054] The Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. Figure 22 shows sectional views of intermediate stages in a manufacturing process for a package according to some embodiments. Some of the structural elements and process steps, which are referenced in the Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. The structural elements and process steps described in section 22 are similar to those described above with reference to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 to Fig. 14 have been described, where similar structural elements are designated with similar reference numbers, and the description of the similar structural elements and process steps is not repeated here.

[0055] In the Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. Figure 22 shows a package area 201 of a package component 200. In some embodiments, the package component 200 has a plurality of package areas, and one or more of the integrated circuit dies are encapsulated into an integrated circuit package in each of the package areas. The integrated circuit packages can also be referred to as InFO packages.

[0056] In Fig. A support substrate 102 is provided, and a deposition layer 104 is produced on the support substrate 102. The support substrate 102 can be a wafer, so that several packages can be produced simultaneously on the support substrate 102. The integrated circuit die 50A (see Fig. 1) and the integrated circuit die 50C (see Fig. 3) are glued to the carrier substrate 102 by means of an adhesive layer 118 which is produced over the release layer 104.

[0057] In Fig. 16. An encapsulation material 120 is produced on and around the integrated circuit dies 50A and 50C. The encapsulation material 120 can be produced over the support substrate 102 such that the integrated circuit dies 50A and 50C are buried or covered. The encapsulation material 120 is also produced in gaps between the integrated circuit dies 50A and 50C. In some embodiments, the encapsulation material 120 can be produced as described above with reference to Fig. Section 6 has been described, and the description will not be repeated here.

[0058] In Fig. In 17, a planarization process is performed on the encapsulation material 120 to expose the die connectors 66. The planarization process can also remove portions of the insulating layers 68, the sacrificial layer 74, and / or the die connectors 66 until the die connectors 66 are fully exposed. After the planarization process, the top surfaces of the die connectors 66, the insulating layers 68, the sacrificial layer 74, and the encapsulation material 120 are substantially coplanar within process variations. The planarization process can be, for example, a CMP, a grinding process, or the like. In some embodiments, the planarization can be omitted, for example, if the die connectors 66 are already exposed.

[0059] In Fig. In 18, a redistribution structure 122 is fabricated over the encapsulation material 120 and the integrated circuit dies 50A and 50C. Subsequently, UBMs 138 are fabricated for external connection to the redistribution structure 122. After the fabrication of the UBMs 138, conductive connecting elements 150 are fabricated onto the UBMs 138. In some embodiments, the redistribution structure 122, the UBMs 138, and the conductive connecting elements 150 can be fabricated as described above with reference to Fig. 10 has been explained, and the description is not repeated here.

[0060] In Fig. In this work, the redistribution structure 122, the passivation layer 64, and the insulating layer 128 of the integrated circuit die 50C are structured to create openings 202 and 204. Suitable photolithographic and etching processes can be used for the structuring process. A suitable etching process may include one or more dry etching processes, one or more wet etching processes, combinations thereof, or the like. The opening 202 extends through the insulating layers 124, 128, 132, and 136, exposing the sacrificial layer 74. The opening 204 extends through the insulating layers 124, 128, 132, and 136, as well as through the passivation layer 64 and the insulating layer 68 of the integrated circuit die 50C. In some embodiments, the opening 204 is used for an external laser source input.

[0061] In Fig. In 20, the sacrificial layer 74 is removed through the opening 202 to expose the edge coupler 76 of the integrated circuit die 50C. In some embodiments, the sacrificial layer 74 is removed as described above with reference to Fig. 8 has been set out, and the description is not repeated here.

[0062] In Fig. 21 A carrier substrate detachment is performed to detach the carrier substrate 102 from the package component 200. In some embodiments, the detachment can be performed as described above with reference to Fig. As described in Section 11, the process is not repeated here. After the carrier substrate 102 is removed, the package component 200 is turned over and placed on a singulation belt 158. Subsequently, a singulation process 160 is carried out by sawing along scoring grooves, e.g., between adjacent package areas of the package component 200. The package area 201 is separated from the rest of the package component 200 by sawing and forms a package 201. In some embodiments, after the singulation process 160, a side wall of the package 201 that is closest to the edge coupler 76 has no encapsulation material 120.

[0063] In Fig. 22 The package 201 is mounted to a package substrate 162 using the conductive connecting elements 150. In some embodiments, the package 201 is mounted to the package substrate 162 as described above with reference to Fig. As described in Section 14, the description is not repeated here. In some embodiments, passive devices, such as surface-mount devices (SMDs; not shown), can also be attached to the package 201 (e.g., to the UBMs 138) or to the package substrate 162 (e.g., to the bond pads 162B). The passive devices can, for example, be attached to the same surface of the package 201 or the package substrate 162 as the conductive connecting elements 150. The passive devices can be attached to the package 201 before it is mounted to the package substrate 162, or they can be attached to the package substrate 162 before or after the package 201 is attached to the package substrate 162.

[0064] In some embodiments, an underfill 164 can be produced between the package 201 and the package substrate 162 and around the conductive connecting elements 150. In some embodiments, the underfill 164 can be produced as described above with reference to Fig. As explained in section 14, the description is not repeated here. In other embodiments, the underfill 164 can be omitted.

[0065] Furthermore, in Fig. 22 an optical fiber 168 is connected to the edge coupler 76 of the integrated circuit die 50C. By performing the singulation process such that the side wall of the package 201 closest to the edge coupler 76 does not have the encapsulation material 120, the connection of the optical fiber 168 to the edge coupler 76 of the integrated circuit die 50C is not prevented.

[0066] The Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. Figure 32 shows sectional views of intermediate stages during a manufacturing process for a package according to some embodiments. Some of the structural elements and process steps, which are referred to in the Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. The structural elements and process steps described in section 32 are similar to those described above with reference to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 to Fig. 14 have been described, where similar structural elements are designated with similar reference numbers, and the description of the similar structural elements and process steps is not repeated here.

[0067] In the Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. Figure 32 shows a package area 301 of a package component 300. In some embodiments, the package component 300 has a plurality of package areas, and one or more of the integrated circuit dies are encapsulated into an integrated circuit package in each of the package areas. The integrated circuit packages can also be referred to as InFO packages.

[0068] In Fig. In the process described in section 23, a support substrate 102 is provided, and a release layer 104 is fabricated on the support substrate 102. The support substrate 102 can be a wafer, allowing multiple packages to be fabricated simultaneously on the support substrate 102. In some embodiments, a redistribution structure 106 is fabricated on the release layer 104. In the illustrated embodiment, the redistribution structure 106 comprises an insulating layer 108, a metallization structure 110 (occasionally also referred to as redistribution layers or redistribution lines), and an insulating layer 112. In other embodiments, the redistribution structure 106 may be omitted. In some embodiments, an insulating layer without metallization structures is fabricated on the release layer 104 instead of the redistribution structure 106. The redistribution structure 106 may also be referred to as a backside redistribution structure.

[0069] The insulating layer 108 can be produced on the release layer 104. A bottom surface of the insulating layer 108 can be in contact with a top surface of the release layer 104. In some embodiments, the insulating layer 108 is made of a polymer, such as PBO, a polyimide, or BCB, or the like. In other embodiments, the insulating layer 108 is made of a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; or the like. The insulating layer 108 can be deposited by a suitable deposition process, such as spin coating, CVD, lamination, or the like, or by a combination thereof.

[0070] The metallization structure 110 can be fabricated on the insulating layer 108. As an example of fabricating the metallization structure 110, a seed layer is fabricated over the insulating layer 108. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with multiple sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be fabricated, for example, by PVD or the like. A photoresist is then fabricated on the seed layer and subsequently patterned. The photoresist can be fabricated by spin coating or the like and can be exposed for patterning. The structure of the photoresist corresponds to the metallization structure 110.Structuring creates openings through the photoresist to expose the seed layer. A conductive material is then deposited in these openings and on the exposed portions of the seed layer. This conductive material can be deposited by plating, such as electroplating or electroless plating, or similar processes. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or similar. The photoresist and the portions of the seed layer where the conductive material was not deposited are then removed. The photoresist can be removed using a suitable stripping or removal method, for example, using an oxygen plasma. After the photoresist has been removed, the exposed portions of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching.The remaining parts of the seed layer and the conductive material form the metallization structure 110.

[0071] The insulating layer 112 is produced on the metallization structure 110 and the insulating layer 108. In some embodiments, the insulating layer 112 can be produced using similar materials and methods as the insulating layer 108, and the description is not repeated here. The insulating layer 112 can then be patterned to create openings 114 that expose portions of the metallization structure 110. The patterning can be carried out using a suitable method, such as by exposing the insulating layer 112 if it is a photosensitive material, or by etching, for example, anisotropic etching, if the insulating layer 112 is not a photosensitive material. If the insulating layer 112 is a photosensitive material, it can be developed after exposure.

[0072] Fig. Figure 23 shows a redistribution structure 106 with only one metallization structure 110 for illustrative purposes. In some embodiments, the redistribution structure 106 can comprise any number of insulating layers and metallization structures. If more insulating layers and metallization structures are to be produced, the steps and processes described above can be repeated.

[0073] In Fig. 24 will be in the openings 114 (see Fig. 23) Through-hole vias 116 are produced, extending away from the top insulating layer of the redistribution structure 106 (e.g., the insulating layer 112). As an example of producing the through-hole vias 116, a seed layer (not shown) is produced over the redistribution structure 106, e.g., on the insulating layer 112 and parts of the metallization structure 110 that have been exposed by the openings 114. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer with a plurality of sublayers made of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be produced, for example, by PVD or the like. Then, a photoresist is produced on the seed layer, which is subsequently patterned.The photoresist can be produced by spin coating or similar processes and can be exposed for patterning. The photoresist's structure corresponds to the conductive vias. Patterning creates openings through the photoresist to expose the seed layer. A conductive material is deposited in the photoresist openings and on the exposed portions of the seed layer. This conductive material can be deposited by plating, such as electroplating or electroless plating, or similar processes. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or similar. The photoresist and the portions of the seed layer where the conductive material was not deposited are then removed. The photoresist can be removed using a suitable stripping or delamination process, for example, using an oxygen plasma or similar technique.After the photoresist has been removed, exposed parts of the seed layer are removed, for example, by a suitable etching process such as wet or dry etching. The remaining parts of the seed layer and the conductive material form the vias 116.

[0074] In Fig. 25 become an integrated circuit - The 50A (see Fig. 1) and an integrated circuit die 50D (see Fig. 4) are adhered to the insulating layer 112 by means of adhesive layers 118. The adhesive layers 118 are produced on the back sides of the integrated circuit dies 50A and 50D and adhere the integrated circuit dies 50A and 50D to the redistribution structure 106, such as the insulating layer 112. The adhesive layers 118 can be applied to the back sides of the integrated circuit dies 50A and 50D, can be applied over the surface of the support substrate 102 if no redistribution structure 106 is used, or can optionally be applied to a top side of the redistribution structure 106. For example, the adhesive layers 118 can be applied to the back sides of the integrated circuit dies 50A and 50D before the integrated circuit dies 50A and 50D are singulated.

[0075] In Fig. 26 An encapsulation material 120 is produced on and around the integrated circuit dies 50A and 50D and on and around the vias 116. The encapsulation material 120 can be produced over the support substrate 102 such that the integrated circuit dies 50A and 50D and the vias 116 are buried or covered. The encapsulation material 120 is also produced in gap regions between the integrated circuit dies 50A and 50D and in gap regions between each of the vias 116 and a respective integrated circuit die 50A and 50D. In some embodiments, the encapsulation material 120 can be produced as described above with reference to Fig. Section 6 has been described, and the description will not be repeated here.

[0076] In Fig. 27 A planarization process is performed on the encapsulation material 120 to expose the die connectors 66 and the vias 116. The planarization process can also remove portions of the insulating layers 68, the sacrificial layer 74, the vias 116, and / or the die connectors 66 until the die connectors 66 and the vias 116 are exposed. After the planarization process, the top surfaces of the die connectors 66, the vias 116, the insulating layers 68, the sacrificial layer 74, and the encapsulation material 120 are substantially coplanar within process variations. The planarization process can be, for example, a CMP, a grinding process, or the like. In some embodiments, the planarization can be omitted, for example, if the die connectors 66 and / or the vias 116 are already exposed.

[0077] In Fig. 28 The sacrificial layer 74 is removed to create an opening 302. The opening 302 extends through the passivation layer 64 and the insulating layer 68 and exposes the grid coupler 78 of the integrated circuit die 50D. In some embodiments, the sacrificial layer 74 is removed as described above with reference to Fig. 8 has been set out, and the description is not repeated here.

[0078] In Fig. 29 A redistribution structure 122 is fabricated over the encapsulation material 120 and the integrated circuit dies 50A and 50D. In some embodiments, the redistribution structure 122 can be fabricated as described above with reference to Fig. as explained in section 10, and the description is not repeated here. In the illustrated embodiment, the insulating layer 124 of the redistribution structure 122 fills the opening 302 (see Fig. 28).

[0079] In Fig. In section 30, the redistribution structure 122 is structured to create an opening 304. Suitable photolithographic and etching processes can be used for the structuring process. A suitable etching process may include one or more dry etching processes, one or more wet etching processes, combinations thereof, or the like. The opening 304 extends through the insulating layers 124, 128, 132, and 136 of the redistribution structure 122 and through the passivation layer 64 and the insulating layer 68 of the integrated circuit die 50D. The opening 304 exposes the grid coupler 78 of the integrated circuit die 50D.

[0080] Furthermore, in Fig. 30 in the illustrated embodiment the sacrificial layer 74 (see Fig. 27) removed before the redistribution structure 122 is produced. In other embodiments, the sacrificial layer 74 can also be removed after the production and structuring of the redistribution structure 122.

[0081] In Fig. 31. A carrier substrate detachment is carried out to remove the carrier substrate 102 (see Fig. 30) to detach from the package component 300. In some embodiments, the detachment can be carried out as described above with reference to Fig. As described in section 11, the description is not repeated here. After the carrier substrate 102 is removed, the package component 300 is turned over and placed on a singulation belt 158. Subsequently, UBMs 170 and conductive connecting elements 172 are made for external connection to the redistribution structure 106.

[0082] In some embodiments, openings are created through the insulating layer 108 to expose parts of the metallization structure 110. The openings can be created, for example, by laser drilling, etching, or the like. The UBMs 170 are manufactured in the openings. In some embodiments, the UBMs 170 are manufactured using similar materials and methods as the UBMs 138 described above with reference to Fig. 10, and the description is not repeated here. After the UBMs 170 have been manufactured, the conductive connecting elements 172 are fabricated on the UBMs 170. In some embodiments, the conductive connecting elements 172 are fabricated using similar materials and methods as the conductive connecting elements 150, which were described above with reference to Fig. 10 have been described, and the description will not be repeated here.

[0083] Subsequently, a singulation process 160 is carried out on the package component 300 by sawing along scoring groove areas, e.g., between adjacent package areas of the package component 300. The package area 301 is separated from the rest of the package component 300 by sawing and forms a package 301.

[0084] In Fig. 32 The package 301 is mounted to a package substrate 162 using the conductive connecting elements 172. In some embodiments, the package 301 is mounted to the package substrate 162 as described above with reference to Fig. as described above, and the description is not repeated here. In some embodiments, an underfill 164 can also be produced between the package 301 and the package substrate 162 and around the conductive connecting elements 172. The underfill 164 can be produced as described above with reference to Fig. As described in section 14, the description is not repeated here. In some embodiments, an optical fiber 168 is inserted into the opening 304 and connected to the grid coupler 78 of the integrated circuit die 50D.

[0085] In some embodiments, passive devices, e.g., surface-mount devices (SMDs; not shown), can also be attached to the package 301 (e.g., to the UBMs 170) or to the package substrate 162 (e.g., to the bond pads 162B). The passive devices can, for example, be bonded to the same surface of the package 301 or the package substrate 162 as the conductive connecting elements 172. The passive devices can be attached to the package 301 before the package 301 is mounted to the package substrate 162, or they can be attached to the package substrate 162 before or after the package 301 is mounted to the package substrate 162.

[0086] Fig. Figure 33 shows a sectional view of a package 401 according to some embodiments. The package 401 is the one described in Fig. Package 301 is similar to the one shown in Figure 32, wherein similar structural elements are designated with similar reference numerals, and the description of the similar structural elements is not repeated here. In some embodiments, Package 401 can be manufactured using the process steps described above with reference to the Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. 32, and the description is not repeated here. In the illustrated embodiment, the UBMs 138 and the conductive connecting elements 150 are manufactured for external connection to the redistribution structure 122. The UBMs 138 and the conductive connecting elements 150 can be manufactured as described above with reference to Fig. As described in Section 10, the description is not repeated here. In some embodiments, the conductive connecting elements 150 are used to connect the package 401 to external components. The external components can be integrated circuit dies, packages, SMDs, package substrates, PCBs, interposers, or the like. In some embodiments, the external components are attached to the conductive connecting elements 150 so that the opening 304 is not blocked. In these embodiments, the optical fiber 168 cannot be blocked by the external components, and it can be inserted into the opening 304 and connected to the grid coupler 78 of the integrated circuit die 50D.

[0087] The Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. Figure 43 shows sectional views of intermediate stages during a manufacturing process for a package according to some embodiments. Some of the structural elements and process steps, which are referred to in the Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. The structural elements and process steps described in section 43 are similar to those described above with reference to the Fig. 5 to 14 and 23 to 32 have been described, where similar structural elements are designated with similar reference numbers, and the description of the similar structural elements and process steps is not repeated here.

[0088] In the Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. Figure 43 shows a package area 501 of a package component 500. In some embodiments, the package component 500 has a plurality of package areas, and one or more of the integrated circuit dies are encapsulated into an integrated circuit package in each of the package areas. The integrated circuit packages can also be referred to as InFO packages.

[0089] In Fig. In 34, a support substrate 102 is provided, and a release layer 104 is produced on the support substrate 102. The support substrate 102 can be a wafer, so that several packages can be produced simultaneously on the support substrate 102. In some embodiments, a redistribution structure 106 is produced on the release layer 104. The redistribution structure 106 can be produced as described above with reference to Fig. 23, and the description is not repeated here. The insulating layer 112 is then structured to create openings 114 that expose parts of the metallization structure 110. The openings 114 can be created as described above with reference to Fig. 23 has been described, and the description will not be repeated here.

[0090] In Fig. 35 are in the openings 114 (see Fig. 34) Vias 116 are produced extending away from the top insulating layer of the redistribution structure 106 (e.g., the insulating layer 112). The vias 116 can be produced as described above with reference to Fig. 24 has been described, and the description is not repeated here. In the illustrated embodiment, the vias 116 are manufactured such that each of the vias 116 is located near an edge of a respective package area (e.g., the package area 501).

[0091] In Fig. 36 become an integrated circuit - The 50A (see Fig. 1) and an integrated circuit die 50C (see Fig. 3) are adhered to the insulating layer 112 by means of adhesive layers 118. The adhesive layers 118 are produced on the back sides of the integrated circuit dies 50A and 50C and adhere the integrated circuit dies 50A and 50C to the redistribution structure 106, such as the insulating layer 112. The adhesive layers 118 can be applied to the back sides of the integrated circuit dies 50A and 50C, can be applied over the surface of the support substrate 102 if no redistribution structure 106 is used, or can optionally be applied to a top side of the redistribution structure 106. For example, the adhesive layers 118 can be applied to the back sides of the integrated circuit dies 50A and 50C before the integrated circuit dies 50A and 50C are separated.

[0092] In Fig. 37. An encapsulation material 120 is produced on and around the integrated circuit dies 50A and 50C and on and around the vias 116. The encapsulation material 120 can be produced over the support substrate 102 such that the integrated circuit dies 50A and 50C and the vias 116 are buried or covered. The encapsulation material 120 is also produced in gap regions between the integrated circuit dies 50A and 50C and in gap regions between each of the vias 116 and a respective integrated circuit die 50A and 50C. In some embodiments, the encapsulation material 120 can be produced as described above with reference to Fig. Section 6 has been described, and the description will not be repeated here.

[0093] In Fig. 38 A planarization process is performed on the encapsulation material 120 to expose the die connectors 66 and the vias 116. The planarization process can also remove portions of the insulating layers 68, the sacrificial layer 74, the vias 116, and / or the die connectors 66 until the die connectors 66 and the vias 116 are exposed. After the planarization process, the top surfaces of the die connectors 66, the vias 116, the insulating layers 68, the sacrificial layer 74, and the encapsulation material 120 are substantially coplanar within process variations. The planarization process can be, for example, a CMP, a grinding process, or the like. In some embodiments, the planarization can be omitted, for example, if the die connectors 66 and / or the vias 116 are already exposed.

[0094] In Fig. 39 The sacrificial layer 74 is removed to create an opening 502. The opening 502 extends through the passivation layer 64 and the insulating layer 68 and exposes the edge coupler 76 of the integrated circuit die 50C. In some embodiments, the sacrificial layer 74 is removed as described above with reference to Fig. 8 has been set out, and the description is not repeated here.

[0095] In Fig. 40 A redistribution structure 122 is fabricated over the encapsulation material 120 and the integrated circuit dies 50A and 50C. In some embodiments, the redistribution structure 122 can be fabricated as described above with reference to Fig. as explained in section 10, and the description is not repeated here. In the illustrated embodiment, the insulating layer 124 of the redistribution structure 122 fills the opening 502 (see Fig. 39).

[0096] In Fig. 41 The redistribution structure 122 is structured to create an opening 504. Suitable photolithographic and etching processes can be used for the structuring process. A suitable etching process may include one or more dry etching processes, one or more wet etching processes, combinations thereof, or the like. The opening 504 extends through the insulating layers 124, 128, 132, and 136 of the redistribution structure 122 and through the passivation layer 64 and the insulating layer 68 of the integrated circuit die 50C. The opening 504 exposes the edge coupler 76 of the integrated circuit die 50C. In the illustrated embodiment, the sacrificial layer 74 (see Fig. 38) removed before the redistribution structure 122 is produced. In other embodiments, the sacrificial layer 74 can also be removed after the redistribution structure 122 has been produced and structured.

[0097] In Fig. 42 A carrier substrate detachment is carried out to remove the carrier substrate 102 (see Fig. 41) to detach from the package component 500. In some embodiments, the detachment can be carried out as described above with reference to Fig. as described above, and the description is not repeated here. After the carrier substrate 102 is removed, the package component 500 is turned over and placed on a singulation belt 158. Subsequently, UBMs 170 and conductive connecting elements 172 are manufactured for external connection to the redistribution structure 106. The UBMs 170 and the conductive connecting elements 172 can be manufactured as described above with reference to Fig. 31 has been described, and the description will not be repeated here.

[0098] Subsequently, a singulation process 160 is performed on the package component 500 by sawing along groove areas, e.g., between adjacent package areas of the package component 500. The package area 501 is separated from the rest of the package component 500 by the sawing and forms a package 501. In some embodiments, after the singulation process 160, a side wall of the package 501 that is closest to the edge coupler 76 does not have the encapsulation material 120.

[0099] In Fig. 43 The package 501 is mounted to a package substrate 162 using the conductive connecting elements 172. In some embodiments, the package 501 is mounted to the package substrate 162 as described above with reference to Fig. 32, and the description is not repeated here. In some embodiments, an underfill 164 can be produced between the package 501 and the package substrate 162 and around the conductive connecting elements 172. The underfill 164 can be produced as described above with reference to Fig. 14 has been set out, and the description is not repeated here.

[0100] In some embodiments, an optical fiber 168 is connected to the edge coupler 76 of the integrated circuit die 50C. By performing the singulation process such that the side wall of the package 501 closest to the edge coupler 76 does not have the encapsulation material 120, the connection of the optical fiber 168 to the edge coupler 76 of the integrated circuit die 50C is not prevented.

[0101] In some embodiments, passive devices, e.g., surface-mount devices (SMDs; not shown), can also be attached to the package 501 (e.g., to the UBMs 170) or to the package substrate 162 (e.g., to the bond pads 162B). The passive devices can, for example, be bonded to the same surface of the package 501 or the package substrate 162 as the conductive connecting elements 172. The passive devices can be attached to the package 501 before the package 501 is mounted to the package substrate 162, or they can be attached to the package substrate 162 before or after the package 501 is mounted to the package substrate 162.

[0102] Fig. Figure 44 shows a sectional view of a package 601 according to some embodiments. The package 601 is the one described in Fig. Package 501 is similar to the one shown in Figure 43, wherein similar structural elements are designated with similar reference numerals, and the description of the similar structural elements is not repeated here. In some embodiments, Package 601 can be manufactured using the process steps described above with reference to the Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. 43, and the description is not repeated here. In the illustrated embodiment, the UBMs 138 and the conductive connecting elements 150 are manufactured for external connection to the redistribution structure 122. The UBMs 138 and the conductive connecting elements 150 can be manufactured as described above with reference to Fig.As already described in Section 10, the description is not repeated here. In some embodiments, the conductive connecting elements 150 are used to connect the package 601 to external components. The external components may be integrated circuit dies, packages, SMDs, package substrates, PCBs, interposers, or the like.

[0103] Further structural elements and processes can be used. For example, test structures can be used to support the verification testing of 3D capping or 3DIC devices. These test structures can include, for example, test pads fabricated in a redistribution layer or on a substrate, enabling the testing of the 3D capping or 3DIC devices, the use of probes and / or probe cards, and the like. Verification testing can be performed on intermediate structures as well as final structures. Furthermore, the structures and procedures described here can be used in conjunction with testing methodologies that include intermediate verification of proven good dies to increase yield and reduce costs.

[0104] According to one embodiment, an integrated circuit package comprises: a photonic integrated circuit die, wherein the photonic integrated circuit die includes an optical coupler; an encapsulation material encapsulating the photonic integrated circuit die, wherein a first face of the photonic integrated circuit die is at the same level as a first face of the encapsulation material; a first redistribution structure on the photonic integrated circuit die and the encapsulation material; and an opening exposing the optical coupler, wherein a side wall of the opening extends through the first redistribution structure. In one embodiment, the optical coupler is an edge coupler. In another embodiment, the opening extends through the first redistribution structure, and the optical coupler is a grating coupler.In one embodiment, the integrated circuit package further comprises an optical waveguide connected to the optical coupler. In another embodiment, the integrated circuit package further comprises a second redistribution structure beneath the photonic integrated circuit die and the encapsulation material. In another embodiment, the integrated circuit package further comprises a through-hole in the encapsulation material that electrically connects the first redistribution structure to the second redistribution structure. In another embodiment, the integrated circuit package further comprises a package substrate attached to the second redistribution structure.

[0105] According to another embodiment, an integrated circuit package comprises: an encapsulation material with a first surface and a second surface opposite the first surface; a photonic integrated circuit die embedded in the encapsulation material, wherein the photonic integrated circuit die includes an optical coupler, with a first surface of the photonic integrated circuit die being at the same level as the first surface of the encapsulation material; a first redistribution structure on the first surface of the encapsulation material; a second redistribution structure on the second surface of the encapsulation material; and an opening exposing the optical coupler, wherein a side wall of the opening extends through the first redistribution structure. In one embodiment, the optical coupler is an edge coupler or a grating coupler.In one embodiment, part of the opening extends from the first surface of the photonic integrated circuit die to a second surface of the photonic integrated circuit die, with the second surface of the photonic integrated circuit die being opposite its first surface. In one embodiment, a first side wall of the photonic integrated circuit die, located near the optical coupler, does not have the encapsulation material. In another embodiment, a second side wall of the photonic integrated circuit die is in physical contact with the encapsulation material, and the second side wall of the photonic integrated circuit die is opposite its first side wall.In one embodiment, the integrated circuit package further comprises a via in the encapsulation material, the via extending from the first surface of the encapsulation material to the second surface of the encapsulation material. In another embodiment, the integrated circuit package further comprises an optical waveguide extending into the opening and coupled to the optical coupler.

[0106] According to a further embodiment, a method comprises the following steps: fabricating a first redistribution structure over a support substrate; attaching a photonic integrated circuit die to the support substrate, the photonic integrated circuit die having an optical coupler; fabricating an encapsulation material over the support substrate and the photonic integrated circuit die, the encapsulation material extending along a side wall of the photonic integrated circuit die; fabricating a second redistribution structure over the photonic integrated circuit die and the encapsulation material; and structuring the second redistribution structure to create an opening in the second redistribution structure, the opening extending through the second redistribution structure and exposing the optical coupler.In one embodiment, the method further comprises fabricating a first redistribution structure over the substrate before attaching the photonic integrated circuit die to the substrate. In another embodiment, the method further comprises fabricating a via over the first redistribution structure before attaching the photonic integrated circuit die to the substrate. In another embodiment, the method further comprises coupling an optical waveguide to the optical coupler. In one embodiment, the optical coupler is an edge coupler. In another embodiment, the optical coupler is a grating coupler.

Claims

[1] Integrated circuit package (301, 401, 501, 601) with: a photonic integrated circuit die (50C; 50D), wherein the photonic integrated circuit die (50C; 50D) has an optical coupler (76; 78); an encapsulation material (120) that encapsulates the photonic integrated circuit die (50C; 50D), wherein a first surface of the photonic integrated circuit die (50C; 50D) is at the same level as a first surface of the encapsulation material (120); a first redistribution structure (122) on the photonic integrated circuit die (50C; 50D) and the encapsulation material (120); and an opening (304; 504) that exposes the optical coupler (76; 78), with one side wall of the opening extending through the first redistribution structure (122). [2] Integrated circuit package (501, 601) according to claim 1, wherein the optical coupler (76) is an edge coupler (76). [3] Integrated circuit package (301, 401) according to claim 1, wherein the optical coupler (78) is a grating coupler (78). [4] Integrated circuit package (301, 401, 501, 601) according to any of the preceding claims, further comprising an optical waveguide (168) coupled to the optical coupler (76; 78). [5] Integrated circuit package (301, 401, 501, 601) according to any of the preceding claims, further comprising a second redistribution structure (106) beneath the photonic integrated circuit die (50C; 50D) and the encapsulation material (120). [6] Integrated circuit package (301, 401, 501, 601) according to claim 5, further comprising a through-hole (116) in the encapsulation material (120) which electrically connects the first redistribution structure (122) to the second redistribution structure (106). [7] Integrated circuit package (301, 401, 501, 601) according to any of the preceding claims, further comprising a package substrate (162) attached to the second redistribution structure (106). [8] Integrated circuit package (301, 401, 501, 601) with: an encapsulation material (120) having a first surface and a second surface opposite the first surface; a photonic integrated circuit die (50C; 50D) embedded in the encapsulation material (120), wherein the photonic integrated circuit die (50C; 50D) has an optical coupler (76; 78) and a first surface of the photonic integrated circuit die (50C; 50D) is at the same level as the first surface of the encapsulation material (120); a first redistribution structure (122) on the first surface of the encapsulation material (120); a second redistribution structure (106) on the second surface of the encapsulation material (120); and an opening (304; 504) that exposes the optical coupler (76; 78), wherein a side wall of the opening (304; 504) extends through the first redistribution structure (122). [9] Integrated circuit package (301, 401, 501, 601) according to claim 8, wherein the optical coupler (76; 78) is an edge coupler (76) or a grating coupler (78). [10] Integrated circuit package (301, 401, 501, 601) according to claim 8 or 9, wherein a part of the opening (304; 504) extends from the first surface of the photonic integrated circuit die (50C; 50D) to a second surface of the photonic integrated circuit die (50C; 50D), the second surface of the photonic integrated circuit die (50C; 50D) being opposite its first surface. [11] Integrated circuit package (301, 401, 501, 601) according to any one of claims 8 to 10, wherein a first side wall of the photonic integrated circuit die (50C; 50D), which is located near the optical coupler (76; 78), does not have the encapsulation material (120). [12] Integrated circuit package (301, 401, 501, 601) according to claim 11, wherein a second side wall of the photonic integrated circuit die (50C; 50D) is in physical contact with the encapsulation material (120) and the second side wall of the photonic integrated circuit die (50C; 50D) is opposite its first side wall. [13] Integrated circuit package (301, 401, 501, 601) according to any one of claims 8 to 12, further comprising a through-hole (116) in the encapsulation material (120), wherein the through-hole (116) extends from the first surface of the encapsulation material (120) to the second surface of the encapsulation material (120). [14] Integrated circuit package (301, 401, 501, 601) according to any one of claims 8 to 13, further comprising an optical waveguide (168) extending into the opening (304; 504) and coupled to the optical coupler (76; 78). [15] Procedure with the following steps: Establishing an initial redistribution structure (106) over a support substrate (102); Attaching a photonic integrated circuit die (50C; 50D) to the support substrate (102), wherein the photonic integrated circuit die (50C; 50D) has an optical coupler (76; 78); Producing an encapsulation material (120) over the support substrate (102) and the photonic integrated circuit die (50C; 50D), wherein the encapsulation material (120) extends along a side wall of the photonic integrated circuit die (50C; 50D); Creating a second redistribution structure (122) over the photonic integrated circuit die (50C; 50D) and the encapsulation material (120); and Structuring the second redistribution structure (122) to create an opening (304; 504) in the second redistribution structure (122), wherein the opening extends through the second redistribution structure, the opening (304; 504) exposing the optical coupler (76; 78). [16] Method according to claim 15, which further comprises creating a through-hole (116) over the first redistribution structure (106) before attaching the photonic integrated circuit die (50C; 50D) to the support substrate (102). [17] Method according to one of claims 15 to 16, further comprising coupling an optical waveguide (168) with the optical coupler (76; 78). [18] Method according to any one of claims 15 to 17, wherein the optical coupler (76) is an edge coupler (76). [19] Method according to any one of claims 15 to 17, wherein the optical coupler (78) is a grating coupler (78).

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