Mesa contact for a power semiconductor device and method for manufacturing a power semiconductor device

Abstract

Power semiconductor device (1), comprising: - a semiconductor body (10) with a drift region (100) of a first conductivity type; - several trenches (14), wherein two adjacent trenches (14) laterally bound a mesa (17) of the semiconductor body (10) and wherein each trench (14) - extends from a semiconductor body surface (110) along a vertical direction (Z) into the semiconductor body (10) and includes a trench electrode (141) which is insulated from the semiconductor body (10) by a trench insulator (142); - has a trench width (TW) along a first lateral direction (X) and a trench length (TL) along a second lateral direction (Y) perpendicular to the first lateral direction (X), the trench length being at least five times the trench width (TW); - a semiconductor body region (102) of a second conductivity type in the mesa (17); - a semiconductor source region (101) of the first conductivity type in the mesa (17), wherein the source region (101) is arranged above the semiconductor body region (102); - an insulating layer (300) over and / or on the source area (101); - a contact plug (111) extending at least from an upper surface of the insulating layer (300) along the vertical direction (Z) to contact both the source region (101) and the semiconductor body region (102), wherein the contact plug (111) has side wall parts (1111) and a lower part (1112) both forming an interface with the semiconductor body (10); where: - the contact plug (111) extends along an entire upper width (WM) of the mesa (17) in the first lateral direction (X) into the semiconductor body (10), and - the source area (101) is contacted by at least one of the side wall parts (1111) of the contact plug (111); wherein - the trench electrode (141) of at least one of the two adjacent trenches (14) is separated from the insulating layer (300) along the vertical direction (Z) by an upper trench insulator (143); - the upper trench insulator (143) has a vertical extent that amounts to up to 90% of the vertical extent of the source area (101); and - one top side of the trench electrode (141) by a distance (T R ) is vertically recessed from the semiconductor body surface (110) of the mesa (17), so that the source region (101) is raised above the top of the trench electrode (141).

Description

TECHNICAL AREA

[0001] This document relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. In particular, this document relates to embodiments in which a contact plug contacts a narrow mesa of the power semiconductor device. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as the conversion of electrical energy and the driving of an electric motor or electric machine, rely on power semiconductor switches. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name just a few, have been used for various applications, including, but not limited to, switches in power supplies and power converters.

[0003] A power semiconductor device typically comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device.

[0004] Furthermore, in the case of a controllable power semiconductor device, for example a transistor, the load current path can be controlled by means of an insulated electrode, commonly referred to as the gate electrode. For example, upon receiving a corresponding control signal, for example from a driver unit, the control electrode can switch the power semiconductor device into a forward conducting state or a blocking state.

[0005] Often the gate electrode can be contained within a trench of the power semiconductor switch, with the trench having a strip configuration.

[0006] Two adjacent trenches laterally bound a portion of the semiconductor body, typically referred to as the mesa. Such a mesa is usually configured to provide a path for the forward load current, for example by having a source region and a body region.

[0007] To provide a path for the forward load current, the mesa must be electrically contacted with one of the load terminals of the power semiconductor device. For example, it is known to establish such a contact using a contact plug structure, according to which an electrically conductive material extends into a groove-like recess in a central part of the mesa to contact both the source region and the body region.

[0008] For various reasons, it may be desirable to keep the width of such a mesa, i.e., the distance between opposing trench sidewalls of the adjacent trenches that laterally bound the mesa, small.

[0009] However, as the mesa width decreases, it also becomes more difficult to reliably contact it based on a contact plug structure.

[0010] US 2010 / 0140657 A1 and US 6359306 B1 each disclose a device with a MOSFET semiconductor structure in which a mesa, in which an inversion channel can be formed, is contacted via a contact plug. WO 2019 / 103135 A1 describes a power semiconductor with an IGBT structure having control electrodes embedded in grooves. SUMMARY

[0011] The invention is defined by the independent claims. Features of some embodiments are specified in the dependent claims.

[0012] According to one embodiment, a power semiconductor device comprises: a semiconductor body with a drift region of a first conductivity type; several trenches, wherein two adjacent trenches laterally bound a mesa of the semiconductor body. Each trench extends from a semiconductor body face along a vertical direction into the semiconductor body and includes a trench electrode insulated from the semiconductor body by a trench insulator, and has a trench width along a first lateral direction and a trench length along a second lateral direction perpendicular to the first lateral direction, the trench length being at least five times the trench width.Furthermore, the device comprises a semiconductor body region of a second conductivity type in the mesa; a source region of the first conductivity type in the mesa, wherein the source region is arranged above the semiconductor body region; an insulating layer above and / or on the source region; a contact plug extending from at least one upper surface of the insulating layer along the vertical direction to contact both the source region and the semiconductor body region, the contact plug having sidewall portions and a lower portion, both of which form an interface with the semiconductor body. The contact plug extends along the entire upper width of the mesa in the first lateral direction into the semiconductor body. The source region is contacted by at least one of the sidewall portions of the contact plug.

[0013] According to another embodiment, a method for manufacturing a power semiconductor device is presented. The device comprises, in a semiconductor body, a drift region of a first conductivity type; and several trenches, wherein two adjacent trenches laterally bound a mesa of the semiconductor body, and wherein each trench: extends from a semiconductor body face along a vertical direction into the semiconductor body and comprises a trench electrode that is insulated from the semiconductor body by a trench insulator;The device comprises a trench width along a first lateral direction and a trench length along a second lateral direction, perpendicular to the first lateral direction, wherein the trench length is at least five times the trench width. Furthermore, the device comprises a semiconductor body region of a second conductivity type in the mesa. The method comprises: forming a source region of the first conductivity type in the mesa, wherein the source region is arranged above the semiconductor body region; forming an insulating layer above and / or on the source region;Providing a mask, wherein the mask has at least one mask bridge covering a first part of the source region and at least one mask opening exposing second parts of the source region in the mesa and below the insulating layer, the first part of the source region separating two adjacent parts of the second part of the source region along the second lateral direction in the mesa; in a region exposed by the at least one mask opening, removing a portion of the insulating layer and the second parts of the source region, such that the remaining first part of the source region forms a raised source bridge between the two adjacent trenches in the mesa; depositing an electrically conductive material to form a contact plug extending at least from one upper surface of the insulating layer along the vertical direction to contact the first part of the source region at a sidewall portion thereof.

[0014] The expert will recognize additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The parts in the figures are not necessarily to scale; instead, the emphasis is on illustrating the basic features of the invention. Furthermore, identical reference numbers in the figures denote corresponding parts. The drawings show: Fig. 1 schematically and exemplarily a section of a vertical cross-section of a power semiconductor device; Fig. 2A-B both schematically and by way of example a section of a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. 3A-B both schematic and exemplary, based on corresponding schematically represented sections of some vertical cross-sections and a horizontal projection, steps of a method for manufacturing a power semiconductor device according to one or more embodiments; Fig. 4. Schematic and exemplary, based on corresponding schematically represented sections of some vertical cross-sections and a horizontal projection, aspects of a power semiconductor device according to one or more embodiments; Fig. 5 schematically and by way of example a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. 6A-C schematically and by way of example, based on corresponding schematically represented sections of some vertical cross-sections and a horizontal projection, steps of a method for manufacturing a power semiconductor device according to some embodiments; Fig. 7 schematically and by way of example a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. 8-12 each schematically and by way of example, based on corresponding schematically represented sections of some vertical cross-sections and a horizontal projection, aspects of a power semiconductor device according to some embodiments; and Fig. 13A-B both schematic and exemplary, based on corresponding schematically represented sections of some vertical cross-sections, steps of a method for manufacturing a power semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0016] The following detailed description refers to the accompanying drawings, which form a part thereof and in which special embodiments in which the invention can be exercised are shown as illustrations.

[0017] In this respect, directional terminology, such as "above," "below," "under," "in front of," "behind," "backward," "leading," "trailing," "above," etc., can be used with reference to the orientation of the figures just described. Since parts of embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes. It is understood that other embodiments may be used and that structural or logical modifications may be made.

[0018] Various embodiments are now described in detail, one or more examples of which are illustrated in the figures. Each example is provided with an explanation. Features illustrated or described as part of an embodiment can, for example, be used in or combined with other embodiments to obtain yet another embodiment. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated with the same reference numerals in the various drawings, unless otherwise indicated.

[0019] The term "horizontal," as used in this document, is intended to describe an orientation essentially parallel to a horizontal surface of a semiconductor substrate or structure. This could be, for example, the surface of a semiconductor wafer, die, or chip. For instance, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, with the first lateral direction X and the second lateral direction Y being perpendicular to each other.

[0020] The term "vertical," as used in this document, is intended to describe an orientation that is essentially perpendicular to the horizontal surface, that is, parallel to the normal direction of the semiconductor wafer / chip / dies surface. For example, the extension direction Z mentioned below can be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to here as the "vertical direction Z."

[0021] In this document, n-doped materials are referred to as the "first conductivity type," while p-doped materials are referred to as the "second conductivity type." Alternatively, opposite doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0022] In this document, the terms "in ohmic contact," "in electrical contact," "in an ohmic connection," and "electrically connected" are used to describe a low-resistance electrical connection or current path between two regions, sections, zones, areas, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal, metallization, or electrode and a region or part of a semiconductor device. Furthermore, in this document, the term "in contact" is used to describe a direct physical connection between two elements of the respective semiconductor device; for example, a junction between two elements in contact may not include any further intermediate element or the like.

[0023] Furthermore, unless otherwise stated, the term "electrical isolation" is used in this document in its generally accepted sense and is intended to describe a situation where two or more components are arranged separately from one another and there is no ohmic connection between them. However, electrically isolated components can nevertheless be coupled to each other, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled. For example, two electrodes of a capacitor can be electrically isolated from each other and simultaneously mechanically and capacitively coupled, for example, by means of insulation such as a dielectric.

[0024] The specific embodiments described in this document relate to a power semiconductor device having a strip cell configuration, e.g., a power semiconductor device that can be used in a power converter or a power supply unit. Thus, in one embodiment, such a device can be configured to carry a load current that is to be supplied to a load or that is provided by a power source. For example, the power semiconductor device can comprise one or more active power semiconductor cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell (e.g., a monolithically integrated cell of two anti-series connected diodes), a monolithically integrated transistor cell, e.g., a monolithically integrated IGBT cell, and / or derivatives thereof.Such diode / transistor cells can be integrated into a power semiconductor module. Several such cells can form a cell array arranged in an active region of the power semiconductor device.

[0025] The term "power semiconductor device," as used in this document, is intended to describe a semiconductor device on a single chip with the capability of blocking high voltage and / or conducting high current. In other words, such a power semiconductor device is designed to handle high current, typically in the ampere range, e.g., up to several dozen or hundreds of amperes, and / or high voltages, typically above 15 V, typically 100 V and above, e.g., up to at least 400 V or even more, e.g., up to at least 3 kV or even up to 10 kV or more.

[0026] For example, the power semiconductor device described below can be a single semiconductor chip that has a strip cell configuration (rather than a cellular / needle cell configuration) and can be configured to be used as a power component in a low, medium and / or high voltage application.

[0027] For example, the term "power semiconductor device" as used in this document does not refer to logic semiconductor devices used, for example, for storing data, calculating data and / or for other types of semiconductor-based data processing.

[0028] This document relates in particular to power semiconductor devices designed as IGBTs, i.e. bipolar power semiconductor transistors controlled by insulated electrodes (gates).

[0029] Fig. Figure 1 schematically and exemplarily represents a section of a vertical cross-section of a power semiconductor device 1. The power semiconductor device 1 can be based on or implemented in a single chip.

[0030] With reference to Fig. 2A The power semiconductor device 1 has an active region 1-2 with a number of power cells 1-1 arranged in a strip cell configuration as shown in Fig. As shown in Figure 2B, the power cells are arranged in a specific way. Accordingly, the extent in the second lateral direction Y of each power cell 1-1 is a multiple of the extent in the first lateral direction X.

[0031] An edge termination region 1-3 of the power semiconductor device 1 surrounds the active region 1-2. Thus, the edge termination region 1-3 can be located outside the active region 1-2. The edge termination region 1-3 is laterally closed by an edge 1-4. The edge 1-4 can form the chip edge of the power semiconductor device 1.

[0032] As used here, the terms "edge termination region" and "active region" are assigned the respective technical meanings that a person skilled in the art would attribute to them in connection with power semiconductor devices. That is to say, the active region 1-2 is primarily configured for forward load current conduction and (where applicable) for switching purposes, while the edge termination region 1-3 primarily serves functions relating to reliable blocking capabilities, suitable guidance of the electric field, sometimes also charge carrier dissipation functions and / or other functions relating to protection and suitable termination of the active region 1-2.

[0033] With renewed reference to Fig. In the power semiconductor device 1, a semiconductor body 10 has a front face 110 and a back face 120. The front face 110 (here also referred to as a semiconductor body surface) and the back face 120 can vertically terminate the semiconductor body 10. That is, the semiconductor body 10 has a total thickness d along the vertical direction Z between the front face 110 and the back face 120. In the lateral directions, the semiconductor body 10 can be defined by the (in Fig. The front (not shown) edge 1-4 is closed. Furthermore, both the front 110 and the back 120 can extend laterally along both the first lateral direction X and the second lateral direction Y. For example, both the front 110 and the back 120 can form a respective horizontal surface of the semiconductor body 10. The thickness d of the semiconductor body 10 can be the distance between the front 110 and the back 120 along the vertical direction Z in the active region 1-2, for example, measured at the center of the active region 1-2.

[0034] The semiconductor body 10 forms part of both the active region 1-2 and the edge termination region 1-3. For example, the possible configurations of the power cell(s) 1-1 described below are primarily implemented in the semiconductor body 10. The semiconductor body 10 is configured in the active region 1-2 to conduct a forward load current between a first load terminal 11 and a second load terminal 12.

[0035] A first load terminal 11 is located on the front face 110 of the semiconductor body, and a second load terminal 12 is located on the rear face 120 of the semiconductor body. For example, the first load terminal 11 includes a front face metallization and / or the second load terminal 12 includes a rear face metallization. For example, the first load terminal 11 is an emitter terminal and the second load terminal 12 is a collector terminal. On the front face 110, the semiconductor body 10 can form an interface with the front face metallization. On the rear face 120, the semiconductor body 10 can form an interface with the rear face metallization.

[0036] In one embodiment, the first load terminal 11 (for example, the front face metallization) overlaps laterally with the active region 1-2 along the first lateral direction X and / or the second lateral direction Y and / or combinations thereof. It should be noted that the first load terminal 11 can be laterally structured, for example, to establish local contacts with the semiconductor body 10 on the front face 110. As shown, for example, in Fig. As shown in Figure 1 as an example, the local contacts can be made by means of a contact plug 111' penetrating the insulation structure 13, e.g. according to which an electrically conductive material extends into a groove-like recess in a middle part of a mesa in order to contact both a source region 101' and a body region 102'.

[0037] Similarly, in one embodiment, the second load terminal 12 (e.g., the backside metallization) overlaps laterally with the active region 1-2 along the first lateral direction X and / or the second lateral direction Y and / or combinations thereof. It should be noted that the second load terminal 12 is generally not structured, but rather formed laterally homogeneously on the backside 120 of the semiconductor body, for example, to establish a laterally homogeneous contact with the semiconductor body 10. Such a homogeneous structure can also be implemented in regions where the load terminal 12 laterally overlaps with the edge termination region 1-3.

[0038] For example, the lateral boundary of the active region 1-2 is defined by the lateral boundary of the outermost power cell(s) 1-1. Thus, the lateral boundary of the active region 1-2 can be defined at the front face 110. This lateral boundary can be defined by one or more outermost source regions 101' (see the more detailed explanation below). For example, all functional elements for enabling the conduction of the load current are present in a vertical projection of the active region 1-2 of the power semiconductor device 1, comprising, for example, at least the first load terminal 11 (for example, a front-facing metal contact therein, for example, one or more of the contact plugs 111), the source region(s) 101', a body region 102', a drift region 100, a back-facing emitter 103, and the second load terminal 12 (for example, a back-facing metallization therein).

[0039] In one embodiment, the edge termination region 1-3 and the active region 1-2 can, for example, be arranged symmetrically to each other with respect to a central vertical axis of the power semiconductor device 1, as shown in Fig. 2A is shown as an example.

[0040] Furthermore, according to one embodiment, the lateral transition between the active region 1-2 and the edge termination region 1-3 can extend exclusively along the vertical direction Z. As explained above, the lateral boundary of the active region 1-2 can be defined at the front 110, and a vertical projection along the vertical direction Z of such a defined lateral boundary can thus be observed at the rear 120.

[0041] With renewed reference to Fig. Section 1 describes an exemplary configuration of one of the power cells 1-1. Each power cell 1-1 of the power semiconductor device 1 can be configured identically. For example, each power cell 1-1 has at least one trench 14 and at least one mesa 17. In other embodiments, each power cell 1-1 can have more than one trench 14 and more than one mesa 17, wherein the trenches 14 and the mesa 17 can be configured identically or differently.

[0042] A body region 102' of the second conductivity type is contained in the semiconductor body 10. The body region 102' can, for example, be arranged in electrical contact with the first load terminal 11 by means of the contact plug 111'. In some power cells 1-1, at least one source region 101' of the first conductivity type is also provided, which, for example, is also arranged in electrical contact with the first load terminal 11 by means of the contact plug 111'. In contrast to the schematic representation in Fig. 1. It is also possible that the source area 101' is located only on one side of the contact plug 111' in the respective mesa 17.

[0043] A main part of the semiconductor body 10 is formed as a drift region 100 of the first conductivity type, which forms an interface and a pn junction with the body region 102'.

[0044] Body area 102' separates source areas 101' from drift area 100.

[0045] Each power cell 1-1 is further associated with a control electrode 141. The control electrodes 141 can be arranged in a respective trench 14 and can be isolated from the semiconductor body 10 by means of a respective trench insulator 142. Upon receiving a corresponding control signal, which is provided, for example, by a gate driver unit (not illustrated), each control electrode 141 can generate a conductive channel in a section of the body region 102' adjacent to the respective trench electrode 141. Thus, some power cells 1-1 are configured to control at least a portion of the load current between the first load terminal 11 and the second load terminal 12.

[0046] The basic configuration of the power cells 1-1 of a power semiconductor device (for example, an IGBT or RC-IGBT) described above is known to the person skilled in the art, and the present document uses the term "power cells" within the scope of protection of the technical meaning that the person skilled in the art usually associates with it.

[0047] Furthermore, in addition to the configuration as control electrodes, other trench electrodes 141 could be provided in some or each of the power cells 1-1, which perform a different function, such as dummy trench electrodes, source trench electrodes, floating trench electrodes and the like.

[0048] As in Fig. As shown in Figure 1, the body region 102' extends from the front face 110 along the vertical direction Z until it forms an interface with the drift region 100. The drift region 100, which may laterally overlap with the entire lateral area occupied by the number of power cells 1-1, extends over a larger area along the vertical direction Z until it forms an interface with a field stop layer 108. The field stop layer 108 is also of the first conductivity type but has a higher dopant dose compared to the drift region 100. The field stop layer 108 typically has a significantly smaller thickness than the drift region 100. Furthermore, it extends along the vertical direction Z until it forms an interface with the back-side emitter 103. The back-side emitter region 103 is in electrical contact with the second load terminal 12, as shown in Figure 1. Fig. 1 is shown.

[0049] In an IGBT, the back-side emitter region 103 acts as a second-type conductance emitter. If the power semiconductor device 1 is implemented as an RC-IGBT, the back-side emitter region 103 may also include some first-type conductance sections with a higher dopant concentration, typically in the range of 10 16 cm -3 up to 10 20 cm -3 , can exhibit.

[0050] Regarding the lateral extent of the rear-side emitter 103, in one embodiment the emitter area 103 can extend laterally with at least 80% or at least 90% of the lateral area occupied by the number of power cells 1-1 in the active area 1-2. In one embodiment, the emitter area 103 can overlap with the drift area 100 with the entire (100% of) the lateral area occupied by the number of power cells 1-1 in the active area 1-2. In other embodiments, the emitter area 103 can, as in Fig. 2A is shown, with less than 100% of the lateral area occupied by the number of power cells 1-1 in the active area 1-2 overlapping, for example with approximately 80% to 90%.

[0051] It should be emphasized that the power semiconductor device 1 can also be designed as a MOSFET with corresponding effects regarding the configuration of the semiconductor areas 103 and 108, or as a device derived from a MOSFET configuration or an IGBT configuration.

[0052] The aspects of the power semiconductor device 1 described above are known to those skilled in the art. The embodiments described here do not deviate from these generally known aspects, but rather concern a new design with respect to the contact between the first load terminal 11 and the mesas, as well as the mesa configuration with respect to the source region 101' and the body region 102'. Since these aspects are modified, particularly according to the embodiments disclosed here, in the following description, reference numeral 102 refers to the body region, reference numeral 101 to the source region, and reference numeral 111 to the contact plug, while the other reference numerals introduced above do not denote components that necessarily differ from those described with reference to Fig. The ones presented in 1-2B differ, and are subsequently used in the same way.

[0053] For various reasons, it may be desirable to keep the width of the mesa, i.e., the distance between opposing trench sidewalls of the adjacent trenches 14 that laterally bound the mesa, small. However, as the mesa width decreases, it also becomes more difficult to align it based on a contact plug 111' onto a Fig. 1. The depicted way to reliably contact them.

[0054] Fig. Figures 3A-B both schematically and exemplarily show, based on corresponding schematically depicted sections of some vertical cross-sections and a horizontal projection, steps of a method for manufacturing a power semiconductor device according to one or more embodiments. The following refers to Fig. 3A-B and on Fig. 4 referenced.

[0055] The procedure described can be briefly outlined as follows, with aspects of it being described in more detail below.

[0056] The described method is a method for manufacturing a power semiconductor device 1. The provided (see Fig. 3A, Step 1)) Power semiconductor device 1 comprises: a drift region 100 of the first conductivity type in a semiconductor body 10; several trenches 14, wherein two adjacent trenches 14 laterally bound a mesa 17 of the semiconductor body 10 and wherein each trench 14 extends from a semiconductor body surface 110 along the vertical direction Z into the semiconductor body 10 and comprises a trench electrode 141 which is insulated from the semiconductor body 10 by a trench insulator 142; has a trench width TW along a first lateral direction X and has a trench length TL along a second lateral direction Y which is perpendicular to the first lateral direction X (cf. Fig. 2B), wherein the trench length is at least five times the trench width TW; a semiconductor body region 102 of a second conductivity type in the mesa 17. With regard to these features of the power semiconductor device 1, reference is made to the Fig. 1-2B Refer to the above description.

[0057] The described procedure includes: Forming (see below). Fig. 3A, step 2) of a source region 101 of the first conductivity type (e.g., a semiconductor source region 101) in the mesa 17, wherein the source region 101 is arranged above the semiconductor body region 102 in the mesa 17; forming (cf. Fig. 3A, Step 3)) of an insulating layer 300 over and / or on the source region 101; providing (see Step 4)) a mask 400, wherein the mask 400 has at least one mask bridge 401 covering a first part of the source region 101, and at least one mask opening 402 exposing second parts of the source region 101 in the mesa 17 and under the insulating layer 300, wherein the first part of the source region 101 separates two adjacent second parts of the source region 101 along the second lateral direction Y in the mesa 17; removing (see Step 4)) a mask 400 in an area exposed by the at least one mask opening 402. Fig. 3B, step 5)) of part of the insulating layer 300 and the second parts of the source area 101, so that the remaining first part of the source area 101 forms a raised source bridge between the two adjacent trenches 14 in the mesa 17; and separation (cf. Fig. 4 (III)) of an electrically conductive material for forming a contact plug 111, which extends at least from an upper surface of the insulating layer 300 along the vertical direction Z to contact the first part of the source region 101 on a side wall part 1011 thereof.

[0058] Regarding step 1), the power semiconductor device 1 to be fabricated can be provided in a conventional configuration, with the multiple trenches 14 laterally bounding the multiple mesas 17. It should be emphasized again that the trenches have a strip configuration (i.e., TW << TL) and that during the fabrication of the device 1, the trench electrodes 141 can be connected to different electrical potentials. That is, not every trench electrode 141 needs to be connected to a control / gate terminal of the device, but could, depending on the desired configuration of the power cells 1-1, also be connected to the first load terminal 11 (usually a source terminal), or be electrically floating, or connected to the control / gate terminal via specific ohmic resistors or another coupling impedance.The same applies analogously to the configuration of Mesas 17: the Mesas 17 can each be configured identically or differ from each other in their configuration. For example, an initial configuration of Mesa 17 can be the same as the configuration with reference to the left of the two in . Fig. The mesa depicted in 3A-B is described, and a second configuration of Mesa 17 can be the same as for the right of the two mesae of the Fig. The mesa shown in Figures 3A-B can be configured as follows: 1. Mesa 17 is not electrically contacted by a contact plug, but is insulated from the first load terminal 11 based on the insulating layer 300, for example, to act as a "dummy mesa". In another variant, the mesa can be configured without the source region 101, but with the body region 102, and the body region 102 can be connected to a contact plug 111, for example, to the left of the two shown above. Fig. The mesa shown in 3A-B can be contacted in a way that allows it to act, for example, as a "diode mesa". Thus, the power cells 1-1 can be manufactured with different configurations.

[0059] In one embodiment, the upper width WM of the mesa 17 is no more than 500 nm, no more than 300 nm, or no more than 100 nm. In another embodiment, the upper width WM of the mesa 17 is less than 50 nm. For example, the upper width WM is measured at the vertical height where the source region 101 forms an interface with the body region 102. Depending on the design of the trenches 14, the mesa width can, of course, vary slightly along the vertical extent of the mesa 17. For example, a lower mesa width can be less than, greater than, or equal to the upper mesa width(s) WM.

[0060] As will be explained in detail below, each of the trenches 14 can also have more than one trench electrode 141. For example, two trench electrodes 141-1 / 2 (see below) can be used. Fig. 7) provided and laterally offset from each other. The two trench electrodes 141-1 / 2 could also be vertically offset from each other.

[0061] According to the invention, the trench electrode 141 of at least one of the two adjacent trenches 14 is separated from the insulating layer 300 along the vertical direction Z by an upper trench insulator 143. ZB, each trench electrode 141 is separated from the insulating layer 300 along the vertical direction Z by a respective upper trench insulator 143. The upper trench insulator 143 has a vertical extent that amounts to up to 90% of the vertical extent of the source region 101. In other words, the upper surfaces of the trench electrodes 141 are separated by a certain distance T. Rvertically recessed from the semiconductor body surface 110, so that the source region 101 is raised above the tops of the trench electrodes 141.

[0062] The pn transition 1021 is formed by a transition between the body region 102 and the drift region 100 along the vertical direction Z in Mesa 17. The pn transition can extend along the entire width of the mesa.

[0063] The illustrated process step 2) concerns the formation of the source region 101 in the mesa 17. For this purpose, a source mask 200 can be used, for example, which covers those parts of the semiconductor body surface 110 under which the source region 101 is not to be formed. In the illustrated example, the right mesa 17 is not to be equipped with the source region 101, but is to act as a dummy mesa (as shown) or as a diode mesa. In one embodiment, the source mask 200 exposes the left mesa 17 along its entire mesa width, so that the formed source region 101 extends in the first lateral direction X along the entire upper width WM of the mesa 17. In other words, the source mask 200 can be structured accordingly, for example, based on a feature length that is greater than the upper mesa width WM or even greater than the trench width TW.With regard to the lithography associated with the formation of source area 101, the procedure does not require a high degree of complexity.

[0064] The formation of the source region 101 may involve one or more implantation processing steps.

[0065] The formed source region 101 can be arranged on the top side of the mesa 17; e.g. the semiconductor body surface 110 can be partially formed by the source region 101 in the mesa 17.

[0066] After the source region 101 is formed, the source mask 200 is removed, and as in Fig. As shown in Figure 3A for step 3), the insulating layer 300 is formed over it, for example on the source region 101. That is, the source region 101 in the mesa 17 can partially form the semiconductor body area 110, and the formed insulating layer 300 can be arranged in contact with the source region 101. For example, the insulating layer 300 is formed over the entire wafer surface and can therefore be in contact with each of the upper trench insulator(s) 143, the trench insulator(s) 142, and the source region(s) 101.

[0067] The formation of the insulating layer 300 can involve one or more deposition processing steps. For example, the insulating layer 300 can contain one or more sublayers. Furthermore, the insulating layer 300 can be densified, for example, based on a temperature control processing step. Regarding the material of the insulating layer 300, it can, for example, contain one or more of TEOS, PSG, BSG, and BPSG.

[0068] For example, the formed insulating layer 300 extends along the entire upper width WM of the mesa 17 between the two adjacent trenches 14.

[0069] It should be noted that the insulating layer 300 can be formed on a surface defined by the upper trench insulator 143, the trench insulator 142, and the semiconductor body surface (which is formed, for example, by the source region 101 and optionally by the body region 102), wherein the surface can be a plane, e.g., a horizontal plane parallel to the first and second lateral extensions X and Y. The insulating layer 300 can be formed homogeneously on such a surface, so that it can have a substantially constant thickness, e.g., in the range of 50 nm to 2000 nm or in the range of 100 nm to 500 nm along the vertical direction Z.

[0070] The in Fig. Step 4) shown in Figure 3B concerns the formation of the contact plug 111, which is ultimately intended to contact the mesa 17. For this purpose, the mask 400 is provided, which is shown in both a vertical cross-section (left side, cut along BB') and a horizontal cross-section (right side). In one embodiment, the first part of the source region 101 (which is covered by the mask bridge 401, see Step 5), right side, cut along A-A'), and the second parts of the source region 101 (which are exposed through the mask openings 402) overlap laterally along the first lateral direction X and do not overlap laterally along the second lateral direction Y in the mesa 17. It should be noted here that the "exposed" second parts of the source region 101 are still covered by the insulating layer 300.

[0071] In one embodiment, the mask openings 402 cover almost the entire mesa 17, in the example according to Fig. 3B namely along the entire upper mesa width WM and along almost the entire mesa length in the second lateral direction Y (cf. length TL in Fig. 2B) with the exception of the area covered by the mask bridge 401. For example, the at least one mask opening 402 completely exposes Mesa 17 under the insulating layer 300 along the first lateral direction X and at least 40% or at least 60% of Mesa 17 along the second lateral direction Y. That is to say, in the Fig. In the example shown in Figure 3B, the width WP1 of the mask opening 402 in the first lateral direction X can be larger than the upper mesa width WM by, for example, 25 nm, 50 nm, or 80 nm, to compensate for overlap tolerances. Due to such an "increased" width of the mask opening 402, step-like structures 1421 can be formed on the trench insulators 142 after the subsequent removal steps.

[0072] In another embodiment, as in Fig. Figure 6B shows that at least one mask opening 402 leaves the mesa 17 partially free along the first lateral direction X by at least 40% or at least 60% of the mesa 17 along the second lateral direction Y. That is, in which Fig. In the example shown in 6B (see step 4), the width WP2 of the mask opening 402 in the first lateral direction X can be smaller than the upper mesa width WM by a total of 25 nm, 50 nm or 80 nm, but not more than a total of 200 nm.

[0073] In one embodiment, the mesa 17 is covered by at least one such mask bridge 401. If more than one source region 101 is to be provided in the mesa 17, more mask bridges 401 can be provided, offset from one another along the second lateral direction Y. The size and / or the number of mask bridges used to cover the mesa portions where the source region(s) are to remain depends on the target parameters of the power semiconductor device 1, such as the desired latch-up robustness.

[0074] The design of the mask 400 thus determines both where the contact plug(s) is / are formed and simultaneously where the source region 101 is removed. According to the embodiments described here, the source regions 101 and the contact plugs 111, which are used to contact the source regions, can therefore be positioned complementarily with respect to the first and second lateral directions X and Y.

[0075] We now turn to process step 5) in Fig. Reference is made to Figure 3B, which shows in the left part the removal of part of the insulating layer 300 and the second parts of the source area 101, such that the remaining first part of the source area 101, as shown in the right section, forms the raised source bridge between the two adjacent trenches 14 in the mesa 17. Accordingly, parts of the body area 102 beneath the second parts of the source area 101 can also be removed with this removal step. The remaining first part of the source area 101 forms, as shown in the right section of step 5) in Fig. 3B and in section (II) of the Fig. Figure 4 shows the raised source bridge with the side wall parts 1011 and a lower part 1012, which forms a pn junction with the body region 102.

[0076] The removal step can include at least one etching step. For example, a first etching step involves etching the exposed sections of insulating layer 300, and a second etching step is a selective etching step that affects the semiconductor material in Mesa 17. The selective etching step can be anisotropic, isotropic, or a combination of both.

[0077] The distance step results in a contact groove 1110 into which the contact plug 111 can extend. The lateral width of the contact groove 1110 can be self-aligned based on the upper mesa width.

[0078] After the contact groove 1110 has been formed, the mask 400 can be removed. In one embodiment, however, the insulating layer 300 remains.

[0079] An optional further step 6) involves, after removal, forming a semiconductor body contact area 1022 with a higher dopant concentration in the remaining semiconductor body area 102, e.g., by applying an implantation processing step. During such a step, the remaining first part of the source area 101, which forms the raised source bridge, is covered by the insulating layer 300 and is therefore not subject to such an implantation processing step.

[0080] In one embodiment, each of the formed contact grooves 1110 has a length in the second lateral direction Y of more than twice the mesa width WM. Furthermore, the length in the second lateral direction Y can be less than ten times the mesa width WM.

[0081] After these steps, tempering processing steps can be carried out, and the contact groove 1110 can be filled with the electrically conductive material to connect the contact plug 111 (see below). Fig. 4) to form, which is now referred to:

[0082] Part (I) of the Fig. 4 represents the mask 400 (as in step 4) of the Fig. 3B / Fig. 6B) with the mask bridge 401 and the mask openings 402 and parts (II) to (IV) represent vertical cross sections along lines A-A', BB' and C-C' respectively, as shown in section (I). If the mask 400 is removed, parts (II) to (IV) do not show the mask 400.

[0083] Part (II) of the Fig. Figure 4 shows a section of the mesa 17 and the shaped contact plug 111 along a plane parallel to the second lateral direction Y and the vertical direction Z. Accordingly, contact between the contact plug 111 and the first part of the source region 101 is formed at the interfaces 1010 where the first part of the source region 101 forms an interface with the second parts of the source region 101 before the second parts of the source region 101 have been removed. The contact plug 111 extends from at least one upper surface of the insulating layer 300 along the vertical direction Z. For example, the upper surface of the insulating layer 300 forms an interface with the contact plug 111, such that the contact plug 111 extends from above the insulating layer 300 along the vertical direction Z, and a lower surface of the insulating layer 300 forms an interface with the source region 101.

[0084] Side wall parts 1111 of the contact plug 111 and side wall parts 1011 of the first part of the source area 101, i.e. the raised source bridge, touch each other at the interfaces 1010.

[0085] The interfaces 1010, i.e. both the side wall parts 1111 of the contact plug 111 and the side wall parts 1011 of the raised source bridge 101, can be inclined with respect to the second lateral direction Y, e.g. perpendicular to it.

[0086] Referring to parts (II) and (III) of the Fig. 4. The semiconductor body region 102 can be contacted by a lower part 1112 of the contact plug 111. The lower part 1112 contacts, for example, the previously formed semiconductor body contact region 1022 with a higher dopant concentration. A lower part 1012 of the raised source bridge 101 is in contact with the underlying part of the semiconductor body region 102, thereby forming a pn junction.

[0087] According to the embodiments described herein, and as set out in parts (II) and (IV) of the Fig. As shown in Figure 4, the raised source bridge 101 is thus separated along the vertical direction Z by the insulating layer 300 from an upper part of the contact plug 111, while on the same part a lower part of the contact plug 111 forms the side wall parts 111 which contact the side wall parts 1011 of the raised source bridge 101 under the insulating layer 300.

[0088] The preceding description, particularly with regard to Fig. 3A-B, Fig. 4 and Fig. 5, applies accordingly to each of the remaining Fig. 6-14, unless explicitly stated otherwise.

[0089] Fig. 5 essentially corresponds to an enlarged version of the Fig. 4, Part (II). Due to the etching processing steps, the insulating layer 300 above the raised source bridge 101 may have a chamfer on its upper surface. Furthermore, due to the tempering processing steps that can be used, the semiconductor body contact area 1022 with a higher dopant concentration may slightly extend into the area corresponding to a vertical projection of the insulating layer 300. The degree to which the raised source bridge 101 is raised relative to the lower parts 1112 of the contact plug 111, which contact the semiconductor body contact area 1022, depends on the manner in which the removal step is carried out, e.g., the duration of the relevant etching processing step (see Steps 5) in Fig. 3B, Fig. 6B and Fig. 6C, in other words, depends on how deep the contact groove 1110 is. For example, it prevents the raised source bridge 101 from forming an interface with the semiconductor body contact area 1022, but only with the semiconductor body area 102.

[0090] Fig. 6A-C represent a variation of the in Fig. The procedure shown in 3A-B is described. However, steps 1) to 3) correspond exactly to steps 1) to 3) of the Fig. 3A, which is why reference is made to the above. The variation concerns mask 400, which is provided in step 4).

[0091] According to the embodiment in Fig. 6B exposes at least one mask opening 402 of the mesa 17 under the insulating layer 300 partially along the first lateral direction X and at least 40% or at least 60% of the mesa 17 along the second lateral direction Y. That is, in which Fig. In the example shown in Figure 6B (see step 4), the width WP2 of the mask opening 402 in the first lateral direction X can be smaller than the upper mesa width WM by, for example, a total of 25 nm, 50 nm, or 80 nm, but not more than a total of 200 nm. Based on such a design, the stepped structures 1421 do not arise.

[0092] According to the embodiment in Fig. 6C has mask 400 with additional mask openings 402 and an additional mask bridge 401 that expose / cover the right mesa 17 where no source region 101 has been formed (see step 2). When the removal step is performed (see step 5), contact grooves 1110 are also formed with respect to the right mesa 17, corresponding to the positions of the mask openings 402 above the mesa 17. Accordingly, the semiconductor body contact region 1022 is also formed in the right mesa 17 (see step 6), and when the electrically conductive material is deposited, a contact plug for the right mesa 70 is also formed, so that this mesa 17 can, for example, act as a "diode mesa". In a vertical cross-section parallel to the second lateral direction Y, this would result in a structure as shown in Fig. 4, Part (II) and Fig. 5 shows the result, with the difference that the raised source bridge 101 is replaced by a corresponding part of the semiconductor body region 102.

[0093] How best to do this with reference to procedure step 4) in Fig. 3B, Fig. As shown in 6B in 6C, the at least one mask bridge 401 and the at least one mask opening 402 can be positioned perpendicular to the trench length TL in the second lateral direction Y and optionally over several adjacent trenches 14 (see 6B in 6C). Fig. 6C) and thus extend over several adjacent Mesa 17, not every Mesa need to be equipped with a Source Area 110, as just explained.

[0094] Fig. Figure 7 schematically and exemplarily represents a section of a vertical cross-section 1 according to one or more embodiments. Here, the trenches 14 are formed as double-electrode trenches 14 with a wider trench width TW and with first and second sidewall trench electrodes 141-1 and 141-2 in each trench 14. The trenches 14 still have a strip configuration with a trench length TL (cf. Figure 7). Fig. 2B), which amounts to at least five times the trench width TW. As can also be fulfilled with regard to the embodiments described above, the trenches 14, for example, extend continuously along the second lateral direction Y through the entire active area 1-2 (cf. 2A-B). Apart from corresponding dimensional adjustments, the process for manufacturing such a power semiconductor device 1 (with wider / double trench electrode) trenches can, however, be carried out as above, e.g., with reference to Fig. 3A-B and Fig. 6A-B / C, procedure steps 1) to 6) have been explained, will be carried out.

[0095] It will now be based on Fig. Reference is made to figures 8-10, which each schematically and exemplarily represent aspects of a power semiconductor device 1 configured in this way according to some embodiments, based on corresponding schematically represented sections of two vertical cross-sections (parts (2) and (3)) and a horizontal projection (part (1)).

[0096] According to the embodiment of the Fig. 8 are adjacent Mesas 17 configured identically, i.e. both have elevated Source Bridges 101 in areas of Mesas 17 that correspond to vertical projections of Mask Bridges 401. Fig. 8 and Fig. 9 emphasize that the mask openings 402 in lateral extension along the first lateral direction X may be narrow in order to only include the relevant sections of the mesas 17 ( Fig. 8) to expose, or extend laterally along the first lateral direction X to also expose parts of trench 14 between the adjacent mesas ( Fig. 9) to expose. For example, each of one or more mask openings 402 can thus expose sections of both of the adjacent mesas 17. Since the insulating layer 300 is removed from under the mask openings 402, see Fig. 9, Part (2), the electrically conductive material for forming the contact plugs 111 extends over the upper trench insulator 143 between the trench sidewall electrodes 141-1 / 2.

[0097] According to the embodiment of the Fig. 10 will be the left of the adjacent mesas 17 as before (e.g., with reference to Fig. 3A-B and Fig. 8) described, and the right of the adjacent mesas 17 is formed as a diode mesa, i.e., without a source region 101. It may be desirable, for example, to contact the diode mesa along its entire extent in the second lateral direction Y, and accordingly, the corresponding mask opening 402 exposes the entire right of the adjacent mesas 17. Another mask, not shown, can be used if the Fig. 3B, Fig. 6B and especially in Fig. The process step 6) shown in Figure 6C is carried out, namely when the semiconductor body contact areas 1022 are formed. The semiconductor body contact area 1022 in the right of the adjacent mesas 17 is structured along the second lateral direction Y based on such a further mask, e.g., such that the semiconductor body contact area 1022 is not formed where the right of the adjacent mesas 17 along the second lateral direction Y overlaps with the raised source area 101 in the left of the adjacent mesas 17, and such that the semiconductor body contact area 1022 is formed where the right of the adjacent mesas 17 along the second lateral direction Y does not overlap with the raised source area 101 in the left of the adjacent mesas 17. Of course, other ways of structuring the semiconductor body contact area 1022 in the right of the adjacent mesas 17 are also possible.Such a structuring can result in improved diode performance of the power semiconductor device 1.

[0098] At least one of the trench electrodes 141-2 and 141-1 adjacent to the right of the neighboring mesas 17 can be connected to the control terminal of the power semiconductor device 1 or to a different potential, e.g., to the first load terminal 11. Both trench electrodes 141-2 and 141-1 adjacent to the left of the neighboring mesas 17 can, for example, be connected to the control terminal. That is, each trench 14 can accommodate at least two trench electrodes 141-1 and 141-2 connected to different electrical potentials.

[0099] It will now be based on Fig. Reference is made to Figure 11, which schematically and exemplarily, based on corresponding schematically depicted sections of two vertical cross-sections (parts (2) and (3)) and a horizontal projection (part (1)), illustrates aspects of the power semiconductor device 1 according to one embodiment. In this embodiment, both of the adjacent mesas 17 are configured identically based on the use of the correspondingly structured mask 400. The mask bridges 401 cover portions of the insulating layer 300, beneath which the source regions 101 remain, and form the raised source bridges 101 (see part (2), section along C-C'). The mask openings 402 expose other portions of the insulating layer 300, which are removed, as well as the source region 101 beneath. In the correspondingly formed contact grooves 1110 (see Fig. 3A-B and Fig. 6A-C) the contact plugs 111 are formed, e.g. in a manner as described above.

[0100] It should be noted that various materials can be used to form the contact plugs 111. For example, a metal silicide can be formed at an interface with the semiconductor material (which is formed, for example, by the semiconductor body contact area 1022), comprising, for example, one or more titanium silicides, cobalt silicides, and nickel silicides. Such a metal silicide can be coated with aluminum-copper, AlSiCu, copper, or the like. Other materials, such as titanium, titanium nitride, and / or tungsten, can be used, particularly in combination with a cover layer made of AlCu or Cu. Fig. Part (2) of Article 11, for example, presents an embodiment in which the contact plugs 111 are formed based on a first material (composition) 1114 extending from the height of the surface of the insulating layer 300 into the contact grooves in order to contact both the respective raised source bridge 101 with the side wall parts 1111 of the contact plug 11 and the semiconductor body contact area 1022 with the lower parts 1112 of the contact plug 111, and on a second material 1115 (e.g. AlCu or Cu) that forms the cover layer over the insulating layer 300.

[0101] Part (3) of the Fig. Figure 11 represents a vertical cross-section along section D-D', the insulating layer 300, the upper trench insulator 143, the trench electrode (which may be either a single trench electrode 141 of trench 14 or one of several trench electrodes 141-1, 141-2), the trench insulator 142 at the bottom of trench 14 and the drift area 100.

[0102] According to the embodiment of the Fig. 12, which is also schematically and exemplarily represented based on correspondingly schematically depicted sections of two vertical cross-sections (parts (2) and (3)) and a horizontal projection (part (1)), the mask 400 is configured differently, e.g. in a way that, with reference to Fig. 9 has been described, i.e., where the mask 400 has a strip-like configuration according to which the mask bridges 401 are formed by mask strips extending continuously along the first lateral direction X, and the mask openings 402 are formed by mask recesses that also extend continuously along the first lateral direction X. Accordingly, such a mask design does not change the configuration of the mesas 17, cf. part (2) of the Fig. 12 (which is essentially identical to part (2) of the Fig. 11), but, since the enlarged mask openings also expose parts of the insulating layer 300 above the upper trench insulator 143, during the removal step (see step 5) in Fig. 3B, Fig. 6B and Fig. 6C) parts of the upper trench insulator 143 are also removed, and the structure formed during the formation of the contact plugs 111 also extends into areas above the trenches 14, see part (3) of the Fig. 12.

[0103] According to the embodiments described herein, the design of the mask 400 determines the lateral positions and lateral dimensions of both the source regions 101 (i.e., the raised source bridges 101) and the contact plug 111. The design of the mask 400 formed based on the mask openings 402 and the mask bridges 401 can be chosen based on the following considerations: The mask bridges 401 can have an extension in the second lateral direction Y in order to limit the path length for holes, e.g., during the turn-off of an IGBT, to achieve an ohmic p-contact with the first load terminal 11 before reaching a potential difference to the source region 101 that would cause injection of holes into the source region 101 and consequently the injection of electrodes into the source region 102, which could lead to control loss of the power semiconductor device 1 and consequently to its destruction.The mask opening(s) 402 can be configured in such a way that the transconductance of the power semiconductor device 1, i.e. the change in load current as a function of the gate potential, is in a suitable range to meet the requirements regarding current rise during the turn-on of the power semiconductor device 1 and current limiting in the event of an overcurrent or failure event.

[0104] As shown throughout the drawings, each of the at least one mask bridge 401, for example, spans the entire mesa 17 (in which the one or more raised source bridges are to be formed) along the first lateral direction X. Furthermore, each of the at least one mask bridge 401 can have a total extent in the second lateral direction Y of no more than 500 nm. This extent is therefore also approximately the extent of the respective raised source bridge 101 in the second lateral extent.If the respective mesa 17 is bridged, for example, by more than one mask bridge 401, the distance between adjacent two of the mask bridges 401 in the second lateral direction Y can be at least 300 nm or at least 600 nm or at least 1000 nm, where such a distance is thus the distance of the respective mask opening 402 between adjacent two of the mask bridges 401 and approximately the extent of the contact plug 111 formed between adjacent two of the mask bridges 401.

[0105] It should be noted here that in one embodiment, the contact plug 111 with its side wall parts 1111 thus contacts two raised source bridges 101 which are separated from each other along the second lateral direction Y, wherein the side wall parts 1111 are inclined with respect to the second lateral direction Y, e.g. are arranged substantially perpendicular to the second lateral direction Y, as shown in parts (2) of the Fig. 11 and Fig. 12 is shown as an example.

[0106] For example, both the mask opening 402 and the corresponding contact plug 111 have a total lateral extent in the second lateral direction Y that is at least twice the upper width WM of the mesa 17. That is to say: The mask opening 402 can have a total lateral extent in the second lateral direction Y that is at least twice as large as the total lateral extent of the adjacent mask bridge 401 in the second lateral direction Y.

[0107] Fig. Figures 13A-B both schematically and exemplarily show, based on corresponding schematically depicted sections of some vertical cross-sections, steps of a method for manufacturing a power semiconductor device according to some embodiments. Steps 1) to 3) shown here can be performed before step 1) of the Fig. 3A or Step 1) of the Fig. 6A are carried out and concern the formation of the trench 14 with two (sidewall) trench electrodes 141-1, 142-2 and the floating semiconductor barrier region 105 under the bottom of the trench 14. After carrying out steps 1) to 3), the procedure of Fig. 13A-B as with reference to steps 1) to 6) of the Fig. 3A-B or Fig. 6A-C described further, so that the device 1 is in a position with respect to step 4) of the Fig. The condition shown in 13B is as shown.

[0108] In step 1) of the Fig. In 13A, the device 1 is provided in a state in which the trenches 14 have been etched and fitted with the trench insulators 142, but not yet with the trench electrodes 141-1 / 2. The mesas 17 have also not yet been processed, but are covered with a mesa mask 500.

[0109] Step 2) is a deposition processing step in which an electrically conductive material is deposited on the trench sidewalls to form the trench electrodes 141-1 / 2. As a result of this process, the electrically conductive material is also accumulated at the bottom of trench 14 and around the mesa mask 500.

[0110] Such superfluous parts of the electrically conductive material are removed, for example, by performing an etching process, such as an anisotropic etching process. The shape of the trench electrodes 141-1 / 2 can be rectangular, but can also be modified in various ways during the etching process, with the dashed and dotted lines schematically representing two examples to illustrate possible changes in the shape of the trench electrodes 141-1 / 2. For the sake of simplicity, the rectangular shape of the trench electrodes 141-1 / 2 is used in all other cases. Fig. Keep 7 to 10.

[0111] Subsequently, in step 3), an implantation processing step or the like is performed to form the floating barrier region 105 beneath the bottom of the trench 14. Based on the implantation energy, dose, number of implantations, implantation angles (inclined, not inclined), and implantation time, the position, extent, and subsequently the dopant concentration of the floating barrier region 105 can be controlled. For example, the floating barrier region 105 can be vertically offset from or in contact with the trench insulator 142 at the bottom of the trench 14. The floating barrier region 105 can extend along the first lateral direction X to overlap with the trench electrodes 141-1 / 2 or even the opening of the mesas 17, or it can be smaller in lateral width so that no overlap with the mesa 17 is formed.

[0112] As mentioned above, after implantation in step 3, the device 1 can be processed in the manner described above. For example, the floating barrier region 105 is also subjected to tempering processing steps (which are applied with regard to the raised source bridges 101 and the semiconductor body contact regions 1022), for example in a manner that results in such an extension of the floating barrier region 105 that it is located at the bottom of the trench 14 in contact with the trench insulator 142.

[0113] This document presents not only a method for fabricating a power semiconductor device, but also the power semiconductor device itself. The power semiconductor device comprises: a semiconductor body with a drift region of a first conductivity type; several trenches, wherein two adjacent trenches laterally bound a mesa of the semiconductor body. Each trench extends from a semiconductor body face along a vertical direction into the semiconductor body and includes a trench electrode insulated from the semiconductor body by a trench insulator. The trench has a width along a first lateral direction and a length along a second lateral direction perpendicular to the first lateral direction, the length being at least five times the width.Furthermore, the device comprises a semiconductor body region of a second conductivity type in the mesa; a source region of the first conductivity type in the mesa, wherein the source region is arranged above the semiconductor body region; an insulating layer above and / or on the source region; a contact plug extending from at least one upper surface of the insulating layer along the vertical direction to contact both the source region and the semiconductor body region, the contact plug having sidewall portions and a lower portion, both of which form an interface with the semiconductor body. The contact plug extends along the entire upper width of the mesa in the first lateral direction into the semiconductor body. The source region is contacted by at least one of the sidewall portions of the contact plug.

[0114] An embodiment of the power semiconductor device described in the preceding paragraph corresponds, with respect to the drawings, to embodiments of the method described. Reference is therefore made to the foregoing. Nevertheless, some embodiments of the power semiconductor device will be described below using the reference numerals described above:

[0115] For example, the semiconductor body area 102 is contacted by the lower part 1112 of the contact plug 111, cf. e.g. Fig. 4, Part (II).

[0116] In one embodiment, the lower part 1112 of the contact plug 111 is arranged at least substantially parallel to both the first lateral direction X and the second lateral direction Y, and the side wall parts 1111 of the contact plug 111 (which touch the source area 101, e.g. the raised source bridge) are arranged at least substantially parallel to both the first lateral direction X and the vertical direction Y.

[0117] Furthermore, in one embodiment, the semiconductor body area 102 is additionally contacted by at least one of the side wall parts 1111 of the contact plug 111. The extent to which such contact is established depends, for example, on the manner in which the removal step (step 5) is carried out. Fig. 3B, Fig. 6B and Fig. 6C), i.e., it depends on how deep the contact groove 1110 extends into the mesa. For the reasons explained above, namely the shielding function of the semiconductor body contact area 1022, which is vertically offset from the raised source bridge 101, it may therefore be appropriate to design the depth of the contact groove 1110 accordingly. Then the semiconductor body area 102 is additionally contacted by at least one of the side wall parts 1111 of the contact plug 111, as for example in Fig. 4, Part (II) is shown. The depth of the contact grooves 1110, measured from a vertical height corresponding to the height of the semiconductor body area 110, may, for example, be 280 nm, and the source region 101 may form an interface with the body region 102 at approximately 230 nm below the vertical height.

[0118] In one embodiment, for example, the lower part 1112 of the contact plug 111 is offset along the vertical direction Z by, for example, at least 30 nm or at least 50 nm from the source region 101, as shown throughout in the drawings. Furthermore, the semiconductor body contact region 1022 can be offset along the vertical direction Z by, for example, the same distance as just mentioned from the source region 101.

[0119] As consistently shown in the drawings, the source area 101 (i.e., the raised source bridge) can also extend along the entire upper width WM of mesa 17 in the first lateral direction X. In this respect, reference is made to the explanations regarding procedure step 2) in Fig. 3A and Fig. 6A is referenced. This means that the source region 101 can be arranged in contact with both trench insulators 142 of the two trenches 14 that laterally bound the mesa 17. However, the side wall parts 1011 of the source region 101 are not those that form an interface with the trench insulators 142, but rather those that are arranged, for example, at least substantially perpendicular to the second lateral direction Y, so that they can form an interface with the side wall parts 1111 of the contact plug 111, as described above.

[0120] As is consistently shown in the drawings, the contact plug 111 can also be in contact with both trench insulators 142 of the adjacent trenches 14, which laterally delimit the mesa 17. When forming the contact grooves 1110 (see step 5) in Fig. 3B, Fig. 6B and Fig. 6C) For example, a portion of the mesa 17 is removed along the entire upper mesa width WM. During the deposition of the electrically conductive material to form the contact plug 111, the contact plug 111 is thus positioned in contact with both trench insulators 142 of the adjacent trenches 14 that laterally bound the mesa 17. According to known configurations, as in Fig. As shown in Figure 1, only central parts of the mesas have been removed, so that the contact plugs 111' are laterally offset from the trench insulators 142; this is necessarily the case because otherwise the contact plugs 111' could not simultaneously contact both the source region 101 and the body region 102.

[0121] Further embodiments of the method correspond to the embodiments of the power semiconductor device described above.

[0122] In addition to power cells that include both a source region and a body region and are controlled by an adjacent gate electrode, other mesas of the power semiconductor device can instead contain diode or resistor structures, as is the case, for example, with reference to RC-IGBTs. It is obvious to those skilled in the art that the technical teaching disclosed herein can be applied to construct such mesas of the power semiconductor device as described above. Fig. 6C, steps 4) to 6) described to contact.

[0123] The preceding section described embodiments relating to power semiconductor devices such as IGBTs and corresponding processing methods. These power semiconductor devices are based, for example, on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body 10 and its regions / zones, e.g., regions, etc., can be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon can be used.

[0124] However, it should be obvious that the semiconductor body 10 and its regions / zones can be made from any semiconductor material suitable for manufacturing a semiconductor device.Examples of such materials include elemental semiconductor materials, such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials, such as cadmium telluride (CdTe) and mercury cadmium telluride. (HgCdTe), to name just a few, but not limited to them. The semiconductor materials mentioned above are also referred to as "homo-junction semiconductor materials".When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials, but are not limited to these. For power semiconductor switch applications, Si, SiC, GaAs, and GaN materials are currently the most commonly used.

[0125] Spatial terms such as "under," "below," "lower," "above," "upper," and the like are used for the sake of simplicity to describe the positioning of one element relative to another. These terms are intended to encompass various orientations of the respective device, in addition to orientations different from those depicted in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, areas, sections, etc. Throughout the description, the same terms refer to the same elements.

[0126] As used herein, the terms “exhibit”, “contain”, “include”, “comprise”, “have” and the like are open terms and indicate the presence of the specified elements or features, but do not exclude any additional elements or features.

Claims

[1] Power semiconductor device (1) comprising: - a semiconductor body (10) with a drift region (100) of a first conductivity type; - several trenches (14), wherein two adjacent trenches (14) laterally bound a mesa (17) of the semiconductor body (10) and wherein each trench (14) - extends from a semiconductor body surface (110) along a vertical direction (Z) into the semiconductor body (10) and includes a trench electrode (141) which is insulated from the semiconductor body (10) by a trench insulator (142); - has a trench width (TW) along a first lateral direction (X) and a trench length (TL) along a second lateral direction (Y) perpendicular to the first lateral direction (X), the trench length being at least five times the trench width (TW); - a semiconductor body region (102) of a second conductivity type in the mesa (17); - a semiconductor source region (101) of the first conductivity type in the mesa (17), wherein the source region (101) is arranged above the semiconductor body region (102); - an insulating layer (300) over and / or on the source area (101); - a contact plug (111) extending at least from an upper surface of the insulating layer (300) along the vertical direction (Z) to contact both the source region (101) and the semiconductor body region (102), wherein the contact plug (111) has side wall parts (1111) and a lower part (1112) both forming an interface with the semiconductor body (10); where: - the contact plug (111) extends along an entire upper width (WM) of the mesa (17) in the first lateral direction (X) into the semiconductor body (10), and - the source area (101) is contacted by at least one of the side wall parts (1111) of the contact plug (111); wherein - the trench electrode (141) of at least one of the two adjacent trenches (14) is separated from the insulating layer (300) along the vertical direction (Z) by an upper trench insulator (143); - the upper trench insulator (143) has a vertical extent that amounts to up to 90% of the vertical extent of the source area (101); and - one top side of the trench electrode (141) by a distance (T R ) is vertically recessed from the semiconductor body surface (110) of the mesa (17), so that the source region (101) is raised above the top of the trench electrode (141). [2] Power semiconductor device (1) according to claim 1, wherein the semiconductor body region (102) is contacted by the lower part (1112) of the contact plug (111). [3] Power semiconductor device (1) according to claim 2, wherein the semiconductor body region (102) is additionally contacted by at least one of the side wall parts (1111) of the contact plug (111). [4] Power semiconductor device (1) according to one of the preceding claims, wherein the side wall parts (1111) of the contact plug (111) extend substantially parallel to the first lateral direction (X) and / or wherein the lower part (1112) of the contact plug (111) extends substantially perpendicular to the vertical direction (Z). [5] Power semiconductor device (1) according to one of the preceding claims, wherein the source region (101) extends in the first lateral direction (X) along an entire upper width (WM) of the mesa (17). [6] Power semiconductor device (1) according to one of the preceding claims, wherein the contact between the contact plug (111) and the source region (101) is established at an interface formed by one of the side wall parts (1111) of the contact plug (111) and a side wall part of the source region (1011). [7] Power semiconductor device (1) according to one of the preceding claims, wherein the contact plug (111) is in contact with both trench insulators (142) of the adjacent trenches (14) that laterally limit the mesa (17). [8] Power semiconductor device (1) according to one of the preceding claims, wherein the lower part (1112) of the contact plug (111) is offset by at least 30 nm along the vertical direction (Z) from the source region (101). [9] Power semiconductor device (1) according to one of the preceding claims, wherein a further side wall part (1111) of the contact plug (111) contacts an additional source region (101) in the mesa (17), wherein the two source regions (101) are separated from each other along the second lateral direction (Y). [10] Power semiconductor device (1) according to one of the preceding claims, wherein the source region (101) is contacted by at least one side wall part (1111) of an additional contact plug (111). [11] Power semiconductor device (1) according to one of the preceding claims, wherein the upper width (WM) of the mesa (17) is at most 500 nm. [12] Method for manufacturing a power semiconductor device (1) comprising: - in a semiconductor body (10) a drift region (100) of a first conductivity type; - several trenches (14), wherein two adjacent trenches (14) laterally bound a mesa (17) of the semiconductor body (10) and wherein each trench (14) - extends from a semiconductor body surface (110) along a vertical direction (Z) into the semiconductor body (10) and includes a trench electrode (141) which is insulated from the semiconductor body (10) by a trench insulator (142); - has a trench width (TW) along a first lateral direction (X) and a trench length along a second lateral direction (Y) perpendicular to the first lateral direction (X), the trench length being at least five times the trench width (TW); - a semiconductor body region (102) of a second conductivity type in the mesa (17); wherein the method comprises: - Forming a source region (101) of the first conductivity type in the mesa (17), wherein the source region (101) is arranged above the semiconductor body region (102); - Forming an insulating layer (300) over and / or on the source area (101); - Providing a mask (400) wherein the mask (400) has at least one mask bridge (401) covering a first part of the source region (101) and at least one mask opening (402) exposing second parts of the source region (101) in the mesa (17) and under the insulating layer (300), wherein the first part of the source region (101) separates two adjacent second parts of the source region (101) along the second lateral direction (Y) in the mesa (17); - in an area exposed by the at least one mask opening (402), remove part of the insulating layer (300) and the second parts of the source area (101) so that the remaining first part of the source area (101) forms a raised source bridge between the two adjacent trenches (14) in the mesa (17); - Deposition of an electrically conductive material to form a contact plug (111) extending at least from an upper surface of the insulating layer (300) along the vertical direction (Z) to contact the first part of the source region (101) on a side wall part thereof; such that - the trench electrode (141) of at least one of the two adjacent trenches (14) is separated from the insulating layer (300) along the vertical direction (Z) by an upper trench insulator (143); - the upper trench insulator (143) has a vertical extent that amounts to up to 90% of the vertical extent of the source area (101); and - one top side of the trench electrode (141) by a distance (T R ) is vertically recessed from the semiconductor body surface (110) of the mesa (17), so that the source region (101) is raised above the top of the trench electrode (141). [13] Method according to claim 12, wherein the formed source region (101) extends in the first lateral direction (X) along an entire upper width (WM) of the mesa (17). [14] Method according to claim 12 or 13, wherein the contact between the contact plug (111) and the first part of the source region (101) is established at an interface (1010) where the first part of the source region (101) forms an interface with one of the second parts of the source region (101) before the second parts of the source region (101) have been removed. [15] Method according to claim 14, wherein the interface (1010) is inclined with respect to the second lateral direction (Y). [16] Method according to any one of claims 12 to 15, wherein the at least one mask bridge (401) spans the entire mesa (17) along the first lateral direction (X) and / or has a total extent in the second lateral direction (Y) of not more than 500 nm. [17] Method according to any one of claims 12 to 16, wherein the formed contact plug (111) has a total lateral extent in the second lateral direction (Y) corresponding to the total lateral extent of the at least one mask opening (402) in the second lateral direction (Y). [18] Method according to any one of claims 12 to 17, wherein the formed contact plug (111) has a total lateral extent in the second lateral direction (Y) which is at least twice the upper width (WM) of the mesa (17), and / or wherein the formed contact plug (111) is in contact with both trench insulators (142) of the adjacent trenches (14) that laterally bound the mesa (17). [19] Method according to any one of claims 12 to 18, wherein the removal of part of the insulating layer (300) and the second parts of the source region (101) includes at least one selective etching processing step. [20] Method according to any one of the preceding claims 12 to 19, further comprising removing the mask (400) prior to depositing the electrically conductive material to form the contact plug (111). [21] Method according to any one of the preceding claims 12 to 20, further comprising, after removing the part of the insulating layer (300) and the second parts of the source region (101) in the area exposed by the at least one mask opening (402), forming a semiconductor body contact region (1022) with a higher dopant concentration in the remaining semiconductor body region (102). [22] Method according to any one of the preceding claims 12 to 21, wherein the at least one mask bridge (401) and the at least one mask opening (402) extend in the second lateral direction (Y) perpendicular to the trench length and optionally over several adjacent trenches (14).

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