Bonding structure and method for forming the same

Abstract

Device comprising: an interconnect structure (108) over a semiconductor substrate (102), the interconnect structure (108) comprising a plurality of first metal pads (112); a first dielectric layer (122) over the interconnect structure (108); a plurality of bond pad vias (128) within the first dielectric layer (122), each bond pad via of the plurality of bond pad vias (128) comprising: a first barrier layer (127) extending along sidewalls of the first dielectric layer (122) and extending in a region below one of the bond pad vias (128) over only a portion of a first metal pad of the plurality of first metal pads (112); and a first conductive material over the first barrier layer (127), wherein a top surface of the first conductive material and a top surface of the first barrier layer (127) are coplanar; a second dielectric layer (312) over the first dielectric layer (122); and a plurality of first bond pads (316) within the second dielectric layer (312), each first bond pad of the plurality of bond pads (316) comprising: a second barrier layer (315) extending along sidewalls of the second dielectric layer (312) and on the first conductive material and sidewalls of the first barrier layer (127) of a first bond pad via of the plurality of bond pad vias (128), wherein the second barrier layer (315) completely covers the upper surface of the first bond pad via (128), and a second conductive material over the second barrier layer (315).

Description

BACKGROUNDIn wafer-to-wafer bonding technology, various methods have been developed to interconnect two package components (such as wafers). Some wafer bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, and the like. In fusion bonding, an oxide surface of one wafer is bonded to an oxide surface or a silicon surface of another wafer. In the eutectic bonding, two eutectic materials are placed together, and a high pressure and a high temperature are applied. The eutectic materials are therefore melted. As the molten eutectic materials harden, the wafers bond. In direct metal-to-metal bonding, two metal pads are pressed together at elevated temperature and inter-diffusion of the metal pads causes bonding of the metal pads. In the hybrid bonding, the metal pads of two wafers are bonded to each other by direct metal-metal bonding, and an oxide surface of one of the two wafers is bonded to an oxide surface or a silicon surface of the other wafer.US 2010 / 0 123 199 A1 relates to a semiconductor component comprising a semiconductor substrate and a multilayer wiring structure. A three-dimensional stack structure is described in US 2018 / 0 012 868 A1. The stack structure includes at least a lower die, an upper die, and a spacer protection structure. The lower die includes contact pads in the non-bonding region. The upper die is placed on the lower die without covering the contact pads of the lower die. The lower die is connected to the upper die by bonding structures. The protective spacer structure is on the lower die and covers the upper die for protection.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1-9 illustrate cross-sectional views of intermediate stages in a process of forming a device structure, in accordance with some embodiments. FIGS. 10-17 illustrate cross-sectional views of intermediate stages in a process of forming a die structure, in accordance with some embodiments. FIGS. 18A, 18B, 19A, 19B, 20A, 20B, and 21 illustrate cross-sectional views of packages having die structures, in accordance with some embodiments. FIGS. 22-26 illustrate cross-sectional views of intermediate stages in a process of forming a package structure, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples which should not be understood as restrictive. For example, forming a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features need not be in direct contact. Further, this disclosure may repeat reference numerals and / or letters of the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations explained.Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of an element or feature to one or more other element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative terms used herein may also be appropriately construed.A bonding structure and method are provided in accordance with some embodiments. Bond pad vias (BPVs) are formed over metal pads in a series of processing steps, and then bond pads are formed over the BPVs in a subsequent series of processing steps. By forming the BPVs and bond pads separately, the metal pads to which the BPVs are connected may be formed more closely together and / or have a smaller area. Furthermore, the BPVs or bond pads may also be formed more closely together and / or with a smaller area. This may reduce the size of a die or package. The respective bond pads of two connected dies may be formed with different areas, such that misalignment between the two dies has little or no effect on contact resistance at the connection between the respective bond pads.FIGS. 1-9 illustrate the cross-sectional views of the intermediates in the formation of a device structure 100 (see FIG. 9 ) in accordance with some embodiments. FIG. 1 illustrates a substrate 102 in accordance with some embodiments. In FIGS. 1-9, in accordance with some embodiments, multiple device structures 100 are formed on a single substrate 102 and are then singulated to form individual device structures 100. The regions labeled "100" in FIGS. 1-8 indicate regions in which the device structures 100 of FIG. 9 are formed, and the region labeled "104" indicates a scribe line region 104 between adjacent device structures 100.The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or the like, which may be doped (e.g., with a p- or n-dopant) or undoped. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulating layer. The insulation layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually a silicon substrate or a glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.In some embodiments, the substrate 102 and features formed thereon are used to form a device die, an integrated circuit die, or the like. In such embodiments, integrated circuit devices may be formed on the top surface of the substrate 102. Example integrated circuit devices may include complementary metal oxide semiconductor (CMOS) transistors, fin field effect (FinFET) transistors, resistors, capacitors, diodes, the like, or a combination thereof. The details of the integrated circuit devices are not illustrated herein. In other embodiments, the substrate 102 is used to form an interposer structure. In such embodiments, no active devices such as transistors are formed on the substrate 102. Passive devices such as capacitors, resistors, inductors, or the like may be formed in the substrate 102. The substrate 102 may also be a dielectric substrate in which the substrate 102 is part of an interposer structure in some embodiments. In some embodiments, vias (not shown) may be formed that extend through the substrate 102 to connect components on the opposing sides of the substrate 102.In FIG. 2, an interconnect structure 108 is formed over the substrate 102. The interconnect structure 108 provides routing and electrical connections between devices formed in the substrate 102, and may be, for example, a redistribution structure or the like. The interconnect structure 108 may include a plurality of isolation layers 110, which may be inter-metal dielectric (IMD) layers, described in more detail below. Each of the isolation layers 110 includes one or more conductive features 113, which may be metal lines and / or vias formed therein in a metallization layer. In other embodiments, the metal lines may be redistribution layers, for example. The conductive features 113 may be electrically coupled to the active and / or passive devices of the substrate 102 through the contacts (not shown in the figures).Some portions of the conductive features 113 formed in the uppermost insulating layer 110 of the interconnect structure 108 may be formed with a relatively larger area than the other conductive features 113 within the interconnect structure 108. The conductive features of the interconnect structure 108 formed in the uppermost insulating layer 110 are separately referred to as metal pads 112 in FIG. 2. The metal pads 112 may be used as for connecting subsequently formed conductive features (e.g., conductive pads 118, bond pad vias (BPVs) 128, or the like) to the interconnect structure 108. In some embodiments, the conductive features of the uppermost insulating layer 110 may also include metal lines or vias, which are not separately shown in FIG. 2. The metal pads 112 may be formed with a width W 1 that is between about 2 μm and about 10 μm wide or has a range that is between about 4 μm 2 and about 100 μm 2 wide. Adjacent metal pads 112 may be separated by a distance D 1 that is between about 2 μm and about 20 μm. Other dimensions or distances are possible. In some cases, the techniques described herein may allow metal pads 112 to have a smaller width W 1 or area. In some cases, the techniques described herein may allow for the formation of metal pads 112 separated by a smaller distance D 1. By forming a smaller or narrower metal pad 112, the dimensions (e.g., the "footprint") of the device structure 100 may be reduced. Further, the routing distance between features may be reduced, which may improve a higher speed operation of the device structure 100.In some embodiments, the isolation layers 110 may be formed of a low-k material having a k value less than about 3.0. The isolation layers 110 may be formed of an extra-low-k (ELK) dielectric having a k value less than 2.5. In some embodiments, the isolation layers 110 may be formed of an oxygen-containing and / or carbon-containing low-k dielectric, hydrogen-silses-quinoxan (HSQ), methyl-silses-quinoxan (MSQ), the like, or a combination thereof. In some embodiments, some or all of the isolation layers 110 are formed of low-k dielectrics, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. In some embodiments, etch stop layers (not shown), which may be formed of silicon carbide, silicon nitride or the like, are formed between insulation layers 110. In some embodiments, the isolation layers 110 are formed of a porous material such as SiOCN, SiCN, SiOC, SiOCH, or the like, and may be formed by spin-on coating or a deposition process such as plasma enhanced vapor deposition (PECVD), CVD, PVD, or the like. In some embodiments, the interconnect structure 108 may include one or more types of layers, such as diffusion barrier layers (not shown).In some embodiments, the interconnect structure 108 may be formed using a single and / or dual damascene process, a via-first process, or a metal-first process. In one embodiment, an isolation layer 110 is formed and openings (not shown) are formed therein using acceptable photolithography and etching techniques. Diffusion barrier layers (not shown) may be formed in the openings and may include a material such as TaN, Ta, TiN, Ti, CoW, or the like, and may be formed in the openings using a deposition process such as CVD, atomic layer deposition (ALD), or the like. A conductive material may be formed in the openings of copper, aluminum, nickel, tungsten, cobalt, silver, combinations thereof, or the like, and may be formed over the diffusion barrier layers in the openings using an electrochemical plating process, CVD, ALD, PVD, the like, or a combination thereof. After forming the conductive material, excess conductive material may be removed using, for example, a planarization process such as CMP, such that conductive features 113 remain in the openings of the respective isolation layer 110. The process may then be repeated to form further isolation layers 110 and conductive features 113 therein. In some embodiments, the top isolation layer 110 and the metal pads 112 formed therein may be formed with a thickness greater than a thickness of the other isolation layers 110 of the interconnect structure 108. In some embodiments, one or more of the uppermost conductive features are dummy metal lines or dummy metal pads 112 electrically isolated from the substrate 102.In FIG. 3, a passivation layer 114 is formed over the interconnect structure 108, and one or more openings are formed in the passivation layer 114. The passivation layer 114 may include one or more layers of one or more materials. For example, the passivation layer 114 may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination. The passivation layer 114 may be formed by a suitable process, such as by CVD, PECVD, PVD, ALD, the like, or a combination thereof. In some embodiments, the passivation layer 114 may be formed with a thickness greater than a thickness of the top isolation layer 110. The openings in the passivation layer 114 may be formed using a suitable photolithographic and etching process. For example, a photoresist may be formed and patterned over the passivation layer 114 and then the patterned photoresist may be used as an etch mask. The passivation layer 114 may be etched using a wet etching process and / or a dry etching process. The openings are formed to expose portions of the metal pads 112 for electrical connection.In FIG. 4, conductive pads 118 are formed over the passivation layer 114 in accordance with some embodiments. One or more conductive pads 118 may be formed to extend through the openings in the passivation layer 114 to electrically connect to one or more of the metal pads 112 of the interconnect structure 108. In some embodiments, the conductive pads 118 may be formed by first depositing a capping layer of a conductive material such as aluminum. For example, CVD, PVD, or the like may be used to deposit a layer of aluminum over the passivation layer 114, the openings, and the metal pads 112. A photoresist layer (not separately illustrated) may then be formed over the aluminum layer and the aluminum layer may be etched to form the conductive pads 118. Conductive pads 118 formed of aluminum in this manner may be referred to as "aluminum pads.".In other embodiments, the conductive pads 118 are formed by first forming a seed layer over the passivation layer 114 and the openings. In some embodiments, the seed layer is a metal layer comprising one or more layers that may be formed from different materials. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer, and conductive material is formed in the openings of the photoresist and at the exposed portions of the seed layer. In some embodiments, the conductive material may be formed by a plating process, such as using an electroplating or electroless plating process or the like. The conductive material may include one or more materials, such as copper, titanium, tungsten, gold, cobalt, the like, or a combination thereof. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed using, for example, a suitable ash or stripping process, such as by using an oxygen plasma or the like. When the photoresist is removed, remaining exposed portions of the seed layer may be removed, such as by using an acceptable etching process, such as a wet etching process or a dry etching process. The remaining portions of the seed layer and the conductive material form the conductive pads 118. The conductive pads 118 may be formed using other techniques in other embodiments, and all of these techniques are considered to be within the scope of this disclosure.In some embodiments, the conductive pads 118 electrically connected to the interconnect structure 108 may be used as test pads before further processing steps are performed. For example, the conductive pads 118 may be probed as part of a wafer acceptance test, a circuit test, a known good die (KGD) test, or the like. The probing may be done to verify the function of the active or passive devices of the 102 or the respective electrical connections within the substrate 102 or the interconnect structure 108 (e.g., the conductive features 113). Probing may be accomplished by contacting a probe needle 119 to the conductive pads 118. The probe needle 119 may be part of a probe card that includes a plurality of probe needles 119, which may be connected to test equipment, for example.In some embodiments, the conductive material of the conductive pads 118 may be different from the conductive material of the metal pads 112. For example, the conductive pads 118 may be aluminum and the metal pads 112 may be copper, but other conductive materials may also be used. In some embodiments, the conductive pads 118 may have a width W 2 of between about 2 μm and about 30 μm or a length (e.g., perpendicular to the width) of between about 20 μm and about 100 μm. In some embodiments, the conductive pads 118 may be separated from an adjacent metal pad 112 by a distance D 2 that is between about 2 μm and about 30 μm. The embodiments described in this disclosure may allow a smaller separation distance between conductive pads 118 and adjacent metal pads 112 without increasing the possibility of causing processing deficiencies such as shorts. In this way, the dimensions of the device structure 100 may be reduced without reducing yield.Referring to FIG. 5, a dielectric layer 122 is formed over the passivation layer 114 and the conductive pads 118. The dielectric layer 122 may be formed of one or more layers of one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, SiOC, SiOCH, SiCH, the like, or a combination thereof. In some embodiments, the dielectric layer 122 may be formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), fluorine doped silicate glass (FSG), tetraethylorthosilicate (TEOS), the like, or a combination thereof. The dielectric layer 122 may be formed by a deposition process, such as by CVD, PECVD, PVD, ALD, the like, or a combination thereof. The dielectric layer 122 may be formed with a greater thickness than the conductive pads 118 such that the material of the dielectric layer 122 laterally surrounds the conductive pads 118 and such that the dielectric layer 122 may be planarized (see below) without exposing the conductive pads 118.In FIG. 6, openings 124 are formed in the dielectric layer 122, in accordance with some embodiments. The openings 124 expose the metal pads 112 to allow subsequently formed bond pad vias (BPVs) 128 to electrically connect to the interconnect structure 108 through the metal pads 112. In some embodiments, the openings 124 expose the conductive pads 118, and the BPVs 128 electrically connect to the interconnect structure 108 through the conductive pads 118 (see, e.g., FIGS. 20A-21 ). The openings 124 may be formed using acceptable photolithography and etching techniques. For example, the photolithography process may include forming a photoresist (not shown) over the dielectric layer 122, patterning the photoresist with openings corresponding to the openings 124, extending the openings 124 through the dielectric layer 122 and the passivation layer 114 to expose the metal pads 112, and then removing the photoresist.Referring to FIG. 7, in some embodiments, bond pad vias (BPVs) 128 are formed in the openings 124. The BPVs 128 may have similar dimensions as the openings 124 in which they are formed and may have a similar shape (e.g., have a tapered profile). In some embodiments, forming the BPVs 128 first includes forming a first barrier layer 127 within the openings 124. The first barrier layer 127 may be, for example, a liner, a diffusion barrier layer, an adhesive layer, or the like. The first barrier layer 127 may include one or more layers including titanium, titanium nitride, tantalum, tantalum nitride, the like, or combinations thereof. The first barrier layer 127 may be deposited as a capping layer over the dielectric layer 122 and within the openings 124. The first barrier layer 127 may be formed by a deposition process, such as by PECVD, PVD, the like, or combinations thereof.The formation of the BPVs 128 may include depositing a conductive material over the first barrier layer 127. The conductive material may include cobalt, copper, a copper alloy, titanium, silver, gold, tungsten, aluminum, nickel, the like, or combinations thereof. The conductive material of the BPVs 128 may be formed by a deposition process, such as by PECVD, PVD, the like, or combinations thereof. In some embodiments, the conductive material of the BPVs 128 is formed by depositing a seed layer (not shown) over the first barrier layer 127, which may comprise copper, a copper alloy, titanium, or the like, and then filling the remaining openings 124, for example, using an electroless plating process or the like.After forming the conductive material, a planarization process, such as a grinding process, a chemical mechanical polishing (CMP) process, or the like, may be performed to remove excess material from a surface of the dielectric layer 122. The remaining first barrier layer 127 and the conductive material thus form the BPVs 128. In this manner, the BPVs 128 may be formed using a single damascene process. In some embodiments, some "dummy" BPVs 128 (not shown) may be formed without having an electrical connection to the metal pads 112. In some cases, dummy BPVs 128 may reduce unequal stress and improve surface planarity after the planarization step that removes excess material.The BPVs 128 may have a width W 3 of between about 1 μm and about 5 μm, although other widths are possible. In some embodiments, the BPVs 128 may have a tapered profile, such as an upper width W 3A that is between about 1 μm and about 5 μm and a lower width W 3B that is between about 0.5 and about 4 μm. The width W 3 of a BPV 128 may be between about 50% and about 95% of the width W 1 of its associated metal pad 112 (see FIG. 2 ). The BPVs 128 may be formed such that the lateral distance D 3 between a sidewall of a BPV 128 and the adjacent sidewall of its associated metal pad 112 is between about 1 μm and about 5 μm, but other distances are also possible. In some cases, by forming the BPVs 128 separate from the bond pads 316 (see FIG. 17 below), the metal pads 112 may be formed with a smaller width W 1 that is closer in size to the width W 3 of the BPVs 128. This may allow for the reduction of lateral separation between features such as conductive pads 118, metal pads 112, BPVs 128, and / or bond pads 316 (see FIG. 17 ). Further, the distance D 3 may be decreased so that the BPVs 128 may be formed closer to the edges of the metal pads 112.Referring to FIG. 8, a bonding layer 126 is formed over the dielectric layer 122. The interconnect layer 126 may be formed of one or more layers of one or more dielectrics and may include a silicon-containing material, such as silicon oxide. In some embodiments, the interconnect layer 126 may include one or more layers of other materials, such as silicon nitride, silicon oxynitride, silicon carbonitride, SiOC, SiOCH, SiCH, the like, or a combination thereof. The interconnect layer 126 may be formed by a deposition process, such as by CVD, PECVD, PVD, ALD, the like, or a combination thereof. In some embodiments, the interconnect layer 126 comprises a different material than the dielectric layer 122.In FIG. 9, a dicing process is performed along scribe line regions 104 to separate adjacent device structures 100. The dicing process may include a dicing process, a sawing process, a laser process, the like, or a combination thereof. In some embodiments, singulated device structures 100 that were probed and located as a known good die (KGD) as described above in FIG. 4 are used in subsequent process steps to form die structures 300 (see FIG. 15 ).FIGS. 10-17 illustrate the cross-sectional views of the intermediates in the formation of a die structure 300 (see FIG. 17 ) incorporating the device structure 100, in accordance with some embodiments. In FIG. 10, the device structure 100 is connected to a carrier 202, according to some embodiments. The carrier 202 may be a silicon substrate (e.g., a silicon wafer), a glass substrate, an organic substrate (e.g., a panel), or the like. In some embodiments, one or more layers, such as oxide layers or etch stop layers, may be formed on the carrier 202, which may be seen as layers 204 in FIGS. 10-13. In some embodiments, a dielectric layer 208 is formed on the carrier 202, and optionally, alignment features 210 may be formed within the dielectric layer 208. In some embodiments, the dielectric layer 208 may be formed of silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, the like, or a combination thereof. The dielectric layer 208 may be formed by a deposition process, such as by CVD, PECVD, PVD, the like, or a combination thereof. In some embodiments, the dielectric layer 208 is formed of a material other than the subsequently formed interconnect layer 212 and may serve as a buffer layer for absorbing stress. According to some embodiments, the alignment features 210 are metal features formed in the dielectric layer 208. The alignment features 210 may be used as alignment marks for aligning the subsequent placement (e.g., using a pick-and-place method) and the bonding of the device structure 100. The alignment features 210 may be formed using a damascene process or another suitable process, for example.A connection layer 212 may then be formed over the dielectric layer 208. The interconnect layer 212 may be formed of one or more layers of one or more dielectrics such as silicon oxide or the like. The interconnect layer 212 may be formed by a deposition process, such as by CVD, PECVD, PVD, ALD, the like, or a combination thereof. The bonding layer 212 may include the same material as the bonding layer 126, or a different material than the bonding layer 126. The combination of the carrier 202, the dielectric layer 208, and the interconnect layer 212 is referred to herein as the first support structure 250.Still referring to FIG. 10, the device structure 100 is placed on the first support structure 250, such as using a pick-and-place process. The alignment features 210 may be used during placement to align the device structure 100. The device structure 100 is placed such that the connection layer 126 and the connection layer 212 are in contact. A plasma cleaning process or a wet chemical cleaning process may be performed prior to placement on the bonding layer 126 or the bonding layer 212 to activate the surfaces. After placement, the interconnect layer 126 of the device structure 100 is connected to the interconnect layer 212 via direct bonding (e.g., "fusion bonding" or "dielectric-dielectric bonding"), which may form, for example, Si-O-Si bonds between the interconnect layer 126 and the interconnect layer 212. In some embodiments, the bonding layer 126 and the bonding layer 212 may be pressed together to simplify the bonding process. The bonding process may be performed at room temperature (e.g., at a temperature of about 21° C. to about 25° C.), but higher temperatures may be used. In some embodiments, post-bonding anneal is performed, which may strengthen the bond between the bond layer 126 and the bond layer 212.Referring to FIG. 11, dielectric regions 214 (otherwise referred to as "gap filler dielectric" regions) are formed around the device structure 100, in accordance with some embodiments. In some embodiments, the dielectric regions 214 may be formed from one or more layers of silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, the like, or a combination thereof. The dielectric of the dielectric regions 214 may be formed by a deposition process, such as by PECVD, PVD, the like, or a combination thereof. In some embodiments, the dielectric may be formed by dispensing a flowable dielectric (e.g., a flowable oxide) and then curing the flowable dielectric. The flowable dielectric may be dispensed using a lamination process, a spin coating process, or the like. After forming the dielectric, a planarization process (e.g., a CMP or grinding process) may be performed to remove excess dielectric from over the substrate 102 of the device structure 100 and form dielectric regions 214. After performing the planarization process, the dielectric regions 214 and the substrate 102 may have planar (e.g., coplanar) surfaces. In some embodiments, the planarization process also thins out the substrate 102.Referring to FIG. 12, a dielectric layer 220 is formed on the dielectric regions 214 and the substrate 102. In some embodiments, optional alignment features 222 are formed within the dielectric layer 220. In some embodiments, the dielectric layer 220 may be formed of silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, the like, or a combination thereof. The dielectric layer 220 may be formed by a deposition process, such as by CVD, PECVD, PVD, the like, or a combination thereof. In some embodiments, the dielectric layer 220 is formed of a material other than the subsequently formed interconnect layer 224 and may serve as a buffer layer for absorbing stress. According to some embodiments, the alignment features 222 are metal features formed in the dielectric layer 220. The alignment features 222 may be formed using a damascene process or another suitable process, for example.A connection layer 224 may then be formed over the dielectric layer 220. The interconnect layer 224 may be formed of one or more layers of one or more dielectrics such as silicon oxide or the like. The bonding layer 224 may be formed from similar materials or using similar techniques as described above for the bonding layer 126.Referring to FIG. 13, in some embodiments, the structure is inverted and connected to a second support structure 350, and then the first support structure 250 is removed. The second support structure 350 may include, for example, a bonding layer 306 formed over a carrier 302. The carrier 302 may be a silicon substrate (e.g., a silicon wafer), a glass substrate, an organic substrate (e.g., a panel), or the like. The interconnect layer 306 may be formed from one or more layers of one or more dielectrics, and may include a silicon-containing material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, SiOC, SiOCH, SiCH, the like, or a combination thereof. The interconnect layer 306 may be formed by a deposition process, such as by CVD, PECVD, PVD, ALD, the like, or a combination thereof. The bonding layer 306 may comprise the same material as the bonding layer 224, or a different material than the bonding layer 224.Still referring to FIG. 13, the structure is reversed and the bonding layer 224 is placed on the bonding layer 306 of the second support structure 350, in accordance with some embodiments. A plasma cleaning process or a wet chemical cleaning process may be performed prior to placement on the bonding layer 224 or the bonding layer 306 to activate the surfaces. After placement, the interconnect layer 224 is coupled to the interconnect layer 306 via direct bonding (e.g., "fusion bonding" or "dielectric-dielectric bonding"), which may form, for example, Si-O-Si bonds between the interconnect layer 224 and the interconnect layer 306. In some embodiments, the bonding layer 224 and the bonding layer 306 may be pressed together to simplify the bonding process. The bonding process may be performed at room temperature (e.g., at a temperature of about 21° C. to about 25° C.), but higher temperatures may be used. In some embodiments, post-bonding anneal is performed, which may strengthen the connection between the interconnect layer 224 and the interconnect layer 306.In FIG. 14, in accordance with some embodiments, the first support structure 250 and the bonding layer 126 are removed. In some embodiments, a planarization process (e.g., a CMP or grinding process) may be performed to remove the carrier 202, the dielectric layer 208, the interconnect layer 212, and the interconnect layer 126. As shown in FIG. 14, the planarization process may expose the BPVs 128 and the dielectric layer 122. Portions of the dielectric layers 214 are also removed by the planarization process such that the surfaces of the remaining dielectric regions 214 are planar with the dielectric layer 122 and the BPVs 128. In some embodiments, one or more etching processes (e.g., dry etching processes or wet etching processes) may be used to remove portions of the first support structure 250 prior to performing the planarization process. In some embodiments, an etching process may be stopped by a layer such as the interconnect layer 212, the dielectric layer 208, or an etch stop layer within the carrier 202 (if present).Referring to FIG. 15, a bonding layer 312 is formed over the dielectric regions 214, the dielectric layer 122, and the BPVs 128. The bonding layer 312 may be formed of one or more layers of one or more dielectrics such as silicon oxide or the like. The bonding layer 312 may be formed from similar materials or using similar techniques as described above for the bonding layer 126 or the bonding layer 224. In some embodiments, the bonding layer 312 is formed to a thickness between about 0.2 nm and about 1 nm. The thickness of the bonding layer 312 may determine the thickness of the subsequently formed bonding pads 316 (see FIG. 17 ).In FIG. 16, openings 314 are formed in the bonding layer 312, in accordance with some embodiments. The openings 314 expose the BPVs 128 to allow subsequently formed bond pads 316 to electrically connect to the interconnect structure 108 through the BPVs 128. The openings 314 may be formed using acceptable photolithography and etching techniques. For example, the photolithography process may include forming a photoresist (not shown) over the interconnect layer 312, patterning the photoresist with openings corresponding to the openings 314, extending the openings 314 through the interconnect layer 312 to expose the BPVs 128, and then removing the photoresist.Referring to FIG. 17, in some embodiments, bond pads 316 are formed in the openings 314 to form a die structure 300. In some embodiments, forming bond pads 316 includes first forming a second barrier layer 315 within openings 314. The second barrier layer 315 may be, for example, a liner, a diffusion barrier layer, an adhesion layer, or the like. The second barrier layer 315 may include one or more layers including titanium, titanium nitride, tantalum, tantalum nitride, the like, or combinations thereof. The second barrier layer 315 may be deposited as a capping layer over the interconnect layer 312 and within the openings 314. The second barrier layer 315 may be formed by a deposition process, such as by PECVD, PVD, the like, or combinations thereof. The second barrier layer 315 may be formed of a similar material to that of the first barrier layer 127 in some embodiments. As shown in FIG. 17, because the BPVs 128 are formed in a separate process step prior to the formation of the bond pads 316, each second barrier layer 315 extends over the top surface of a BPV 218, which may include extending over the top surfaces of the first barrier layer 127. In this manner, the first barrier layer 127 of a BPV 128 and the second barrier layer 315 of a bond pad 316 are formed separately, rather than the BPVs 128 and bond pads 316 sharing a single continuous barrier layer formed in a single step.The formation of bond pads 316 may include depositing a conductive material over second barrier layer 315. The conductive material may include, for example, copper or a copper alloy. The conductive material may include other materials, such as titanium, silver, gold, tungsten, aluminum, nickel, cobalt the like, or combinations thereof. The conductive material of bond pads 316 may be formed by a deposition process, such as by PECVD, PVD, the like, or combinations thereof. In some embodiments, the conductive material of bond pads 316 is formed by depositing a seed layer (not shown) over second barrier layer 315, which may comprise copper, a copper alloy, titanium, or the like, and then filling remaining openings 314 using, for example, an electroless plating process or the like. The bond pads 316 may be formed of a similar material to that of the BPVs 128, in some embodiments.After forming the conductive material, a planarization process, such as a grinding process, a chemical mechanical polishing (CMP) process, or the like, may be performed to remove excess material from a surface of the bonding layer 312. The remaining second barrier layer 315 and the conductive material thus form the bond pads 316. In this manner, bond pads 316 may be formed using a single damascene process. In some embodiments, some "dummy" bond pads 316 (not shown) may be formed without having an electrical connection to the BPVs 128 and / or the metal pads 112. In some cases, dummy bond pads 316 may reduce unequal stress and improve surface planarity after the planarization step that removes excess material.In some embodiments, bond pads 316 may have a width W 4 of between about 0.2 μm and about 5 μm, but other widths are also possible. In some embodiments, the width W 4 of a bond pad 316 may be between about 120% and about 200% of the width W3 of its associated BPV 128 (see FIG. 7 ). In some embodiments, bond pads 316 may be formed such that the lateral distance D 4 between a sidewall of a bond pad 316 and the adjacent sidewall of its associated BPV 128 is between about 0.5 μm and about 2 μm, but other distances are possible. In some embodiments, the lateral separation between adjacent bond pads 316 may have a distance D 5 that is between about 2 μm and about 7 μm. In some cases, the bond pads 316 may be formed by forming the BPVs 128 separate from the bond pads 316 as described herein with a smaller separation distance D 5. In some cases, by forming the BPVs 128 in a separate process step from the bond pads 316, lateral separation (e.g., distance) between features such as conductive pads 118, metal pads 112, BPVs 128, and / or bond pads 316, and the sizes of such features, may be reduced without risking electrical shorts or other process deficiencies.Referring to FIGS. 18A to B, a package 500 including the first die structure 300 and a second die structure 400 connected to each other is illustrated in accordance with some embodiments. FIG. 18B shows a package 500 similar to that of FIG. 18A, however, for illustrative purposes, some features are shown in FIG. 18B with a stronger alignment pitch than in FIG. 18A. The first die structure 300 of the package 500 may be similar to the die structure 300 described for FIG. 17. In some embodiments, the second die structure 400 includes dielectric regions 402 (otherwise known as "gap filler dielectric" regions), a device structure 440, a bonding layer 412, and one or more bond pads 410. The second die structure 400 of FIGS. 18A-B is an example, and the second die structure 400, or components thereof (e.g., the device structure 440), may have other structures or other types of structures than illustrated without departing from the scope of this disclosure.The device structure 440 may be similar to that described above for device structure 100. For example, the device structure 440 may include a substrate 442 similar to the substrate 102, which may include integrated circuit devices formed thereon. In some embodiments, through substrate vias (TSVs) 446 may extend through the substrate 442. The TSVs 446 may be formed, for example, by forming openings that extend through the substrate 442 with a suitable photolithography and etching process. The openings may then be filled with a conductive material, such as copper or the like, which may be formed using a suitable process, such as a plating process. In some embodiments, the device structure 440 includes metal pads 444 or conductive pads 450, which may be similar to the metal pads 112 and the conductive pads 118 of the device structure 100, respectively.The dielectric regions 402 may be similar to the dielectric regions 214 described above, such as by being formed of silicon oxide or the like. The bonding layer 412 may be formed of one or more layers of one or more dielectrics such as silicon oxide or the like. The bonding layer 412 may be formed from similar materials or using similar techniques as described above for the bonding layer 126, bonding layer 224, or bonding layer 312. The bond pads 410 may be formed of a conductive material such as copper, a copper alloy, or the like. Bond pads 410 may also include a barrier layer (not shown). Bond pads 410 may be formed from one or more similar materials or using similar techniques, in some embodiments, as described above for bond pads 316.In some embodiments, bond pads 410 may have a width W 5 of between about 1 μm and about 5 μm, but other widths are also possible. In some embodiments, the width W 5 of a bond pad 410 may be between about 95% and about 150% of the width W 4 of its associated bond pad 316. In this way, the width W 5 of the bond pads 410 may be greater than the width W 4 of the bond pads 316. After bonding bond pads 410 to bond pads 316, bond pads 410 may extend laterally beyond bond pads 316, as shown in FIG. 18. FIG. 18A shows bond pads 410 approximately centered on bond pads 316, but in other cases there may be some lateral displacement between bond pad 410 and bond pad 316. A shift may be, for example, a pick-and-place overlay shift during placement of the second die structure 400 on the first die structure 300. For example, in FIG. 18B, a bond pad 410 is shown displaced a distance S 1 from a bond pad 316. The distance S 1 corresponds to the lateral distance between the center of the bond pad 410 (e.g., at half the width W 5) and the center of the bond pad 316 (e.g., at half the width W 4). In some cases, forming bond pads 410 that are wider than bond pads 316 may increase the possibility that the entirety of the top surfaces of bond pads 316 may be connected to bond pads 410 when there is a shift between first die structure 300 and second die structure 400. In some cases, the maximum displacement distance (e.g., S 1) for which the entire surface of a bond pad 316 remains connected remains indicated by the difference between the width W 5 of the bond pad 410 and the width W 4 of the bond pad 316. Connecting the entire top surfaces of bond pads 316 may reduce contact resistance between bond pads 316 and bond pads 410 and thus improve electrical performance of package 500. In this way, undesired effects due to the displacement may be reduced by forming bond pads 410 having a width greater than that of the bond pads 316.Other displacements are possible. For example, FIG. 18A shows bond pads 316 approximately centered on BPVs 128, but in other cases there may be some lateral displacement between a bond pad 316 and a BPV 128. For example, in FIG. 18B, a bond pad 316 is shown displaced a distance S2from a BPV 128. The distance S 2 corresponds to the lateral distance between the center of the bond pad 316 (e.g., at half the width W 4) and the center of the BPV 128 (e.g., at half the width W 3). In some cases, forming bond pads 316 that are wider than BPVs 128 may increase the possibility that the entirety of the top surfaces of the BPVs 128 are covered by the overlying bond pads 316 when there is a displacement between the bond pads 316 and the BPVs 128. In some cases, the maximum displacement distance (e.g., S 2) for which the entire top surface of a BPV 128 remains covered by an overlying bond pad 316 remains indicated by the difference between the width W 4 of the bond pad 316 and the width W 3 of the BPV 128. Covering the entire top surfaces of the BPVs 128 may reduce contact resistance between the bond pads 316 and the BPVs 128, thereby improving the electrical performance of the package 500. In this way, undesired effects due to the shift may be reduced by forming bond pads 316 having a width greater than that of the BPVs 128.The second die structure 400 may also include a redistribution structure 452 including dielectric layers 460 and 462 and metallization structures 454 and 456. Redistribution structure 452 may be designed to connect the various features, such as device structure 440 and vias 408 (described below) to form functional circuitry. The metallization structures may also be referred to as redistribution layers or redistribution lines. More or fewer dielectric layers and metallization structures than illustrated may be formed in redistribution structure 452. If fewer dielectric layers and metallization structures are to be formed, steps and the process may be repeated as explained below. If more dielectric layers and metallization structures are to be formed, the steps and process may be repeated as explained below.As an example of forming redistribution structure 452, metallization structure 454 may be formed first. To form metallization pattern 454, a seed layer is formed over device pattern 400 and dielectric regions 402. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to metallization pattern 454. The patterning forms openings through the photoresist for exposing the seed layer. A conductive material is then formed in the openings of the photoresist and at the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying portions of the seed layer form metallization pattern 454. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ash or stripping process, such as by using oxygen plasma or the like. When the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.The dielectric layer 460 is then deposited on the metallization pattern 454, the device 440, and the dielectric layers 402. In some embodiments, the dielectric layer 460 is formed of a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer 460 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 460 is then patterned. The patterning forms openings that expose portions of metallization pattern 454. The patterning may be performed by an acceptable process, such as by exposing the dielectric layer 124 when the dielectric layer 460 is a photosensitive material, or by etching, for example using anisotropic etching. When the dielectric layer 460 is a photosensitive material, the dielectric layer 460 may be developed after exposure.Metallization pattern 456 is then formed on patterned dielectric layer 460 and extends into the openings in dielectric layer 460 to contact metallization pattern 454. Metallization pattern 456 may be formed in a manner similar to metallization pattern 454 and may be formed of a similar material as metallization pattern 454. The dielectric layer 462 may be formed on the metallization pattern 456 and the dielectric layer 460. The dielectric layer 462 may be formed in a manner similar to the dielectric layer 460 and may be formed of a similar material as the dielectric layer 460. Redistribution structure 452 may be formed using materials or techniques other than those described in this example.In some embodiments, the second die structure 400 includes one or more vias 408 that extend partially or completely through the second die structure 400 to connect to the redistribution structure 452 or other features on opposite sides of the second die structure 400. A second die structure 400 may include zero, one, two, or more than two vias 408 in some embodiments. The second die structure 400 of FIG. 18 also includes under bump metallizations (UBMs) 418, and external connectors 420 formed on the redistribution structure 452, in accordance with some embodiments. The UBMs 418 provide an electrical connection with conductive features within the second die structure 400, and the external connectors 420 (e.g., solder balls, bumps, or the like) are formed on the UBMs 418. In some embodiments, the UBMs 418 are not formed before forming the external connectors 420, and in some embodiments, the external connectors 420 are not formed on the second die structure 400.The illustrated second die structure 400 is an illustrative example, and it will be appreciated that any suitable dies, chips, devices, or the like are contemplated within the scope of this disclosure. In some embodiments, the second die structure 400 may be formed in a manner similar to the first die structure 300. For example, the second die structure 400 may include BPVs (not individually labeled) formed in a first process step, and the bond pads 410 may be formed over the BPVs in a separate process step, as described above for FIGS. 7 and 17.In some embodiments, the second die structure 400 is connected to the first die structure 300 using, e.g., direct bonding or hybrid bonding to form package 500. Before performing the bonding, a surface treatment may be performed on the second die 400 or the first die 300 to activate the surfaces. In some embodiments, the surface treatment includes a plasma treatment. The plasma treatment may be performed in a vacuum environment (e.g., a vacuum chamber, not shown). The process gas used for generating a plasma may be a hydrogen-containing gas including a first gas including hydrogen (H 2) and argon (Ar), a second gas including H 2 and nitrogen (N 2) or a third gas including H 2 and helium (He). The plasma treatment may also be performed using pure or substantially pure H 2, Ar, or N 2 as the process gas that treats the surfaces of the bond pads 316 / 410 and the bond layers 312 / 412. The second die structure 400 or the first die structure 300 may be treated with the same surface treatment process, or with other surface treatment processes, or may remain untreated. In some embodiments, the second die structure 400 or the first die structure 300 may be cleaned after the surface treatment. Cleaning may include, for example, performing chemical cleaning and cleaning / rinsing with deionized water.Next, a pre-bonding process may be performed with the second die structure 400 and the first die structure 300. The second die structure 400 is placed on the first die structure 300, such as using a pick-and-place process. The alignment features 222 may be used during placement to align the second die structure 400. The second die structure 400 and the first die structure 300 are aligned such that the bond pads 410 and / or the vias 408 of the second die structure 400 are aligned with the bond pads 316 of the first die structure 300. After the alignment, the second die structure 400 and the first die structure 300 may be pressed against each other. The compressive force may be less than about 5 newtons per die in some embodiments, however, a greater or lesser force may be used. The pre-bonding process may be performed at room temperature (e.g., at a temperature of about 21° C. to about 25° C.), but higher temperatures may be used. The pre-bond time may be less than about 1 minute in some embodiments.After the pre-bonding, the bonding layer 412 of the second die structure 400 and the bonding layer 312 of the first die structure 300 are bonded together to form package 500. The connection between the bonding layers 312 / 412 may be strengthened in a subsequent annealing step. The package 500 may be annealed at a temperature of about 300° C. to about 400° C. and for a period of between about 1 hour and about 2 hours. During the anneal, metals in bond pads 316 and 410 may diffuse, thus also forming metal-to-metal interconnects. Connections between bond pads 316 and corresponding vias 408 may be similarly formed. Therefore, the resulting connections between the first die structure 300 and the second die structure 400 may be hybrid connections. In some embodiments, after the anneal, there is no material interface between the bond pads 316 and the corresponding bond pads 410 or vias 408. In some embodiments, post-bond singulation onto the package may be performed 500.FIG. 18A shows via 408 approximately centered on bond pad 316, but in other cases there may be some lateral displacement between via 408 and bond pad 316. For example, in FIG. 18B, a via 408 is shown displaced a distance S 3 from a bond pad 316. The distance S 3 corresponds to the lateral distance between the center of the via 408 and the center of the bond pad 316 (e.g., at half the width W 4). In some cases, forming bond pads 316 that are wider than vias 408 may increase the possibility that the entirety of the surfaces of vias 408 may be connected to corresponding bond pads 316 when there is a shift between bond pads 316 and vias 408. In some cases, the maximum displacement distance (e.g., S 3) for which the entire area of a via 408 remains connected to a corresponding bond pad 316 remains indicated by the difference between the width W 4 of the bond pad 316 and the width of the via 408.FIGS. 19A-B, 20A-B, and 21 illustrate packages 510, 520, and 530, each including a first die structure 300 connected to a second die structure 400, in accordance with some embodiments. For each of the packages 510, 520, and 530, the first die structure 300 and the second die structure 400 may be similar to the first die structure 300 and the second die structure 400 as described for FIGS. 18A-B, and the first die and the second die may be connected in a similar manner as described for FIGS. 18A-B. All such variations of forming packages are contemplated within the scope of this disclosure.First, with reference to FIG. 19A, package 510 is similar to package 500 of FIG. 18A, except that bond pads 410 of second die structure 400 have a width W 6 that is less than width W 4 (see FIG. 17 ) of bond pads 316 of first die structure 300. FIG. 19B shows a package 510 similar to that of FIG. 19A, however, for illustrative purposes, some features are shown in FIG. 19B with a stronger alignment pitch than in FIG. 19A. In some embodiments, bond pads 410 may have a width W 6 of between about 1.5 μm and about 5 μm, but other widths are also possible. In some embodiments, the width W 6 of a bond pad 410 may be between about 40% and about 90% of the width W 4 of its associated bond pad 316. In this way, the width W 6 of the bond pads 410 may be less than the width W 4 of the bond pads 316. After bonding bond pads 410 to bond pads 316, bond pads 316 may extend laterally beyond bond pads 410 as shown in FIG. 19A.FIG. 19A shows a bond pad 410 approximately centered on a bond pad 316, but in other cases there may be some lateral displacement between a bond pad 410 and a bond pad 316. For example, in FIG. 19B, a bond pad 410 is shown displaced a distance S 4 from a bond pad 316. The distance S 4 corresponds to the lateral distance between the center of the bond pad 410 (e.g., at half the width W 6) and the center of the bond pad 316 (e.g., at half the width W 4). In some cases, forming bond pads 410 that are less wide than bond pads 316 may increase the possibility that the entirety of the top surfaces of the bond pads 410 may be connected to the bond pads 316 when there is a shift between the first die structure 300 and the second die structure 400. In some cases, the maximum displacement distance (e.g., S 4) for which the entire surface of a bond pad 410 remains connected remains indicated by the difference between the width W 6 of the bond pad 410 and the width W 4 of the bond pad 316. Connecting the entire bond areas of the bond pads 410 may reduce the contact resistance between the bond pads 316 and the bond pads 410 and thus improve the electrical performance of the package 510. In this way, undesired effects due to the shift may be reduced by forming bond pads 410 having a width narrower than that of the bond pads 316.Turning now to FIGS. 20A-B and 21, the packages 520 and 530 are similar to the package 500 of FIGS. 18A-B, except that the BPVs 128 contact the conductive pads 118 and electrically connect to the interconnect structure 108 through the conductive pads 118. FIGS. A-B show a package 520 in which the bond pads 410 of the second die structure 400 have a width that is greater than the bond pads 316 of the first die structure 300, similar to package 500 of FIGS. 18A-18B. FIG. 20B shows a package 520 similar to that of FIG. 20A, however, for illustrative purposes, some features are shown in FIG. 20B with a stronger alignment pitch than in FIG. 20A. FIG. 21 shows a package 530 in which the bond pads 410 of the second die structure 400 have a width that is less than the bond pads 316 of the first die structure 300, similar to the package 510 of FIG. 19, A shift similar to that described for FIGS. 18A to B, 19A to B, and 20A may also be present for the package 530 described for FIG. 21, but is not shown in a separate figure.The conductive pads 118 that contact the BPVs 128 may be formed in a similar manner as the conductive pad 118 illustrated above for FIGS. 3-4. For example, the passivation layer 114 may be structured to expose the metal pads 112 and then the conductive pads 118 formed over the metal pads 112. The BPVs 128 may be formed in a similar manner as the BPVs 128 of FIGS. 6-7, for example, openings 124 may be formed in the dielectric layer 122, except that the openings expose the conductive pads 118 instead of the metal pads 112. The first barrier layer 127 and the conductive material of the BPVs 128 may then be formed in the openings 124, as described for FIG. 7. As in FIGS. 20A through B and 21, some conductive pads 118 may not be connected to a BPV 128. In some embodiments, the lateral separation between adjacent conductive pads 118 may have a distance D 6 that is between about 2 μm and about 100 μm.In some cases, the bond pads 316 may be formed by forming the BPVs 128 separate from the conductive pads 118 as described herein with a smaller separation distance and / or a separation distance D 6. In some cases, the BPVs 128 may be formed by forming the BPVs 128 to contact the conductive pads 118 with a smaller size and separation distance. For example, the lesser depth of the openings 124 for contacting the conductive pads 118 may allow for more accurate photolithographic patterning. In some embodiments, conductive pads 118 formed to be contacted by BPVs 128 may have a smaller width than conductive pads 118 not contacted by BPVs 128. For example, the conductive pads 118 that are not probed may be formed with a narrower width. In some embodiments, the conductive pads 118 formed to be contacted by BPVs 128 may have a width W2' that is between about 1% and about 90% less than the width W2 of the other conductive pads 118.FIG. 20A shows a BPV 128 approximately centered on a conductive pad 118, but in other cases there may be some lateral displacement between a BPV 128 and a conductive pad 118. For example, in FIG. 20B, a BPV 128 is shown displaced a distance S 5 from a conductive pad 118. The distance S5 corresponds to the lateral distance between the center of the BPV 128 (e.g., at half the width W3) and the center of the conductive pad 118 (e.g., at half the width W2'). In some cases, forming the BPVs 128 in a separate process step from that of the bond pads 316 allows forming the BPVs 128 with a smaller width (e.g., W3). Forming BPVs 128 having a lesser width (e.g., a lesser width than corresponding conductive pads 118) may increase the likelihood that the entirety of the surfaces of the BPVs 128 will be connected to the conductive pads 118 when there is misalignment. In some cases, the maximum displacement distance (e.g., S 5) for which the entire area of a BPV 128 remains connected remains indicated by the difference between the width W 3 of the BPV 128 and the width W 2 of the corresponding conductive pad 118. Connecting the entire bonding areas of the BPVs 128 may reduce the contact resistance between the BPVs 128 and the conductive pads 118, thereby improving the electrical performance of the package 520. In this way, the size or spacing of some conductive features of a connected package may be reduced without increasing the risk of undesired effects due to shift or other process deficiencies.FIGS. 22-26 illustrate intermediate steps of forming a package structure 1000 including a package 600, in accordance with some embodiments. FIG. 22 illustrates a first die structure 300 and a second die structure 400 that have been connected into a package 600. The first die structure 300 and a second die structure 400 may be similar to the first die structure 300 or the second die structure 400 described above for FIGS. 17 to 21. Package 600 may be similar to packages 500, 510, 520, or 530 previously described for FIGS. 18A-21, but with external connectors 420 not formed on second die structure 400. As shown in FIG. 22, the package 600 includes contact pads 602 formed on the second die structure 400, which allows electrical connections to the package 600.FIG. 22 also illustrates a carrier substrate 721 having an adhesion layer 723 and a polymer layer 725 over the adhesion layer 723. In some embodiments, the carrier substrate 721 includes, for example, silicon-based materials such as glass or silicon oxide, or other materials such as aluminum oxide, combinations of any of these materials, or the like. The carrier substrate 721 may be planar to accommodate attachment of devices such as the package 600. The adhesion layer 723 is placed on the carrier substrate 721 to aid in the adhesion of overlying structures (e.g., the polymer layer 725). In some embodiments, the adhesion layer 723 may comprise a light-to-heat conversion (LTHC) material or an ultraviolet adhesive that loses its adhesion properties when exposed to ultraviolet light. Other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxy adhesives, combinations thereof, or the like, may also be used. The adhesive layer 723 may be applied to the supporting substrate 721 in a semi-liquid or gel form which is easily deformable under pressure.The polymer layer 725 is placed over the adhesion layer 723 and used to provide protection for the package 600. In some embodiments, the polymer layer 725 may be polybenzoxazole (PBO), however, any suitable material such as polyimide or a polyimide derivative may alternatively be used. For example, the polymer layer 725 may be placed to a thickness of between about 2 μm and about 15 μm, such as about 5 μm, using a spin coating process, however, any suitable method and thickness may be used instead.In some embodiments, vias such as dielectric vias (TDVs) 727 are formed over polymer layer 725. In some embodiments, a seed layer (not shown) is first formed over the polymer layer 725. The seed layer is a thin layer of conductive material that aids in the formation of a thicker layer during subsequent processing steps. In some embodiments, the seed layer may comprise a layer of titanium about 50 nm thick followed by a layer of copper about 300 nm thick. The seed layer may be formed using processes such as sputtering, evaporation, or PECVD processes, depending on the desired materials. When the seed layer is formed, a photoresist (not shown) may be formed over the seed layer and patterned. The TDVs 727 are then formed with the patterned photoresist. In some embodiments, the TDVs 727 comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and may be formed by electroplating, electroless plating, or the like, for example. In some embodiments, an electroplating process is used in which the seed layer and the photoresist are dipped or submerged in an electroplating solution. When the TDVs 727 are formed using the photoresist and the seed layer, the photoresist may be removed using a suitable removal process. In some embodiments, a plasma ash process may be used to remove the photoresist, whereby the temperature of the photoresist may be increased until the photoresist undergoes thermal decomposition and may be removed. Any other suitable process, such as wet striping, may alternatively be used. The removal of the photoresist may expose the underlying portions of the seed layer. When the TDVs 727 are formed, exposed portions of the seed layer are then removed, for example, using a wet or dry etching process. The TDVs 727 may be formed with a height of between about 180 μm and about 200 μm, with a critical dimension of about 190 μm and a pitch of about 300 μm.After forming the TDVs 727, the package 600 is attached to the polymer layer 725. In some embodiments, package 600 may be placed using a pick-and-place process, for example. However, any suitable method of placing package 600 may be used.FIG. 23 illustrates an encapsulation of the package 600 and the TDVs 727 with an encapsulation material 729. The encapsulation material 729 may be a molding compound such as a resin, polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations thereof, or the like. FIG. 24 illustrates thinning of the encapsulation material 729 to expose the TDVs 727 and the package 600. The thinning may be performed using a CMP process or another process, for example. The thinning of the encapsulation material 729 may expose the contact pads 602 of the package 600.FIG. 25 illustrates formation of a redistribution structure 800 having one or more layers over the encapsulation material 729. In some embodiments, redistribution structure 800 may be formed by initially forming a first redistribution passivation layer 801 over encapsulation material 729. In some embodiments, the first redistribution passivation layer 801 may be polybenzoxazole (PBO), however, any suitable material such as polyimide or a polyimide derivative such as a low temperature cured polyimide may alternatively be used. The first redistribution passivation layer 801 may be placed to a thickness of between about 5 μm and about 17 μm, such as about 7 μm, for example, using a spin coating process, however any suitable method and thickness may be used instead.Once the first redistribution passivation layer 801 has been formed, the first redistribution vias 803 may be formed through the first redistribution passivation layer 801 to make electrical connections to the package 600 and the TDVs 727. For example, the first redistribution vias 803 may be formed to make electrical contact with the contact pads 602. In some embodiments, the first redistribution vias 803 may be formed using a damascene process, a dual damascene process, or another process. After forming the first redistribution vias 803, a first redistribution layer 805 is formed over and in electrical communication with the first redistribution vias 803. In some embodiments, the first redistribution layer 805 may be formed by initially forming a seed layer (not shown) of a titanium copper alloy by a suitable forming process such as CVD or sputtering. A photoresist (i.e., not shown) may then be formed to cover the seed layer and the photoresist may then be patterned to expose the portions of the seed layer that are where the first redistribution layer 805 is to be placed.Once the photoresist has been formed and patterned, a conductive material, such as copper, may be formed on the seed layer by a deposition process, such as plating. The conductive material may be formed to have a thickness between about 1 μm and about 10 μm, such as about 4 μm. However, while the discussed material and methods are suitable for forming the conductive material, these materials are merely exemplary. Any other suitable materials, such as AlCu or Au, and any other suitable processes of formation, such as CVD or PVD, may alternatively be used to form the first redistribution layer 805.After forming the first redistribution layer 805, a second redistribution passivation layer 807 may be formed and patterned to help isolate the first redistribution layer 805. In some embodiments, the second redistribution passivation layer 807 may be similar to the first redistribution passivation layer 801, such as a positive tone PBO, or may be different from the first redistribution passivation layer 801, such as a negative tone material such as a low temperature cured polyimide. The second redistribution passivation layer 807 may be applied to a thickness of about 7 μm. After placement, the redistribution passivation layer 807 may be patterned to form openings using, e.g., a photolithographic masking and etching process or, if the material of the second redistribution passivation layer 807 is photosensitive, by exposing and developing the material of the second redistribution passivation layer 807. Any suitable material and method of patterning may be used.After the second redistribution passivation layer 807 is patterned, a second redistribution layer 809 may be formed to extend through the openings formed in the second redistribution passivation layer 807 and electrically connect to the first redistribution layer 805. In some embodiments, the second redistribution layer 809 may be formed using materials and processes similar to the first redistribution layer 805. For example, a seed layer may be deposited and covered by a patterned photoresist, a conductive material such as copper may be deposited on the seed layer, the patterned photoresist may be removed, and the seed layer may be etched using the conductive material as a mask. In some embodiments, the second redistribution layer 809 is etched to a thickness of about 4 μm. However, any suitable material or process of manufacture may be used.After forming the second redistribution layer 809, a third redistribution passivation layer 811 is deposited over the second redistribution layer 809 to help isolate and protect the second redistribution layer 809. In some embodiments, the third redistribution passivation layer 811 may be formed of similar materials and in a similar manner as the second redistribution passivation layer 807 with a thickness of about 7 μm. For example, the third redistribution passivation layer 811 may be formed of PBO or a low temperature cured polyimide deposited and patterned as described above with respect to the second redistribution passivation layer 1007. However, any suitable material or process of manufacture may be used.After the third redistribution passivation layer 811 is patterned, a third redistribution layer 813 may be formed to extend through the openings formed in the third redistribution passivation layer 811 and to electrically connect to the second redistribution layer 809. In some embodiments, the third redistribution layer 813 may be formed using materials and processes similar to the first redistribution layer 805. For example, a seed layer may be deposited and covered by a patterned photoresist, a conductive material such as copper may be deposited on the seed layer, the patterned photoresist may be removed, and the seed layer may be etched using the conductive material as a mask. In some embodiments, the third redistribution layer 813 is etched to a thickness of 5 μm. However, any suitable material or process of manufacture may be used.After forming the third redistribution layer 813, a fourth redistribution passivation layer 815 may be formed over the third redistribution layer 813 to help isolate and protect the third redistribution layer 813. In some embodiments, the fourth redistribution passivation layer 815 may be formed of similar materials and in a similar manner as the second redistribution passivation layer 807. For example, the fourth redistribution passivation layer 815 may be formed of PBO or a low temperature cured polyimide deposited and patterned as described above with respect to the second redistribution passivation layer 807. In some embodiments, the fourth redistribution passivation layer 815 is etched to a thickness of about 8 μm. However, any suitable material or process of manufacture may be used.In other embodiments, redistribution vias and redistribution layers of redistribution structure 800 may be formed using a damascene process, such as a dual damascene process. For example, a redistributed passivation layer may be formed over encapsulant 729. The first redistribution passivation layer is then patterned using one or more photolithographic steps to form both vias and conductive line openings within the first redistribution passivation layer. A conductive material may be formed in the vias and conductive line openings to form the first redistribution vias and the first redistribution layer. Further redistribution passivation layers may be formed over the first redistribution passivation layer and further sets of redistribution vias and conductive lines may be formed in the further redistribution passivation layers as described for the first redistribution passivation layer, thereby forming the redistribution structure 800. These or other techniques may be used to form redistribution structure 800.FIG. 25 further illustrates formation of under bump metallizations 819 and third external connections 817 to make electrical contact with the third redistribution layer 813. In some embodiments, the sub-bump metallizations 819 may each represent three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will appreciate that there are numerous suitable arrangements of materials and layers, such as an arrangement of chromium / chromium copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold, suitable for forming the under bump metallizations 819. All suitable materials or material layers that may be used for the sub-bump metallizations 819 are intended to be fully included within the scope of the embodiments.In some embodiments, the sub-bump metallizations 819 are created by forming each layer over the third redistribution layer 813 and along the interior of the openings through the fourth redistribution passivation layer 815. The formation of each layer may be performed using a plating process, such as electrochemical plating, however, other processes of formation, such as sputtering, evaporation, or a PECVD process may be used depending on the materials desired. The under bump metallizations 819 may be formed to have a thickness between about 0.7 μm and about 10 μm, such as about 5 μm.In some embodiments, the third external connectors 817 may be placed on the under bump metallizations 819 and may be a ball grid array (BGA) comprising a eutectic material such as solder, but any suitable materials may be used. In some embodiments where the third external connectors 817 are solder balls, the third external connectors 817 may be formed using a ball drop process, such as a direct ball drop process. In another embodiment, the solder balls may be formed by initially forming a layer of tin by any suitable method such as evaporation, electroplating, printing, solder transfer, and then performing a reflow to form the material into the desired bump shape. Once the third external connectors 817 have been formed, a test may be performed to ensure that the structure is suitable for further processing.FIG. 26 illustrates bonding of a device package 900 to the TDVs 727 through the polymer layer 725. Prior to the bonding of the device package 900, the support substrate 721 and the adhesion layer 723 are removed from the polymer layer 725. The polymer layer 725 is also patterned to expose the TDVs 727. In some embodiments, the polymer layer 725 may be patterned using, for example, a laser drilling process. In such a method, a protective layer, such as a light-to-heat conversion (LTHC) layer or a HogoMax layer (not separately illustrated), is first deposited over the polymer layer 725. After protection, a laser is directed to the portions of the polymer layer 725 that are to be removed to expose the underlying TDVs 727. During the laser drilling process, the drilling energy may be in a range from 0.1 mJ to about 30 mJ, and a drilling angle may be from about o degrees (perpendicular to polymer layer 725) to about 85 degrees perpendicular to polymer layer 725. In some embodiments, the patterning may be formed to form openings over the TDMs 727 having a width between about 100 μm and about 300 μm, such as about 200 μm.In another embodiment, the polymer layer 725 may be patterned by initially applying a photoresist (not individually illustrated) to the polymer layer 725 and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) to initiate a chemical reaction, thereby inducing a physical change in portions of the photoresist that has been exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending on the desired pattern, and the underlying exposed portion of the polymer layer 725 is removed, e.g., by a dry etching process. However, any other suitable method of patterning the polymer layer 725 may be used.In some embodiments, device package 900 includes a substrate 902 and one or more stacked dies 910 (e.g., 910A and 910B) coupled to substrate 902. Although only one set of stacked dies 910A / 910B is illustrated, in other embodiments, multiple stacked dies 910 (each of which includes one or more stacked dies) may be arranged side-by-side and coupled to a same surface of the substrate 902. The substrate 902 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Further, the substrate 902 may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate 902 is based on an insulation core, such as a fiberglass reinforced resin core, in an alternative embodiment. An exemplary core material is fiberglass resin such as FR 4. Alternatives for the core material include bismaleimide triazine (BT) resin, or alternatively other board (PCB) materials or films. Build-up films such as Ajinomoto build-up film (ABF) or other laminates may be used for the substrate 902.The substrate 902 may include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to generate the structural and functional requirements of the design for device package 900. The devices may be formed using any method.The substrate 902 may also include metallization layers or conductive vias (not shown). The metallization layers may be formed over the active and passive devices and may connect the various devices to form functional circuitry. The metallization layers may be formed from alternating layers of dielectric (e.g., low-k dielectric) and conductive material (e.g., copper), where vias connect the layers of conductive material and may be formed by any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate 902 is substantially free of active and passive devices.The substrate 902 may include bond pads 904 on a first side of the substrate 902 to couple the stacked dies 910 and bond pads 906 on a second side of the substrate 902, the second side opposing the first side of the substrate 902 to couple the external interconnects 901. In some embodiments, bond pads 904 and 906 are formed by forming cut-outs (not shown) in dielectric layers (not shown) on the first and second sides of substrate 902. The cut-outs may be formed to allow the bond pads 904 and 906 to be embedded in the dielectric layers. In other embodiments, the cut-outs are omitted because bond pads 904 and 906 may be formed on the dielectric layer. In some embodiments, bond pads 904 and 906 include a thin seed layer (not shown) of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of bond pads 904 and 906 may be deposited over the thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, CVD, atomic layer deposition (ALD), PVD, the like, or a combination thereof. In an embodiment, the conductive material of bond pads 904 and 906 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.In one embodiment, bond pads 904 and bond pads 906 are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers exist, such as an arrangement of chromium / chromium copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold may be used to form bond pads 904 and 906. All suitable materials or material layers that may be used for bond pads 904 and 906 are fully intended to be included within the scope of the present application. In some embodiments, the conductive vias extend through the substrate 902 and couple at least one of the bond pads 904 to at least one of the bond pads 906.In the illustrated embodiment, the stacked dies 910 are coupled to the substrate 902 by wire bonds 912, however, other connections may be used, such as conductive bumps. In an embodiment, the stacked dies 910 are stacked memory dies. For example, the stacked dies 910 may be memory dies, such as low power dual data rate (LP DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules.The stacked dies 910 and the wire bonds 912 may be encapsulated with a molding material 914. The molding material 914 may be formed on the stacked dies 910 and the wire bonds 912, for example, by die casting. In some embodiments, the molding material 914 is a molding compound, a polymer, an epoxy, silica filler material, the like, or a combination thereof. A curing process may be performed to cure the molding material 914. The curing process may be a thermosetting, a UV curing, the like, or a combination thereof.In some embodiments, the stacked dies 910 and the wire bonds 912 are buried in the molding material 914 and, after curing the molding material 914, a planarization step, such as grinding, is performed to remove excess portions of the molding material 914 and provide a substantially flat surface for the device package 900.In some embodiments, external connections 901 may be formed to provide an external connection between device package 900 and, e.g., TDVs 727. The external connections 901 may be contact bumps such as micro bumps or controller collapse chip connection (C4) bumps, and may include a material such as tin or other suitable materials such as silver or copper. In some embodiments where the external connections 901 are tin solder bumps, the external connections 901 may be formed by initially forming a layer of tin by any suitable method, such as evaporation, electroplating, pressure, solder transfer, ball replacement, or the like, to a thickness of about 100 μm, for example. When a layer of tin has been formed on the structure, reflow is performed to form the material into the desired bump shape.When the external connections 901 have been formed, the external connections 901 are aligned with and placed over the TDVs 727, and connection is performed. For example, in some embodiments where external connections 901 are solder bumps, the bonding process may include a reflow process, thereby raising the temperature of the external connections 901 to a point where the external connections 901 liquify and flow, so that they bond the device package 900 to the TDVs 727 when the external connections 901 rebure. An encapsulation material 903 may be formed to encapsulate and protect the device package 900. The encapsulation material 903 may extend between the polymer layer 725 and the device package 900 and may constitute an underfill in some embodiments. In this manner, a package structure 1000 may be formed.Embodiments may achieve advantages. By forming the bond pad vias (BPVs) and the bond pads of a die in two different processing steps, the size and / or separation (e.g., pitch) of features such as metal lines, conductive pads, the BPVs, and / or the bond pads may be reduced. For example, by forming the BPVs in a first photolithography and etching step, closer to other features, such as conductive pads (e.g., aluminum pads), may be formed without an increased likelihood of process deficiencies such as electrical shorts. In this way, the size of a die or a package including a die may be reduced. Further, the routing density of the die or package may be increased. In some cases, a first bond pad of a first die may be formed such that its entire bond pad is connected to the corresponding second bond pad of a second die, even if a shift occurs during the bonding process. For example, the first bond pad of the first die may have a width that is less than the second bond pad such that the entire bonding surface of the first bond pad remains in contact with the second bond pad, even if there is some displacement between the first bond pad and the second bond pad. In this way, a package comprising connected dies may have an improved contact resistance between connected pads when a shift occurs.In an embodiment, a device includes an interconnect structure over a semiconductor substrate, the interconnect structure including first conductive pads, a first dielectric layer over the interconnect structure, bond pad vias in the first dielectric layer, each bond pad via of the bond pad vias including a first barrier layer extending along sidewalls of the first dielectric layer and over a first conductive pad of the first conductive pads, and a first conductive material over the first barrier layer, wherein a top surface of the first conductive material and a top surface of the first barrier layer are coplanar, a second dielectric layer over the first dielectric layer, and first bond pads within the second dielectric layer, each first bond pad including a second barrier layer extending along sidewalls of the second dielectric layer and on the first conductive material and the first barrier layer of a first bond pad via of the bond pad vias, wherein the second barrier layer completely covers the top surface of the first conductive material and the top surface of the first bond pad via, and comprises a second conductive material over the second barrier layer. In an embodiment, the device further comprises a third dielectric layer extending over sidewalls of the first dielectric layer, the interconnect structure, and the semiconductor substrate. In an embodiment, the second dielectric layer extends over the third dielectric layer and the first dielectric layer. In an embodiment, the device further comprises an aluminum pad within the first dielectric layer, wherein the aluminum pad contacts a first conductive pad of the first conductive pads. In one embodiment, a bond pad via contacts the aluminum pad. In an embodiment, the device further comprises a passivation layer extending over the first conductive pads, wherein the bond pad vias extend through the passivation layer. In an embodiment, adjacent first conductive pads are laterally separated by a distance that is between 2 μm and 20 μm. In an embodiment, the second barrier layer comprises titanium, titanium nitride, tantalum or tantalum nitride.In an embodiment, a package includes a first die including a first metallization layer, one or more first bond pad vias on the first metallization layer, a first barrier layer extending across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, a second barrier layer extending across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, a second bond pad connected to a first bond pad of the first die. In an embodiment, the first die includes a first bonding layer, the first bonding pad disposed within the first bonding layer, the second die includes a second bonding layer, the second bonding pad disposed within the second bonding layer, and the first bonding layer is connected to the second bonding layer. In an embodiment, a width of the first bond pad is between 95% and 150% of a width of the second bond pad. In an embodiment, a width of the second bond pad is between 95% and 150% of a width of the first bond pad. In an embodiment, the second die further comprises a via, the via connected to the first bond pad of the first die. In an embodiment, the package further comprises a conductive pad on the first metallization layer, wherein the conductive pad comprises a different conductive material than the one or more first bond pad vias. In an embodiment, the conductive pad is laterally separated from an adjacent first bond pad via by a distance that is between 2 μm and 100 μm.In an embodiment, a method includes forming an interconnect structure on a top surface of a semiconductor substrate, the interconnect structure including a first conductive pad, forming a first dielectric layer over the interconnect structure, etching the first dielectric layer to form a first opening exposing the first conductive pad, depositing a first barrier layer within the first opening in the first dielectric layer, depositing a first conductive material within the first opening and on the first barrier layer, forming a second dielectric layer over the first dielectric layer, etching the second dielectric layer to form a second opening exposing the first conductive material, depositing a second barrier layer within the second opening in the second dielectric layer, depositing a second conductive material within the second opening and on the second barrier layer, bonding a semiconductor die to the second dielectric layer, the semiconductor die comprising a bonding layer and a bonding pad, the bonding connecting the bonding layer of the semiconductor die to the second dielectric layer and bonding the bonding pad of the semiconductor die to the second conductive material. In an embodiment, the method includes, after depositing the first conductive material, forming a sacrificial layer over the first dielectric layer and the first conductive material, attaching the sacrificial layer to a first support structure, thinning the semiconductor substrate, and removing the first support structure and the sacrificial layer, wherein the second dielectric layer is formed over the first dielectric layer after the sacrificial layer is removed. In an embodiment, the method includes forming a passivation layer over the interconnect structure and forming a conductive pad over the passivation layer, wherein the first dielectric layer is formed over the conductive pad and the passivation layer. In an embodiment, the bond pad of the semiconductor die has a lateral width that is less than the second conductive material. In an embodiment, the bond pad of the semiconductor die has a lateral width that is greater than the second conductive material.The above outlines features of several embodiments that will be more readily understood by those skilled in the art to understand aspects of the present disclosure. Those skilled in the art should understand that they may readily use this disclosure as a basis for designing or altering other processes and structures to accomplish the same purposes and / or achieve the same advantages of the embodiments introduced herein.

Claims

An apparatus comprising: an interconnect structure (108) over a semiconductor substrate (102), the interconnect structure (108) comprising a plurality of first metal pads (112); a first dielectric layer (122) over the interconnect structure (108); a plurality of bond pad vias (128) within the first dielectric layer (122), each bond pad via of the plurality of bond pad vias (128) comprising: a first barrier layer (127) extending along sidewalls of the first dielectric layer (122) and extending over only a portion of a first metal pad of the plurality of first metal pads (112) in a region below one of the bond pad vias (128); and a first conductive material over the first barrier layer (127), wherein a top surface of the first conductive material and a top surface of the first barrier layer (127) are coplanar; a second dielectric layer (312) over the first dielectric layer (122); and a plurality of first bond pads (316) within the second dielectric layer (312), each first bond pad of the plurality of bond pads (316) comprising: a second barrier layer (315) extending along sidewalls of the second dielectric layer (312) and on the first conductive material and sidewalls of the first barrier layer (127) of a first bond pad via of the plurality of bond pad vias (128), the second barrier layer (315) completely covering the top surface of the first bond pad via (128), and a second conductive material over the second barrier layer (315).The device of claim 1, further comprising a third dielectric layer extending over sidewalls of the first dielectric layer (122), the interconnect structure (108), and the semiconductor substrate (102).The device of claim 2, wherein the second dielectric layer (312) extends over the third dielectric layer and the first dielectric layer (122).The device of any preceding claim, further comprising an aluminum pad (118) within the first dielectric layer (122), wherein the aluminum pad (118) contacts a first metal pad of the plurality of first metal pads (112).The apparatus of claim 4, wherein a bond pad via of the plurality of bond pad vias (128) contacts the aluminum pad (118).The device of any preceding claim, further comprising a passivation layer extending over the plurality of first metal pads (112), wherein the plurality of bond pad vias (128) extend through the passivation layer.The device of any preceding claim, wherein contiguous first metal pads of the plurality of first metal pads (112) are laterally separated by a distance that is between 2 μm and 20 μm.The device of any preceding claim, wherein the second barrier layer (315) comprises titanium, titanium nitride, tantalum, or tantalum nitride.A package comprising: a first die (300) comprising: a first metallization layer (112); one or more first bond pad vias (128) on the first metallization layer (112), wherein a first barrier layer (127) extends over the first metallization layer (112) between each first bond pad via (128) and the first metallization layer (112); one or more first bond pads (316) on the one or more first bond pad vias (128), wherein a second barrier layer (315) extends between a first bond pad (316) and a first bond pad via (128) over the first bond pad via (128); and a conductive pad on the first metallization layer (112), wherein the conductive pad comprises a different conductive material than the one or more first bond pad vias (128); and a second die (400) comprising one or more second bond pads (410), wherein a second bond pad (410) is connected to a first bond pad (316) of the first die (300).The package of claim 9, wherein the first die (300) comprises a first bonding layer, wherein the first bonding pad (316) is disposed within the first bonding layer, wherein the second die (400) comprises a second bonding layer (412), wherein the second bonding pad (410) is disposed within the second bonding layer (412), and wherein the first bonding layer is connected to the second bonding layer (412).The package of claim 9 or 10, wherein the width of the first bond pad (316) is between 95% and 150% of the width of the second bond pad (410).The package of any of claims 9 and 10, wherein the width of the second bond pad (410) is between 95% and 150% of the width of the first bond pad (316).The package of any of claims 9 to 12, wherein the second die (400) further comprises a via, the via connected to the first bond pad (316) of the first die (300).The package of any of claims 9 to 13, wherein the conductive pad is laterally separated from an adjacent first bond pad via (128) by a distance that is between 2 μm and 100 μm.A method comprising: forming an interconnect structure (108) on a top surface of a semiconductor substrate (102), the interconnect structure (108) comprising a first conductive pad (112); forming a first dielectric layer (122) over the interconnect structure (108); etching the first dielectric layer (122) to form a first opening (124) exposing the first conductive pad (112); depositing a first barrier layer (127) within the first opening (124) in the first dielectric layer (122); depositing a first conductive material within the first opening (124) and on the first barrier layer (127); forming a second dielectric layer (312) over the first dielectric layer (122); etching the second dielectric layer (312) to form a second opening (314) exposing the first conductive material; depositing a second barrier layer (315) within the second opening (314) in the second dielectric layer (312); depositing a second conductive material within the second opening (314) and at the second barrier layer (315); and bonding a semiconductor die to the second dielectric layer (312), the semiconductor die comprising a bonding layer (412) and a bonding pad (410), wherein the bonding connects the bonding layer (412) of the semiconductor die to the second dielectric layer (312) and bonds the bonding pad (410) of the semiconductor die to the second conductive material.The method of claim 15, further comprising: after depositing the first conductive material, forming a sacrificial layer over the first dielectric layer (122) and the first conductive material; attaching the sacrificial layer to a first support structure; thinning the semiconductor substrate (102); and removing the first support structure and the sacrificial layer, wherein the second dielectric layer (312) is formed over the first dielectric layer (122) after the sacrificial layer is removed.The method of claim 15 or 16, further comprising: forming a passivation layer over the interconnect structure (108); and forming a conductive pad over the passivation layer, wherein the first dielectric layer (122) is formed over the conductive pad and the passivation layer.The method of any of claims 15 to 17, wherein the bond pad (410) of the semiconductor die has a lateral width less than that of the second conductive material.The method of any of claims 15 to 18, wherein the bond pad (410) of the semiconductor die has a lateral width greater than that of the second conductive material.

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