Single-chip power diode and method for manufacturing a single-chip power diode

Abstract

Single-chip power diode (1), comprising: - a first load terminal (11), a second load terminal (12) and, between the first load terminal (11) and the second load terminal (12), a semiconductor body (10) comprising an anode region (102) coupled to the first load terminal (11), a cathode region (103) coupled to the second load terminal (12) and, between the anode region (102) and the cathode region (103), a drift region (100); - an active region (1-1) configured to conduct a load current between the load terminals (11, 12) based on the anode region (102), the drift region (100) and the cathode region (103), wherein a thickness of the semiconductor body (10) is defined by a distance (d) between at least a first interface (102-11) formed between the first load terminal (11) and the anode region (102) and a second interface (103-12) formed between the second load terminal (12) and the cathode region (103); - an edge termination region (1-3) surrounding the active region (1-1) and terminated by a chip edge (1-4); wherein at least one inactive sub-region (1-11) is contained in the active region (1-1), each inactive sub-region (1-11): - has a barrier area (102-131) with a minimum lateral extent (MLE) of at least 20% of a drift region thickness (dd); - is configured to prevent passage of the load current between the first load terminal (11) and the semiconductor body (10) through the barrier area (102-131); and - is at least partially not arranged next to the edge termination region (1-3); and wherein - the anode region (102) is laterally structured with respect to the at least one inactive sub-region (1-11) in the active region (1-1).

Description

TECHNICAL FIELDThis document relates to embodiments of a single chip power diode and to embodiments of a method for processing a single chip power diode. In particular, this document relates to embodiments of a diode for fast switching applications.BACKGROUNDMany functions of modern devices in automotive, consumer and industrial applications, such as conversion of electrical energy and driving an electric motor or machine rely on power semiconductor switches. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications including, but not limited to, switches in power supplies and power converters.A power semiconductor device typically comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device.Further, in the case of a controllable power semiconductor device, e.g. a transistor or a controllable diode, the load current path may be controlled by means of an insulated electrode commonly referred to as gate electrode. For example, upon receiving a corresponding control signal, e.g. from a driver unit, the control electrode may put the power semiconductor device in a forward conducting state or a blocking state.A typical power semiconductor device is a power diode whose basic configuration is known to a person skilled in the art.Typical design goals for power diodes include high current carrying capabilities, soft recovery losses, and so-called diode softness. At the same time, thermal constraints must be fulfilled.Sometimes, by using techniques for shortening the carrier lifetime, such as doping platinum in the drift zone of the power diode and / or carrier concentration reduction by damage implantation of e.g. argon or helium in the anode and / or cathode emitter, a switching loss reduction of a power diode is achieved for a fast switching application. According to another approach, the cathode of the diode is patterned. However, some disadvantages can be observed in these approaches:For example, damage implantations are associated with the risk of an increased leakage current. By using platinum doping, the temperature coefficient of the diode forward voltage becomes more negative, which restricts the possibility of parallel connection of the diode to another power semiconductor device. Furthermore, a recombination efficiency of a platinum doping at an elevated temperature is reduced, which leads to an increased stored charge and increased switching losses. And by using a patterned cathode, the carrier concentration at the backside may be reduced, which may result in poorer diode softness performance.EP 1 033 761 A2 describes a semiconductor device comprising a base layer of a first conductivity type having a high resistance, an anode layer of a second conductivity type formed on one surface of the base layer of the first conductivity type, an anode electrode formed on one surface of the anode layer of the second conductivity type, a cathode layer formed on the other surface of the base layer of the first conductivity type, and a cathode electrode formed on one surface of the cathode layer, said anode electrode being connected to a part of the second anode layer, and an area ratio S1 / S2 being between 5 and 30, wherein S1 is the area over which said electrode is not connected to the anode layer of the second conductivity type, and S2 is the area, through which the anode electrode is connected to the anode layer of the second conductivity type.US 2019 / 0 043 998 A1 describes a diode in which the electric field is prevented from concentrating in a p layer during reverse recovery.JP H10-326 900 A describes a diode with certain reverse recovery properties.SUMMARYAccording to an embodiment, a single chip power diode comprises: a first load terminal, a second load terminal, and between the first load terminal and the second load terminal, a semiconductor body comprising an anode region coupled to the first load terminal, a cathode region coupled to the second load terminal, and a drift region between the anode region and the cathode region; an active region configured to conduct a load current between the load terminals based on the anode region, the drift region, and the cathode region, wherein a thickness of the semiconductor body is defined by a distance between at least one first interface formed between the first load terminal and the anode region and a second interface formed between the second load terminal and the cathode region; an edge termination region surrounding the active region and terminated by a chip edge. At least one inactive sub-region is included in the active region, each inactive sub-region comprising: a blocking surface having a minimum lateral extension of at least 20% of a drift region thickness; configured to prevent passage of the load current between the first load terminal and the semiconductor body through the blocking surface; and at least partially not arranged adjacent to the edge termination region. The anode region is laterally structured with respect to the at least one inactive sub-region in the active region.According to a further embodiment, a power semiconductor package comprises one or more single chip power diodes according to the preceding paragraph.According to another embodiment, a method of manufacturing a single chip power diode includes forming the following components:a first load terminal, a second load terminal, and between the first load terminal and the second load terminal of a semiconductor body comprising an anode region coupled to the first load terminal, a cathode region coupled to the second load terminal, and a drift region between the anode region and the cathode region; an active region configured to conduct a load current between the load terminals based on the anode region, the drift region, and the cathode region, wherein a thickness of the semiconductor body is defined by a distance between at least a first interface formed between the first load terminal and the anode region and a second interface formed between the second load terminal and the cathode region; an edge termination region surrounding the active region and terminated by a chip edge. Further, the method comprises including at least one inactive sub-region in the active region, each inactive sub-region:a blocking surface having a minimum lateral extension of at least 20% of a drift region thickness; configured to prevent a passage of the load current between the first load terminal and the semiconductor body through the blocking surface; and at least partially not arranged next to the edge termination region. The anode region is laterally structured with respect to the at least one inactive sub-region in the active region.The proposed embodiments involve the finding that, in a diode with a weak anode, the stored charge density on the anode side increases approximately with the square root of the current density. Generally, a weak anode is desirable for low charge density at the anode, which is associated with low soft recovery peak current (which would result in low turn-on losses of an IGBT connected in parallel therewith). On the cathode side, the carrier density increases approximately linearly with the current density. For softness during switching, a carrier density having a high concentration on the cathode side is desired, which is more easily achieved at a higher current density. Thus, for better dynamic performance of a diode, a higher current density is preferred because it reduces soft recovery and exhibits lower switching losses.According to embodiments described herein, only a portion of the diode die area is configured electrically active; e.g., a local current density may be higher compared to the conventional diode. A remainder of the diode chip area functions as a heat conductor / capacitor which ensures favorable thermal performance. In this way, the active area can be made smaller as compared with the conventional diode with the same current carrying capability.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon review of the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe parts in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings, there are shown: FIG. 1 schematically and by way of example a section of a vertical cross section of a diode; FIG. 2 shows schematically and by way of example a section of a horizontal projection of a diode; FIGS. 3-4 both schematically and exemplarily show a portion of a horizontal projection of a diode, according to some embodiments; FIGS. 5-11 each schematically and exemplarily show a portion of a vertical cross section of a diode according to some embodiments; FIGS. 12-13 both schematically and exemplarily show a portion of a horizontal projection of a diode according to some embodiments; FIGS. 14-15 both schematically and exemplarily show a portion of a vertical cross section of a power semiconductor package according to some embodiments; and FIG. 16 schematically and exemplarily illustrates a portion of a vertical cross-section and a portion of a horizontal projection of a diode included in a power semiconductor package according to one or more embodiments.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.In this regard, directional terminology, such as "top," "bottom," "below," "front," "behind," "back," "leading," "trailing," "above," etc., may be used with reference to the orientation of the described figures. Since portions of embodiments may be positioned in a number of different orientations, directional terminology is used for purposes of illustration and is in no way limiting. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures.The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been denoted by the same reference numerals throughout the several drawings, unless otherwise indicated.The term "horizontal" as used herein is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may be, for example, the surface of a semiconductor wafer or a die or a chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.The term "vertical" as used herein is intended to describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / die / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as "vertical direction Z".In this specification, n-doped is referred to as "first conductivity type", while p-doped is referred to as "second conductivity type". Alternatively, opposite doping relationships may be used such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.As used herein, the terms "in ohmic contact", "in electrical contact", "in ohmic connection", and "electrically connected" are intended to describe that there is a low ohmic electrical connection or current path between two regions, portions, zones, regions or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a region or part of a semiconductor device. Further, as used herein, the term "in contact" is intended to describe that there is a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include a further intermediate element or the like.Moreover, the term "electrical insulation" is used within the scope of its generally valid understanding, unless otherwise stated, and is thus intended to describe that two or more components are arranged separately from one another and that there is no ohmic connection connecting these components. However, components electrically insulated from one another may nevertheless be coupled to one another, for example mechanically coupled and / or capacitively coupled and / or inductively coupled. To name an example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, for example by means of an insulation, for example a dielectric.Specific embodiments described herein relate to a power semiconductor device, e.g., a power semiconductor device, that may be used within a power converter or a power supply, without being limited thereto. Thus, in one embodiment, such an apparatus may be configured to carry a load current to be supplied to a load or provided by a power source. For example, the power semiconductor device may comprise one or more active power semiconductor cells such as a monolithically integrated diode cell and / or a derivative of a monolithically integrated diode cell (e.g. a monolithically integrated cell of two antiseries connected diodes). Such diode cells may be integrated in a power semiconductor module. A plurality of such cells may form a cell array disposed in an active region of the power semiconductor device.The term "power semiconductor device" as used herein is intended to describe a power semiconductor device on a single chip with high voltage blocking and / or high current carrying capabilities. In other words, the power semiconductor device described herein is configured for a high current, typically in the Ampere range, for example up to several tens or hundred Ampere, and / or high voltages, typically above 15 V, more typically 100 V and above, e.g. up to at least 400 V or even more, e.g. up to at least 3 kV or even up to 10 kV or more.For example, the power semiconductor device described below may be a single semiconductor chip configured to be used as a power component in a low, medium and / or high voltage application.For example, the term "power semiconductor device" as used herein is not directed to logic semiconductor devices used, e.g., for storing data, computing data, and / or other types of semiconductor-based data processing.The present document relates in particular to power semiconductor devices which are configured as respective diodes.FIG. 1 schematically and exemplarily shows a portion of a vertical cross section of a single-chip power diode 1 (also referred to herein as diode 1). Referring also to FIG. 2, the diode 1 has an active region 1- 1. An edge termination region 1- 3 of the diode 1 surrounds the active region 1- 1. Thus, the edge termination region 1- 3 may be arranged outside the active region 1- 1. The edge termination region 1- 3 is laterally terminated by an edge 1- 4. The edge 1- 4 may form the chip edge of the diode 1.As used herein, the terms "edge termination region" and "active region" are assigned the respective technical meaning that one skilled in the art in connection with power semiconductor devices will cite. That is, the active region 1- 1 is primarily configured for forward load current conduction, while the edge termination region 1- 3 serves primarily functions with respect to reliable blocking capabilities, suitable electric field guidance, sometimes also charge carrier dissipation functions and / or further functions with respect to protection and suitable termination of the active region 1- 1.Referring again to FIG. 1, the diode 1 includes a semiconductor body 10 having a front side 110 and a back side 120. The front side 110 (also referred to herein as semiconductor body surface) and the back side 120 may vertically terminate the semiconductor body 10. That is, the semiconductor body 10 has a total thickness d along the vertical direction Z between the front side 110 and the back side 120. In the lateral directions, the semiconductor body 10 may be terminated by the edge 1- 4. Furthermore, both the front side 110 and the rear side 120 may extend laterally along both the first lateral direction X and the second lateral direction Y. For example, both the front side 110 and the back side 120 may form a respective horizontal surface of the semiconductor body 10. The thickness d of the semiconductor body 10 may be the distance between the front side 110 and the back side 120 measured along the vertical direction Z in the active region 1- 1, for example at a center of the active region 1- 1. A further definition of the thickness t of the semiconductor body 10 is given below.The semiconductor body 10 and a drift region 100 thereof form a part of both the active region 1- 1 and the edge termination region 1- 3. The semiconductor body 10 is configured in the active region 1- 1 to conduct a forward load current between a first load terminal 11 and a second load terminal 12A first load terminal 11 is arranged on the semiconductor body front side 110 and a second load terminal 12 is arranged on the semiconductor body rear side 120. For example, the first load terminal 11 comprises a front side metallization and / or the second load terminal 12 comprises a rear side metallization. For example, the first load terminal 11 is an anode terminal and the second load terminal 12 is a cathode terminal. At the front side 110, the semiconductor body 10 may be coupled to the front side metallization. At the rear side 120, the semiconductor body 10 can be coupled to the rear side metallization.In an embodiment, the first load terminal 11 (e.g. the front side metallization) laterally overlaps with the active region 1- 1, i.e. along the first lateral direction X and / or the second lateral direction Y and / or combinations thereof. It should be noted that the first load terminal 11 may be laterally structured. Analogously, in an embodiment, the second load terminal 12 (e.g. the back side metallization) laterally overlaps with the active region 1- 1, i.e. along the first lateral direction X and / or the second lateral direction Y and / or combinations thereof. It should be noted that the second load terminal 12 is generally not structured, but rather is formed homogeneously and monolithically on the semiconductor body rear side 120, in order to produce a laterally homogeneous contact with the semiconductor body 10, for example, on the rear side 120. Such a homogeneous structure may also be implemented in regions in which the load terminal 12 laterally overlaps with the edge termination region 1- 3.For example, the lateral boundary of the active region 1- 1 is defined by the lateral boundary of the outermost structure of the semiconductor body 10 allowing carrying of the load current and being electrically connected to both the first load terminal 11 and the second load terminal 12. For example, the lateral boundary of the active region 1- 1 may be defined at the front side 110. This lateral boundary may be defined by an outermost part of an anode region 102' (see the more detailed explanation below). For example, all functional elements for enabling the conduction of the load current are present in a vertical projection of the active region 1- 1 of the diode 1, e.g. including at least the first load terminal 11 (e.g. a front side metal contact thereof), the part of the anode region 102', a drift region 100, a part of a cathode region 103' and the second load terminal 12 (e.g. a back side emitter thereof). Of course, the diode 1 may be provided with further semiconductor regions in the semiconductor body 10, e.g. a field stop layer (not shown) between the cathode region 103' and the drift region 100.In an embodiment, the edge termination region 1- 3 and the active region 1- 1 may be arranged symmetrically to each other with respect to two (not shown) central vertical planes of the power semiconductor device 1, for example, as is exemplarily and schematically shown in FIG. 2.Furthermore, the lateral transition between the active region 1- 1 and the edge termination region 1- 3 may extend exclusively along the vertical direction Z according to an embodiment. As explained above, the lateral boundary of the active region 1- 1 may be defined at the front side 110, and a vertical projection along the vertical direction Z of such a defined lateral boundary may thus be observed at the back side 120.Referring back to FIG. 1, an exemplary configuration of the diode 1 will be described. The semiconductor body 10 comprises the anode region 102' coupled to the first load terminal 11, the cathode region 103' coupled to the second load terminal 12, and between the anode region 102' and the cathode region 103' the drift region 100.The active region 1- 1 is configured to conduct the load current between the load terminals 11, 12 based on the anode region 102', the drift region 100 and the cathode region 103'. A thickness of the semiconductor body 10 may also be defined as the distance d between at least a first interface 102'-11 formed (at the front side 110) between the first load terminal 11 and the anode region 102' and a second interface 103'-12 formed (at the back side 120) between the second load terminal 12 and the cathode region 103'.The anode region 102' may be of the second conductivity type. Both the drift region 100 and the cathode region 103' may be of the first conductivity type, wherein the cathode region 103' typically has a higher dopant concentration than the drift region 100. The anode region 102' may be arranged in electrical contact with the first load terminal 11.A main part of the semiconductor body 10 is formed as the drift region 100 of the first conductivity type, which is coupled to the body region 102' and forms a pn-junction 1021 therewith. As shown in FIG. 1, the anode 102' extends from the front side 110 along the vertical direction Z until it interfaces with the drift region 100. The drift region 100 extends along the vertical direction Z for a greater distance until it is coupled to the cathode region 103'. The cathode region 103' is arranged in electrical contact with the second load terminal 12, as illustrated in FIG. 1.In a conventional diode, as shown in FIG. 2, there is only a first interface 102'-11 formed (at the front 110) between the first load terminal 11 and the anode region 102' and extending continuously across the entire active region 1-1.The above-described basic configuration of the diode 1 is known per se to those skilled in the art. The embodiments described herein do not deviate from these generally known aspects with regard to diodes, but relate, inter alia, to a new design with regard to the contact between the first load terminal 11 and the anode region 102'. Because these aspects and optionally the cathode region 103' may be particularly modified according to the embodiments disclosed herein, reference is made to the anode region of the following description with reference numeral 102 and to the cathode region with reference numeral 103 (and the first / second interface(s) with reference numerals 102-11 and 103-12, respectively), while the other reference numerals introduced above do not designate components that are forcibly different from those presented with reference to FIGS. 1-2, and are subsequently used in the same manner accordingly.FIGS. 3-4 both schematically and exemplarily illustrate a portion of a horizontal projection of a diode 1 according to one or more embodiments. Diode 1 is a single-chip power diode 1 and comprises: the first load terminal 11, the second load terminal 12 and, between the first load terminal 11 and the second load terminal 12, the semiconductor body 10 comprising the anode region 102 (cf. FIG. 5 ff.) coupled to the first load terminal 11, the cathode region 103 (cf. FIG. 5 ff.) coupled to the second load terminal 12, and the drift region 100 between the anode region 102 and the cathode region 103; the active region 1- 1 configured to conduct a load current between the load terminals 11, 12 based on the anode region 102, the drift region 100 and the cathode region 103, wherein the thickness of the semiconductor body 10 is defined by a distance d between the at least one first interface 102- 11 formed between the first load terminal 11 and the anode region 102 (cf. FIG. 5 ff.) and the second interface 103- 12 formed between the second load terminal 12 and the cathode region 103; the edge termination region 1- 3 surrounding the active region 1- 1 and terminated by the chip edge 1- 4. At least one inactive sub-region 1- 11 is included in the active region 1- 1, wherein each inactive sub-region 1- 11 comprises: a blocking surface 102- 131 (cf. FIG. 5 et seq.) having a lateral minimum extension MLE of at least 20% of a drift region thickness dd; is configured to prevent a passage of the load current between the first load terminal 11 and the semiconductor body 10 through the blocking surface 102- 131; and is at least partially not arranged next to the edge termination region 1- 3.In one embodiment, diode 1 is integrated on a single chip and does not have transistor functionality. For example, the diode 1 does not have an IGBT portion or the like, but is a "diode-only" device.For example, the drift region thickness dd is the thickness of the drift region 100, measured as the vertical distance between the pn-junction 1021and a junction between the cathode region 103 (or the stack of a field stop region (not shown) and the cathode region 103) and the drift region 100, e.g. not in the inactive sub-region 1- 11 but in an active sub-region 1- 10 (cf. FIG. 8 ). For example, the drift region thickness dd amounts to at least 25% of the semiconductor body thickness d or even more than 95% of the semiconductor body thickness d (e.g., if a wafer thinning process was applied). In an embodiment, the transition between the drift region 100 and the cathode region 103 (or the boundary between the drift region 100 and the stack of the field stop region (not shown) and the cathode region 103) is at a vertical height at which the dopant concentration of dopants of the first conductivity type has increased along the vertical direction Z to a value of 1*10 17 cm -3.At least one inactive sub-region 1- 11 is included in the active region 1- 1. Referring to FIG. 4, the diode 1 comprises only one inactive sub-region 1- 11 extending continuously in the active region 1- 1, for example. According to FIG. 3, the diode 1 has a plurality of inactive subareas 1- 11 in the active area 1- 1.For example, each of the one or more inactive sub-regions 1- 11 may have a respective blocking surface 102- 131 (cf. FIG. 5 et seq.) with a lateral minimum extension MLEof at least 20% of the drift region thickness dd. For example, each of the at least one inactive sub-region 1- 11 comprises an insulating layer 131 (cf. FIG. 5 et seq.), wherein the insulating layer 131 forms the blocking surface 102- 131 of the at least one inactive sub-region 1- 11. That is, . The load current may not pass through via the blocking surface 102- 131 from the first load terminal 11 to the semiconductor body 10 (or vice versa); instead, the load current may have to follow a path comprising a portion of the at least one first interface 102- 11.For example, the insulating layer 131 comprises or is made of a silicon oxide, silicon nitride, silicon oxynitride, or other insulating material and / or has a thickness in a range of about 100 nm to 3 μm or about 0.5 μm to 2 μm.The minimum lateral extension MLE of each blocking surface 102- 131 may amount to at least 20%, to at least 50%, to at least 100%, or even to more than 200% of the drift region thickness dd. In an embodiment, the minimum lateral extension MLE of each blocking surface 102- 131 may amount to at least 20%, to at least 50%, to at least 100% or even to more than 200% of the semiconductor body thickness d. In the example according to FIG. 16, the MLE amounts to approximately four times the semiconductor body thickness d, for example.For example, a minimum lateral extension of the insulating layer 130 also amounts to the above-mentioned value MLE.The active region 1- 1 may include one or more active sub-regions 1- 10. If a plurality of active sub-regions 1- 10 are provided, these may be separated from each other, e.g., based on the one or more inactive sub-regions 1- 11, e.g., by a distance amounting to at least the minimum lateral extension MLE of the respective blocking surface 102- 131. For example, at least the first interface 102- 11 is formed in the one or more active sub-regions 1- 10.As illustrated in FIGS. 3 and 4, each of the one or more inactive sub-regions 1- 11 is at least partially not arranged next to the edge termination region 1- 3; instead, the transition between the edge termination region 1- 3 and the active region 1- 1 is at least partially formed by a transition between the edge termination region 1- 3 and at least one of the one or more active sub-regions 1- 10. The lateral surface of the active region 1- 1 may thus be defined by an envelope 1- 2 surrounding outermost portions of the at least one first interface 102- 11 in the active region 1- 1.According to embodiments described herein, the total lateral area of the active region 1- 1 may be divided into one or more first interfaces 102- 11 that allow a passage of the load current between the first load terminal 11 and the semiconductor body 10 and into one or more blocking areas 102- 31 that do not allow such a passage. For example, the sum of the one or more first interfaces 102- 11 and the one or more blocking surfaces 102- 31 amounts to the lateral surface of the active region 1- 1.For example, the sum of one or more first boundary surfaces 102- 11 is within the range of 10% to 90% of the lateral area of the active region 1- 1. Further, the sum of one or more blocking areas 102- 131 is within the range of 10% to 90% of the lateral area of the active region 1- 1.Several different design options are possible to arrange the at least one inactive sub-region 1- 11 and the at least one active sub-region 1- 10 in the active region 1- 1, wherein FIGS. 3 and 4 only schematically illustrate two example options. For example, embodiments follow at least one of the following design constraints: (i) the sum of each at least one first interface 102- 11 totals at least 10% of the lateral area of the active region 1- 1 and totals no more than 90% of the lateral area of the active region 1- 1; and / or (ii) the sum of each at least one blocking surface 102- 131 totals at least 10% of the lateral area of the active region 1- 1 and totals no more than 90% of the lateral area of the active region 1- 1; and / or (iii) each of at least 90% of the active sub-regions 1- 10 has a respective first interface 102- 11 and has an area with a minimum lateral extension of at least 20%, 50%, 100% or 200% of the drift region thickness dd; and / or (iv) each of at least 90% of the one or more inactive sub-regions 1- 11 has a respective blocking surface 102- 131 and has a surface with a minimum lateral extension MLEof at least 20%, 50%, 100% and 200% of the drift region thickness dd.That is, according to one or more embodiments, a substantial portion of the active area is occupied by the one or more inactive sub-regions 1- 11 that do not allow a passage of the load current between the first load terminal 11 and the semiconductor body 10, i.e. no such passage is possible at the respective blocking surface 102- 131.As indicated above, several design options are available. Instead of the separate active sub-regions 1- 10 in FIG. 3, which each have a substantially rectangular shape, it would also be possible, for example, for a single continuous active sub-region 1- 10 to be present with a meandering profile and a correspondingly constructed single continuous inactive sub-region 1- 11. Furthermore, the circular structures shown in FIG. 4 could be replaced by ellipsoidal structures. Furthermore, a stripe pattern is possible where, for example, a respective active sub-region 1- 10 has a stripe configuration and two laterally adjacent inactive sub-regions 1- 11 also have a stripe configuration (cf. FIG. 16, part ( 2)).Thus, for example, if more than one inactive sub-region 1- 11 is provided, according to an embodiment, the inactive sub-regions 1- 11 may be arranged between or around the spatially separated active sub-regions 1- 10.Regardless of the actual positioning and dimensioning of the one or more active sub-regions 1- 10 and the one or more inactive sub-regions 1- 11, according to some embodiments described herein, an anode efficiency of the single chip power diode 1 within the active region 1- 1 is spatially modulated, e.g. based on the blocking surface(s) 102- 131 of the at least one inactive sub-region 1- 11 in the active region 1- 1. An additional spatial modulation may be achieved by a lateral structure of the anode region 102 and / or a lateral structure of the cathode region 103, as described further below.FIGS. 5-11 each schematically and exemplarily illustrate a portion of a vertical cross-section of the diode 1 according to some embodiments. Each of FIGS. 5-11 shows a vertical cross-section that may correspond to, for example, a right-hand portion of the embodiments shown in FIGS. 3-4, e.g., a vertical cross-section along section line A-A' shown in FIGS. 3-4.Accordingly, starting at the respective right-hand part of FIGS. 5-11, the chip edge 1- 4 laterally closes the edge termination region 1- 3 of the diode 1. At the front side 110, the edge termination region 1- 3 may include an isolation structure 13 (as also shown in FIG. 1 ), which may be constructed in a conventional manner. By way of example, the extension 102- 3 of the anode region 102 may extend from the active region 1- 1 into the edge termination region 1- 3 below the isolation structure 13. Furthermore, doped semiconductor portions 105, 106 of the first or second conductivity type may be provided at an outermost portion of the edge termination structure 1- 3 and in contact with the isolation structure 13, for example, to form a channel stopper. Furthermore, an electrically conductive runner structure 115 can be arranged on the insulation structure 13. Further constructions of the edge termination region 1- 3 are possible.As the anode region 102, the first load terminal 11 may include an extension 11- 3 extending from the active region 1- 1 into the edge termination region 1- 3 but above the isolation structure 13. Based on the isolation structure 13, however, according to an embodiment, a transition of the load current between the semiconductor body 10 and the first load terminal is not possible in the edge termination region 1- 3.The first load terminal 11, e.g. a front side metallization thereof, may extend continuously through the entire area of the active region 1- 1. For example, the entire region bounded by the envelope 1- 2 (cf. also FIGS. 3 and 4 ) is covered by the front side metallization of the first load terminal 11In each of the one or more active sub-regions 1- 10, the first load terminal 11 is coupled to the anode region 102, e.g. to emitter portions 102- 2 thereof, thereby forming the one or more first interfaces 102- 11 allowing a passage of the load current.In each of the one or more inactive sub-regions 1- 11, the first load terminal 11 is coupled to the respective insulation layer 131, which in turn is coupled to the semiconductor body 10, e.g. also to the anode region 102, e.g. to the structure parts 102- 1 (cf. e.g. FIG. 5 ) thereof, thereby forming the one or more blocking surfaces 102- 131 that do not allow passage of the load current.Referring to FIG. 8, the anode region 102 interfaces with the drift region 100, thereby forming the pn junction 1021. The drift region 100 extends along the vertical direction Z until it couples to the cathode region 103 arranged in electrical contact with the second load terminal 12, thereby forming the second interface 103- 12. Like the anode region 102, the cathode region 103 may include emitter portions 103- 2 and structure portions 103- 1 (see e.g. FIG. 9 ) in the active region 1- 1 and an extension 103- 3 extending into the edge termination region 1- 3 as illustrated in FIG. 8.As indicated above, a spatial modulation of the behavior of the diode 1 may be achieved by a corresponding design of the anode region 102 and / or the cathode region 103, wherein a few examples are presented below:Generally, the anode region 102 may be laterally structured in the active region 1- 1. Additionally or alternatively, the cathode region 103 may be laterally structured. The lateral structures of these regions may be selected according to the lateral structure of the active region 1- 1 based on the inactive sub-region(s) and active sub-region(s).Referring again to FIG. 5, the anode region 102 may be structured such that the dopant concentration in the structure portions 102- 1 (i.e., those portions of the anode region 102 that form a portion of the inactive sub-region(s) 1- 10) is lower compared to the dopant concentration in the emitter portions 102- 2 (i.e., those portions of the anode region 102 that form a portion of the active sub-region(s)). Of course, such a difference in dopant concentration may result in a corresponding ripple of the course of the pn-junction 1021; e.g. the pn-junction 1021 may be closer to the front side 110 in the inactive sub-region(s) 1- 10 due to the reduced dopant concentration compared to the active sub-region(s) 1- 11. In an embodiment, the body region 102 does not extend or only slightly extends into the inactive(s) sub-region(s) 1- 11, such that no structure portions 102- 1 are implemented and the pn-junction 1021 is accordingly interrupted in the lateral direction X, as illustrated in FIG. 7. In another extreme, the anode region 102 is not patterned, but extends laterally with a substantially spatially homogeneous dopant concentration into both the active sub-regions 1- 10 and the inactive sub-regions 1- 11, which consist e.g. of only emitter parts 102- 2 merging seamlessly into each other, as illustrated in FIG. 6. Essentially, depending on the desired anode efficiency, one of the extremes as well as "intermediate solutions" such as a reduced dopant concentration in the structural parts 102- 2 are possible, which can also be realized based on a respective VLD design (VLD, variation of the lateral doping). That is, in an embodiment, the anode region 102 has a VLD profile in which the anode region 102 laterally overlaps with the blocking surface 102- 131 of the at least one inactive sub-region 1- 11 (e.g. with a minimum dopant concentration at a middle portion of the respective structure part 102- 1 and an increasing dopant concentration towards the adjacent emitter parts 102- 2). Generally, compared to where the anode region 102 laterally overlaps with the blocking surface 102- 131 of the at least one inactive sub-region 1- 11, the anode region 102 may have a higher (average) dopant concentration where the anode region 102 laterally overlaps with the at least one first interface 102- 11.Similar considerations apply with respect to the cathode region 103. In an embodiment, as illustrated in FIG. 8, the cathode region 103 in the active region 1- 1 is not laterally structured, but consists of substantially identically doped emitter parts 103- 2 which merge seamlessly into one another, whereby a laterally homogeneously doped cathode region 103 is formed. The extension 103- 3 of the cathode region 103 may have the same dopant concentration as the emitter portions 103- 2 or a different dopant concentration therefrom.According to the embodiment of FIG. 9, the structure portions 103- 1 of the cathode region 103 in the inactive subregion(s) 1- 11 are more weakly doped compared to the emitter portions 103- 2 in the active region(s) 1- 10. It is also possible in other embodiments that the structure parts 103- 1 of the cathode region 103 in the inactive subregion(s) 1- 11 are more heavily doped compared to the emitter parts 103- 2 in the active subregion(s) 1- 10.In an embodiment, the extension 103- 3 of the cathode region 103 may have a lower dopant concentration than the emitter portions 103- 2. Additionally or alternatively, the structure portions 102- 1 of the anode region 102 in the active sub-region(s) 1- 11 may be more weakly doped compared to the emitter portions 102- 2 of the anode region 102 in the active sub-region(s) 1- 10. In another embodiment, the structure portions 102- 1 of the anode region 102 in the inactive sub-region(s) 1- 11 may be more heavily doped compared to the emitter portions 102- 2 of the anode region 102 in the active sub-region(s) 1- 10.According to an embodiment, as illustrated in FIGS. 10-11, the emitter portions 103- 2 and / or the structure portions 103- 1 of the cathode region 103 may include sub-structures. For example, each of the emitter parts 103- 2 comprises one or more highly doped sub-portions 103- 22 and one or more weakly doped sub-portions 103- 21, and each of the structure parts 103- 1 comprises one or more highly doped sub-portions 103- 12 and one or more weakly doped sub-portions 103- 11. The highly doped sub-portions 103- 12 / 103- 22 and the lightly doped sub-portions 103- 11 / 103- 21 may be arranged to be laterally arranged with respect to each other and positioned and dimensioned as appropriate for the specified characteristics of the diode 1. Furthermore, the extension 103- 3 of the cathode region may also include one or more highly doped sub-portions 103- 32 (e.g. in a region adjacent to the active region 1- 1) and one or more weakly doped sub-portions 103- 31 (e.g. in a region adjacent to the edge 1- 4).In yet another embodiment, as illustrated in FIG. 11, the structural part(s) 103- 1 and / or the extension 103- 3 of the cathode region may / may be of the second conductivity type, and / or the one or more lightly doped subsection(s) 103- 21 of the emitter parts 103- 2 of the cathode region 103 may / may also be of the second conductivity type.According to another embodiment, the cathode region 103 and / or the anode region 102 is / are structured in the inactive sub-region(s) 1- 11 and homogeneously formed in the active sub-region(s) 1- 10.According to an embodiment, the cathode region 103 is laterally structured according to the lateral structure of the anode region 102 schematically illustrated in FIG. 12. According to a variant illustrated in part (1) of FIG. 12, for example, the lateral pitch of the emitter parts 103- 2 of the cathode region 103 is matched to the lateral pitch of the emitter parts 102- 2 of the anode region 102, and the lateral dimensions of the structure parts 103- 1 of the cathode region 103 correspond to the lateral dimension of the structure parts 102- 1 of the anode region 102 / the insulating layers 131 (e.g. as also shown in FIGS. 9, 10 and 11 ) in the process variants. For example, depending on the determined characteristics of the diode 1, the emitter portions 103- 2 of the cathode region 102 may also be laterally larger than the emitter portions 102- 2 of the anode region 102 as illustrated in part (2) of FIG. 12 (and the structure portions 103- 1 of the cathode region 102 may accordingly be laterally smaller than the structure portions 102- 1 of the anode region 102) or vice versa as illustrated in part (3) of FIG. 12.In another embodiment, the pattern of the anode region 102 and the pattern of the cathode region 103 are different from each other. For example, referring to part (1) of FIG. 13, the structure of the cathode region 103 may be oriented along a direction perpendicular to the orientation of the structure of the anode region 102, or at any other angle. In another variant, the structure of the cathode region 103 may be based on circular and circle-complementary regions, while the structure of the anode region 102 may have a stripe-shaped structure.A power semiconductor package is also presented herein, wherein both FIGS. 14 and 15 schematically and exemplarily illustrate a portion of a vertical cross-section of a power semiconductor package 8 (i.e., only portions thereof), in accordance with some embodiments. The power semiconductor package 8 comprises one or more single chip power diodes 1 according to one or more of the embodiments described above.As described above, the first load terminal 11, e.g. a front side metallization thereof, may extend over the insulating layer(s) 131 of the inactive sub-region / sub-regions 1- 11, as also illustrated in FIGS. 14 and 15. That is, in the inactive sub-region(s) 1- 11, the first load terminal is not coupled to the semiconductor body 10, but to the respective insulating layer 131. The insulating layer 131 may thus partially function as a carrier for the first load terminal 11.The power semiconductor package 8 may comprise one or more bond wires 15 for electrically contacting the first load terminal / terminals of the single chip power diode(s) 1. According to the variant illustrated in FIG. 14, the bond wire / bond wires may / may be coupled to the first load terminals in regions corresponding to vertical projections of the active sub-regions 1- 10. For example, the interface between the respective bond wire 15 and the respective portion of the first load terminal 11 laterally overlaps with the emitter parts 102- 2 of the anode region 102.Furthermore, in an embodiment, the first load terminal 11 is laterally structured in that the insulating layer(s) 131 is / are not or only partially covered by metallization of the first load terminal 11.In another embodiment, as illustrated in FIG. 15, in a region in which the lateral overlap with the insulating layer 131 is formed, the bond wire 15 is coupled, e.g. bonded, to the first load terminal 11. By providing the bond wires 15 only at such regions, the risk of damage to the semiconductor body 10 during the bonding process may be reduced. A combination of both approaches (FIGS. 14 and 15 ) is also possible.FIG. 16 schematically and exemplarily illustrates a portion of a vertical cross section (part ( 1)) and a portion of a horizontal projection (part ( 2)) of the diode 1 as included in the power semiconductor package 8, according to one or more embodiments. For example, the package 8 comprises a heat sink 5, a thermal coupling layer 4 (such as a thermal foil), an electrically conductive lead frame 3 (e.g. made of copper) coupled via the second load terminal 12 to (a) back side(s) 120 of the semiconductor body(s) 10, which may comprise a die attach layer. The first load terminal 11 is provided on the front side(s) 110 of the semiconductor body / s 10. The horizontal projection illustrated in part (2) of FIG. 16 shows a configuration of a diode 1 included in the package 8, and accordingly, the active region 1- 1 surrounded by the envelope 1- 2 surrounded by the edge termination region 1- 3 is equally divided into the active and inactive sub-regions 1- 10 and 1- 11, wherein both the active sub-regions 1- 10 and the inactive sub-regions 1- 11 have a stripe configuration and, as illustrated, are alternately arranged side by side. Each of the active sub-regions 1- 10 and the inactive sub-regions 1- 11 may have the same width of e.g. 400 μm, which is also the above-mentioned lateral minimum extension MLE. Further dimensions are for example as follows:First load connection 113 μmSemiconductor body 10100 μmSecond load connection 1260 μmLead Frame 32 mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mmHeat coupling layer 4150 μmHeat sink 510 mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mmThe package 8 may be a discrete package and may include one or more of the diodes 1 described above.There is also provided herein a method of manufacturing a single chip power diode, the method comprising forming the following components: a first load terminal, a second load terminal, and between the first load terminal and the second load terminal, a semiconductor body comprising an anode region coupled to the first load terminal, a cathode region coupled to the second load terminal, and between the anode region and the cathode region a drift region; an active region configured to conduct a load current between the load terminals based on the anode region, the drift region, and the cathode region, wherein a thickness of the semiconductor body is defined by a distance between at least a first interface formed between the first load terminal and the anode region and a second interface formed between the second load terminal and the cathode region; an edge termination region surrounding the active region and terminated by a chip edge. Further, the method comprises including at least one inactive sub-region in the active region, each inactive sub-region comprising: a blocking surface having a minimum lateral extension of at least 20% of a drift region thickness; configured to prevent a passage of the load current between the first load terminal and the semiconductor body through the blocking surface; and at least partially not arranged next to the edge termination region.Embodiments of the method correspond to embodiments of the diode 1 and the embodiment of the housing 8 described above.Above, embodiments related to power semiconductor devices such as diodes and respective processing methods have been explained. These power semiconductor devices are based on silicon (Si), for example. Accordingly, a monocrystalline(s) semiconductor region or layer, e.g. the semiconductor body 10 and its regions / zones, e.g. regions etc., a monocrystalline(s) may be Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.It should be appreciated, however, that the semiconductor body 10 and its regions / zones may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), Aluminum gallium indium nitride (AlGaInN) or Indiumgalliumarsenidphosphid (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The above-mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When combining two different semiconductor materials, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For applications with power semiconductor switches, Si, SiC, GaAs and GaN materials are mainly used at present.Spatial terms such as "below," "below," "lower," "over," "upper," and the like are used to describe the positioning of an element relative to a second element for convenience of description. These terms are intended to include different orientations of the respective device in addition to orientations different from those depicted in the figures. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.

Claims

A single-chip power diode (1) comprising: - a first load terminal (11), a second load terminal (12), and between the first load terminal (11) and the second load terminal (12), a semiconductor body (10) comprising an anode region (102) coupled to the first load terminal (11), a cathode region (103) coupled to the second load terminal (12), and between the anode region (102) and the cathode region (103), a drift region (100); an active region (1-1) configured to conduct a load current between the load terminals (11, 12) based on the anode region (102), the drift region (100) and the cathode region (103), wherein a thickness of the semiconductor body (10) is defined by a distance (d) between at least a first interface (102-11) formed between the first load terminal (11) and the anode region (102) and a second interface (103-12) formed between the second load terminal (12) and the cathode region (103); an edge termination region (1-3) surrounding the active region (1-1) and terminated by a chip edge (1-4); wherein at least one inactive sub-region (1-11) is included in the active region (1-1), wherein each inactive sub-region (1-11) comprises: - a blocking surface (102-131) having a minimum lateral extension (MLE) of at least 20% of a drift region thickness (dd); - configured to prevent a passage of the load current between the first load terminal (11) and the semiconductor body (10) through the blocking surface (102-131); and - at least partially not arranged next to the edge termination region (1-3); and wherein - the anode region (102) is laterally structured with respect to the at least one inactive sub-region (1-11) in the active region (1-1).The single chip power diode (1) according to claim 1, wherein each of the at least one first interface (102-11) allows a passage of the load current, and wherein the sum of each of the at least one first interface (102-11) totals at least 10% of the lateral area of the active region (1-1) and totals no more than 90% of the lateral area of the active region (1-1).The single chip power diode (1) according to claim 1 or 2, wherein the sum of each of the at least one blocking surface (102-131) totals at least 10% of the lateral surface of the active region (1-1) and totals no more than 90% of the lateral surface of the active region (1-1).The single chip power diode (1) according to claim 2 or 3, wherein the lateral surface of the active region (1-1) is defined by an envelope surrounding outermost portions of the at least one first interface (102-11) in the active region (1-1).The single-chip power diode (1) according to any of the preceding claims, wherein the at least one inactive sub-region (1-11) comprises an insulating layer (131), wherein the insulating layer (131) forms the blocking surface (102-131) of the at least one inactive sub-region (1-11).The single-chip power diode (1) according to claim 5, wherein the first load terminal (11) overlaps with the insulating layer (131) of the at least one inactive sub-region (1-11).The single-chip power diode (1) according to any of the preceding claims, wherein the cathode region (103) is laterally structured in the active region (1-1).The single chip power diode (1) according to claim 7, wherein the cathode region (103) is laterally structured according to the lateral structure of the anode region (102).The single-chip power diode (1) according to any of the preceding claims, wherein - the anode region (102) has a higher dopant concentration compared to where the anode region (102) laterally overlaps with the blocking surface (102-131) of the at least one inactive sub-region (1-11), where the anode region (102) laterally overlaps with the at least one first interface (102-11); or wherein - the anode region (102) is not provided in regions overlapping with the blocking surface (102-131) of the at least one inactive sub-region (1-11).The single-chip power diode (1) according to any of the preceding claims, wherein the cathode region (103) has a higher dopant concentration compared to where the cathode region (103) laterally overlaps with the blocking surface (102-131) of the at least one inactive sub-region (1-11) where the cathode region (103) laterally overlaps with the at least one first interface (102-11).The single-chip power diode (1) according to any of the preceding claims, wherein an anode efficiency of the single-chip power diode (1) is spatially modulated within the active region (1-1).The single-chip power diode (1) according to any of the preceding claims, wherein the blocking surface (102-131) of the at least one inactive sub-region (1-11) in the active region (1-1) structures the active region (1-1) into at least two spatially separated active sub-regions (1-10).The single-chip power diode (1) according to claim 12, wherein a distance between each two of the at least two spatially separated active sub-regions (1-10) amounts to the minimum lateral extension (MLE).Single-chip power diode (1) according to any of the preceding claims, comprising only an inactive sub-region (1-11) extending continuously in the active region (1-1).The single chip power diode (1) according to claim 12 or 13, comprising more than one inactive sub-region (1-11), wherein the inactive sub-regions (1-11) are arranged between or around the spatially separated active sub-regions (1-10).The single-chip power diode (1) according to any of the preceding claims 14-17, wherein each of at least 90% of the active sub-regions (1-10) has a respective first interface (102-11) and has an area with a minimum lateral extension of at least 20% of the drift region thickness (dd).The single chip power diode (1) according to any of the preceding claims, wherein each of at least 90% of the one or more inactive sub-regions (1-11) has a respective blocking surface (102-131) and has a surface with a minimum lateral extension (MLE) of at least 20% of the drift region thickness (dd).The single chip power diode (1) according to any of the preceding claims, wherein the sum of one or more of the first interfaces (102-11) and the one or more blocking areas (102-131) amounts to the lateral area of the active region 1-1).A method for manufacturing a single chip power diode (1), the method comprising forming the following components: - a first load terminal (11), a second load terminal (12), and between the first load terminal (11) and the second load terminal (12) a semiconductor body (10) comprising an anode region (102) coupled to the first load terminal (11), a cathode region (103) coupled to the second load terminal (12), and between the anode region (102) and the cathode region (103) a drift region (100); an active region (1-1) configured to conduct a load current between the load terminals (11, 12) based on the anode region (102), the drift region (100) and the cathode region (103), wherein a thickness of the semiconductor body (10) is defined by a distance (d) between at least a first interface (102-11) formed between the first load terminal (11) and the anode region (102) and a second interface (103-12) formed between the second load terminal (12) and the cathode region (103); an edge termination region (1-3) surrounding the active region (1-1) and terminated by a chip edge (1-4); wherein the method further comprises incorporating at least one inactive sub-region (1-11) in the active region (1-1), wherein each inactive sub-region (1-11): - has a blocking surface (102-131) having a minimum lateral extension (MLE) of at least 20% of a drift region thickness (dd); - is configured to prevent passage of the load current between the first load terminal (11) and the semiconductor body (10) through the blocking surface (102-131); and - is at least partially not arranged next to the edge termination region; and wherein the method further comprises: laterally patterning the anode region (102) with respect to the at least one inactive sub-region (1-11) in the active region (1-1).

Images