Semiconductor device and method

Abstract

Device comprising: a first Finn (54); a gate structure (100) above the first fin; a first source / drain region (92) adjacent to the gate structure (100); an etch stop layer (94) over the first source / drain region (92); a conductor track (118) in a trench over the first source / drain region (92), which is surrounded laterally and towards the first source / drain region by the etch stop layer (94), whereby the conductor track is isolated from the first source / drain region (92) by the etch stop layer (94) and wherein a top surface of the conductor track (118) is coplanar with a top surface of the gate structure (100); and a busbar contact (158) extending through the first fin (54), wherein the busbar contact (158) is connected to the first source / drain region (92P).

Description

BACKGROUND

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric, conductive, and semiconductor material layers onto a semiconductor substrate, and then lithographically structuring the different material layers to create circuit components and elements.

[0002] The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by steadily reducing the minimum feature size, thus making it possible to integrate more components into a given area. However, reducing the minimum feature size introduces new problems that require solutions.

[0003] The prior art relevant to the present invention is given by US 2005 / 0042867A1 and DE 102018127446A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates an example of simplified nanostructured field-effect transistors (nano-FETs) according to some embodiments. The Fig. Figures 2 to 19D are different views of intermediate stages in the manufacture of semiconductor devices according to some embodiments. The Fig. Figures 20 to 27D show different views of further intermediate stages in the manufacture of semiconductor devices according to some embodiments. The Fig. Figures 28A to 28D are different views of semiconductor devices according to some further embodiments. Fig. Figure 29 shows a cross-sectional view of semiconductor devices according to some further embodiments. DETAILED DESCRIPTION

[0005] The invention is defined by the subject matter of the independent claims. Specific embodiments are given by the additional features of the dependent claims. The following disclosure provides many different embodiments and examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples.For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals may be repeated in the disclosure given to the various examples. This repetition serves the purpose of simplicity and clarity and does not, in principle, prescribe any relationship between the various embodiments and / or configurations described herein.

[0006] Furthermore, terms describing spatial relationships, such as "below," "down," "above," "above," "upward," and similar terms, are used herein, where necessary for the sake of simplicity, to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the drawings. These spatial relationship terms are intended to encompass not only the orientation depicted in the drawings but also other orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial relationship descriptions used herein may be interpreted analogously.

[0007] According to various embodiments, a semiconductor device (semiconductor device) is formed that has a component layer (device layer) arranged between two interconnect structures. The component layer contains transistors, e.g., nanostructured field-effect transistors (nanoFETs). One of the interconnect structures is located on the front side of the component layer and has conductive features that connect the transistors of the component layer to each other to form functional circuits. The other interconnect structure is located on the back side of the component layer and has conductive features that are used to provide power circuits for the component layer. Specifically, the backside interconnect structure has dedicated power rails for providing a reference voltage, supply voltage, or similar to the functional circuits.The busbars are located on the back sides of the source / drain regions of the transistors in the component layer. Contacts with the front sides of these source / drain regions are therefore undesirable and are not formed. Avoiding the formation of such contacts can improve the performance of the transistors and frees up space in the component layer that can be used for other purposes, such as the creation of additional traces for interconnect routing.

[0008] Fig. Figure 1 illustrates an example of simplified nano-FETs according to some embodiments. Fig. Figure 1 is a three-dimensional sectional view, with some features of the nano-FETs omitted for clarity. The nano-FETs may be nanosheet field-effect transistors (NS-FETs), nanowire field-effect transistors (NWFETs), gate all-around field-effect transistors (GAAFETs), or similar.

[0009] The nanoFETs have nanostructures 56 above a substrate 50, for example, above fins 54 extending from the substrate 50. The nanostructures 56 are semiconductor layers that act as channel regions 68 for the nanoFETs. Insulation regions 60, for example, shallow trench insulation regions (STI regions), are arranged above the substrate 50 and between adjacent fins 54, which may protrude above and between adjacent insulation regions 60. Although the insulation regions 60 are described / illustrated as separate from the substrate 50, the term "substrate" as used here can refer to the substrate 50 alone or to a combination of the substrate 50 and the insulation regions 60.Although the fins 54 are illustrated as individual materials associated with the substrate 50, the fins 54 and / or the substrate 50 can consist of a single material or multiple materials. In this context, the fins 54 refer to the section extending over and between the adjacent isolation regions 60.

[0010] Gate structures 100 are wound around the nanostructures 56 and arranged over the fins 54. The gate structures 100 have gate dielectrics 102 and gate electrodes 104. The gate dielectrics 102 are located along the top, side, and bottom surfaces of the nanostructures 56 and can extend along side surfaces and / or over the top surfaces of the fins 54. The gate electrodes 104 are located on the gate dielectrics 102. Epitaxial source / drain regions 92 are arranged on opposite sides of the gate structures 100. In embodiments in which multiple transistors are formed, the epitaxial source / drain regions 92 can be used by different transistors.For example, adjacent epitaxial source / drain regions 92 can be electrically coupled, such as by connecting the epitaxial source / drain regions 92 through epitaxial growth or by coupling the epitaxial source / drain regions 92 to an identical source / drain contact. One or more interlayer dielectric layers (ILD layers) (explained in more detail below) are located above the epitaxial source / drain regions 92 and / or the gate structures 100, through which contacts (explained in more detail below) are formed to the epitaxial source / drain regions 92 and the gate electrodes 104. The epitaxial source / drain regions 92 and the gate electrodes 104 are interconnected to form functional circuits.As explained in more detail below, a first subset of the epitaxial source / drain regions 92P is connected to dedicated power rails to provide a reference voltage, supply voltage or the like to the circuits, while a second subset of the epitaxial source / drain regions 92S is not connected to the dedicated power rails.

[0011] Some embodiments discussed here are addressed in the context of nanoFETs fabricated using a gate-load process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs).

[0012] Fig. Figure 1 further illustrates a reference cross-section used in subsequent figures. Cross-section AA runs along a longitudinal axis of a nanostructure 56 and, for example, in a current flow direction between the epitaxial source / drain regions 92. Cross-section BB runs perpendicular to cross-section AA and along a longitudinal axis of a gate structure 100. Cross-section CC runs perpendicular to cross-section AA through the epitaxial source / drain regions 92S. Cross-section DD runs perpendicular to cross-section AA through the epitaxial source / drain regions 92P. For clarity, subsequent figures refer to this reference cross-section.

[0013] The Fig. Figures 2 to 19D show different views of intermediate stages in the fabrication of semiconductor devices according to some embodiments. Specifically, the fabrication of a component layer of nano-FETs is illustrated. Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are three-dimensional views that provide a similar three-dimensional view to Fig. Show 1. The Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A and Fig. 19A are cross-sectional views that run along the reference cross-section AA in Fig. 1 are shown. Fig. 10B, Fig. 11B, Fig. 13B and Fig. 19B are cross-sectional views that follow the reference cross-section BB in Fig. 1 are shown. Fig. 7B, Fig. 8B, Fig. 9B and Fig. 9C are cross-sectional views taken along one of the reference cross-sections CC or DD in Fig. 1 are shown, except that two Finns are depicted. Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B and Fig. 19C are cross-sectional views that are aligned along the reference cross-section CC in Fig. 1 are shown, except that two Finns are depicted. Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C and Fig. 19D are cross-sectional views that run along the reference cross-section DD in Fig. 1 are shown, except that two Finns are shown. Fig. Figure 18 is a top view.

[0014] In Fig. 2. A substrate 50 is provided to form nanoFETs. The substrate 50 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or similar, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Essentially, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or similar. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, can also be used.In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor containing silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0015] Substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-type devices, for example, NMOS transistors, e.g., n-nanoFETs, and the p-region 50P can be used to form p-type devices, for example, PMOS transistors, e.g., p-nanoFETs. The n-region 50N can be physically separated from the p-region 50P (not shown separately), and any number of device features (e.g., additional active components, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P.

[0016] Substrate 50 can be readily doped with a p- or n-type foreign material. Anti-punch-through (APT) implantation can be performed on an upper portion of substrate 50 to form an APT region. During APT implantation, dopants can be implanted into the n-region 50N and the p-region 50P. The dopants can have a conductivity type that is opposite to the conductivity type of source / drain regions subsequently formed in the n-region 50N and the p-region 50P, respectively. The APT region can extend beneath subsequently formed source / drain regions in the nanoFETs formed in later processes. The APT region can be used to reduce leakage from the source / drain regions into substrate 50. In some embodiments, the doping concentration in the APT region can be in the range of approximately 10 18 cm -3 up to about 10 19 cm -3 lay.

[0017] A multilayer stack 52 is formed on top of the substrate 50. The multilayer stack 52 comprises alternating first semiconductor layers 52A and second semiconductor layers 52B. The first semiconductor layers 52A are formed from a first semiconductor material, and the second semiconductor layers 52B are formed from a second semiconductor material. The semiconductor materials can each be selected from the semiconductor materials suitable for the substrate 50. In the illustrated embodiment, the multilayer stack 52 comprises four layers each of the first semiconductor layers 52A and the second semiconductor layers 52B. It should be noted that the multilayer stack 52 can have any number of first semiconductor layers 52A and second semiconductor layers 52B.

[0018] In the illustrated embodiment, the second semiconductor layers 52B are used to form channel regions for the nanoFETs in both the n-region 50N and the p-region 50P. The first semiconductor layers 52A are sacrificial (or dummy) layers that are subsequently removed to expose the top and bottom surfaces of the second semiconductor layers 52B in both regions. The second semiconductor material of the second semiconductor layers 52B is a material suitable for both n- and p-nanoFETs, for example, silicon, and the first semiconductor material of the first semiconductor layers 52A is a material exhibiting high etch selectivity with respect to the second semiconductor material, for example, silicon-germanium.

[0019] In another embodiment, the first semiconductor layers 52A are used to form channel regions for the nanoFETs in one region (e.g., the p-region 50P), and the second semiconductor layers 52B are used to form channel regions for the nanoFETs in another region (e.g., the n-region 50N). The first semiconductor material of the first semiconductor layers 52A can be suitable for p-nanoFETs, for example, silicon germanium (e.g., SixGe1-x, where x can be in the range of 0 to 1), pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like, and the second semiconductor material of the second semiconductor layers 52B can be suitable for n-nanoFETs, for example, silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like.The first semiconductor material and the second semiconductor material can exhibit high etch selectivity towards each other, so that in the n-region 50N the first semiconductor layers 52A can be removed without removing the second semiconductor layers 52B, and in the p-region 50P the second semiconductor layers 52B can be removed without removing the first semiconductor layers 52A.

[0020] Each layer of the multilayer stack 52 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or similar. Each layer can be formed with a small thickness, for example, in the range of about 5 nm to about 30 nm. In some embodiments, one group of layers (e.g., the second semiconductor layers 52B) is formed thinner than another group of layers (e.g., the first semiconductor layers 52A).In embodiments where the first semiconductor layers 52A are sacrificial (or dummy) layers and the second semiconductor layers 52B are used to form channel regions, the first semiconductor layers 52A can, for example, be formed with a first thickness T1 and the second semiconductor layers 52B with a second thickness T2, the second thickness T2 being about 30% to 60% less than the first thickness T1. By forming the second semiconductor layers 52B with a smaller thickness, the channel regions can be formed at a higher density.

[0021] In Fig. In step 3, grooves are etched into the substrate 50 and the multilayer stack 52 to form fins 54 and nanostructures 56. The fins 54 are structured semiconductor strips in the substrate 50. The nanostructures 56 have the remaining sections of the multilayer stack 52 on the fins 54. Specifically, the nanostructures 56 alternate between first nanostructures 56A and second nanostructures 56B. The first nanostructures 56A and the second nanostructures 56B are formed from remaining sections of the first semiconductor layers 52A and the second semiconductor layers 52B, respectively. After formation, the second nanostructures 56B are arranged in the intermediate layers of the structure between two of the first nanostructures 56A. Etching can refer to any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or a combination thereof.Etching can be done anisotropically.

[0022] The fins 54 and the nanostructures 56 can be structured by any suitable method. For example, the fins 54 and the nanostructures 56 can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-alignment processes, thereby enabling the creation of structures that, for example, exhibit smaller spacings than would otherwise be achievable using a simple direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed, and the remaining spacers can then be used as masks to structure the fins 54 and the nanostructures 56.

[0023] The fins 54 and the nanostructures 56 can have thicknesses in the range of approximately 8 nm to 40 nm. For illustrative purposes, the fins 54 and the nanostructures 56 in the n-region 50N and the p-region 50P are shown with substantially the same widths. In some embodiments, the fins 54 and the nanostructures 56 in one region (e.g., the n-region 50N) can be wider or narrower than the fins 54 and the nanostructures 56 in the other region (e.g., the p-region 50P).

[0024] In Fig. 4 STI regions 60 are formed adjacent to the fins 54. The STI regions 60 can be formed by depositing an insulating material over the substrate 50 and the nanostructures 56 and between adjacent fins 54. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, similar materials, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), similar processes, or a combination thereof. Other insulating materials formed by any acceptable process can also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be carried out.In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 56. Although the insulating material is shown as a single layer, some embodiments can utilize multiple layers. For example, in some embodiments, a lining can first be formed along the surfaces of the substrate 50, the fins 54, and the nanostructures 56. Subsequently, a filler material such as those described above can be formed over the lining.

[0025] Subsequently, a removal process is applied to the insulating material to remove excess insulating material covering the nanostructures 56. In some embodiments, a planarization process such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or similar processes can be used. The planarization process exposes the nanostructures 56 such that, after completion of the planarization process (within process deviations), the respective top surfaces of the nanostructures 56 and the insulating material are coplanar.

[0026] The insulating material is then recessed to form the STI regions 60. The insulating material is recessed such that at least one section of the nanostructures 56 protrudes between adjacent STI regions 60. In the illustrated embodiment, the top surfaces of the STI regions 60 are coplanar with the top surfaces of the fins 54 (within process variations). In some embodiments, the top surfaces of the STI regions 60 lie above or below the top surfaces of the fins 54. Furthermore, the top surfaces of the STI regions 60 can have a flat surface as shown, a convex surface, a concave surface (in a bowl shape), or a combination thereof. The top surfaces of the STI regions 60 can be formed as flat, convex, and / or concave by a suitable etching process.The STI regions 60 can be deepened by means of an acceptable etching process, for example one that is selective with respect to the insulating material (e.g., selectively etching the insulating material of the STI regions 60 at a faster rate than the materials of the fins 54 and the nanostructures 56). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) can be employed.

[0027] The process described above is just one example of how the fins 54 and the nanostructures 56 can be formed. In some embodiments, the fins 54 and the nanostructures 56 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be deepened such that the epitaxial structures protrude from the dielectric layer to form the fins 54 and the nanostructures 56. The epitaxial structures can have the alternating semiconductor materials discussed above, such as the first semiconductor material and the second semiconductor material.In embodiments in which epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thereby eliminating the need for prior and / or subsequent implantations, although doping in situ and by implantation can also be used together.

[0028] Furthermore, suitable wells can be formed in the substrate 50, the fins 54, and / or the nanostructures 56. In some embodiments, a p-well can be formed in the n-region 50N and an n-well in the p-region 50P. In another embodiment, p-wells or n-wells can be formed in both the n-region 50N and the p-region 50P.

[0029] In embodiments with different well types, various implantation steps for the n-region 50N and the p-region 50P can be achieved using a photoresist or other masks. For example, a photoresist can be formed over the fin 54, the nanostructures 56, and the STI regions 60 in the n-region 50N. The photoresist is structured to expose the p-region 50P. The photoresist can be formed using a spin-deposition technique and structured using acceptable photolithography techniques. Once the photoresist is structured, n-foreign substances are implanted into the p-region 50P, with the photoresist acting as a mask to essentially prevent the implantation of n-foreign substances into the n-region 50N. The n-foreign substances can be phosphorus, arsenic, antimony, or similar elements, which are introduced into the region at a concentration in the range of approximately 10 13 cm -3 up to about 10 14 cm -3The photoresist is implanted. After implantation, it is removed, for example by an acceptable ashing process.

[0030] Following the implantation of the p-region 50P, a photoresist is formed over the fin 54, the nanostructures 56, and the STI regions 60 within the p-region 50P. The photoresist is structured to expose the n-region 50N. It can be formed using spin coating and structured using acceptable photolithography techniques. Once the photoresist is structured, p-substances can be implanted into the n-region 50N. The photoresist can act as a mask to essentially prevent the implantation of p-substances into the p-region 50P. These p-substances can be boron, boron trifluoride, indium, or similar materials, introduced into the region at a concentration of approximately 10⁻⁵. 13 cm -3 up to about 10 14 cm -3The photoresist can be implanted. After implantation, it can be removed, for example by an acceptable ashing process.

[0031] Following the implantation of the n-region 50N and the p-region 50P, annealing can be performed to repair implantation damage and activate the implanted p- and / or n-substances. In some embodiments, the grown materials of the epitaxial fins can be doped in situ during growth, thus eliminating the need for implantation; however, in situ and implantation-based doping can also be used together.

[0032] In Fig. A dummy dielectric layer 62 is formed on the fins 54 and the nanostructures 56. The dummy dielectric layer 62 can be, for example, silicon oxide, silicon nitride, a combination thereof, or similar materials, and can be deposited or thermally grown using acceptable techniques. A dummy gate layer 64 is formed over the dummy dielectric layer 62, and a mask layer 66 is formed over the dummy gate layer 64. The dummy gate layer 64 can be deposited over the dummy dielectric layer 62 and then planarized, for example, by a CMP process. The mask layer 66 can be deposited over the dummy gate layer 64.The dummy gate layer 64 can be a conductive or non-conductive material and can be selected from a group that includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer 64 can be deposited by physical vapor deposition (PVD), continuous vapor deposition (CVD), sputtering, or other techniques for depositing the selected material. The dummy gate layer 64 can be made of one or more materials that exhibit high etch selectivity with respect to insulating materials, such as the one or more materials of the STI regions 60 and / or the dummy dielectric layer 62. The mask layer 66 can comprise one or more layers of, for example, silicon nitride, silicon oxynitride, or the like.In this example, a single dummy gate layer 64 and a single mask layer 66 are formed over the n-region 50N and the p-region 50P. Although it is shown that the dummy dielectric layer 62 covers the STI regions 60, it should be noted that the dummy dielectric layer 62 can also be formed in other ways. In some embodiments, for example, when the dummy dielectric layer 62 is thermally grown, the dummy dielectric layer 62 is formed such that it only covers the fins 54 and the nanostructures 56.

[0033] In Fig. In step 6, the mask layer 66 is structured using acceptable photolithography and etching techniques to form masks 76. The structure of the masks 76 is then transferred to the dummy gate layer 64 using an acceptable etching technique to form dummy gates 74. Optionally, the structure of the masks 76 can also be transferred to the dummy dielectric layer 62 using an acceptable etching technique to form dummy dielectrics 72. The dummy gates 74 cover sections of the nanostructures 56 that are exposed in subsequent processing to form channel regions. Specifically, the dummy gates 74 extend along the sections of the nanostructures 56 that are used to form channel regions 68. The structure of the masks 76 can be used to physically separate adjacent dummy gates 74.The dummy gates 74 can also have longitudinal directions which (within process deviations) run essentially perpendicular to the longitudinal directions of the fins 54. The masks 76 can optionally be removed after structuring, for example by an acceptable etching technique.

[0034] The Fig. Figures 7A to 19D illustrate further intermediate steps in the fabrication of nano-FETs. Fig. Figures 7A to 19D can be applied to both the n-region 50N and the p-region 50P. Differences (if any) in the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

[0035] In the Fig. 7A and Fig. Gate spacers 80 are formed on exposed sidewalls of the masks 76 (if present), the dummy gates 74, and the dummy dielectrics 72 above the nanostructures 56 and the fins 54. The gate spacers 80 can be formed by conformal forming of an insulating material and subsequent etching of the insulating material. The insulating material of the gate spacers 80 can be silicon nitride, silicon carbonitride, silicon oxycarbonitride, combinations thereof, or similar materials, and they can be formed by thermooxidation, deposition, a combination thereof, or similar processes. The gate spacers 80 can be formed from a single layer of insulating material or from multiple layers of insulating materials. In some embodiments, the gate spacers 80 each have multiple layers of silicon oxycarbonitride, each layer having a different silicon oxycarbonitride composition.In some embodiments, the gate spacers 80 each have a layer of silicon oxide sandwiched between two layers of silicon nitride. Other spacer structures can also be formed. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etching process such as RIE, NBE, or similar. After etching, the gate spacers 80 can have straight or curved sidewalls. In the illustrated embodiment, the gate spacers 80 are formed on the top surfaces of the STI regions 60, thus blocking subsequent epitaxial growth.

[0036] Prior to the formation of the gate spacers 80, implantations for lightly doped source / drain regions (LDD regions) can be performed. In embodiments with different component types, a mask, such as a photoresist, can be formed over the n-region 50N, similar to the implantations described above, leaving the p-region 50P exposed. Foreign materials of a suitable type (e.g., p-type foreign materials) can then be implanted into the nanostructures 56 and fins 54 exposed in the p-region 50P. The mask can then be removed.The n-type foreign substances can be any of the previously treated n-type foreign substances, and the p-type foreign substances can be any of the previously treated p-type foreign substances. The lightly doped source / drain regions can have a foreign substance concentration in the range of approximately 10. 15 cm -3 up to about 10 19 cm -3 exhibiting [unclear text]. A tempering process can be used to repair implantation damage and activate the implanted foreign materials. During implantation, the canal regions 68 remain covered by the dummy gates 74, so that the canal regions 68 remain essentially free of the foreign material implanted into the LDD regions.

[0037] It is noted that the foregoing disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences can also be used. For example, fewer or additional spacers can be used, a different sequence of steps can be used (e.g., additional spacers can be formed and removed, etc.), and / or similar. Furthermore, the n- and p-type devices can be formed using different structures and steps.

[0038] In the Fig. 8A and Fig. Source / drain depressions 82 are formed in the nanostructures 56. In the illustrated embodiment, the source / drain depressions 82 extend through the nanostructures 56 such that they expose the fins 54. The source / drain depressions 82 can also extend into the substrate 50 and / or the fins 54. In various embodiments, the source / drain depressions 82 can extend to a top surface of the substrate 50 without etching the substrate 50, the substrate 50 can be etched such that bottom surfaces of the source / drain depressions 82 are located below the top surfaces of the STI regions 60, or similar configurations. The source / drain depressions 82 can be formed by etching the nanostructures 56 using anisotropic etching processes such as RIE, NBE, or similar techniques.During the etching processes used to form the source / drain depressions 82, the gate spacers 80 and the dummy gates 74 together mask sections of the nanostructures 56, the fins 54, and the substrate 50. A single etching process can be used to etch each of the nanostructures 56. In other embodiments, multiple etching processes can be used to etch the nanostructures 56. Time-controlled etching processes can be used to stop the etching of the source / drain depressions 82 after they have reached a desired depth.

[0039] Optionally, inner spacers 84 can be formed on the sidewalls of the remaining sections of the first nanostructures 56A, e.g., the sidewalls exposed by the source / drain depressions 82. As will be explained in more detail below, source / drain regions are subsequently formed in the source / drain depressions 82, and the first nanostructures 56A are subsequently replaced by corresponding gate structures. The inner spacers 84 act as insulating features between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the inner spacers 84 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, for example, etching processes used to form the gate structures.

[0040] As an example of the formation of the inner spacers 84, the source / drain depressions 82 can be laterally extended. Specifically, sections of the sidewalls of the first nanostructures 56A exposed by the source / drain depressions 82 can be deepened. Although the sidewalls of the first nanostructures 56A are shown straight, they can also be concave or convex. The sidewalls can be deepened using an acceptable etching process, for example, one that is selective with respect to the material of the first nanostructures 56A (e.g., the material of the first nanostructures 56A etches selectively at a faster rate than one or more materials of the second nanostructures 56B and the fins 54). The etching can be isotropic.For example, if the fins 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A are formed from silicon germanium, the etching process can be a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process can be a dry etching process using a fluorine-based gas such as hydrogen fluoride gas (HF gas). In some embodiments, the same etching process can be carried out continuously to form both the source / drain depressions 82 and the sidewalls of the first nanostructures 56A. The inner spacers 84 can then be formed by conformal forming of an insulating material and subsequent etching of the insulating material.The insulating material can be a material such as silicon nitride or silicon oxynitride, but any suitable material, such as materials with a low dielectric constant (low-k materials) with a k-value of less than approximately 3.5, can be used. The insulating material can be deposited by a conformal deposition process such as ALD, CVD, or similar. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etching process such as RIE, NBE, or similar. Although it is shown that the outer sidewalls of the inner spacers 84 are flush with the sidewalls of the gate spacers 80, the outer sidewalls of the inner spacers 84 can extend beyond or be recessed relative to the sidewalls of the gate spacers 80.In other words, the inner spacers 84 can partially fill, completely fill, or overfill the side wall recesses. Furthermore, although the side walls of the inner spacers 84 are shown straight, they can also be concave or convex.

[0041] In Fig. Epitaxial source / drain regions 92 are formed in the source / drain depressions 82 at points 9A to 9C. In some embodiments, the epitaxial source / drain regions 92 exert a load on the channel regions 68, thereby improving performance. The epitaxial source / drain regions 92 are formed in the source / drain depressions 82 such that each dummy gate 74 is arranged between respective adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the gate spacers 80 are used to separate the epitaxial source / drain regions 92 from the dummy gates 74, and the inner spacers 84 are used to separate the epitaxial source / drain regions 92 from the first nanostructures 56A by a suitable lateral distance so that the epitaxial source / drain regions 92 are not short-circuited with subsequently formed gates of the resulting nano-FETs.

[0042] The epitaxial source / drain regions 92 in the n-region 50N can be formed by masking the p-region 50P. Subsequently, the epitaxial source / drain regions 92 are epitaxially grown in the source / drain depressions 82 in the n-region 50N. The epitaxial source / drain regions 92 can contain any acceptable material suitable for n-nanoFETs. For example, the epitaxial source / drain regions 92 in the n-region 50N can contain materials that exert tensile stress on the channel regions 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or similar materials. The epitaxial source / drain regions 92 in the n-region 50N may have surfaces that are raised relative to the respective surfaces of the second nanostructures 56B and the fins 54, and may have facets.

[0043] The epitaxial source / drain regions 92 in the p-region 50P can be formed by masking the n-region 50N. Subsequently, the epitaxial source / drain regions 92 are epitaxially grown in the source / drain depressions 82 in the p-region 50P. The epitaxial source / drain regions 92 can contain any acceptable material suitable for p-nanoFETs. For example, the epitaxial source / drain regions 92 in the p-region 50P can contain materials that exert compressive stress on the channel regions 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or similar materials. The epitaxial source / drain regions 92 in the p-region 50P may have surfaces that are raised relative to the respective surfaces of the second nanostructures 56B and the fins 54, and may have facets.

[0044] Similar to the process previously described for the formation of lightly doped source / drain regions, dopants can be implanted into the epitaxial source / drain regions 92, the second nanostructures 56B, and / or the fins 54 to form source / drain regions, followed by an annealing process. The source / drain regions can have a foreign substance concentration in the range of approximately 10 19 cm -3 up to about 10 21 cm -3 exhibiting. The n- and / or p-substances for source / drain regions can be any of the previously discussed substances. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0045] As a result of the epitaxial processes used to form the epitaxial source / drain regions 92 in the n-region 50N and the p-region 50P, the upper surfaces of the epitaxial source / drain regions 92 exhibit facets that widen laterally outwards beyond the sidewalls of the second nanostructures 56B and the fins 54. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is complete, as shown by Fig. Figure 9B illustrates this. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nano-FET to merge, as shown by Fig. Figure 9C illustrates this. In the illustrated embodiment, the gate spacers 80 are formed on the top surfaces of the STI regions 60, thereby blocking epitaxial growth. In some other embodiments, the spacer etching process used to form the gate spacers 80 can be modified to remove the spacer material, allowing the epitaxially grown regions to extend to the top surfaces of the STI regions 60.

[0046] The epitaxial source / drain regions 92 can have one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 can have a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. Any number of semiconductor material layers can be used for the epitaxial source / drain regions 92. The first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer can each be formed from different semiconductor materials and can be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer can have a lower dopant concentration than the second semiconductor material layer and a higher concentration than the third semiconductor material layer.In embodiments in which the epitaxial source / drain regions 92 comprise three semiconductor material layers, the first semiconductor material layer can be deposited, the second semiconductor material layer can be deposited over the first semiconductor material layer, and the third semiconductor material layer can be deposited over the second semiconductor material layer.

[0047] In the Fig. 10A and Fig. 10B, a first ILD 96 is deposited over the epitaxial source / drain regions 92, the gate spacers 80, the masks 76 (if present) or the dummy gates 74, and the STI regions 60. The first ILD 96 can be formed from a dielectric and can be deposited by any suitable process such as CVD, plasma-enhanced CVD (PECVD), FCVD, or similar. Dielectrics can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or similar. Other insulating materials formed by any acceptable process can also be used.

[0048] In some embodiments, a contact etch stop layer (CESL) 94 is formed between the first ILD 96 and the epitaxial source / drain regions 92, the gate spacers 80, and the STI regions 60. The CESL 94 can be formed from a dielectric such as silicon nitride, silicon oxide, silicon oxynitride, or the like, exhibiting high etch selectivity with respect to the first ILD 96. The CESL 94 can be formed by any suitable method, such as CVD, ALD, or the like.

[0049] In the Fig. 11A and Fig. In 11B, a planarization process is performed to bring the top surfaces of the first ILD 96 to the same level as the top surfaces of the masks 76 (if present) or the dummy gates 74. In some embodiments, a planarization process such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or similar processes may be used. The planarization process may also remove the masks 76 on the dummy gates 74 as well as sections of the gate spacers 80 along the side walls of the masks 76. After the planarization process, the top surfaces of the gate spacers 80, the first ILD 96, the CESL 94, and the masks 76 (if present) or the dummy gates 74 (within process deviations) are coplanar. Accordingly, the top surfaces of the masks 76 (if present) or the dummy gates 74 are exposed through the first ILD 96.In the illustrated embodiment, the masks 76 remain, and the planarization process brings the top surfaces of the first ILD 96 to the same level as the top surfaces of the masks 76.

[0050] In the Fig. 12A and Fig. In 12B, the masks 76 (if present) and the dummy gates 74 are removed in an etching process, forming depressions 98. Sections of the dummy dielectrics 72 in the depressions 98 can also be removed. In some embodiments, the dummy gates 74 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process that uses one or more reactive gases that selectively etch the dummy gates 74 at a faster rate than the first ILD 96 or the gate spacers 80. During the removal process, the dummy dielectrics 72 can be used as etch stop layers when the dummy gates 74 are etched. After the dummy gates 74 have been removed, the dummy dielectrics 72 can then be removed. Each depression 98 exposes and / or overlays sections of the channel regions 68.Sections of the second nanostructures 56B, which act as the channel regions 68, are arranged between adjacent pairs of the epitaxial source / drain regions 92.

[0051] The remaining portions of the first nanostructures 56A are then ablated to enlarge the recesses 98. The remaining portions of the first nanostructures 56A can be ablated by an acceptable etching process that selectively etches the material of the first nanostructures 56A at a higher rate than the materials of the second nanostructures 56B, the fins 54, and the STI regions 60. The etching can be isotropic. For example, if the fins 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A are formed from silicon germanium, the etching process can be a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In some embodiments (explained in more detail below), a trimming process is performed to reduce the thicknesses of the exposed portions of the second nanostructures 56B.

[0052] In the Fig. 13A and Fig. Gate dielectrics 102 and gate electrodes 104 for replacement gates are formed in 13B. The gate dielectrics 102 are conformally formed in the recesses 98, for example, on the top and side walls of the fins 54 and on the top, side walls, and bottom surfaces of the second nanostructures 56B. The gate dielectrics 102 can also be deposited on the top surfaces of the first ILD 96, the gate spacers 80, and the STI regions 60. The gate dielectrics 102 have one or more dielectric layers, for example, an oxide, a metal oxide, a metal silicate, similar materials, or combinations thereof. In some embodiments, the gate dielectrics 102 contain silicon oxide, silicon nitride, or multiple layers of these materials.In some embodiments, the gate dielectrics 102 contain a high-k dielectric, and in these embodiments, the gate dielectrics 102 can have a k-value greater than approximately 7.0 and can contain a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectrics 102 can have multiple layers. For example, in some embodiments, the gate dielectrics 102 can each have a silicon oxide interface formed by thermo-oxidation or chemical oxidation, and a metal oxide layer above the interface. The one or more materials of the gate dielectrics 102 can be formed by molecular beam deposition (MBD), ALD, PECVD, or similar processes.

[0053] The gate electrodes 104 are deposited over the gate dielectrics 102 and fill the remaining sections of the wells 98. The gate electrodes 104 can contain a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations of these, or multiple layers of these. For example, although single-layer gate electrodes 104 are illustrated, the gate electrodes 104 can have any number of lining layers, any number of work function tuning layers, and a filler. Any combination of the layers forming the gate electrodes 104 can be deposited in the regions between each of the second nanostructures 56B and between the fins 54 and the second nanostructures 56B. The one or more materials of the gate electrodes 104 can be formed by ALD, PECVD, or similar processes.

[0054] After filling the wells 98, a planarization process, such as a CMP process, can be performed to remove the excess material from the gate dielectrics 102 and the gate electrodes 104, with the excess material lying above the top surfaces of the first ILD 96 and the gate spacer 80. The remaining material from the gate dielectrics 102 and the gate electrodes 104 thus forms substitute gates of the resulting nanoFETs. The gate dielectrics 102 and the gate electrodes 104 can be collectively referred to as gate structures 100 or “gate stacks”.

[0055] The formation of the gate dielectrics 102 in the n-region 50N and the p-region 50P can occur simultaneously such that the gate dielectrics 102 in each region are formed from the same materials, and the formation of the gate electrodes 104 can also occur simultaneously such that the gate electrodes 104 in each region are formed from the same materials. In some embodiments, the gate dielectrics 102 in each region can be formed by different processes such that the gate dielectrics 102 can be made of different materials, and / or the gate electrodes 104 in each region can be formed by different processes such that the gate electrodes 104 can be made of different materials. If different processes are used, different masking steps can be employed to mask or expose suitable regions.

[0056] In the Fig. In sections 14A to 14C, source / drain contact openings 106 are formed by the first ILD 96 and the CESL 94, thereby exposing a subset of the epitaxial source / drain regions 92S. The source / drain contact openings 106 can initially be formed in the first ILD 96 using acceptable photolithography and etching techniques, for example, with an etching process that is selective with respect to the first ILD 96 (e.g., etching the material of the first ILD 96 at a faster rate than the material of the CESL 94). For example, the source / drain contact openings 106 can initially be formed by the first ILD 96 using a dry etching process with ammonia (NH3) and hydrogen fluoride (HF) gas. Subsequently, the source / drain contact openings 106 are enlarged by the CESL 94 using acceptable etching techniques, for example with an etching process that is selective towards the CESL 94 (e.g.The material of CESL 94 etches at a faster rate than the material of the epitaxial source / drain regions 92S). For example, the source / drain contact openings 106 through CESL 94 can be enlarged by a dry etching process using a fluorine-based gas (e.g., C4F6) and hydrogen (H2) or oxygen (O2) gas. In some embodiments, the etching process parameters used for etching the source / drain contact openings 106 by the first ILD 96 (e.g., etchant, duration, environment, etc.) differ from the etching process parameters used for etching the source / drain contact openings 106 by CESL 94.

[0057] During the process of forming the source / drain contact openings 106, a mask 108 with a structure corresponding to the source / drain contact openings 106 is formed over the first ILD 96. The mask 108 is used as an etching mask during the etching processes performed by the first ILD 96 and the CESL 94 to etch the source / drain contact openings 106.

[0058] In some embodiments, the mask 108 is formed from a photoresist, for example, a single-layer, two-layer, three-layer, or similar photoresist. For example, the mask 108 may be a three-layer photoresist comprising a bottom layer (e.g., a bottom antireflective coating (BARC layer)), a middle layer (e.g., a hard mask), and a top layer (e.g., a photoresist). The type of photoresist used (e.g., single-layer, two-layer, three-layer, etc.) may depend on the photolithography process used for subsequent structuring of the photoresist. For example, in extreme ultraviolet lithography (EUV lithography) processes, the mask 108 may be a single-layer or a two-layer photoresist.The photoresist can be formed by spin coating, a deposition process such as CVD, combinations of these or similar processes, and can be structured using acceptable photolithography techniques to have a structure of the source / drain contact openings 106.

[0059] In some embodiments, the mask 108 is formed from spacers. For example, a sacrificial layer can be formed over the first ILD 96 and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-alignment process. Subsequently, the sacrificial layer is removed, and the remaining spacers can then be used as the mask 108. Other types of masks can also be used to etch the source / drain contact openings 106.

[0060] Subsequently, source / drain contacts are formed in the source / drain contact openings 106 and attached to the front faces of the epitaxial source / drain regions 92S. As noted above, a first subset of the epitaxial source / drain regions 92P is connected to dedicated busbars, while a second subset of the epitaxial source / drain regions 92S is not connected to the dedicated busbars. As will be explained in more detail below, the busbars are subsequently attached through the back faces of the epitaxial source / drain regions 92P. Contacts to the front faces of the epitaxial source / drain regions 92P are therefore undesirable. According to various embodiments, the source / drain contact openings 106 are formed over and exposed the front faces of the epitaxial source / drain regions 92S, while the front faces of the epitaxial source / drain regions 92P are completely covered by dielectric (e.g.,the CESL 94). In other words, the entire front surface of each of the epitaxial source / drain regions 92P is covered by dielectric (e.g., the CESL 94). The formation of the source / drain contact openings 106 over the epitaxial source / drain regions 92P can be avoided in various ways.

[0061] In some embodiments, a simple structuring process is used to structure the mask 108. Simple structuring can be used when the mask 108 is formed from a photoresist. In such embodiments, the photoresist can be formed to have a structure of openings over the epitaxial source / drain regions 92S, but not over the epitaxial source / drain regions 92P. The photoresist can be structured by exposing it to a structured energy source (e.g., a structured light source) to induce a chemical reaction, thereby causing a physical change in the sections of the photoresist exposed to the structured light source. The structured energy source has a structure only over the epitaxial source / drain regions 92S, but not over the epitaxial source / drain regions 92P.The photoresist can then be developed by applying a developer to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed section of the photoresist or the unexposed section of the photoresist, depending on the desired structure.

[0062] In some embodiments, a multi-structuring process is used to structure the mask 108. Multi-structuring can be used when the mask 108 is formed from spacers. In such embodiments, the mask 108 can first be formed with a structure of openings over all epitaxial source / drain regions 92P, 92S. Subsequently, the portions of the structure of openings over the epitaxial source / drain regions 92P are covered or filled, so that only the portions of the structure of openings over the epitaxial source / drain regions 92S remain in the mask 108. The openings over the epitaxial source / drain regions 92P can be covered or filled by forming an additional mask, for example, a structured photoresist, a structured hard mask, or something similar.

[0063] Selective formation of the source / drain contact openings 106 across the epitaxial source / drain regions 92S may involve additional processing steps, particularly if a multi-structuring process is used to structure the mask 108. However, as noted above, contacts to the front faces of the epitaxial source / drain regions 92P are undesirable. If unwanted contacts were formed to the front faces of the epitaxial source / drain regions 92P, such contacts would remain isolated and unused, thereby increasing the parasitic capacitance of the nanoFETs. Although avoiding the formation of contacts to the front faces of the epitaxial source / drain regions 92P involves additional processing steps, preventing the formation of such contacts can thus improve the performance of the nanoFETs.

[0064] In the Fig. From 15A to 15C, mask 108 is removed. If mask 108 contains a photoresist, the photoresist can be removed, for example, by an acceptable ashing process. If mask 108 has additional layers (e.g., a BARC layer, a hard mask, spacers, etc.), acceptable etching processes can be used to remove these layers.

[0065] Metal-semiconductor alloy regions 110 can optionally be formed in the source / drain contact openings 106, for example on sections of the epitaxial source / drain regions 92S exposed by the source / drain contact openings 106. The metal-semiconductor alloy regions 110 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or similar. The metal-semiconductor alloy regions 110 can be formed by depositing a metal in the source / drain contact openings 106 and subsequently carrying out a thermal tempering process.The metal can be any metal capable of reacting with the semiconductor materials (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain regions 92S to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare-earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or similar. In one embodiment, the metal-semiconductor alloy regions 110 are silicide regions formed from titanium-silicon. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the source / drain contact openings 106, for example, from the top surfaces of the first ILD 96.

[0066] Subsequently, lower source / drain contacts 112 are formed in the source / drain contact openings 106. A lining, for example a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the source / drain contact openings 106. The lining can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The lining can be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the lining can include an adhesive layer, and at least a portion of the adhesive layer can be treated to form a diffusion barrier layer. The conductive material can be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like.The conductive material can be deposited by ALD, CVD, PVD, or similar processes. A planarization process, such as a CMP process, can be performed to remove excess material from the top surfaces of the first ILD 96. The remaining lining and conductive material in the source / drain contact openings 106 form the lower source / drain contacts 112. The lower source / drain contacts 112 are physically and electrically coupled to the metal-semiconductor alloy regions 110 (if present) or the front surfaces of the epitaxial source / drain regions 92S. The top surfaces of the lower source / drain contacts 112, the gate electrodes 104, the first ILD 96, and the gate spacer 80 are coplanar (within process variations).

[0067] In the Fig. In sections 16A to 16C, trenches 114 are formed through the first ILD 96, exposing sections of the CESL 94 above the epitaxial source / drain regions 92P. The trenches 114 can be formed in the first ILD 96 using acceptable photolithography and etching techniques, for example, with an etching process that is selective with respect to the first ILD 96 (e.g., etching the material of the first ILD 96 at a faster rate than the material of the CESL 94). For example, the trenches 114 can be formed through the first ILD 96 using a dry etching process with ammonia (NH3) and hydrogen fluoride (HF) gas. In some embodiments, the trenches 114 in the first ILD 96 can be formed using similar etching process parameters that were also used to initially form the source / drain contact openings 106 through the first ILD 96.

[0068] During the process of forming the trenches 114, a mask 116 with a trench 114 structure is formed over the first ILD 96. The mask 116 is used as an etching mask during the etching processes used to etch the trenches 114 by the first ILD 96. The mask 116 can be formed in a similar manner and using similar materials as those described in the Fig. Mask 108, as explained in sections 14A to 14C, is formed. As described by Fig. As shown in Figure 16C, the trenches 114 extend over several adjacent epitaxial source / drain regions 92P. In other words, the trenches 114 extend over several fins 54 (or over several groups of fins 54 if the adjacent epitaxial source / drain regions 92 of an identical nanoFET are fused, as shown in Figure 16C). Fig. 9C illustrates).

[0069] In the Fig. In steps 17A to 17C, mask 116 is removed. If mask 116 contains a photoresist, the photoresist can be removed, for example, by an acceptable ashing process. If mask 116 has additional layers (e.g., a BARC layer, a hard mask, spacers, etc.), acceptable etching processes can be used to remove these layers.

[0070] Subsequently, conductive tracks 118 are formed in the grooves 114. A lining, for example, a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the grooves 114. The lining can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The lining can be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the lining can have an adhesive layer, and at least a portion of the adhesive layer can be treated to form a diffusion barrier. The conductive material can be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like. The conductive material can be deposited by ALD, CVD, PVD, or the like.A planarization process, such as a CMP process, can be performed to remove excess material from the top surfaces of the first ILD 96. The remaining lining and conductive material in the grooves 114 form the conductor tracks 118. The top surfaces of the conductor tracks 118, the lower source / drain contacts 112, the gate electrodes 104, the first ILD 96, and the gate spacer 80 are (within process variations) coplanar.

[0071] No metal-semiconductor alloy regions are formed in the grooves 114, and the conductor tracks 118 are physically and electrically isolated from the epitaxial source / drain regions 92P by the CESL 94. As noted above, contact with the front faces of the epitaxial source / drain regions 92P is undesirable. The sections of the first ILD 96 above the epitaxial source / drain regions 92P can therefore be used for other purposes. Specifically, the conductor tracks 118 are formed in the sections of the first ILD 96 above the epitaxial source / drain regions 92P, while the front faces of the epitaxial source / drain regions 92P remain completely covered by dielectric (e.g., the CESL 94), with the dielectric positioned between the conductor tracks 118 and the front faces of the epitaxial source / drain regions 92P. As will be discussed in more detail below, the conductor tracks 118 can be used for additional guidance.For example, the conductor tracks 118 can be used to carry signals from an overlying interconnect structure (discussed in more detail below).

[0072] The conductor tracks 118 extend over several adjacent epitaxial source / drain regions 92P and have sections above the STI regions 60 (e.g., between and adjacent to the epitaxial source / drain regions 92P). The sections of the conductor tracks 118 above the STI regions 60 have a greater height than the sections of the conductor tracks 118 above the epitaxial source / drain regions 92P. For example, the sections of the conductor tracks 118 above the epitaxial source / drain regions 92P can have a height H1 in the range of approximately 5 nm to approximately 30 nm, and the sections of the conductor tracks 118 above the STI regions 60 can have a height H2 in the range of approximately 50 nm to approximately 100 nm. Since the lower source / drain contacts 112 are formed by the CESL 94, but the conductor tracks 118 are not, the lower source / drain contacts 112 thus have a greater height than the sections of the conductor tracks 118 above the epitaxial source / drain regions 92P.For example, the lower source / drain contacts 112 can have a height H3 in the range of approximately 10 nm to approximately 40 nm. The height H3 is greater than the height H1 and less than the height H2.

[0073] Fig. Figure 18 is a simplified view of a semiconductor device in a similar processing step to the semiconductor device of the Fig. 17A to 17C, except that more gate structures 100 are shown and some features have been omitted for clarity of illustration. As shown, the lower source / drain contacts 112 are arranged over respective fins 54. The conductor tracks 118 extend over several fins 54 (or over several groups of fins 54 if the adjacent epitaxial source / drain regions 92 of an identical nanoFET are fused, as shown by Fig. (Figure 9C illustrates this). Each of the conductor tracks 118 can extend only through the n-region 50N, only through the p-region 50P, or through both the n-region 50N and the p-region 50P. In a direction parallel to the longitudinal axes of the gate structures 100, the conductor tracks 118 have a greater length than the lower source / drain contacts 112. For example, the lower source / drain contacts 112 can have a length L1 in the range of approximately 15 nm to approximately 50 nm, and the conductor tracks 118 can have a length L2 in the range of approximately 50 nm to approximately 150 nm. In some embodiments, the conductor tracks 118 and the lower source / drain contacts 112 can have the same widths in a direction parallel to the longitudinal axes of the fins 54. For example, the lower source / drain contacts 112 and the conductor tracks 118 can each have a width W1 in the range of about 10 nm to about 30 nm.

[0074] In the Fig. In embodiments 19A to 19D, a second ILD 122 is deposited over the first ILD 96, the gate electrodes 104, the lower source / drain contacts 112, and the conductor tracks 118. The second ILD 122 can be formed from a material selected from the same group of materials available for the first ILD 96 and can be deposited using a method selected from the same group of methods available for depositing the first ILD 96. The first ILD 96 and the second ILD 122 can be formed from the same material, or they can contain different materials. After formation, the second ILD 122 can be planarized, for example, by a CMP process. In some embodiments, an etch stop layer is formed between the first ILD 96 and the second ILD 122.The etch stop layer may contain a dielectric such as silicon nitride, silicon oxide, silicon oxynitride or similar materials with a different etch rate than the material of the second ILD 122.

[0075] Gate contacts 124, upper source / drain contacts 126, and line contacts 128 are then formed, extending through the second ILD 122. Contact openings are formed through the second ILD 122. The contact openings can be formed using acceptable photolithography and etching techniques. Subsequently, a lining, for example, a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the contact openings. The lining can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The lining can be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the lining can include an adhesive layer, and at least a portion of the adhesive layer can be treated to form a diffusion barrier.The conductive material can be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or similar. The conductive material can be deposited by ALD, CVD, PVD, or similar processes. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the second ILD 122. The remaining liner and conductive material in the contact openings form the gate contacts 124, the upper source / drain contacts 126, and the conductor contacts 128. The gate contacts 124 are physically and electrically coupled to the gate electrodes 104. The upper source / drain contacts 126 are physically and electrically coupled to the lower source / drain contacts 112. The conductor contacts 128 are physically and electrically coupled to the conductor tracks 118.

[0076] As explained in more detail below, a first interconnect structure (e.g., a front-facing interconnect structure) is formed on the substrate 50. Subsequently, the substrate 50 is partially or completely removed and replaced by a second interconnect structure (e.g., a back-facing interconnect structure). Thus, a component layer 130 consisting of active components is formed between the front-facing and back-facing interconnect structures. Both the front-facing and back-facing interconnect structures have conductive features that are electrically connected to the nanoFETs of the component layer 130. The conductive features (e.g.,Metallization structures (also referred to as interconnects) of the front-side interconnect structure are electrically connected to the front faces of the epitaxial source / drain regions 92S and the gate electrodes 104 to form functional circuits, such as logic circuits, memory circuits, image sensor circuits, or the like. The conductive features (e.g., busbars) of the rear-side interconnect structure are electrically connected to the back faces of the epitaxial source / drain regions 92P to provide a reference voltage, supply voltage, or the like to the functional circuits. Although the component layer 130 is described as having nanoFETs, other embodiments may have a component layer 130 with a different transistor type (e.g., planar FETs, FinFETs, TFTs, or the like).

[0077] The Fig. Figures 20 to 27D show various views of further intermediate stages in the fabrication of semiconductor devices according to some embodiments. Specifically, the fabrication of front- and back-side interconnect structures for nano-FETs is illustrated. Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26 and Fig. 27A are cross-sectional views that extend along the reference cross-section AA in Fig. 1 are shown. Fig. 27B is a cross-sectional view taken along the reference cross-section BB in Fig. 1 is shown. Fig. 27C is a cross-sectional view taken along the reference cross-section CC in Fig. 1 is shown, except that two Finns are shown. Fig. 27D is a cross-sectional view that follows the reference cross-section DD in Fig. 1 is shown, except that two Finns are shown.

[0078] In Fig. 20, an interconnect structure 140 is formed on the component layer 130, e.g., on the second ILD 122. The interconnect structure 140 can also be referred to as a front-side interconnect structure, since it is formed on a front side of the substrate 50 / the component layer 130 (e.g., a side of the substrate 50 on which the component layer 130 is formed).

[0079] The interconnect structure 140 can have one or more layers of conductive features 142 formed in one or more stacked dielectric layers 144. Each of the dielectric layers 144 can contain a dielectric, for example, a low-k dielectric, an extra-low-k dielectric (ELK dielectric), or the like. The dielectric layers 144 can be deposited by a suitable process, for example, CVD, ALD, PVD, PECVD, or the like.

[0080] The conductive features 142 can include conductor tracks and vias that connect the conductor track layers to one another. The vias can extend through respective dielectric layers 144 to provide vertical connections between conductor track layers. The conductive features 142 can be formed by any suitable process. For example, the conductive features 142 can be formed by a damascening process, such as a single damascening process, a double damascening process, or the like. In a damascening process, a respective dielectric layer 144 is patterned using a combination of photolithography and etching techniques to form grooves corresponding to the desired structure of the conductive features 142.An optional diffusion barrier layer and / or an optional adhesive layer can be deposited, and subsequently the trenches can be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In one embodiment, the conductive features 142 can be formed by depositing a nucleation layer of copper or a copper alloy and filling the trenches by electroplating. A chemical-mechanical planarization (CMP) process or the like can be used to remove excess conductive material from a surface of the respective dielectric layer 144 and to planarize the surface for further processing.

[0081] In the illustrated example, five layers of conductive features 142 and dielectric layers 144 are shown. However, it should be noted that the interconnect structure 140 can have any number of conductive features arranged in any number of dielectric layers. The conductive features 142 of the interconnect structure 140 are electrically connected to the gate contacts 124, the upper source / drain contacts 126, and the conductor contacts 128 to form functional circuits. In other words, the conductive features 142 connect the conductor tracks 118, the epitaxial source / drain regions 92, and the gate electrodes 104 to each other. In some embodiments, the functional circuits formed by the interconnect structure 140 can include logic circuits, memory circuits, image sensor circuits, or the like.The second ILD 122, the gate contacts 124, the upper source / drain contacts 126 and the line contacts 128 can also be considered as part of the interconnect structure 140, for example as part of a first level of conductive features of the interconnect structure 140.

[0082] As noted above, the conductor tracks 118 can be used for additional routing. The conductor tracks 118 are thus each coupled to several conductor contacts 128, so that one conductor track 118 is connected to several conductive features 142 of the interconnect structure 140. The conductor tracks 118 can act as additional interconnects for the interconnect structure 140. For example, a signal carrier can be routed downwards through a first conductive feature 142 to a conductor track 118 and then upwards again to a second conductive feature 142. This allows for increased flexibility in signal routing.

[0083] In Fig. In step 21, a support substrate 146 is bonded to a top surface of the interconnect structure 140 by bonding layers 148 (e.g., bonding layers 148A, 148B). The support substrate 146 can be a glass support substrate, a ceramic support substrate, a semiconductor substrate (e.g., a silicon substrate), a wafer (e.g., a silicon wafer), or the like. The support substrate 146 can provide structural support in subsequent processing steps and in the finished device. The support substrate 146 can be essentially free of any active or passive components.

[0084] In various embodiments, the support substrate 146 can be bonded to the interconnect structure 140 using a suitable technique such as dielectric-to-dielectric bonding or similar methods. Dielectric-to-dielectric bonding can include the deposition of bonding layers 148A, 148B on the interconnect structure 140 or the support substrate 146, respectively. In some embodiments, bonding layer 148A comprises silicon oxide (e.g., a high-density plasma oxide (HDP oxide) or similar) deposited by CVD, ALD, PVD, or similar processes. Bonding layer 148B can also be an oxide layer formed prior to bonding, for example, by thermal oxidation or similar processes such as CVD, ALD, or PVD. Other suitable materials can also be used for bonding layers 148A, 148B.

[0085] The dielectric-to-dielectric bonding process can further include applying a surface treatment to one or more of the bonding layers 148. The surface treatment can include plasma treatment. The plasma treatment can be performed in a vacuum environment. After the plasma treatment, the surface treatment can further include a cleaning process (e.g., rinsing with deionized water or similar) that can be applied to one or more of the bonding layers 148. Subsequently, the support substrate 146 is aligned with the interconnect structure 140, and the two are pressed together to initiate pre-bonding of the support substrate 146 to the interconnect structure 140. The pre-bonding can be performed at room temperature (e.g., in a range of approximately 20 °C to approximately 25 °C).After pre-bonding, a tempering process can be applied, for example by heating the interconnect structure 140 and the support substrate 146 to a temperature of about 170 °C.

[0086] In Fig. In step 22, the intermediate structure is inverted so that the back side of the substrate 50 faces upwards. The back side of the substrate 50 refers to the side opposite the front side of the substrate 50, on which the device layer 130 is formed. Subsequently, the substrate 50 is thinned to remove (or at least reduce the thickness of) the back sections of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, chemical-mechanical polishing (CMP), or similar), a back-etching process, combinations thereof, or similar processes. The thinning process exposes the STI regions 60 and the surfaces of the fins 54 on the back side of the device layer 130.

[0087] Subsequently, a dielectric layer 152 is deposited over the back side of the device layer 130, for example, over the fins 54 and the STI regions 60. The dielectric layer 152 is part of an interconnect structure formed on the device layer 130. The dielectric layer 152 can physically contact surfaces of the remaining sections of the fins 54 and the STI regions 60. The dielectric layer 152 can be formed from a material selected from the same group of materials available for the first ILD 96 and can be deposited using a process selected from the same group of processes available for depositing the first ILD 96. The first ILD 96 and the dielectric layer 152 can be formed from the same material or they can contain different materials.

[0088] In Fig. 23. Busbar contact openings 154 are formed by the dielectric layer 152 and the fins 54. The busbar contact openings 154 can be formed in the dielectric layer 152 using acceptable photolithography and etching techniques, for example, with an etching process that is selective with respect to the dielectric layer 152 (e.g., the material of the dielectric layer 152 etches at a faster rate than the material of the fins 54), using the mask 134 as an etching mask. For example, the busbar contact openings 154 can first be formed through the dielectric layer 152 by means of a dry etching process using ammonia (NH3) and hydrogen fluoride (HF) gas. Subsequently, the busbar contact openings 154 are enlarged by the fins 54 using acceptable photolithography and etching techniques, for example with an etching process that is selective towards the fins 54 (e.g.The material of the fins 54 etches at a faster rate than the material of the epitaxial source / drain regions 92P). For example, the busbar contact openings 154 can be enlarged by the fins 54 using a dry etching process with a fluorine-based gas such as hydrogen fluoride (HF) gas.

[0089] In Fig. 24 Metal-semiconductor alloy regions 156 are optionally formed in the busbar contact openings 154, for example, on sections of the epitaxial source / drain regions 92P exposed by the busbar contact openings 154. The metal-semiconductor alloy regions 156 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or similar. The metal-semiconductor alloy regions 156 can be formed by depositing a metal in the busbar contact openings 154 and subsequently performing a thermal annealing process.The metal can be any metal capable of reacting with the semiconductor materials (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain regions 92P to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare-earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or similar. In one embodiment, the metal-semiconductor alloy regions 156 are silicide regions formed from titanium-silicon. After the thermal tempering process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the busbar contact openings 154, for example, from the top surfaces of the dielectric layer 152 and the STI regions 60.

[0090] Subsequently, busbar contacts 158 are formed in the busbar contact openings 154. A lining, for example a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the busbar contact openings 154. The lining can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The lining can be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the lining can have an adhesive layer, and at least a portion of the adhesive layer can be treated to form a diffusion barrier. The conductive material can be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like.The conductive material can be deposited by ALD, CVD, PVD, or similar processes. A planarization process, such as CMP, can be performed to remove excess material from the top surfaces of the dielectric layer 152 and the STI regions 60. The remaining lining and conductive material in the busbar contact openings 154 form the busbar contacts 158. The busbar contacts 158 are physically and electrically coupled to the metal-semiconductor alloy regions 156 (if present) or the back surfaces of the epitaxial source / drain regions 92P. The top surfaces of the busbar contacts 158, the dielectric layer 152, and the STI regions 60 are coplanar (within process variations).

[0091] In Fig. 25 Conductive features 160 and a dielectric layer 162 are formed above the dielectric layer 162 and the busbar contacts 158. The dielectric layer 162 and the conductive features 160 are also part of an interconnect structure formed on the component layer 130. The dielectric layer 162 can be formed from a material selected from the same group of materials available for the first ILD 96 and can be deposited using a process selected from the same group of processes available for depositing the first ILD 96. The first ILD 96 and the dielectric layer 162 can be formed from the same material, or they can contain different materials.

[0092] The conductive features 160 are formed in the dielectric layer 162 and can be conductive traces. Forming the conductive features 160 can involve structuring depressions in the dielectric layer 162 by a combination of photolithography and etching processes. The structure of the openings in the dielectric layer 162 can correspond to the structure of the conductive features 160. The conductive features 160 are then formed by depositing a conductive material in the depressions. In some embodiments, the conductive features 160 have a metal layer, which can be a single layer or a composite layer comprising sublayers of several different materials. In some embodiments, the conductive features 160 contain copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or similar materials.Prior to filling the wells with the conductive material, an optional diffusion barrier layer and / or an optional adhesive layer may be deposited. Suitable materials for the barrier / adhesive layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or similar materials. The conductive feature(s) 160 may be formed, for example, by CVD, ALD, PVD, plating, or similar processes. The conductive features 160 are electrically connected to the epitaxial source / drain regions 92P via the metal-semiconductor alloy regions 156 (if present) and the busbar contacts 158. A planarization process (e.g., CMP, grinding, back-etching, or similar) may be performed to remove excess portions of the conductive features 160 formed above the dielectric layer 162.

[0093] Some or all of the conductive features 160 are busbars 160P, which are conductor tracks that electrically connect the epitaxial source / drain regions 92P to a reference voltage, supply voltage, or similar. Advantages can be gained by placing the busbars 160P on a back side of the component layer 130 instead of on a front side. For example, the gate density of the nanoFETs and / or the interconnect density of the interconnect structure 140 can be increased. Furthermore, the back side of the component layer 130 can accommodate wider busbars, which reduces resistance and increases the efficiency of the current supply to the nanoFETs. For example, the width of the conductive features 160 can be at least twice the width of a first-level conductor track (e.g., conductor track 142A) of the interconnect structure 140.

[0094] In Fig. 26. On the back side of the component layer 130, for example, above the dielectric layer 162 and the conductive features 160, remaining sections of an interconnect structure 150 are formed. The interconnect structure 150 can also be referred to as a backside interconnect structure, since it is formed on the back side of the component layer 130. The remaining sections of the interconnect structure 150 can resemble the interconnect structure 140. For example, the interconnect structure 150 can comprise similar materials and be formed by similar processes as the interconnect structure 140. In particular, the interconnect structure 150 can comprise stacked layers of conductive features 164 formed in stacked dielectric layers 166. The conductive features 164 can include guide lines (e.g., for guiding to and from subsequently formed contact pads and external terminals).The conductive features 164 can further include conductive vias extending into the dielectric layers 166 to provide a vertical connection between stacked layers of the conductor tracks. The interconnect structure 150 thus comprises the dielectric layers 152, 162, 166 and the conductive features 160, 164. The busbar contact 158 ​​extends between the interconnect structure 150 and the component layer 130.

[0095] In some embodiments, the conductive features of the interconnect structure 150 can be structured to include one or more embedded passive components, such as resistors, capacitors, inductors, or the like. The embedded passive components can be integrated with the conductive features 160, 164 (e.g., the busbars 160P) to provide circuits (e.g., electrical circuits) on the back side of the component layer 130.

[0096] In the Fig. In components 27A to 27D, a passivation layer 172, UBMs 174, and external connections 176 are formed over the interconnect structure 150. The passivation layer 172 can comprise polymers such as polyimide, polybenzoxazole (PBO), a benzocyclobutene (BCB)-based polymer, or similar materials. Alternatively, the passivation layer 172 can contain inorganic dielectrics such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or similar materials. The material of the passivation layer 172 can be deposited, for example, by CVD, PVD, ALD, or similar processes.

[0097] The UBMs 174 are formed by the passivation layer 172 up to the conductive features 164 of the interconnect structure 150, and the external connections 176 are formed on the UBMs 174. The UBMs 174 can comprise one or more layers of copper, nickel, gold, or the like, formed by a plating process or similar method. The external connections 176 (e.g., solder beads) are formed on the UBMs 174. The formation of the external connections 176 can involve placing solder beads on the exposed portions of the UBMs 174 and subsequently melting the solder beads. In alternative embodiments, the formation of the external connections 176 involves performing a plating step to form solder regions over the uppermost conductive feature 164 and subsequently melting the solder regions.In another embodiment, the external terminals 176 are metal terminals with substantially vertical sidewalls, such as microbumps. The UBMs 174 and the external terminals 176 can be used to provide input / output connections to other electrical components, such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like. The UBMs 174 and the external terminals 176 can also be referred to as rear-side input / output pads that can provide signal, reference, supply, and / or ground connections to the nanoFETs of the device layer 130.

[0098] The Fig. Figures 28A to 28D are different views of semiconductor devices according to some further embodiments. This embodiment is similar to the embodiment of Fig. 27A to 27D, except that the traces 118 and the leads 128 are omitted, so that no conductive features are arranged in sections of the first ILD 96 above / below the epitaxial source / drain regions 92P. The traces 118 and the leads 128 can be omitted if no additional guidance is desired. Omitting the traces 118 and the leads 128 can help to further reduce the parasitic capacitance of the nanoFETs, thereby improving their performance.

[0099] Fig. Figure 29 shows a cross-sectional view of semiconductor devices according to several other embodiments. This embodiment is similar to the embodiment shown in Figure 29. Fig. 27A, except that the second nanostructures 56B are truncated. The truncation reduces the thicknesses of the second nanostructures 56B from the second thickness T2 (above with reference to Fig. 2 treated) to a third thickness T3, wherein the third thickness T3 is in a range of about 3 nm to about 8 nm and the third thickness T3 is about 40% to about 70% less than the second thickness T2. The trimming can be carried out simultaneously with the formation of the depressions 98 (with reference to the Fig. 12A and Fig.12B treated) or after the wells 98 have been formed. The exposed sections of the second nanostructures 56B and the fins 54 can, for example, be trimmed by an acceptable etching process that selectively etches the materials of the second nanostructures 56B and the fins 54 at a faster rate than the materials of the first nanostructures 56A, the inner spacers 84, and the gate spacers 80. The etching can be isotropic. For example, if the fins 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A are formed from silicon germanium, the etching process can be a wet etching process using a dilute ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), or the like.

[0100] Embodiments can be advantageous. Since the busbars 160P are attached to the back faces of the epitaxial source / drain regions 92P, contacts to the front faces of the epitaxial source / drain regions 92P are undesirable. Avoiding the formation of unwanted contacts to the front faces of the epitaxial source / drain regions 92P ensures that the resulting semiconductor devices do not have isolated and unused contacts. The parasitic capacitance of the nanoFETs in layer 130 can thus be reduced, increasing their performance. Furthermore, avoiding the formation of such contacts in the first ILD 96 frees up space that can be used for other purposes. For example, the conductor tracks 118 can be formed and used for additional interconnect routing. This allows for increased flexibility in signal routing.

[0101] The device comprises: a first fin; a gate structure over the first fin; a first source / drain region adjacent to the gate structure; an etch stop layer over the first source / drain region; a conductor track over the etch stop layer, wherein the conductor track is insulated in a trench through the etch stop layer from the first source / drain region and a top surface of the conductor track is coplanar with a top surface of the gate structure; and a busbar contact extending through the first fin, wherein the busbar contact is connected to the first source / drain region.

[0102] In some embodiments, the device further comprises: a second source / drain region adjacent to the gate structure, wherein the etch stop layer is arranged over the second source / drain region; and a source / drain contact extending through the etch stop layer, wherein the source / drain contact is connected to the second source / drain region and one top surface of the source / drain contact is coplanar with the top surface of the conductor track and the top surface of the gate structure. In some embodiments, the device further comprises: dielectric layers over the gate structure and the conductor track; and interconnects in the dielectric layers, wherein the interconnects link the conductor track, the source / drain contact, and the gate structure to one another.In some embodiments of the device, the conductor track has a first section and a second section, wherein the first section is arranged above the first source / drain region and the second section is arranged next to the first source / drain region. In some embodiments of the device, the first section of the conductor track has a first height, the second section of the conductor track has a second height, and the source / drain contact has a third height, wherein the third height is greater than the first height and less than the second height. In some embodiments of the device, the conductor track has a first length, the source / drain contact has a second length, and the first length is greater than the second length, wherein the first length and the second length are each measured in a direction parallel to a longitudinal axis of the gate structure.In some embodiments of the device, the conductor track has a first width and the source / drain contact has a first width, the first width being measured in a direction parallel to a longitudinal axis of the first fin. In some embodiments, the device further comprises: a second fin, wherein the gate structure is located above the second fin; and a second source / drain region adjacent to and within the second fin, wherein the etch stop layer is arranged above the second source / drain region and the conductor track extends over the first source / drain region and the second source / drain region. In some embodiments, the device further comprises: a nanostructure above the first fin, wherein the gate structure surrounds the nanostructure.

[0103] The device comprises: a rear interconnect structure having a busbar; a front interconnect structure having interconnects; and a device layer between the rear interconnect structure and the front interconnect structure, the device layer comprising a transistor having: a first epitaxial source / drain region; a source / drain contact contacting a front face of the first epitaxial source / drain region, the interconnects being connected to the source / drain contact; a second epitaxial source / drain region; and a busbar contact contacting a rear face of the second epitaxial source / drain region, the busbar being connected to the busbar contact and a front face of the second epitaxial source / drain region being completely covered by dielectric.

[0104] The device layer further comprises: a conductive track, wherein the dielectric is arranged between the conductive track and the front face of the second epitaxial source / drain region, and the surfaces of the conductive track and the source / drain contact are coplanar. In some embodiments of the device, the conductive track and the source / drain contact have the same width in a first direction, and the conductive track has a greater length than the source / drain contact in a second direction, the second direction being perpendicular to the first direction. In some embodiments of the device, the front-facing interconnect structure further comprises: multiple conductor contacts contacting the conductive track, wherein the interconnects are connected to the conductor contacts. In some embodiments of the device, the interconnects comprise a conductive track, wherein one width of the busbar is greater than one width of the conductive track.

[0105] A method comprises: depositing an etch stop layer on a first epitaxial source / drain region, a second epitaxial source / drain region, and a gate structure, wherein the first epitaxial source / drain region and the second epitaxial source / drain region are located on opposite sides of the gate structure; depositing an interlayer dielectric (ILD) on the etch stop layer; etching a first opening through the ILD and the etch stop layer, wherein the first opening exposes a front face of the first epitaxial source / drain region and a front face of the second epitaxial source / drain region remains covered by the etch stop layer after etching the first opening; and forming a source / drain contact in the first opening, wherein the source / drain contact contacts the first epitaxial source / drain region.

[0106] The method for etching the first opening comprises the following: structuring a mask over the ILD, wherein the mask has a structure of openings over the first epitaxial source / drain region and the second epitaxial source / drain region; after structuring, covering a portion of the structure of openings over the second epitaxial source / drain region; and after covering, etching the ILD and the etch stop layer using the mask as the etch mask. In some embodiments of the method, etching the first opening comprises the following: structuring a mask over the ILD, wherein the mask has a structure of openings over the first epitaxial source / drain region but not over the second epitaxial source / drain region; and after structuring, etching the ILD and the etch stop layer using the mask as the etch mask.In some embodiments, the method further comprises: etching a second opening through the ILD, wherein the second opening exposes the etch stop layer; and forming a conductor track in the second opening, wherein the conductor track contacts the etch stop layer. In some embodiments of the method, etching the first opening comprises etching the ILD with first etching process parameters and etching the etch stop layer with second etching process parameters, wherein the second etching process parameters differ from the first etching process parameters. In some embodiments of the method, etching the second opening comprises etching the ILD with the first etching process parameters and does not include etching the etch stop layer.

Claims

[1] comprising a device: a first Finn (54); a gate structure (100) above the first fin; a first source / drain region (92) adjacent to the gate structure (100); an etch stop layer (94) over the first source / drain region (92); a conductor track (118) in a trench over the first source / drain region (92), which is surrounded laterally and towards the first source / drain region by the etch stop layer (94), whereby the conductor track is isolated from the first source / drain region (92) by the etch stop layer (94) and wherein a top surface of the conductor track (118) is coplanar with a top surface of the gate structure (100); and a busbar contact (158) extending through the first fin (54), wherein the busbar contact (158) is connected to the first source / drain region (92P). [2] Device according to claim 1, further comprising: a second source / drain region (92) adjacent to the gate structure (100), wherein the etch stop layer (94) is arranged above the second source / drain region (92); and a source / drain contact (112) extending through the etch stop layer (94), wherein the source / drain contact (112) is connected to the second source / drain region (92) and a top surface of the source / drain contact (112) is coplanar with the top surface of the conductor track (118) and the top surface of the gate structure (100). [3] Device according to claim 2, further comprising: Dielectric layers over the gate structure (100) and the conductor track (118); and Interconnects in the dielectric layers wherein the interconnects connect the conductor track (118), the source / drain contact (112) and the gate structure (100). [4] Device according to claim 2 or 3, wherein the conductor track (118) has a first section and a second section, wherein the first section is arranged above the first source / drain region (92) and the second section is arranged adjacent to the first source / drain region (92). [5] Device according to claim 4, wherein the first section of the conductor track (118) has a first height, the second section of the conductor track (118) has a second height and the source / drain contact (112) has a third height, wherein the third height is greater than the first height and less than the second height. [6] Device according to any one of claims 2 to 5, wherein the conductor track (118) has a first length, the source / drain contact (112) has a second length and the first length is greater than the second length, wherein the first length and the second length are each measured in a direction parallel to a longitudinal axis of the gate structure (100). [7] Device according to any one of claims 2 to 6, wherein the conductor track (118) has a first width and the source / drain contact (112) has a first width, wherein the first width is measured in a direction parallel to a longitudinal axis of the first fin. [8] Device according to one of the preceding claims, further comprising: a second fin (54), wherein the gate structure (100) lies above the second fin (54); and a second source / drain region adjacent to the gate structure (100) and in the second fin (54), wherein the etch stop layer (94) is arranged over the second source / drain region and the conductor track (118) extends over the first source / drain region and the second source / drain region. [9] Device according to one of the preceding claims, further comprising: a nanostructure (56) above the first fin, wherein the gate structure (100) surrounds the nanostructure (56). [10] comprising a device: a rear interconnect structure (150) which includes a power rail (160P); a front-side interconnect structure (140) comprising interconnects; and a device layer (130) between the rear interconnect structure (150) and the front interconnect structure (140), wherein the device layer (130) has a transistor having the following: - a first epitaxial source / drain region (92); - a source / drain contact (112) that contacts a front face of the first epitaxial source / drain region (92), with the interconnects connected to the source / drain contact (112); - a second epitaxial source / drain region; and - a busbar contact (158) that contacts a rear side of the second epitaxial source / drain region, wherein the busbar (160P) is connected to the busbar contact (158) and a front side of the second epitaxial source / drain region (92) is completely covered with a dielectric; wherein the device layer (130) further comprises the following: a conductor track (118) wherein the dielectric is arranged between the conductor track (118) and the front face of the second epitaxial source / drain region (92) and surfaces of the conductor track (118) and the source / drain contact (112) are coplanar. [11] Device according to claim 10, wherein the conductor track (118) and the source / drain contact (112) have the same width in a first direction and the conductor track (118) has a greater length in a second direction than the source / drain contact (112), wherein the second direction is perpendicular to the first direction. [12] Device according to claim 10 or 11, wherein the front interconnect structure (140) further comprises: several line contacts (128) that contact the conductor track (118), wherein the interconnects are connected to the line contacts (128). [13] Device according to any one of the preceding claims 10 to 12, wherein the interconnects have a conductor track (118), wherein a width of the busbar (160P) is greater than a width of the conductor track (118). [14] Procedure encompassing: Deposition of an etch stop layer (94) on a first epitaxial source / drain region (92), a second epitaxial source / drain region (92) and a gate structure (100), wherein the first epitaxial source / drain region (92) and the second epitaxial source / drain region (92) are arranged on opposite sides of the gate structure (100); Deposition of an interlayer dielectric, ILD (96), on the etch stop layer (94); Etching of a first opening (106) through the ILD (96) and the etch stop layer (94), wherein the first opening (106) exposes a front face of the first epitaxial source / drain region (92) and a front face of the second epitaxial source / drain region (92) remains covered by the etch stop layer (94) after etching of the first opening (106); and Forming a source / drain contact (112) in the first opening (106), wherein the source / drain contact (112) contacts the first epitaxial source / drain region (92), wherein the etching of the first opening comprises: Structuring a mask (108) over the ILD (96), wherein the mask (108) has a structure of openings over the first epitaxial source / drain region (92) and the second epitaxial source / drain region (92); after structuring, covering a section of the structure of openings above the second epitaxial source / drain region (92); and after covering, etching the ILD (96) and the etch stop layer (94) using the mask (108) as an etching mask. [15] The method of claim 14, further comprising: Etching of a second opening (114) through the ILD (96), wherein the second opening exposes the etch stop layer (94); and Forming a conductor track (118) in the second opening (114), wherein the conductor track (118) contacts the etch stop layer (94). [16] The method of claim 15, wherein the etching of the first opening (106) comprises: Etching of the ILD (96) with initial etching process parameters; and Etching of the etch stop layer (94) with second etching process parameters, where the second etching process parameters are different from the first etching process parameters. [17] Method according to claim 16, wherein etching the second opening (114) comprises etching the ILD (96) with the first etching process parameters and does not include etching the etch stop layer (94).

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