INTEGRATED CIRCUIT LAYOUT, METHOD, STRUCTURE AND SYSTEM

Abstract

Method (200) for generating an IC layout diagram, the method comprising: Arranging (210) a first active area (AR2) between and adjacent to a second and a third active area (AR1, AR3) in the IC layout diagram, wherein the first, second and third active areas each extend in a first direction (X); Crossing (220) of the first active region (AR2) with the first to fourth adjacent gate regions (GR2, ..., GR5), defining the respective positions of a gate of an antifuse structure (B2P) of a first antifuse bit (B2), a gate of a transistor (B2R) of the first antifuse bit (B2), a gate of a transistor (B5R) of a second antifuse bit (B5) and a gate of an antifuse structure (B5P) of the second antifuse bit (B5); Align (230) separate first and second conductive areas (Z1, Z3) along the first direction (X) and between the first and second active area (AR2, AR1), thereby intersecting the first conductive area (Z1) with the first gate area (GR2) and the second conductive area (Z3) with the fourth gate area (GR5); Align (240) separate third and fourth conductive areas (Z2, Z4) along the first direction (X) and between the first and third active areas (AR2, AR3), thereby either intersecting the third conductive area (Z2) with the first gate area (GR2) and the fourth conductive area (Z4) with the third gate area (GR4), or intersecting the third conductive area (Z2) with the second gate area (GR3) and the fourth conductive area (Z4) with the fourth gate area (GR5), Arranging a first via area (VR1) at the intersection of the first conductive area (Z1) and the first gate area (GR2); Arranging a second via area (VR3) at the intersection of the second conductive area (Z3) and the fourth gate area (GR5); and if aligning the separated third and fourth conductive areas (Z2, Z4) involves crossing the third conductive area (Z2) with the first gate area (GR2) and the fourth conductive area (Z4) with the third gate area (GR4): placing a third via area (VR2) at the intersection of the third conductive area (Z2) and the first gate area (GR2), and placing a fourth via area (VR4) at the intersection of the fourth conductive area (Z4) and the third gate area (GR4); or where aligning the separated third and fourth conductive regions (Z2, Z4) includes crossing the third conductive region (Z2) with the second gate region (GR3) and the fourth conductive region (Z4) with the fourth gate region (GR5): arranging a third via region (VR2) at the intersection of the third conductive region (Z2) and the second gate region (GR3), and arranging a fourth via region (VR4) at the intersection of the fourth conductive region (Z4) and the fourth gate region (GR5); wherein at least one of the operations is arranging (210) the first active region (AR2), crossing (220) the first active region (AR2) with the first to fourth adjacent gate regions (GR2, ..., GR5), alignment (230) of the separated first and second conductive areas (Z1, Z3) or alignment (240) of the separated third and fourth conductive areas (Z2, Z4) is performed by a processor of a computer.

Description

STATE OF THE ART

[0001] Integrated circuits (ICs) sometimes incorporate one-time programmable memory (OTP) elements to provide non-volatile memory (NVM), in which data is not lost when the IC is powered off. One type of NVM includes an antifuse bit, which is integrated into the IC using a layer of dielectric material (oxide, etc.) connected to other circuit elements. To program an antifuse bit, an electrical programming field is applied to the dielectric material layer to permanently modify (for example, break down) the dielectric material, thereby reducing its resistance. To determine the status of an antifuse bit, a read voltage is typically applied to the dielectric material layer, and the resulting current is measured.

[0002] German patent application DE 10 2016 103 820 A1 describes a semiconductor device comprising a substrate, a first transistor which is driven by an inverted voltage level of a first input signal to pull up a first node, a second transistor which is driven by a voltage level of a second input signal to pull down the first node, a third transistor which is driven by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor which is driven by a voltage level of the first input signal to pull down the first node, a fifth transistor which is driven by the voltage level of the second input signal to pull down a second node, and a sixth transistor which is driven by the inverted voltage level of the first input signal to pull up the second node.a seventh transistor, which is driven by the voltage level of the first input signal to pull the second node down, and an eighth transistor, which is driven by the inverted voltage level of the second input signal to pull the second node up.

[0003] DE 10 2019 101 570 A1 describes a method for generating an IC layout diagram comprising the following steps: crossing an active region with a first and a second gate region to define positions of a first and a second anti-fuse structure; superimposing the first gate region with a first conductive region to define a position of an electrical connection between the first conductive region and the first gate region; and superimposing the second gate region with a second conductive region to define a position of an electrical connection between the second conductive region and the second gate region.The first and second conductive regions are aligned along a direction perpendicular to a direction along which the first and second gate regions run, and at least one of the steps crossing the active region with the first gate region, crossing the active region with the second gate region, superimposing the first gate region, and superimposing the second gate region is performed by a computer processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1A - 1D are diagrams of antifuse layouts in accordance with some embodiments. The Fig. Figures 1E - 1G are schematic diagrams of sections of an antifuse arrangement in accordance with some embodiments. Fig. Figure 2 is a flowchart of a method for generating an IC layout diagram in accordance with some embodiments. The Fig. 3A - 3D are diagrams of antifuse arrangements in accordance with some embodiments. Fig. Figure 4 is a flowchart of a method for generating an IC layout diagram in accordance with some embodiments. The Fig. 5A - 5C are diagrams of an IC component in accordance with some embodiments. Fig. Figure 6 is a flowchart of a method for operating an antifuse bit in accordance with some embodiments. Fig. Figure 7 is a block diagram of an electronic design automation (EDA) system in accordance with some embodiments. Fig. Figure 8 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, processes, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples. Other components, values, processes, materials, arrangements, or the like are considered.For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact with each other, but may also include embodiments in which additional features may be formed between the first and second features in such a way that the first and second features cannot be in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and / or symbols in the various examples. This repetition serves the purpose of simplification and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, terms describing spatial relationships, such as "below," "underneath," "low," "above," "upper," and the like, may be used herein for the purpose of simplifying the description of the relationship between an element or feature depicted in the figures and another element or feature. These terms describe spatial relationships to encompass various orientations of the device during use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the terms describing spatial relationships used herein may be interpreted accordingly.

[0007] In various embodiments, an IC layout and an antifuse device manufactured based on the IC layout feature four electrical connections between each of the active areas corresponding to two antifuse bits and the two adjacent active areas. Compared to approaches with fewer than four electrical connections between an active area corresponding to the two antifuse bits and the adjacent active areas, an increased number of parallel current paths to a given antifuse bit reduces the path resistance, thereby increasing the current and improving performance in both programming and reading operations.

[0008] The Fig. 1A - 1C are diagrams of antifuse layouts 100A - 100C in accordance with some embodiments. Fig. Figures 1A-1C show top views of the respective antifuse layouts 100A-100C, with an X-direction and a Y-direction perpendicular to the X-direction. Antifuse layout 100A has a layout cell CA1 adjacent to a layout cell CB1 along the X-direction, thus sharing a common boundary BA extending in the Y-direction; antifuse layout 100B has a layout cell CB2 adjacent to a layout cell CC1 along the X-direction, thus sharing a common boundary BB extending in the Y-direction; and antifuse layout 100C has a layout cell CB2 adjacent to a layout cell CB1 along the X-direction, thus sharing a common boundary BC extending in the Y-direction.

[0009] Each of the antifuse layouts 100A and 100B has an alternative embodiment, indicated by an optionally reversed orientation in the Y direction. The alternative embodiment of antifuse layout 100A has a layout cell CA2, which corresponds to layout cell CA1 reversed in the Y direction, and the alternative embodiment of antifuse layout 100B has a layout cell CC2, which corresponds to layout cell CC1 reversed in the Y direction. Due to considerations of vertical symmetry, layout cells CB1 and CB2 are not affected by the reversal in the Y direction.

[0010] An IC layout diagram, for example an IC layout diagram which has an antifuse layout 100A - 100C, can be used in a manufacturing process, such as an IC manufacturing flow in connection with an IC manufacturing system 800, which is shown below in relation to Fig. 8 is discussed as part of a definition of one or more features of an IC component, such as an IC 500, which is discussed below in relation to the Fig. 5A - 5C is discussed, will be used.

[0011] In various embodiments, a layout cell, such as layout cell CA1, CA2, CB1, CB2, CC1 or CC2, is a standalone cell, such as one in a cell library, such as cell library 707, which is described below in relation to Fig. 7 is discussed, stored standard cell, or is part of a larger IC layout diagram, such as a standard cell or other circuit, which has features in addition to those which are in Fig. 1A - 1C are shown. In some embodiments, several layout cells, such as layout cells CA1(CA2) / CB1, CB2 / CC1(CC2), or CB2 / CB1, are stored as a single cell in a cell library. In some embodiments, an antifuse arrangement, such as an antifuse layout 100, which is shown below with respect to Fig. 1D - 1G discusses a layout cell, for example the layout cell CA1, CA2, CB1, CB2, CC1 or CC2.

[0012] Each of the antifuse layouts 100A–100C has a bit line BL1 extending in the X direction. In some embodiments, the corresponding layout cell CA1, CA2, CB1, CB2, CC1, or CC2 has a segment of the bit line BL1 that intersects with a specific layout cell. In other embodiments, the corresponding layout cell CA1, CA2, CB1, CB2, CC1, or CC2 does not have the segment of the bit line BL1 that intersects with a specific layout cell; instead, the segment is a component of the antifuse layout 100A, 100B, or 100C, separate from the layout cell in question.

[0013] Each of the antifuse layouts 100A - 100C has adjacent gate regions GR1 - GR6 extending in the Y direction. In various embodiments, the corresponding layout cell CA1, CA2, CB1, CB2, CC1 or CC2 either has sections of some or all of the gate regions GR1 - GR6 that intersect with a particular layout cell, or the corresponding layout cell CA1, CA2, CB1, CB2, CC1 or CC2 does not have these sections, which instead are components of the antifuse layout 100A, 100B or 100C separate from the layout cell in question.

[0014] Each of the layout cells CA1, CA2, CB1, CB2, CC1, and CC2 has sections of each of the adjacent active areas AR1, AR2, and AR3 extending in the X-direction. A layout cell CA1, CA2, or CB2 adjacent to a layout cell CB1, CC1, or CC2 along the X-direction jointly defines a combined section of active area AR1, an entirety of active area AR2, and a combined section of active area AR3. In various embodiments, a layout cell CA1, CA2, or CB2 adjacent to a layout cell CB1, CC1, or CC2 jointly borders layout cells (not shown) in addition to layout cell CA1, CA2, or CB2 and layout cell CB1, CC1, or CC2, thereby jointly defining one or both of the active areas AR1 or AR3 in their entirety.

[0015] An active region, for example, active region AR1, AR2, or AR3, is a region in an IC layout diagram, for example, an IC layout diagram that includes an antifuse layout 100A-100C, which is incorporated in a manufacturing process as part of the definition of an active region, also referred to as an oxide diffusion or definition (OD), in a semiconductor substrate in which one or more IC component features, for example, a source / drain region, are formed. In various embodiments, an active region is an active n- or p-region of a planar transistor or a fin field-effect transistor (FinFET). In some embodiments, an active region is part of a definition of an active region AA1-AA4, which is subsequently described in relation to the Fig. 5A - 5C is discussed and incorporated into a manufacturing process.

[0016] A gate region, for example, a gate region GR1-GR6, is a region in an IC layout diagram, for example, an IC layout diagram that has an antifuse layout 100A-100C, which is incorporated in the manufacturing process as part of a definition of a gate structure in the IC component, which has at least one conductive material or one dielectric material. In various embodiments, one or more gate structures corresponding to gate regions GR1-GR6 have at least one conductive material arranged over at least one dielectric material. In some embodiments, a gate region is incorporated in a manufacturing process as part of a definition of a gate structure G2-G5, which is subsequently described in relation to the Fig. 5A - 5C will be discussed.

[0017] In the embodiments which are described in the Fig. As shown in Figures 1A-1C, each of the gate regions GR2-GR5 intersects with each of the active regions AR1, AR2, and AR3. In various embodiments, one or more of the gate regions GR2-GR5 do not intersect with one or more of the active regions AR1 or AR3, or one or more of the gate regions (not shown) intersect with one or more of the active regions AR1, AR2, or AR3 in addition to the gate regions GR2-GR5.

[0018] In the embodiments which are described in the Fig. As shown in Figures 1A-1C, neither gate region GR1 nor GR6 intersects with any of the active regions AR1, AR2, or AR3. In some embodiments, gate regions GR1 and GR6 are referred to as dummy gate regions, corresponding to the dummy gate structures of an IC component. In various embodiments, one or more of gate regions GR1 or GR6 intersect with, or are adjacent to, one or more of the active regions AR1, AR2, or AR3. In various embodiments, layout cell CA1, CA2, or CB2 has one or more gate regions (not shown) in addition to gate regions GR1-GR3, and / or layout cell CA1, CA2, or CB2 does not have one or more of gate regions GR1-GR3.In various embodiments, the layout cell CB1, CC1 or CC2 has one or more gate areas (not shown) in addition to the gate areas GR4 - GR6, and / or the layout cell CB1, CC1 or CC2 does not have one or more of the gate areas GR4 - GR6.

[0019] Each of the layout cells CA1, CA2, and CB2 has a conductive area Z1 extending in the X direction between the active areas AR1 and AR2, and a conductive area Z2 extending in the X direction between the active areas AR2 and AR3. Each of the layout cells CB1, CC1, and CC2 has a conductive area Z3 extending in the X direction between the active areas AR1 and AR2, and a conductive area Z4 extending in the X direction between the active areas AR2 and AR3. Conductive area Z1 is aligned in the X direction with conductive area Z3, and conductive area Z2 is aligned in the X direction with conductive area Z4.

[0020] A conductive region, for example, the bit line BL1 or a conductive region Z1-Z4, is a region in an IC layout diagram, for example, an IC layout diagram showing an antifuse layout 100A-100C, which the manufacturing process includes as part of a definition of one or more segments of one or more conductive layers in an IC component. In various embodiments, one or more of the conductive regions Z1-Z4 or the bit line BL1 correspond to one or more segments of the same or other conductive layer(s) in the IC component. In various embodiments, one or more of the conductive regions Z1-Z4 or the bit line BL1 correspond to one or more of a first metal layer, a second metal layer, or a higher metal layer in the IC component.In some embodiments, one or more of the conductive regions Z1–Z4 or the bit line BL1 correspond to a metal layer, which is referred to as the metal zero layer in the IC component. In some embodiments, a manufacturing process includes a conductive region, for example, a conductive region Z1–Z4 or the bit line BL1, as part of a definition of a conductive segment M11–M18 or M21–M24 or a bit line MBL1–MBL4, which are subsequently referred to in relation to the... Fig. 5A - 5C will be discussed.

[0021] In each of the antifuse layouts 100A - 100C, the conductive area Z1 intersects with the gate areas GR1 and GR2, and a via area VR1 is located at the position where the conductive area Z1 intersects with the gate area GR2.

[0022] In antifuse layout 100A, the conductive area Z2 intersects with each of the gate areas GR1–GR3, and a via area VR2 is located at the position where the conductive area Z2 intersects with the gate area GR3. In some embodiments, a conductive area Z2 in antifuse layout 100A intersects with the gate areas GR2 and GR3 but does not intersect with the gate area GR1. In antifuse layouts 100B and 100C, the conductive area Z2 intersects with the gate areas GR1 and GR2, and a via area VR2 is located at the position where the conductive area Z2 intersects with the gate area GR2.

[0023] In each of the antifuse layouts 100A - 100C, the conductive area Z3 intersects with the gate areas GR5 and GR6, and a via area VR3 is located at the position where the conductive area Z3 intersects with the gate area GR5.

[0024] In antifuse layouts 100A and 100C, the conductive area Z4 intersects with gate areas GR5 and GR6, and a via area VR4 is located at the point where conductive area Z4 intersects with gate area GR5. In antifuse layout 100B, the conductive area Z4 intersects with each of gate areas GR4–GR6, and a via area VR4 is located at the point where conductive area Z4 intersects with gate area GR4. In some embodiments, a conductive area Z4 in antifuse layout 100B intersects with gate areas GR4 and GR5 but does not intersect with gate area GR6.

[0025] A via area, for example a via area V1 - V4, is an area in an IC layout diagram, for example an IC layout diagram having the antifuse layout 100A - 100C, which the manufacturing process includes as part of the definition of one or more segments of one or more conductive layers in the IC component, which are designed to form an electrical connection between a segment of a conductive layer, corresponding to a conductive area, and a gate structure, corresponding to a gate area, or another segment of a conductive layer, corresponding to another conductive area.In various embodiments, one or more segments of a conductive layer, which is formed based on a via region, have a via between a gate structure or a segment in a specific metal layer and a segment in an overlying metal layer of the IC device. In some embodiments, a via region corresponds to a slot via or a square via in the IC device. In some embodiments, a via region in a manufacturing process is part of the definition of a via V11-V18 or V21-V28, which is subsequently referred to in relation to the... Fig. 5A - 5C will be discussed.

[0026] In each of the antifuse layouts 100A - 100C, the bit line BL1 crosses the active area AR2, and a contact area CR1 is located within the active area AR2 between the gate areas GR3 and GR4 and along the boundary BA, BB, or BC between a layout cell CA1, CA2, or CB2 and a layout cell CB1, CC1, or CC2. In various embodiments, one or more antifuse layouts 100A - 100C have one or more bit lines (not shown) and one or more contact areas (not shown) in addition to the bit line BL1 and the contact area CR1, for example, a bit line and a contact area that cross the active area AR1 or AR3.

[0027] A contact area, for example contact area CR1, is an area in an IC layout diagram, for example an IC layout diagram having the antifuse layout 100A - 100C, which the manufacturing process includes as part of defining one or more segments of one or more conductive layers in the IC device. This contact area is configured to form an electrical connection between a segment corresponding to a conductive area, such as bit line BL1, and an active area corresponding to an active area, such as active area AR2. In various embodiments, the one or more segments of a conductive layer formed based on a contact area have contact between the corresponding active area and the conductive segment of the IC device.In some embodiments, a manufacturing process includes a contact area as part of the definition of a contact C1 - C4, which is subsequently referred to in relation to the . Fig. 5A - 5C will be discussed.

[0028] Due to the design discussed above, an IC component manufactured based on an antifuse layout 100A - 100C has antifuse bits B2 and B5, which are located within the active area based on the active region AR2. The antifuse bit B2 has an antifuse structure B2P, which has a gate (also designated B2P) located at a position defined by the intersection of the active region AR2 and the gate region GR2, and a transistor B2R, which has a gate (also designated B2R) located at a position defined by the intersection of the active region AR2 and the gate region GR3.The antifuse bit B5 has an antifuse structure B5P, which has a gate (also designated B5P) arranged at a position defined by the intersection of the active area AR2 and the gate area GR5, and a transistor B5R, which has a gate (also designated B5R) arranged at a position defined by the intersection of the active area AR2 and the gate area GR4.

[0029] In embodiments where an antifuse layout 100A-100C is located on layout cells adjacent to the active area AR1, an IC component manufactured based on the antifuse layout 100A-100C and the adjacent layout cells has antifuse bits B1 and B4, which are located within the active area based on the active area AR1. Antifuse bit B1 has an antifuse structure B1P, which includes a gate (also designated B1P) located at a position defined by the intersection of the active area AR1 and the gate area GR2, and a transistor B1R, which has a gate (also designated B1R) located at a position defined by the intersection of the active area AR1 and the gate area GR3.The antifuse bit B4 has an antifuse structure B4P, which has a gate (also designated as B4P) arranged at a position defined by the intersection of the active area AR1 and the gate area GR5, and a transistor B4R, which has a gate (also designated as B4R) arranged at a position defined by the intersection of the active area AR1 and the gate area GR4.

[0030] In embodiments where an antifuse layout 100A-100C is located on layout cells adjacent to the active area AR3, an IC component fabricated based on the antifuse layout 100A-100C and the adjacent layout cells has antifuse bits B3 and B6, which are located within the active area based on the active area AR3. Antifuse bit B3 has an antifuse structure B3P, which includes a gate (also designated B3P) located at a position defined by the intersection of the active area AR3 and the gate area GR2, and a transistor B3R, which has a gate (also designated B3R) located at a position defined by the intersection of the active area AR3 and the gate area GR3.The antifuse bit B6 has an antifuse structure B6P, which has a gate (also designated as B6P) arranged at a position defined by the intersection of the active area AR3 and the gate area GR5, and a transistor B6R, which has a gate (also designated as B6R) arranged at a position defined by the intersection of the active area AR3 and the gate area GR4.

[0031] For each of the antifuse structures B1P - B6P, at least one section of the gate structure, based on the corresponding gate region GR2 or GR5 and arranged above the active area based on the corresponding active region AR1 - AR3, corresponds to a gate comprising a layer of one or more dielectric materials. These materials are configured such that, during operation, a sufficiently strong electric field applied across the dielectric layer permanently alters the dielectric material, thereby significantly reducing the resistance of the dielectric layer from its level prior to the application of the electric field. This permanent alteration of the dielectric material is also referred to as dielectric breakdown in some embodiments. In some embodiments, one or more of the antifuse structures B1P - B6P are designated as a programming transistor.

[0032] Accordingly, transistors B1R - B6R are electrically connected to their respective antifuse structures B1P - B6P via active area sections based on corresponding active areas AR1 - AR3 between gate areas GR2 and GR3 or between gate areas GR4 and GR5. Transistors B1R - B6R are also electrically connected in series via active area sections based on corresponding active areas AR1 - AR3 between gate areas GR3 and GR4 to one or more conductive segments corresponding to contact area CR1, and to one or more segments based on corresponding bit lines, for example, bit line BL1.

[0033] The gate structure corresponding to gate area GR2 is designed as a connection for each of the antifuse structures B1P - B3P, the gate structure corresponding to gate area GR3 is designed as the gate for each of the transistors B1R - B3R, the gate structure corresponding to gate area GR4 is designed as the gate for each of the transistors B4R - B6R, and the gate structure corresponding to gate area GR5 is designed as a connection for each of the antifuse structures B4P - B6P.

[0034] In each of the antifuse layouts 100A - 100C, the conductive area Z1 and the via area VR1 define a position of an electrical connection to each of the antifuse structures B1P - B3P through the gate structure, which corresponds to the gate area GR2.

[0035] In the 100A antifuse layout, the conductive area Z2 and the via area VR2 define a position for an electrical connection to each of the transistors B1R - B3R through the gate structure, which corresponds to the gate area GR3. In the 100B and 100C antifuse layouts, the conductive area Z2 and the via area VR2 define a position for an electrical connection to each of the antifuse structures B1P - B3P through the gate structure, which corresponds to the gate area GR2.

[0036] In each of the antifuse layouts 100A - 100C, the conductive area Z3 and the via area VR3 define a position of an electrical connection to each of the antifuse structures B4P - B6P through the gate structure, which corresponds to the gate area GR5.

[0037] In the 100A and 100C antifuse layouts, the conductive area Z4 and the via area VR4 define a position for an electrical connection to each of the antifuse structures B4P - B6P through the gate structure, which corresponds to the gate area GR5. In the 100B antifuse layout, the conductive area Z4 and the via area VR4 define a position for an electrical connection to each of the transistors B4R - B6R through the gate structure, which corresponds to the gate area GR4.

[0038] In each of the antifuse layouts 100A - 100C, the conductive areas Z1 and Z3 are separated by a distance D1 in the X direction. In the antifuse layouts 100A and 100B, the conductive areas Z2 and Z4 are separated by a distance D2 in the X direction, and in the antifuse layout 100C, the conductive areas Z2 and Z4 are separated by a distance D1.

[0039] Each of the distances D1 and D2 has a value greater than or equal to a predetermined distance based on one or more design rules for the conductive layer, which has the conductive regions Z1–Z4, and thus corresponds to one or more of the design rules. In various embodiments, the predetermined distance is based on one or more combinations of a minimum distance rule for a metal layer, for example, a first metal layer, or a minimum distance rule for a voltage difference based on the circuit design between the conductive regions Z1 and Z3 or between the conductive regions Z2 and Z4.In one example, a minimum distance rule for a voltage difference based on circuit design is a minimum distance between two conductors which are designed such that one of the two conductors is able to carry a power supply voltage level, and the other of the two conductors is able to carry a reference or ground voltage level.

[0040] In some embodiments, one or both of the distances D1 or D2 have a value greater than or equal to a minimum distance rule based on one or more constraints of the manufacturing process. In some embodiments, the minimum distance rule is based on a wavelength of an electromagnetic wave used in one or more lithographic operations of a manufacturing process. In some embodiments, the minimum distance rule is based on an extreme ultraviolet (EUV) manufacturing process. In some embodiments, an EUV manufacturing process corresponds to a wavelength in the range of 12 nanometers (nm) to 15 nm. In some embodiments, an EUV manufacturing process corresponds to a wavelength in the range of approximately 13.5 nm.

[0041] In the embodiments, which are a the Fig. In the illustrations 1A - 1C, the distance D1 is greater than the distance D2. In various embodiments, the distance D1 is equal to or less than the distance D2.

[0042] In the embodiments which are described in the Fig. In the figures 1A-1C, the distance D1 is sufficiently large so that the corresponding conductive area Z1 or Z2 does not intersect with the gate area GR3, and the corresponding conductive area Z3 or Z4 does not intersect with the gate area GR4. In various embodiments, the distance D1 corresponds to one or both of the corresponding conductive areas Z1 or Z2 that intersect with the gate area GR3, or to the corresponding conductive area Z3 or Z4 that intersects with the gate area GR4.

[0043] The distance D2 is sufficiently small that either the conductive area Z2 crosses with the gate area GR3 and the conductive area Z4 with the gate area GR5, or that the conductive area Z2 crosses with the gate area GR2 and the conductive area Z4 with the gate area GR4.

[0044] In an IC component manufactured based on antifuse layouts 100A-100C, the total number of electrical connections to the antifuse structures B1P-B6P and the transistors B1R-B6R is based on two via-gate connections between each pair of adjacent active areas, in which antifuse bits B1-B6 are located. A total of four electrical connections are thus arranged between the two active areas adjacent to the active areas corresponding to two antifuse bits. Compared to approaches where a single via-gate connection is arranged between adjacent active areas, an IC component manufactured based on antifuse layouts 100A-100C is therefore able to have a higher number of electrical connections per antifuse bit.Based on the increased number of parallel current paths to a given antifuse bit, the path resistance is reduced and the current is increased, thereby improving performance in both programming and reading operations, as discussed further below.

[0045] Fig. Figure 1D is a diagram of the antifuse layout 100 in accordance with some embodiments. The antifuse layout 100 is an example of a layout of an antifuse arrangement based on a combination of antifuse layouts 100A - 100C. As shown in Fig. As shown in 1D, the antifuse layout 100, based on antifuse layouts 100A and 100B, has a layout cell CA1, which is adjacent to layout cell CB1 along the X-direction, and layout cells CA1 and CB1, which are adjacent to layout cells CB2 and CC1 together in the Y-direction. Details of layout cells CA1, CB1, CB2, and CC1 have been omitted for clarity.

[0046] Based on the design of layout cells CA1, CB1, CB2, and CC1, two unlabeled layout cells in the negative Y direction adjacent to layout cells CB2 and CC1, and gate regions GR2–GR5, antifuse layout 100 corresponds to antifuse bits AB1–AB8, each of which represents an example of antifuse bits B1–B6. Bit line ABL1 is connected to antifuse bits AB1 and AB5, bit line ABL2 is connected to antifuse bits AB2 and AB6, bit line ABL3 is connected to antifuse bits AB3 and AB7, and bit line ABL4 is connected to antifuse bits AB4 and AB8. Conductive regions AZ1–AZ8 correspond to examples of conductive regions Z1–Z4 of antifuse layouts 100A–100C.

[0047] The antifuse layout 100 features conductive areas MR1–MR4, each extending in the Y direction. Conductive area MR1 intersects with each of conductive areas AZ1–AZ4, and vias AVR1, AVR3, and AVR4 are located at the points where conductive area MR1 intersects with conductive areas AZ1, AZ3, and AZ4, respectively. Conductive area MR2 intersects with each of conductive areas AZ1–AZ4, and a via AVR2 is located at the point where conductive area MR2 intersects with conductive area AZ2. The conductive area MR3 intersects with each of the conductive areas AZ5 - AZ8, and a via area AVR8 is located at the position where the conductive area MR3 intersects with the conductive area AZ8.The conductive area MR4 intersects with each of the conductive areas AZ5 - AZ8, and via areas AVR5 - AVR7 are located at the positions where the conductive area MR4 intersects with the conductive areas AZ5 - AZ7.

[0048] In the Fig. In the embodiment shown in Figure 1D, the antifuse layout has 100 conductive areas MR1–MR4, gate areas GR2–GR5, and bit lines ABL1–ABL4, which correspond to a total of eight antifuse bits AB1–AB8. In various embodiments, the antifuse layout has 100 conductive areas MR1–MR4 and gate areas GR2–GR5 extending in the positive and / or negative Y direction, thus corresponding to additional antifuse bits (not shown) besides AB1–AB8. In various embodiments, the antifuse layout has 100 bit lines ABL1–ABL4 extending in the positive and / or negative X direction, thus corresponding to additional antifuse bits (not shown) besides AB1–AB8.

[0049] An IC component, for example an antifuse arrangement, manufactured on the basis of the antifuse layout 100 is therefore designed such that a conductive segment based on the conductive area MR1 is electrically connected to terminals of antifuse structures of each of the antifuse bits AB1 - AB4 by at least three current paths corresponding to the conductive areas AZ1, AZ3 and AZ4, and a conductive segment based on the conductive area MR2 is electrically connected to gates of transistors of each of the antifuse bits AB1 - AB4 by at least one current path corresponding to the conductive area AZ2.A conductive segment based on the conductive area MR3 is electrically connected to the gates of transistors of each of the antifuse bits AB5 - AB8 by at least one current path corresponding to the conductive area AZ8, and a conductive segment based on the conductive area MR4 is electrically connected to the terminals of antifuse structures of each of the antifuse bits AB5 - AB8 by at least three current paths corresponding to the conductive areas AZ5 - AZ7.

[0050] The gate structure corresponding to gate area GR2 is configured as the connection for each of the antifuse structures of antifuse bits AB1-AB4 and responds to a WLPo signal received at the segment corresponding to the conductive area MR1. The gate structure corresponding to gate area GR3 is configured as the gate for each of the transistors of antifuse bits AB1-AB4 and responds to a WLR0 signal received at the segment corresponding to the conductive area MR2. The gate structure corresponding to gate area GR4 is configured as the gate for each of the transistors of antifuse bits AB5-AB8 and responds to a WLR1 signal received at the segment corresponding to the conductive area MR3.The gate structure corresponding to gate area GR5 is designed as the connection of each of the antifuse structures of antifuse bits AB5–AB8 and responds to a signal WLP1 received at the segment corresponding to the conductive area MR4. The signals WLPo, WLRo, WLR1, and WLP1, and the antifuse bits AB1–AB8, are subsequently described in relation to the... Fig. 1E - 1G discussed.

[0051] Fig. Figure 1E is a schematic diagram of a section of the antifuse layout 100, corresponding to the antifuse bits AB1 and AB5, in accordance with some embodiments. As in Fig. As shown in Figure 1E, the bit line ABL1 is electrically connected to the first source / drain terminals of each of the transistors AB1R of the antifuse bit AB1 and AB5R of the antifuse bit AB5 in the corresponding section of the active area between the gate regions GR3 and GR4. The second source / drain terminal of transistor AB1R is electrically connected to a source / drain terminal of an antifuse structure AB1P of the antifuse bit AB1 in the corresponding section of the active area between the gate regions GR2 and GR3, and the second source / drain terminal of transistor AB5R is electrically connected to a source / drain terminal of an antifuse structure AB5P of the antifuse bit AB5 in the corresponding section of the active area between the gate regions GR4 and GR5.

[0052] The gate structure section corresponding to the gate area GR2 between the antifuse bit AB1 and one of the conductive areas AZ1 or AZ2 is embodied as a resistor RPo, and the gate structure section corresponding to the gate area GR5 between the antifuse bit AB5 and one of the conductive areas AZ5 or AZ6 is embodied as a resistor RP1.

[0053] During programming and reading operations at the antifuse bit AB1, the signal WLPo is applied to the antifuse structure AB1P via resistor RPo. Transistor AB1R is switched on in response to the signal WLR0 applied by the gate structure corresponding to gate area GR3, and a reference voltage is applied to the bit line ABL1. During programming and reading operations at the antifuse bit AB5, the signal WLP1 is applied to the antifuse structure AB5P via resistor RP1. Transistor AB5R is switched on in response to the signal WLR1 applied by the gate structure corresponding to gate area GR4, and the reference voltage level is applied to the bit line ABL1.

[0054] During programming and reading operations on one of the antifuse bits AB1 or AB5, a current IBL flows to the bit line ABL1. The magnitudes and polarities of the current IBL are based on the magnitudes and polarities of the signals WLPo and WLP1 with respect to the reference voltage applied to the bit line ABL1, as well as on path resistance values, which are embodied either by the series consisting of resistor RPo, antifuse structure AB1P and transistor AB1R, or by the series consisting of resistor RP1, antifuse structure AB5P and transistor AB5R.

[0055] In the Fig. In the embodiment shown in Figure 1E, the antifuse structures AB1P and AB5P and the transistors AB1R and AB5R are NMOS devices, whereby the transistors AB1R and AB5R are configured to be switched on in response to a respective signal WLR0 or WLR1 that has a sufficiently large positive value with respect to the reference voltage level. In some embodiments, the antifuse structures AB1P and AB5P and the transistors AB1R and AB5R are PMOS devices, whereby the transistors AB1R and AB5R are configured to be switched on in response to a respective signal WLR0 or WLR1 that has a sufficiently large negative value with respect to the reference voltage level.

[0056] During a programming process, the signal WLP0 or WLP1 has a programming voltage level such that a difference between the programming voltage level and the reference voltage level generates an electric field at the dielectric layer of the gate of the corresponding antifuse structure AB1P or AB5P, which is sufficiently large to permanently alter the dielectric material, with the resulting reduced resistance value being Fig. 1E is represented as a respective resistor RAB1 or RAB5.

[0057] In a read operation, the signal WLP0 or WLP1 has a read voltage level such that a difference between the read voltage level and the reference voltage level generates an electric field which is small enough to prevent a permanent change in the dielectric material of the corresponding antifuse structure AB1P or AB5P, and large enough to generate the current IBL, which has a detectable quantity by a read amplifier (not shown) and is used to determine a programmed status of the corresponding antifuse structure AB1P or AB5P.

[0058] In various embodiments, either the programming voltage level or the read voltage level, or both, are either positive or negative with respect to the reference voltage level.

[0059] Fig. 1F is a schematic diagram of a section of the antifuse layout 100, which corresponds to the antifuse bits AB1 - AB8, in accordance with some embodiments. Fig. 1F has the signals WLP0, WLR0, WLR1 and WLP1, the resistors RPo and RP1, the bit lines ABL1 - ABL4 and the antifuse bits AB1 - AB8, which are described above in relation to the Fig. 1D and Fig. 1E have been discussed, and the gate structures G2 - G5 are based on the respective gate areas GR2 - GR5, which are discussed above in relation to the Fig. 1A - 1D have been discussed.

[0060] Furthermore, it Fig. The 1F resistor also includes resistors RRo, RR1, and RABL1-RABL4. Resistor RR0 represents the section of the gate structure G3 between a specific antifuse bit AB1-AB4 and the conductive area AZ2; resistor RR1 represents the section of the gate structure G4 between a specific antifuse bit AB5-AB8 and the conductive area AZ8; and each of resistors RABL1-RABL4 represents one or more conductive segments corresponding to one of the bit lines ABL1-ABL4.

[0061] As above in relation to Fig. As discussed in 1E, the resistor RPo represents the length of the section of the gate structure G2 between the antifuse bit AB1 and one of the conductive areas AZ1 or AZ2, and the resistor RP1 represents the length of the section of the gate structure G5 between the antifuse bit AB5 and one of the conductive areas AZ5 or AZ6. In the Fig. 1F and Fig. In the embodiment shown in Figure 1G, each section of the gate structure G2 between the antifuse bits AB1 - AB4 and one of the nearest conductive areas AZ1, AZ3 or AZ4 has the same length, so that the resistance RPo has the same value for each of the antifuse bits AB1 - AB4, and each section of the gate structure G5 between the antifuse bits AB5 - AB8 and one of the nearest conductive areas AZ5 - AZ7 has the same length, so that the resistance RP1 has the same value for each of the antifuse bits AB1 - AB4.

[0062] Based on the layout of the antifuse 100, the length of a gate structure segment between a specific antifuse bit AB1-AB8 and the nearest conductive area AZ2 or AZ8 differs, at least in some cases, from the lengths of one or more gate structure segments between one or more other antifuse bits AB1-AB8 and the nearest conductive area AZ2 or AZ8. In such cases, the corresponding resistors RRo and / or RR1 have nominal values ​​that differ based on these varying lengths.

[0063] In at least some cases, in some embodiments, the length of a gate structure segment between a specific antifuse bit AB1-AB8 and the nearest conductive area AZ2 or AZ8 is equal to the length of one or more gate structure segments between one or more other antifuse bits AB1-AB8 and the nearest conductive area AZ2 or AZ8. In such cases, corresponding resistors RR0 and / or RR1 have the same nominal value based on the same lengths.

[0064] The resistances RABL1 - RABL4 have values ​​that vary based on the dimensions of the one or more conductive segments corresponding to the respective bit lines ABL1 - ABL4, where the dimensions encompass the bit line lengths, which vary based on the position of a specific antifuse bit along a particular bit line. In the Fig. 1F and Fig. In the embodiment shown in 1G, the specific resistance of one or more conductive segments is sufficiently small so that deviations are not significant, and it is assumed that each of the resistances RABL1 - RABL4 has the same nominal value.

[0065] Fig. 1G is a schematic diagram of a section of the antifuse layout 100, corresponding to the antifuse bits AB5 - AB8, in accordance with some embodiments. In addition to a subset of features, which are described in Fig. 1F are shown, indicates Fig. 1G the resistors RVZ and 2RPO.

[0066] Each of the resistors RVZ embodies a conductive path which connects to one of the via areas AVR5 - AVR7, a corresponding example of the via areas VR3 or VR4, which are described above in relation to the Fig. 1A - 1C have been discussed, and corresponds to a corresponding section of the conductive segment based on the conductive area AZ5 - AZ7 between one of the via areas AVR5 - AVR7 and the example of the via area VR3 or VR4. Based on each of the conductive areas AZ5 - AZ7 having similar layouts, the resistors RVZ have the same nominal value.

[0067] Each of the 2RPO resistors represents the section of the gate structure G5 between adjacent antifuse bits AB7 and AB8, free of any electrical connection corresponding to an example of the via VR3 or VR4. Since the gate structure G5 has two sections, one corresponding to a resistor RPo for the section corresponding to resistor 2RPo, the 2RPo resistor has a nominal value significantly larger than that of resistors RPo. In some embodiments, the 2RPo resistor has a nominal value approximately twice that of resistor RPo.

[0068] As above in relation to Fig. As discussed in 1E, the signal WLP1, during a read operation at the antifuse bit B5, causes the current IBL to flow through the antifuse bit AB5 and the bit line ABL1, and the value of the current IBL is used to determine the programmed state of the antifuse bit AB5. As discussed in the Fig. 1F and Fig. As shown in 1G, the read current path for the antifuse bit AB5 includes the antifuse bit AB5 itself and the resistor RABL1.

[0069] Based on the design of the Antifuse layout 100 according to the figure in Fig. 1G, the read current path also has parallel current paths between the antifuse bit AB5 and the signal WLP1 at the conductive segment corresponding to the conductive area MR4. Based on the conductive areas AZ5 and AZ6 adjacent to the antifuse bit AB5, each of the two parallel current paths has a path resistance equal to the sum of RPo and RVZ. Based on the conductive area AZ7, which is separated from the antifuse bit AB5 by the antifuse bit AB6, a third parallel current path has a path resistance equal to RVZ plus three times RPo.

[0070] Similarly, for each of the antifuse bits AB6-AB8, the read current path includes the corresponding antifuse bit, one of the resistors RABL2-RABL4 corresponding to a respective bit line ABL2-ABL4, and parallel current paths between the antifuse bit AB6-AB8 and the signal WLP1 at the conductive segment corresponding to the conductive area MR4. For each of the antifuse bits AB6-AB8, the parallel paths have at least one path with a path resistance equal to the sum of RPo and RVZ based on a corresponding conductive area AZ5-AZ7 adjacent to the antifuse bit AB6-AB8.

[0071] In comparison to approaches where parallel current paths have no conductive area adjacent to each of the antifuse bits, an antifuse arrangement based on the antifuse layout 100 has a reduced average current path resistance and therefore increased operating current values ​​for certain values ​​of a signal, for example the signal WLP1.

[0072] Since the parallel read current paths have at least one path based on a conductive area AZ5 - AZ7 adjacent to the antifuse bit AB8 - AB8, in an example based on the one in the Fig. In the embodiment shown in Figure 1D - 1G, the equivalent read current path resistance is reduced by 20% compared to an equivalent read current path resistance in an approach in which a particular antifuse bit does not have at least one path of parallel read current paths adjacent to the particular antifuse bit.

[0073] Fig. Figure 2 is a flowchart of a method 200 for generating an IC layout diagram in accordance with some embodiments. In some embodiments, generating the IC layout diagram includes generating an IC layout diagram of an antifuse layout, for example, an antifuse layout 100A - 100C, which is described above in relation to the Fig. 1A - 1C has been discussed, or an antifuse layout 100, which is mentioned above in relation to the Fig. 1D - 1G has been discussed.

[0074] The processes of method 200 can be carried out as part of a process for forming one or more IC components, including one or more antifuse structures, for example, the IC component 500, which is subsequently described in relation to the Fig. Sections 5A-5C discuss the manufacturing process based on the generated IC layout diagram. Examples of IC components include memory circuits, logic devices, processing devices, signal processing circuits, and the like.

[0075] In some embodiments, part of or the entire method 200 is executed by a computer processor. In some embodiments, part of or the entire method 200 is executed by a processor 702 of an EDA system 700, which is described below with respect to Fig. 7 is discussed and explained.

[0076] Some or all of the operations of procedure 200 can be carried out as part of a design process in a design house, e.g., design house 820, which is described below in relation to Fig. 8 will be discussed and explained.

[0077] In some embodiments, the processes of method 200 are described in the Fig. The processes are carried out in the sequence shown in Figure 2. In some embodiments, the operations of method 200 are carried out in a different order than that shown in Figure 2. Fig. The sequence shown in point 2 is carried out. In some embodiments, one or more operations are carried out before, between, during and / or after the execution of one or more operations of method 200.

[0078] In process 210, a first active region is arranged between and adjacent to a second and a third active region in an IC layout diagram, the first, second, and third active regions each extending in a first direction. In some embodiments, arranging the first active region includes obtaining one or more layout cells comprising some or all of the first, second, and third active regions. In some embodiments, arranging the first active region includes obtaining one or more layout cells from a cell library, for example, cell library 707, which is described below with respect to Fig. 7 is discussed.

[0079] In some embodiments, the arrangement of the first active area comprises defining one or more active areas by placing one or more layout cells adjacent to one or more additional layout cells. In some embodiments, the arrangement of the first active area comprises placing the active area AR2 between and adjacent to the active areas AR1 and AR3, which are described above with respect to the antifuse layouts 100A - 100C and the Fig. 1A - 1C have been discussed. In some embodiments, the respective arrangement of the first, second and third active areas, which extend in the first direction, includes the arrangement of active area AR2 between and adjacent to active areas AR1 and AR3, which extend in the X direction and are described above with respect to antifuse layouts 100A - 100C and the Fig. 1A - 1C have been discussed.

[0080] In some embodiments, the arrangement of the first active area comprises the arrangement of a plurality of active areas, including the first, second, and third active areas. In some embodiments, the arrangement of the plurality of active areas comprises the arrangement of the plurality of active areas of an antifuse arrangement. In some embodiments, the arrangement of the plurality of active areas of the antifuse arrangement comprises the arrangement of the plurality of active areas of the antifuse arrangement, which has the antifuse layout 100 described above in relation to the Fig. 1D - 1G has been discussed.

[0081] In process 220, the first active region is crossed with the first through fourth adjacent gate regions, thereby defining the positions of the gates of antifuse structures and transistors of a first and a second antifuse component, which in some embodiments are also referred to as antifuse bits. Crossing the first active region with the first gate region defines the position of the gate of the antifuse structure of the first antifuse bit; crossing the first active region with the second gate region defines the position of the gate of the transistor of the first antifuse bit; crossing the first active region with the third gate region defines the position of the gate of the transistor of the second antifuse bit; and crossing the first active region with the fourth gate region defines the position of the gate of the antifuse structure of the second antifuse bit.

[0082] In various embodiments, crossing the first active area with the first to fourth adjacent gate areas includes crossing the first active area with one or more gate areas in addition to the first to fourth adjacent gate areas and / or crossing the first to fourth adjacent gate areas with one or more active areas in addition to the first active area.

[0083] In some embodiments, the crossing of the first active area with the first to fourth adjacent gate areas includes the crossing of active area AR2 and one or both of the active areas AR1 or AR3 with the gate areas GR2 - GR5, which are described above with respect to the antifuse layouts 100A - 100C and the Fig. 1A - 1C have been discussed.

[0084] In some embodiments, crossing the first active region with the first to fourth adjacent gate regions comprises crossing a plurality of active regions, which include the first active region, with a plurality of gate regions, which include the first to fourth adjacent gate regions. In some embodiments, crossing the plurality of active regions with the plurality of gate regions comprises crossing the plurality of active regions with the plurality of gate regions of an antifuse arrangement. In some embodiments, crossing the plurality of active regions with the plurality of gate regions of the antifuse arrangement comprises crossing the plurality of active regions with the plurality of gate regions of the antifuse arrangement, which includes the above with respect to the Fig. 1D - 1G discussed antifuse layout 100 features.

[0085] In process 230, separate first and second conductive regions are aligned along the first direction and between the first and second active regions. Aligning the separate first and second conductive regions involves crossing the first conductive region with the first gate region and crossing the second conductive region with the fourth gate region. This alignment process also includes crossing the first conductive region with a gate region corresponding to the gate of the antifuse structure of the first antifuse component, and crossing the second conductive region with a gate region corresponding to the gate of the transistor of the second antifuse component.

[0086] In various embodiments, aligning the separate first and second conductive areas along the first direction includes aligning the conductive area Z1 of layout cell CA1(CA2) and the conductive area Z3 of layout cell CB1 along the X-direction as discussed above with respect to the antifuse layout 100A and the Fig. 1A, or aligning the conductive area Z1 of layout cell CB2 and the conductive area Z3 of layout cell CC1(CC2) along the X-direction according to the above discussion with respect to the antifuse layout 100B and Fig. 1B, or aligning the conductive area Z1 or Z2 of layout cell CB2 and the corresponding conductive area Z3 or Z4 of layout cell CB1 along the X-direction according to the above discussion with respect to the antifuse layout 100C and Fig. 1C.

[0087] In some embodiments, aligning the separated first and second conductive areas along the first direction comprises aligning first conductive areas of a plurality of first conductive areas with corresponding second conductive areas of a plurality of second conductive areas along the first direction. In various embodiments, aligning the separated first and second conductive areas along the first direction comprises aligning conductive areas AZ1 and AZ5 along the X-direction and / or aligning conductive areas AZ3 and AZ7 along the X-direction as discussed above with respect to the antifuse layout 100 and the Fig. 1D - 1G.

[0088] In some embodiments, aligning the separated first and second conductive regions involves separating the first and second conductive regions by a distance equal to or greater than a predetermined distance based on one or more design rules for the conductive layer containing the separated first and second conductive regions. In some embodiments, aligning the separated first and second conductive regions involves separating the first and second conductive regions by a distance equal to or greater than the minimum distance rule of a metal layer. In some embodiments, aligning the separated first and second conductive regions involves separating the first and second conductive regions by a distance corresponding to a minimum distance rule of an EUV manufacturing process.

[0089] In some embodiments, aligning the separated first and second conductive areas comprises arranging a plurality of conductive areas, each comprising the first and second conductive areas and one or more additional conductive areas. In some embodiments, arranging the plurality of conductive areas comprises arranging one or more bit lines. In various embodiments, arranging one or more bit lines comprises arranging one or more elements from the bit line BL1 and the contact area CR1, as described above with respect to the Fig. 1A - 1C have been discussed, or the bit lines ABL1 - ABL4, which are mentioned above in relation to the Fig. 1D - 1G have been discussed.

[0090] In process 240, separate third and fourth conductive areas are aligned along the first direction and between the first and third active areas. The alignment of the separate third and fourth conductive areas involves either crossing the third conductive area with the first gate area and the fourth conductive area with the third gate area, or crossing the third conductive area with the second gate area and the fourth conductive area with the fourth gate area.

[0091] In some embodiments, aligning the separated third and fourth conductive regions along the first direction includes separating the third and fourth conductive regions by a distance corresponding to a minimum distance rule, for example, the minimum distance rule of the EUV manufacturing process. In some embodiments, aligning the third and fourth conductive regions along the first direction includes separating the third and fourth conductive regions by a first distance corresponding to a minimum distance rule, and aligning the separated first and second conductive regions along the first direction includes separating the first and second conductive regions by a second distance greater than the first distance.In some embodiments, the separation of the third and fourth conductive areas by the first distance comprises the separation of conductive areas Z2 and Z4 by a distance D2, and the separation of the first and second conductive areas by the second distance comprises the separation of conductive areas Z1 and Z3 by the distance D1, according to the above discussion with respect to the antifuse layouts 100A - 100C and the . Fig. 1A - 1C.

[0092] In various embodiments, aligning the separated third and fourth conductive areas along the first direction includes aligning conductive area Z2 of layout cell CA1(CA2) and conductive area Z4 of layout cell CB1 along the X-direction as discussed above with respect to antifuse layout 100A and the Fig. 1A, or aligning the conductive area Z2 of layout cell CB2 and the conductive area Z4 of layout cell CC1(CC2) along the X-direction according to the above discussion with respect to the antifuse layout 100B and Fig. 1B.

[0093] In some embodiments, aligning the separated third and fourth conductive areas along the first direction comprises aligning third conductive areas of a plurality of third conductive areas with corresponding fourth conductive areas of a plurality of fourth conductive areas along the first direction. In various embodiments, aligning the separated third and fourth conductive areas along the first direction comprises aligning conductive areas AZ2 and AZ6 along the X-direction and / or aligning conductive areas AZ4 and AZ8 along the X-direction as discussed above with respect to the antifuse layout 100 and the Fig. 1D - 1G.

[0094] While in some embodiments the alignment of the separated third and fourth conductive areas includes the crossing of the third conductive area with the first gate area and the fourth conductive area with the third gate area, the alignment of the separated first and second conductive areas includes the crossing of the first conductive area with the second gate area and the second conductive area with the fourth gate area, for example, the alignment of conductive area Z2 of layout cell CA1(CA2) and conductive area Z4 of layout cell CB1 along the X-direction according to the above discussion with respect to antifuse layout 100A and Fig. 1A.

[0095] While in some embodiments the alignment of the separated third and fourth conductive areas includes the crossing of the third conductive area with the second gate area and the fourth conductive area with the fourth gate area, the alignment of the separated first and second conductive areas includes the crossing of the first conductive area with the first gate area and the second conductive area with the third gate area, for example, the alignment of conductive area Z2 of layout cell CB2 and conductive area Z4 of layout cell CC1(CC2) along the X-direction according to the above discussion with respect to antifuse layout 100B and Fig. 1B.

[0096] In some embodiments, both aligning the separated first and second conductive areas along the first direction and aligning the separated third and fourth conductive areas along the first direction include separating the respective first and second or third and fourth conductive areas by a distance that corresponds to a minimum distance rule. In some embodiments, both aligning the separated first and second conductive areas along the first direction and aligning the separated third and fourth conductive areas along the first direction include separating the respective first and second or third and fourth conductive areas by the distance D2, which is described above with reference to the antifuse layouts 100A - 100C and the Fig. 1A - 1C has been discussed.

[0097] In various embodiments, aligning the separated third and fourth conductive areas along the first direction includes aligning conductive areas AZ1 and AZ5 along the X-direction and / or aligning conductive areas AZ3 and AZ7 along the X-direction as discussed above with respect to the antifuse layout 100 and the Fig. 1D - 1G.

[0098] In some embodiments, aligning the separated third and fourth conductive areas along the first direction includes aligning separated fifth and sixth conductive areas along the first direction. In some embodiments, the third active area is located between the third and fourth conductive areas and the fifth and sixth conductive areas, and aligning the separated fifth and sixth conductive areas includes crossing the fifth conductive area with the first gate area and the sixth conductive area with the fourth gate area, for example, crossing one of the conductive areas AZ1 or AZ3 with the gate area GR2 and one of the conductive areas AZ5 or AZ7 with the gate area GR5, as discussed above with respect to the antifuse layout 100. Fig. 1D - 1G.

[0099] In some embodiments, the first active region is arranged between the first and second conductive regions and the fifth and sixth conductive regions, and if the alignment of the separated third and fourth conductive regions includes the crossing of the third conductive region with the first gate region and the fourth conductive region with the third gate region, then the alignment of the separated fifth and sixth conductive regions includes the crossing of the fifth conductive region with the second gate region and the sixth conductive region with the fourth gate region, and if the alignment of the separated third and fourth conductive regions includes the crossing of the third conductive region with the second gate region and the fourth conductive region with the fourth gate region,Thus, aligning the separated fifth and sixth conductive regions includes crossing the fifth conductive region with the first gate region and the sixth conductive region with the third gate region. In some embodiments, both aligning the separated third and fourth conductive regions and aligning the separated fifth and sixth conductive regions along the first direction include separating the respective third and fourth or fifth and sixth conductive regions by a distance corresponding to a minimum distance rule.

[0100] In some embodiments of process 250, the first to fourth vias are arranged. The first via is located at the intersection of the first conductive area and the first gate area, the second via is located at the intersection of the second conductive area and the fourth gate area, the third via is located at the intersection of the third conductive area and one of the first or second gate areas, and the fourth via is located at the intersection of the fourth conductive area and one of the third and fourth gate areas.

[0101] In various embodiments, the arrangement of the first to fourth vias comprises the arrangement of respective vias VR1, VR3, VR2 and VR4 of one of the antifuse layouts 100A - 100C, which are described above in relation to the Fig. 1A - 1C have been discussed.

[0102] In some embodiments, the arrangement of the first to fourth vias comprises the arrangement of a plurality of vias, each containing the first to fourth vias. In various embodiments, the arrangement of the plurality of vias comprises the arrangement of vias AVR1-AVR8, which are described above with respect to the antifuse layout 100 and the Fig. 1D - 1G have been discussed.

[0103] In some embodiments, the arrangement of the first via area up to the arrangement of the fourth via area each comprises the arrangement of a slotted or a square via area.

[0104] In process 260, the IC layout diagram is stored in a storage device in some embodiments. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in non-volatile, computer-readable memory or a cell library, e.g., a database, and / or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram over the network 714 of the EDA system 700, which is described below in relation to Fig. 7 is discussed.

[0105] In process 270, the IC layout diagram is arranged within an IC layout diagram of an antifuse assembly in some embodiments. In some embodiments, arranging the IC layout diagram within the IC layout diagram of the antifuse assembly involves rotating the IC layout diagram about one or more axes or translating the IC layout diagram relative to one or more additional IC layout diagrams in one or more directions.

[0106] In various embodiments, the arrangement of the IC layout diagram in the IC layout diagram of an antifuse arrangement includes the arrangement of one or more active areas in addition to the first and second active areas, the arrangement of one or more gate areas in addition to the first to fourth gate areas, the arrangement of one or more conductive areas in addition to the first and second conductive areas and / or the arrangement of one or more via areas in addition to the first and second via areas.

[0107] In some embodiments, arranging the IC layout diagram in the IC layout diagram of an antifuse arrangement includes arranging the IC layout diagram in one of the antifuse arrangements 300A - 300D, which are described below in relation to the Fig. 3A - 3D will be discussed.

[0108] In some embodiments, arranging the IC layout diagram in the IC layout diagram of an antifuse arrangement includes performing one or more operations of method 400, which is described below with respect to Fig. 4 is discussed.

[0109] In some embodiments, process 280 involves fabricating at least one or more semiconductor masks or at least one component in a layer of a semiconductor IC based on the IC assembly diagram. The fabrication of one or more semiconductor masks or at least one component in a layer of a semiconductor IC is described below with reference to Fig. 8 discussed.

[0110] In some embodiments, process 290 involves performing one or more manufacturing operations based on the IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the IC layout diagram. The performance of one or more manufacturing operations, e.g., one or more lithographic exposures, based on the IC layout diagram, is described below in relation to Fig. 8 discussed.

[0111] By performing some or all of the operations of procedure 200, an IC layout diagram is generated in which gate areas, according to the read current paths, exhibit the properties - and thus the advantages - that have been discussed above with regard to the antifuse layouts 100A - 100C and 100.

[0112] The Fig. 3A - 3D are diagrams of the respective antifuse arrangements 300A - 300D in accordance with some embodiments. Each of the Fig. 3A - 3D shows a top view of an IC layout diagram of an arrangement of layout cells CA1, CA2, CB1, CB2, CC1 and CC2, simplified for clarity, and the X and Y directions, each with respect to the Fig. 1A - 1D have been discussed.

[0113] Layout cells CA1 and CA2 are jointly embodied as layout cells CA, such that a position labeled CA corresponds to one of layout cells CA1 or CA2, and layout cells CC1 and CC2 are jointly embodied as layout cells CC, such that a position labeled CC corresponds to one of layout cells CC1 or CC2.

[0114] In antifuse arrangements 300A and 300B, pairs of rows are repeated in four columns extending in the Y direction, and in antifuse arrangements 300C and 300D, groups of three rows are repeated in columns extending in the Y direction. The total number of layout cells in each of the Fig. The illustration shown in 3A - 3D is for illustrative purposes only. In various embodiments, one or more of the antifuse arrangements 300A - 300D have layout cells (not shown) in addition to the layout cells shown in the Fig. 3A - 3D are depicted.

[0115] In the 300A antifuse arrangement, which is in Fig. As shown in 3A, each pair of rows has a first row (not marked) in which each of the layout cells CA is adjacent to a layout cell CB1 in the X direction, corresponding to the antifuse layout 100A, which is shown above in relation to Fig. 1A has been discussed, and a second row (not marked) in which each of the layout cells CB2 is adjacent to a layout cell CC in the X direction, corresponding to the antifuse layout 100B, which was discussed above in relation to Fig. As discussed in 1B, within each of the row pairs, each pair of layout cells CA and CB1 abuts a pair of layout cells CB2 and CC in the Y direction, corresponding to the antifuse layout 100, which was discussed above in relation to the Fig. 1D - 1G has been discussed.

[0116] In the Antifuse Arrangement 300B, which is in Fig. As shown in Figure 3B, each row pair has a first row (unlabeled) in which a first layout cell CA is adjacent to a layout cell CB1 in the X direction, corresponding to the antifuse layout 100A, and a layout cell CB2 is adjacent to a second layout cell CA in the X direction. Each row pair also has a second row (unlabeled) in which a layout cell CB2 is adjacent to a first layout cell CC in the X direction and a second layout cell CC is adjacent to a layout cell CB1 in the X direction. Within each row pair, each pair of layout cells CA and CB1 is adjacent to a pair of layout cells CB2 and CC in the Y direction, and each pair of layout cells CB2 and CA is adjacent to a pair of layout cells CC and CB1 in the Y direction.

[0117] In the Antifuse arrangement 300C, which is in Fig. As shown in Figure 3C, row pairs, configured in the manner described above with respect to the antifuse arrangement 300A, are separated by additional rows (unlabeled) that alternate between layout cells CB2 and layout cells CB1. In each additional row, each layout cell CB2 abuts a layout cell CB1, corresponding to the antifuse layout 100C, which is shown above with respect to Fig. 1C has been discussed. Each pair of layout cells CB2 and CB1 is adjacent in the Y direction to a pair of layout cells CA and CB1 and in the Y direction to a pair of layout cells CB2 and CC.

[0118] In the 300D antifuse arrangement, which is in Fig. As depicted in 3D, row pairs designed in the manner described above with respect to the antifuse arrangement 300B are separated by additional rows (not marked) designed as described above with respect to the antifuse arrangement 300C. In each additional row, first pairs of layout cells CB2 and CB1 are adjacent in the Y-direction to pairs of layout cells CA and CB1 and in the Y-direction to pairs of layout cells CB2 and CC; second pairs of layout cells CB2 and CB1 are adjacent in the Y-direction to pairs of layout cells CB2 and CA and in the Y-direction to pairs of layout cells CC and CB1.

[0119] Through the above-discussed configurations, each of the groups of four layout cells, which are highlighted in bold in each of the antifuse arrangements 300A and 300B, corresponds to two columns of antifuse bits, in which the highlighted cells define a total of three electrical connections to antifuse structures of the first column, one electrical connection to transistors of the first column, three electrical connections to antifuse structures of the second column, and one electrical connection to transistors of the second column.

[0120] Through the above-discussed configurations, each of the groups of six layout cells, which are highlighted in bold in each of the antifuse arrangements 300C and 300D, corresponds to two columns of antifuse bits, in which the highlighted cells define a total of five electrical connections to antifuse structures of the first column, one electrical connection to transistors of the first column, five electrical connections to antifuse structures of the second column, and one electrical connection to transistors of the second column.

[0121] In some embodiments, an antifuse arrangement (not shown) has additional rows of layout cells CB2 and CB1 in addition to those shown in the Fig. 3C and Fig. 3D depicted between and / or within pairs of lines, which according to the illustration in the Fig. 3A or Fig. 3B are designed, and the antifuse arrangement thus has groups of layout cells which have more than five, for example seven, electrical connections to antifuse structures for each electrical connection to transistors in a given column of antifuse bits.

[0122] In some embodiments, an antifuse arrangement (not shown) incorporates one or more combinations of the layout cell configurations described in the Fig. 3A - 3D are depicted, and thus exhibits groups of layout cells which have at least three electrical connections to antifuse structures for each electrical connection to transistors in a given column of antifuse bits.

[0123] By incorporating the designs discussed above, the IC layout diagram of the 300A - 300D antifuse arrangements and IC components manufactured on the basis thereof are able to realize the advantages discussed above with regard to the 100A - 100C and 100 antifuse layouts.

[0124] Fig. Figure 4 is a flowchart of a method 400 for generating an IC layout diagram in accordance with some embodiments. In some embodiments, generating the IC layout diagram includes generating an IC layout diagram of an antifuse arrangement, for example, an antifuse layout 100, which is described above in relation to the Fig. 1D - 1G has been discussed, or an antifuse arrangement 300A - 300D, which was discussed above in relation to the Fig. 3A - 3D has been discussed.

[0125] The processes of method 400 can be part of a process for forming one or more IC components, including one or more antifuse structures, for example, the IC component 500, which is subsequently described in relation to the Fig. Sections 5A-5C discuss the manufacturing process based on the generated IC layout diagram. Examples of IC components include memory circuits, logic devices, processing devices, signal processing circuits, and the like.

[0126] In some embodiments, part or all of the method 400 is executed by a computer processor. In some embodiments, part or all of the method 400 is executed by a processor 702 of an EDA system 700, which is described below with respect to Fig. 7 is discussed and explained.

[0127] Some or all of the operations of Procedure 400 can be carried out as part of a design process in a design house, e.g., Design House 820, which is described below in relation to Fig. 8 will be discussed and explained.

[0128] In some embodiments, the processes of method 400 are described in the Fig. The process is carried out in the sequence shown in Figure 4. In some embodiments, the operations of method 400 are carried out in a different order than that shown in Figure 4. Fig. The sequence shown in Figure 4 is carried out. In some embodiments, one or more operations are carried out before, between, during and / or after the execution of one or more operations of Method 400.

[0129] In some embodiments, process 410 includes recording the first through fourth layout cells. Recording the first through fourth layout cells comprises recording one of layout cells CA1 or CA2, one of layout cells CC1 or CC2, layout cell CB1, and layout cell CB2, which are described above with respect to antifuse layouts 100A–100C and the Fig. 1A - 1C have been discussed.

[0130] In some embodiments, taking up the first to fourth layout cells includes performing one or more operations of method 200, which is described above in relation to Fig. 2 has been discussed.

[0131] In some embodiments, taking up the first to fourth layout cells includes obtaining one or more layout cells from a cell library, for example, cell library 707, which is subsequently referred to in relation to Fig. 7 is discussed.

[0132] In process 420, the first through fourth layout cells are arranged by placing the first and second layout cells adjacent to the third and fourth layout cells. The first layout cell adjacent to the second layout cell defines a first active area, corresponding to a first and second antifuse bit; the third layout cell adjacent to the fourth layout cell defines a second active area, corresponding to a third and fourth antifuse bit; the first through fourth layout cells together define a third active area, corresponding to a fifth and sixth antifuse bit adjacent to the first and second antifuse bits, as well as the third and fourth antifuse bits.The first layout cell has a first via area that overlaps with a first gate area shared by the antifuse structures of the first, third, and fifth antifuse bits, and a second via area that overlaps with a second gate area shared by the transistor structures of the first, third, and fifth antifuse bits; the fourth layout cell has a third via area that overlaps with a third gate area shared by the transistor structures of the second, fourth, and sixth antifuse bits, and a fourth via area that overlaps with a fourth gate area shared by the antifuse structures of the second, fourth, and sixth antifuse bits;The third layout cell has fifth and sixth via areas which overlap with the first gate area; and the second layout cell has seventh and eighth via areas which overlap with the fourth gate area.

[0133] In some embodiments, the second via is arranged between the first and the third active area, or the third via is arranged between the second and the third active area.

[0134] In some embodiments, the arrangement of the first to fourth layout cells comprises attaching each of the layout cell arrangements of the plurality of identical layout cell arrangements to at least two additional layout cell arrangements of the plurality of identical layout cell arrangements, thereby forming an antifuse arrangement.

[0135] In some embodiments, the arrangement of the first to fourth layout cells comprises attaching a fifth and a sixth layout cell to the first and second layout cells, wherein the fifth layout cell has a ninth and a tenth via region that overlap with the first gate region, and the sixth layout cell has an eleventh and a twelfth via region that overlap with the fourth gate region. In some embodiments, the arrangement of the first to fourth layout cells further comprises attaching each of the layout cell arrangements of the plurality of identical layout cell arrangements to at least two additional layout cell arrangements of the plurality of identical layout cell arrangements, thereby forming an antifuse arrangement.

[0136] In various embodiments, the arrangement of the first to fourth layout cells comprises the arrangement of layout cells CA, CB1, CB2 and CC in accordance with one of the antifuse arrangements 300A - 300D, which are described above in relation to the Fig. 3A - 3D have been discussed.

[0137] In some embodiments, process 430 generates an IC layout diagram comprising the arrangement of the first to fourth layout cells. In some embodiments, generating the IC layout diagram includes generating the IC layout diagram comprising one or more of the antifuse layouts 100A - 100C, which are described above in relation to the Fig. 1A - 1C have been discussed, the antifuse layout 100, which is mentioned above in relation to the Fig. 1D - 1G has been discussed, or the antifuse arrangement 300A - 300D, which was discussed above in relation to the Fig. 3A - 3D has been discussed.

[0138] In process 440, the IC layout diagram is stored in a storage device in some embodiments. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in non-volatile, computer-readable memory or a cell library, e.g., a database, and / or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram over the network 714 of the EDA system 700, which is described below in relation to Fig. 7 is discussed.

[0139] In some embodiments, process 450 involves fabricating at least one or more semiconductor masks or at least one component in a layer of a semiconductor IC based on the IC layout diagram. The fabrication of one or more semiconductor masks or at least one component in a layer of a semiconductor IC is described below with reference to Fig. 8 discussed.

[0140] In some embodiments, process 460 involves performing one or more manufacturing operations based on the IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the IC layout diagram. The performance of one or more manufacturing operations, e.g., one or more lithographic exposures, based on the IC layout diagram, is described below in relation to Fig. 8 discussed.

[0141] By performing some or all of the operations of procedure 400, an IC layout diagram is generated in which gate areas, according to the read current paths, exhibit the properties - and thus the advantages - that have been discussed above with regard to the antifuse layouts 100A - 100C and 100.

[0142] The Fig. Figures 5A-5C are diagrams of IC component 500 in accordance with some embodiments. IC component 500 is formed by performing some or all of the operations of methods 200 and / or 400, and is based on the antifuse layouts 100A-100C and 100, which are described above in relation to the Fig. 1A - 1G have been discussed. In some embodiments, the IC component 500 is part of an IC component 860, which is manufactured by an IC manufacturer / fabrication company (“fab”) 850, as described below with reference to Fig. 8 is discussed.

[0143] Fig. Figure 5A shows a top view of IC component 500, simplified for clarity, showing the X and Y directions, which are shown above in relation to the Fig. 1A - 1D have been discussed, and the antifuse bits AB1 - AB8, which are mentioned above in relation to the Fig. 1D - 1G have been discussed. Fig. 5B depicts a cross-sectional view along a plane A-A', with the X-direction and a Z-direction perpendicular to the X- and Y-directions, and Fig. 5C displays a cross-sectional view along a plane BB' and the X and Z directions.

[0144] The IC component 500 features active areas AA1 - AA4, gate structures G2 - G5, contacts C1 - C4, conductive segments MBL1 - MBL4, M11 - M18 and M21 - M24 and vias V11 - V18 and V21 - V28, which are designed as discussed below.

[0145] Each of the active regions AA1 - AA4 is an active N or P region of the substrate 500S, which extends in the X direction and corresponds to an active region, for example an active region AR1 - AR3, which is described above in relation to the Fig. 1A - 1C have been discussed, and are designed.

[0146] Gate structures G2-G5 are gate structures that extend in the Y direction and correspond to the respective gate areas GR2-GR5, which are described above in relation to the Fig. 1A - 1D have been discussed, are designed, whereby they have gate conductors GC2 - GC5 over respective dielectric layers GD2 - GD5.

[0147] Contacts C1-C4 are conductive structures that are electrically connected to their respective active areas AA1-AA4, and which correspond to a contact area, for example contact area CR1, which is described above in relation to the Fig. 1A - 1C have been discussed and designed.

[0148] The conductive segments MBL1 - MBL4, which in some embodiments are also referred to as bit lines MBL1 - MBL4, are conductive segments extending in the X direction, which are electrically connected to respective contacts C1 - C4, and which are in accordance with a conductive area, for example the bit line BL1, which is described above in relation to the Fig. 1A - 1C have been discussed. In the embodiment which is described in Fig. As shown in Figure 5, the conductive segments MBL1–MBL4 are conductive segments of a first metal layer. In some embodiments, one or more of the conductive segments MBL1–MBL4 are conductive segments of a layer other than the first metal layer, for example, a second or a third metal layer.

[0149] The conductive segments M11 - M18 are conductive segments that extend in the X direction and are in accordance with a conductive area, for example a conductive area Z1 - Z4, which is described above in relation to the Fig. 1A - 1C has been discussed, or a conductive area AZ1 - AZ8, which is mentioned above in relation to Fig. 1D has been discussed, are designed. In the embodiment which is described in Fig. As shown in Figure 5, the conductive segments M11-M18 are conductive segments of a first metal layer. In some embodiments, one or more of the conductive segments M11-M18 are conductive segments of a layer other than the first metal layer, for example, a second or a third metal layer.

[0150] The conductive segments M21 - M24 are conductive segments, which in some embodiments are referred to as conductor tracks, extending in the Y direction and corresponding to a conductive area, for example a conductive area MR1 - MR4, which is described above in relation to Fig. 1D has been discussed, are designed. In the embodiment which is described in Fig. As shown in Figure 5, the conductive segments M21-M24 are conductive segments of a second metal layer. In some embodiments, one or more of the conductive segments M21-M24 are conductive segments of a layer other than the second metal layer, for example, a third or a fourth metal layer.

[0151] Each of the vias V11 - V18 is a conductive structure that is electrically connected to one of the gate conductors GC2 - GC5 and to the conductive segment M11 - M18 located above it, and is aligned with a via area, for example a via area VR1 - VR4, which is shown above in relation to the Fig. 1A - 1G has been discussed and designed.

[0152] Each of the vias V21 - V28 is a conductive structure which is electrically connected to the conductive segments M11 - M18 located below it and to the conductive segments M21 - M24 located above it, and is in accordance with a via area, for example one of the via areas AVR1 - AVRB, which are referred to above. Fig. 1D - 1G have been discussed and designed.

[0153] The illustrations of the IC component 500 in the Fig. Figures 5A-5C are simplified for illustrative purposes. In various embodiments, the IC component 500 has one or more additional elements, for example, source / drain regions within each of the active regions AA1-AA4, in addition to those discussed above.

[0154] Unless explicitly stated otherwise, the elements discussed above differ from those in the Fig. 5A - 5C show shapes, sizes, and spatial relationships depicted for illustrative purposes only. In various embodiments, the IC component 500 has elements that differ from those shown in the Fig. 5A - 5C exhibit the shapes, sizes and / or spatial relationships shown.

[0155] As in Fig. Figure 5B shows that the gate structure G2, which is arranged above the active area AA1, is a component of an antifuse structure ABP1 of the antifuse bit AB1; the gate structure G3, which is arranged above the active area AA1, is a component of a transistor ABR1 of the antifuse bit AB1; the gate structure G4, which is arranged above the active area AA1, is a component of a transistor ABR5 of the antifuse bit AB5; and the gate structure G5, which is arranged above the active area AA1, is a component of an antifuse structure ABP5 of the antifuse bit AB5.

[0156] Similarly, the gate structures G2 and G3, which are arranged above the active area AA2, are components of an antifuse structure or a transistor of the antifuse bit AB2; the gate structures G2 and G3, which are arranged above the active area AA3, are components of an antifuse structure or a transistor of the antifuse bit AB3; the gate structures G2 and G3, which are arranged above the active area AA4, are components of an antifuse structure or a transistor of the antifuse bit AB4; the gate structures G4 and G5, which are arranged above the active area AA2, are components of a transistor or an antifuse structure of the antifuse bit AB6; the gate structures G4 and G5, which are arranged above the active area AA3, are components of a transistor or an antifuse structure of the antifuse bit AB7;The gate structures G4 and G5, which are arranged above the active area AA4, are components of a transistor and an antifuse structure of the antifuse bit AB8, respectively. For the sake of clarity, the antifuse structures and transistors corresponding to the antifuse bits AB2-AB4 and AB6-AB8 are not shown or labeled in detail.

[0157] As in Fig. As shown in Figure 5B, contact C1 is electrically connected to the conductive segment MBL1 and to the active area AA1 between gate structures G3 and G4, thus forming part of a current path from the conductive segment MBL1 to both transistor ABR1 of antifuse bit AB1 and transistor ABR5 of antifuse bit AB5. The section of IC component 500, which is shown in Fig. The diagram shown in 5B corresponds to the schematic diagram of the one in Fig. 1E illustrated and discussed above, antifuse layouts 100.

[0158] As in Fig. As shown in Figure 5C, the via V12 is electrically connected to the gate conductor GC3 located below it and the conductive segment M12 located above it, and the via V22 is electrically connected to the conductive segment M12 located below it and the conductive segment M22 located above it. The via V16 is electrically connected to the gate conductor GC5 located below it and the conductive segment M16 located above it, and the via V26 is electrically connected to the conductive segment M16 located below it and the conductive segment M24 located above it. The conductive segments M12 and M16, which are aligned in the X direction, thus correspond to the respective conductive areas AZ2 and AZ4 of the antifuse layout 100, which is shown in Figure 5C. Fig. 1D is shown and discussed above.

[0159] Likewise, the conductive segment M11, which is electrically connected to the gate conductor GC2 via the via V11 and to the conductive segment M21 via the via V21, is aligned in the X direction to the conductive segment M15, is electrically connected to the gate conductor GC5 via the via V15 and to the conductive segment M24 via the via V25, together correspond to the respective conductive areas AZ1 and AZ5 of the antifuse layout 100;The conductive segment M13, which is electrically connected to the gate conductor GC2 via the via V13 and to the conductive segment M21 via the via V23, is aligned in the X direction to the conductive segment M17, is electrically connected to the gate conductor GC5 via the via V17 and to the conductive segment M24 via the via V27, together correspond to the respective conductive areas AZ3 and AZ7 of the antifuse layout 100; and the conductive segment M14, which is electrically connected to the gate conductor GC2 via the via V14 and to the conductive segment M21 via the via V24, is aligned in the X direction to the conductive segment M18, is electrically connected to the gate conductor GC4 via the via V18 and to the conductive segment M23 via the via V28, together correspond to the respective conductive areas AZ4 and AZ8 of the antifuse layout 100.;

[0160] Through the above discussed and in the Fig. The design shown in sections 5A - 5C corresponds to the IC component 500 as described above. Fig. 1D - 1G discussed antifuse layout 100, which arranged the layout cells CA, CB1, CB2 and CC in accordance with the above regarding Fig. The IC component 500 has the antifuse arrangement discussed in section 3A. It thus has a first antifuse structure, which includes a dielectric layer between a first gate conductor and a first active region, for example, the antifuse structure of antifuse bit AB3, including the dielectric layer GD2 between gate conductor GC2 and active region AA3; a second antifuse structure, which includes a dielectric layer between a second gate conductor and the first active region, for example, the antifuse structure of antifuse bit AB7, including the dielectric layer GD5 between gate conductor GC5 and active region AA3; a first transistor; a third gate conductor, for example, the transistor of antifuse bit AB3, including a gate conductor GC3 between the first and second gate conductors;comprising a second transistor; comprising a fourth gate conductor, for example the transistor of the antifuse bit AB7; comprising a gate conductor GC4 between the second and the third gate conductors; a first and a second via, for example the vias V13 and V14, which are electrically connected to the first gate conductor; a third via, for example the via V17, which is electrically connected to the second gate conductor;and a fourth via, for example via V18, which is electrically connected to the fourth gate conductor. The first and third vias are aligned with each other along the X-direction, the second and fourth vias are aligned with each other along the X-direction, and both the first and second, as well as the third and fourth vias, are located closer to the first active region than the second and third active regions, for example active regions AA2 and AA4, which are located adjacent to the first active region along the Y-direction.

[0161] In various embodiments, the IC component 500 corresponds to layout cells CA, CB1, CB2 and CC, which are arranged differently, for example in accordance with one or more of the antifuse arrangements 300B - 300D, which are described above in relation to the Fig. 3B - 3D are discussed, and thereby has the design discussed above, with each of the first to fourth vias being located closer to a first active area than a second and a third active area, which are located along the Y-direction adjacent to the first active area.

[0162] Because it is in accordance with the antifuse layouts 100A - 100C and 100 and / or the antifuse arrangements 300A - 300D, which are described above in relation to the Fig. 1A - 1D and 3A - 3D have been discussed, designed and by carrying out one or all of the operations of procedures 200 and 400, which above in relation to the Fig. 2 and Fig. As discussed in section 4, the IC component 500 enables the realization of the advantages discussed above with regard to the antifuse layouts 100A - 100C and 100.

[0163] Fig. Figure 6 is a flowchart of a method 600 for operating an antifuse bit in accordance with some embodiments. The operations of method 600 can be considered part of a method for operating one or more IC devices comprising one or more antifuse structures, for example, the IC device 500, which is described above in relation to the Fig. 5A - 5C will be discussed and implemented.

[0164] In some embodiments, the processes of method 600 are described in the Fig. The processes of method 600 are carried out in the sequence shown in Figure 6. In some embodiments, the processes of method 600 are carried out in a different order than that shown in Figure 6. Fig. The sequence shown in Figure 6 is carried out. In some embodiments, one or more operations are carried out before, between, during and / or after the execution of one or more operations of Method 600.

[0165] In process 610, a first voltage is applied to a programming line, which is electrically connected to a gate structure that is part of the antifuse structures of each of four adjacent antifuse bits. In various embodiments, applying the first voltage to the programming line includes applying a read voltage as part of a read operation or applying a programming voltage as part of a programming operation.

[0166] In some embodiments, applying the first electrical voltage to the programming line includes applying the signal WLP0 or WLP1, which is described above in relation to the antifuse layout 100 and the Fig. 1D - 1G has been discussed, to the respective conductor track M21 or M24, which is mentioned above in relation to the IC component 500 and the Fig. 5A - 5C has been discussed.

[0167] In process 620, a second voltage is applied to a bit line which is electrically connected to a first antifuse bit of the four adjacent antifuse bits, causing a bit cell current to flow through the antifuse structure of the first antifuse bit, wherein a current path of the bit cell current has four vias between the programming line and the gate structure, each of the four vias being adjacent to an antifuse bit of the four adjacent antifuse bits.

[0168] One dimension of the bit cell current is based on the voltage level of the first voltage, the voltage level of the second voltage, and the resistance of the current path between the programming line and the gate structure. In some embodiments, the current path between the programming line and the gate structure has vias V11, V13, V14, and a fourth via (not shown) adjacent to the antifuse bits AB1-AB4, or vias V15-V17 and a fourth via (not shown) adjacent to the antifuse bits AB5-AB5, which are described above with respect to IC component 500 and the Fig. 5A - 5C have been discussed.

[0169] In some embodiments, applying the second voltage includes applying a bit line voltage to one of the bit lines MBL1 - MBL4, which are referred to above in relation to the IC component 500 and the Fig. 5A - 5C have been discussed.

[0170] In some embodiments of process 630, the bit cell current is detected using a read amplifier. In some embodiments, detecting the bit cell current using the read amplifier includes determining a programmed state of the corresponding antifuse structure.

[0171] In some embodiments, process 640 involves repeating one or more of processes 610-630 for at least one second bit cell structure, thereby causing bit cell currents to flow into two or more bit cell structures. In various embodiments, repeating one or more of processes 610-630 includes causing a bit cell current to flow into a second of the four bit cell structures and / or causing a bit cell current to flow into a different bit cell structure.

[0172] By performing some or all of the operations of procedure 600, an antifuse bit operation is performed in which gate structure sections of read current paths exhibit the properties, and thus the advantages, that have been discussed above with regard to the antifuse layouts 100A - 100C and 100.

[0173] Fig. Figure 7 is a block diagram of an Electronic Design Automation (EDA) 700 system in accordance with some embodiments.

[0174] In some embodiments, the EDA system 700 incorporates an APR system. Methods described herein for designing layout diagrams that represent wire routing arrangements in accordance with one or more embodiments are, for example, feasible using the EDA system 700 in accordance with some embodiments.

[0175] In some embodiments, the EDA system 700 is a multi-purpose data processing device comprising a hardware processor 702 and a non-volatile, computer-readable storage medium 704. The storage medium 704 is, among other things, encoded with, that is, it stores, computer program code 706, i.e., a set of executable instructions. The execution of the instructions 706 by the hardware processor 702 constitutes (at least in part) an EDA tool, which performs a section or the complete method 200 described above in relation to Fig. 2 has been discussed, and / or the procedure 400, which is discussed above in relation to Fig. 4 has been discussed (hereinafter referred to as the listed processes and / or procedures) and implements.

[0176] The processor 702 is electrically coupled to the computer-readable storage medium 704 via a bus 708. The processor 702 is also electrically coupled to an I / O interface 710 via the bus 708. A network interface 712 is likewise electrically connected to the processor 702 via the bus 708. The network interface 712 is connected to a network 714, enabling the processor 702 and the computer-readable storage medium 704 to communicate with external elements via the network 714. The processor 702 is designed to execute computer program code 706, which is encoded in the computer-readable storage medium 704, to enable the system 700 to execute a portion or all of the listed processes and / or procedures.In one or more embodiments, the 702 processor is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0177] In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or a corresponding device or apparatus). For example, the computer-readable storage medium 704 comprises a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a magnetic hard disk, and / or an optical disk. In one or more embodiments that utilize optical disks, the computer-readable storage medium 704 comprises a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0178] In one or more embodiments, the storage medium 704 stores computer program code 706, which is configured to enable the system 700 (in which this embodiment represents (at least in part) the EDA tool) to be used to execute a section of the processes and / or procedures listed above. In one or more embodiments, the storage medium 704 also stores information that enables the execution of a section of the processes and / or procedures listed above. In one or more embodiments, the storage medium 704 stores the cell library 707, which comprises cells such as those disclosed herein, such as a layout cell CA1, CA2, CB1, CB2, CC1, or CC2, and / or an antifuse layout 100A-100C, which is described above in relation to the Fig. 1A - 1C has been discussed.

[0179] The EDA system 700 features the input / output (I / O) interface 710. The I / O interface 710 is connected to an external circuit. In one or more embodiments, the I / O interface 710 includes a keyboard, keypad, mouse, ball, touchscreen, and / or cursor keys for transmitting information and commands to the processor 702.

[0180] The EDA System 700 also includes the network interface 712, which is connected to the processor 702. The network interface 712 enables the System 700 to communicate with the network 714, to which one or more other computer systems are connected. The network interface 712 has wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a section or the complete processes and / or procedures listed are implemented in two or more Systems 700.

[0181] The System 700 is configured to receive information through the I / O interface 710. The information received through the I / O interface 710 includes one or more elements from the group comprising instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by the Processor 702. The information is transmitted to the Processor 702 via the bus 708. The EDA System 700 is also configured to receive information related to a UI (User Interface) through the I / O interface 710. This information is stored on the computer-readable medium 704 as the User Interface (UI) 742.

[0182] In some embodiments, a section of the listed processes and / or methods, or the complete processes and / or methods, are implemented as a standalone software application for execution by a processor. In some embodiments, a section of the listed processes and / or methods, or the complete processes and / or methods, are implemented as a software application that forms part of an additional software application. In some embodiments, a section of the listed processes and / or methods, or the complete processes and / or methods, are implemented as a plug-in module of a software application. In some embodiments, at least one of the listed processes and / or methods is implemented as a software application that forms part of an EDA tool.In some embodiments, a section or all of the listed processes and / or procedures are implemented as a software application used by the EDA System 700. In some embodiments, a layout diagram containing standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout creation tool.

[0183] In some embodiments, the processes are implemented as functions of a program stored on a non-volatile, computer-readable recording medium. Examples of a non-volatile, computer-readable recording medium include external / removable and / or internal / built-in storage devices or storage units, for example, one or more elements from the group comprising an optical disc, such as a DVD; a magnetic disk, such as a hard disk; a semiconductor memory, such as a ROM; a RAM; a memory card; and the like.

[0184] Fig. Figure 8 is a block diagram of an IC fabrication system 800 and an associated IC fabrication flow in accordance with some embodiments. In some embodiments based on a layout diagram, at least (A) one or more semiconductor masks or (B) at least one component in a layer of an integrated semiconductor circuit is fabricated using the fabrication system 800.

[0185] In Fig. Figure 8 comprises an IC manufacturing system 800 units, such as a design house 820, a mask house 830, and an IC manufacturer / fabrication (“fab”) 850, which cooperate with each other with respect to design, development, and manufacturing cycles and / or services related to the manufacture of an IC component 860. The units in the system 800 are interconnected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a multitude of different networks, such as an intranet and the Internet. The communication network has wired and / or wireless communication channels. Each unit interacts with one or more of the other units and provides or receives services from one or more of the other units.In some embodiments, two or more of the units Design House 820, Mask House 830, and IC Manufacturer 850 are owned by a single larger company. In some embodiments, two or more of the units Design House 820, Mask House 830, and IC Manufacturer 850 are located in a common facility and share resources.

[0186] The design house (or design team) 820 generates an IC design layout diagram 822. The IC design layout diagram 822 has various geometric structures, e.g., an IC layout diagram which is in the Fig. 1A - 1D or 3A - 3D is shown and for an IC component 860, for example the IC component 500, which is shown above in relation to the Fig. 5A - 5C has been discussed and designed. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC component 860 to be manufactured. The different layers connect to each other to form various IC features. For example, a section of the IC design layout diagram 822 includes various IC features, such as an active area, a gate electrode, source and drain, metal traces or vias of an interlayer connection, and openings for bond pads to be formed in a semiconductor substrate (such as a silicon wafer), as well as various metal layers arranged on the semiconductor substrate. Design House 820 implements an appropriate design procedure to form the IC design layout diagram 822.The design process includes one of the elements from the group encompassing a logical design, a physical design, or location and routing. The IC design layout diagram 822 is represented in one or more data files containing information about the geometric structures. For example, the IC design layout diagram 822 can be expressed in a GDSII file format or a DFII file format.

[0187] The mask house 830 comprises the data preparation 832 and the mask fabrication 844. The mask house 830 uses the IC design layout diagram 822 to produce one or more masks 845, which are to be used to fabricate the various layers of the IC component 860 according to the IC design layout diagram 822. The mask house 830 performs the mask data preparation 832, in which the IC design layout diagram 822 is translated into a representative data file (“RDF”). The mask data preparation 832 provides the RDF to the mask fabrication 844. The mask fabrication 844 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reed plate) 845 or a semiconductor wafer 853. The design layout diagram 822 is processed by the mask data preparation 832 to meet the specific characteristics of the mask writer and / or the requirements of the IC manufacturer 850. Fig. Figure 8 illustrates the mask data preparation 832 and the mask manufacturing 844 as separate elements. In some embodiments, the mask data preparation 832 and the mask manufacturing 844 can be referred to together as mask data preparation.

[0188] In some embodiments, the mask data preparation 832 includes near-field optical correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those caused by diffraction, interference, other process effects, and the like. The OPC adapts the IC design layout diagram 822. In some embodiments, the mask data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliaries, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, reverse lithography technology (ILT) is also used, which treats the OPC as a reverse image preparation problem.

[0189] In some embodiments, the mask data preparation 832 comprises a mask rule checker (MRC) which verifies the IC design layout diagram 822, which has undergone OPC processes, against a set of mask creation rules. These rules include certain geometric and / or connection constraints to ensure adequate margins, account for variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 822 to compensate for constraints during mask fabrication 844 that could undo some of the modifications performed by the OPC, in order to comply with the mask creation rules.

[0190] In some embodiments, the mask data preparation 832 includes a lithography process check (LPC) that simulates the processing performed by the IC manufacturer 850 to manufacture the IC component 860. The LPC simulates this processing based on the IC design layout diagram 822 to create a simulated manufactured device, such as the IC component 860. The process parameters of the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of field (DOF), mask defect improvement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, OPC and / or MRC are repeated after a simulated manufactured device has been created by the LPC if the simulated device does not sufficiently meet the design rules with respect to its shape to further refine the IC design layout diagram 822.

[0191] It is understood that the above description of the mask data preparation 832 has been simplified for the sake of clarity. In some embodiments, the data preparation 832 includes additional features, such as a logical operation (LOP) to modify the IC design layout diagram 822 according to the manufacturing rules. Furthermore, the processes performed on the IC design layout diagram 822 during the data preparation 832 can be carried out in a variety of different sequences.

[0192] Following mask data preparation 832 and during mask fabrication 844, a mask 845 or a group of masks 845 is produced based on the modified IC design layout diagram 822. In some embodiments, mask fabrication 844 includes performing one or more lithographic exposures based on the IC design layout diagram 822. In some embodiments, an electron beam (E-beam) or a mechanism consisting of multiple electron beams is used to form a structure on a mask (photomask or reticle) 845 based on the modified IC design layout diagram 822. The mask 845 can be formed using various technologies. In some embodiments, the mask 845 is formed using a binary technology. In some embodiments, a mask structure has opaque and transparent areas.A beam of radiation, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) with which a wafer has been coated, is blocked by the opaque area and penetrates the transparent areas. In one example, a binary mask version of the 845 mask has a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) with which the opaque areas of the binary mask are coated. In another example, the 845 mask is formed using a phase-shift technology. In a phase-shift mask (PSM) version of the 845 mask, various features in the structure formed on the phase-shift mask are configured to exhibit a suitable phase difference to improve resolution and image quality.In various examples, the phase-shift mask can be a damped PSM or an alternating PSM. The mask(s) produced by mask fabrication 844 are used in a variety of processes. For example, such a mask is / are used in an ion implantation process to form different doped regions in the semiconductor wafer 853, in an etching process to form different etched regions in the semiconductor wafer 853, and / or in other suitable processes.

[0193] IC Manufacturer 850 is an IC manufacturing company that has one or more manufacturing facilities for producing a variety of different IC products. In some embodiments, IC Manufacturer 850 is a semiconductor manufacturer. For example, there may be one manufacturing facility for the front-end manufacturing of a variety of IC products (front-end-of-line manufacturing (FEOL manufacturing)), while a second manufacturing facility may provide the back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line manufacturing (BEOL manufacturing)), and a third manufacturing facility may provide other services to the manufacturing company.

[0194] The IC manufacturer 850 comprises wafer manufacturing tools 852, which are configured to perform various manufacturing operations on the semiconductor wafer 853 such that the IC component 860 is manufactured in accordance with the mask(s), for example, the mask 845. In various embodiments, the manufacturing tools 852 comprise one or more of the tools from the group comprising a wafer stepper, an ion implantation device, a photoresist coating device, a process chamber, for example, a CVD chamber or an LPCVD oven, a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0195] IC manufacturer 850 uses a mask 845, produced by mask house 830, to manufacture IC component 860. Thus, IC manufacturer 850 uses, at least indirectly, IC design layout diagram 822 to manufacture IC component 860. In some embodiments, IC manufacturer 850 produces semiconductor wafer 853 using mask 845 to form IC component 860. In some embodiments, IC manufacturing includes performing one or more lithographic exposures, at least indirectly based on IC design layout diagram 822. Semiconductor wafer 853 has a silicon substrate or other suitable substrate having material layers formed on it. The semiconductor wafer 853 further exhibits one or more different doped regions, dielectric features, multi-level interconnects and the like (which are formed in successive manufacturing steps).

[0196] Details relating to an integrated circuit manufacturing system (IC manufacturing system) (e.g., the System 800 from Fig. 8) and an IC manufacturing flow related thereto can be found, for example, in US 9 256 709 B2, issued on February 9, 2016, US Pre-grant Publication US 2015 / 0 278 429 A1, issued on October 1, 2015, US Pre-grant Publication US 2014 / 0 040 838 A1, issued on February 6, 2014, and US 7 260 442 B2, issued on August 21, 2007.

[0197] The invention is defined by the main claim and the dependent claims. The subclaims describe further embodiments of the invention.

Claims

[1] Method (200) for generating an IC layout diagram, the method comprising: Arranging (210) a first active area (AR2) between and adjacent to a second and a third active area (AR1, AR3) in the IC layout diagram, wherein the first, second and third active areas each extend in a first direction (X); Crossing (220) of the first active region (AR2) with the first to fourth adjacent gate regions (GR2, ..., GR5), thereby defining the respective positions of a gate of an antifuse structure (B2P) of a first antifuse bit (B2), a gate of a transistor (B2R) of the first antifuse bit (B2), a gate of a transistor (B5R) of a second antifuse bit (B5) and a gate of an antifuse structure (B5P) of the second antifuse bit (B5); Align (230) separate first and second conductive areas (Z1, Z3) along the first direction (X) and between the first and second active area (AR2, AR1), thereby intersecting the first conductive area (Z1) with the first gate area (GR2) and the second conductive area (Z3) with the fourth gate area (GR5); Align (240) separate third and fourth conductive areas (Z2, Z4) along the first direction (X) and between the first and third active areas (AR2, AR3), thereby either intersecting the third conductive area (Z2) with the first gate area (GR2) and the fourth conductive area (Z4) with the third gate area (GR4), or intersecting the third conductive area (Z2) with the second gate area (GR3) and the fourth conductive area (Z4) with the fourth gate area (GR5), Arranging a first via area (VR1) at the intersection of the first conductive area (Z1) and the first gate area (GR2); Arranging a second via area (VR3) at the intersection of the second conductive area (Z3) and the fourth gate area (GR5); and if aligning the separated third and fourth conductive areas (Z2, Z4) involves crossing the third conductive area (Z2) with the first gate area (GR2) and the fourth conductive area (Z4) with the third gate area (GR4): placing a third via area (VR2) at the intersection of the third conductive area (Z2) and the first gate area (GR2), and placing a fourth via area (VR4) at the intersection of the fourth conductive area (Z4) and the third gate area (GR4); or where aligning the separated third and fourth conductive areas (Z2, Z4) includes crossing the third conductive area (Z2) with the second gate area (GR3) and the fourth conductive area (Z4) with the fourth gate area (GR5): arranging a third via area (VR2) at the intersection of the third conductive area (Z2) and the second gate area (GR3), and arranging a fourth via area (VR4) at the intersection of the fourth conductive area (Z4) and the fourth gate area (GR5); wherein at least one of the operations is arranging (210) the first active area (AR2), crossing (220) the first active area (AR2) with the first to fourth adjacent gate areas (GR2, ..., GR5), alignment (230) of the separated first and second conductive areas (Z1, Z3) or alignment (240) of the separated third and fourth conductive areas (Z2, Z4) is performed by a processor of a computer. [2] Method (200) according to claim 1, wherein the alignment (240) of the separated third and fourth conductive areas (Z2, Z4) along the first direction (X) comprises separating the third from the fourth conductive area by a first distance (D2) which corresponds to a minimum distance rule of an extreme ultraviolet manufacturing process. [3] Method (200) according to claim 2, wherein the alignment (230) of the separated first and second conductive areas (Z1, Z3) along the first direction (X) comprises separating the first from the second conductive area by a second distance (D1) which is larger than the first distance (D2). [4] Method (200) according to one of the preceding claims, further comprising aligning separate fifth and sixth conductive areas along the first direction (X), wherein the third active area (AR3) is located between the third and fourth conductive areas (Z2, Z4) and the fifth and sixth conductive areas, and The alignment of the fifth and sixth conductive areas includes crossing the fifth conductive area with the first gate area (GR2) and the sixth conductive area with the fourth gate area (GR5). [5] Method (200) according to any one of claims 1 to 3, further comprising aligning separate fifth and sixth conductive areas along the first direction (X), wherein the second active area (AR1) is located between the first and second conductive areas (Z1, Z3) and the fifth and sixth conductive areas, If the alignment of the separated third and fourth conductive areas (Z2, Z4) involves the crossing of the third conductive area (Z2) with the first gate area (GR2) and of the fourth conductive area (Z4) with the third gate area (GR4), then the alignment of the separated fifth and sixth conductive areas involves the crossing of the fifth conductive area with the second gate area (GR3) and of the sixth conductive area with the fourth gate area (GR5), and If the alignment of the separated third and fourth conductive areas (Z2, Z4) includes crossing the third conductive area (Z2) with the second gate area (GR3) and the fourth conductive area (Z4) with the fourth gate area (GR5), then the alignment of the separated fifth and sixth conductive areas includes crossing the fifth conductive area with the first gate area (GR2) and the sixth conductive area with the third gate area (GR4). [6] Method (200) according to claim 5, wherein both the alignment of the separated third and fourth conductive areas (Z2, Z4) along the first direction (X) and the alignment of the separated fifth and sixth conductive areas along the first direction (X) comprise separating the respective third and fourth or fifth and sixth conductive areas by a distance (D2) which corresponds to a minimum distance rule. [7] Method (200) according to one of the preceding claims, wherein the arrangement of the first via area (VR1) up to the arrangement of the fourth via area (VR4) each comprises the arrangement of a slot via area. [8] Method (200) according to any one of claims 1 to 6, wherein the arrangement of the first via-hole region (VR1) up to the arrangement of the fourth via-hole region (VR4) each comprises the arrangement of a square via-hole region. [9] IC device (500), comprising: comprising a first antifuse structure (AB3) comprising a first dielectric layer (GD2) between a first gate conductor (GC2) extending in a first direction (Y) and a first active region (AA3) extending in a second direction (X) perpendicular to the first direction; comprising a second antifuse structure (AB7) comprising a second dielectric layer (GD5) between a second gate conductor (GC5) extending in the first direction (Y) and the first active region (AA3); comprising a first transistor (AB3) and a third gate conductor (GC3) extending in the first direction (Y) between the first and second gate conductors (GC2, GC5); having a second transistor (AB7) and a fourth gate conductor (GC4) extending in the first direction (Y) between the second and third gate conductors (GC5, GC3); a first and a second via (V13, V14) which are electrically connected to the first gate conductor (GC2); a third via (V17) which is electrically connected to the second gate conductor (GC5); and a fourth via (V18) which is electrically connected to the fourth gate conductor (GC4), where the first and third vias (V13, V17) are aligned with each other along the second direction (X) and are located between the first active region (AA3) and a second active region (AA2), with the first active region (AA3) and the second active region (AA2) being adjacent along the first direction (Y); and the second and fourth vias (V14, V18) are aligned with each other along the second direction (X) and are located between the first active region (AA3) and a third active region (AA4), with the first active region (AA3) and the third active region (AA4) being adjacent along the first direction (Y). [10] IC device (500) according to claim 9, further comprising a fifth and a sixth via (V16, V12) which are aligned with each other along the second direction (X), wherein the second active area (AA2) is located between the fifth and sixth vias (V16, V12) and the first and third vias (V13, V17), the fifth via (V16) is electrically connected to the second gate conductor (GC5), and the sixth via (V12) is electrically connected to the third gate conductor (GC3). [11] IC device (500) according to claim 9, further comprising a fifth and a sixth via which are aligned with each other along the second direction (X), wherein the third active area (AA4) is located between the fifth and sixth vias and the second and fourth vias (V14, V18), the fifth via is electrically connected to the first gate conductor (GC2), and the sixth via is electrically connected to the second gate conductor (GC5). [12] IC device (500) according to claim 11, further comprising: a first conductor track (M21) which extends in the first direction (Y) and is electrically connected to the first, second and fifth vias, a second conductor track (M24), which extends in the first direction (Y) and is electrically connected to the third and sixth vias, and a third conductor track (M23) which extends in the first direction (Y) and is electrically connected to the fourth via (V18). [13] IC device (500) according to claim 9, further comprising a fifth and a sixth via which are aligned with each other along the second direction (X), wherein the second active area (AA2) is located between the fifth and sixth vias and the first and third vias (V13, V17), the fifth via is electrically connected to the first gate conductor (GC2), and the sixth via is electrically connected to the second gate conductor (GC5). [14] IC device (500) according to claim 13, further comprising: a seventh and an eighth via, which are aligned with each other along the second direction (X); and a fourth active area adjacent to the second active area (AA2), where the fourth active area is located between the seventh and eighth vias and the fifth and sixth vias, the seventh via is electrically connected to the first gate conductor (GC2), and the eighth via is electrically connected to the second gate conductor (GC5). [15] IC device (500) according to claim 14, further comprising: a first conductor track (M21) which extends in the first direction (Y) and is electrically connected to the first, second, fifth and seventh vias, a second conductor track (M24), which extends in the first direction (Y) and is electrically connected to the third, sixth and eighth vias, and a third conductor track (M23) which extends in the first direction (Y) and is electrically connected to the fourth via (V18). [16] System (700) comprising electronic design automation: a processor (702); and a non-volatile, computer-readable storage medium (704) which contains computer program code (706) for one or more programs, wherein the non-volatile, computer-readable storage medium and the computer program code are configured, together with the processor (702), to cause the system (700): first to fourth layout cells by placing the first and second layout cells (CA1, CB1) at the third and fourth layout cells (CB2, CC1) (420), wherein the first layout cell (CA1), which is adjacent to the second layout cell (CB1), together defines a first active area (AA1), which corresponds to a first and a second antifuse bit (AB1, AB5), the third layout cell (CB2), which is adjacent to the fourth layout cell (CC1), together defines a second active area (AA3), which corresponds to a third and a fourth antifuse bit (AB3, AB7), the first to fourth layout cells together define a third active area (AA2), which corresponds to a fifth and a sixth antifuse bit (AB2, AB6) adjacent to the first and second antifuse bits (AB1, AB5) and the third and fourth antifuse bits (AB3, AB7), the first layout cell (CA1) has a first via area (V11) which overlaps with a first gate area (GR2) which is shared by the antifuse structures of the first, third and fifth antifuse bits (AB1, AB3, AB2), and a second via area (V12) which overlaps with a second gate area (GR3) which is shared by transistor structures of the first, third and fifth antifuse bits, the fourth layout cell (CC1) has a third via area (V18) which overlaps with a third gate area (GR4) which is shared by transistor structures of the second, fourth and sixth antifuse bits (AB5, AB7, AB6), and a fourth via area (V17) which overlaps with a fourth gate area (GR5) which is shared by antifuse structures of the second, fourth and sixth antifuse bits, the third layout cell (CB2) has a fifth and a sixth via area (V13, V14) which overlap with the first gate area (GR2), and the second layout cell (CB1) has a seventh and an eighth via area (V15, V16) which overlap with the fourth gate area (GR5); and an integrated circuit layout diagram (IC layout diagram) showing the arrangement of the first to fourth layout cells (430). [17] System (700) according to claim 16, wherein The arrangement of the first to fourth layout cells is a first layout cell arrangement of a plurality of identical layout cell arrangements, and the non-volatile, computer-readable storage medium (704) and the computer program code (706) are configured, together with the processor (702), to cause the system (700) to connect each of the layout cell arrangements of the plurality of identical layout cell arrangements to at least two additional layout cell arrangements of the plurality of identical layout cell arrangements, thereby forming an antifuse arrangement (300A). [18] System (700) according to claim 16, wherein the non-volatile, computer-readable storage medium (704) and the computer program code (706) are configured, together with the processor (702), to cause the system (700) to add a fifth and a sixth layout cell (CB2, CB1) to the first and second layout cells (CA1, CB1), wherein the fifth layout cell (CB2) has a ninth and a tenth via area which overlap with the first gate area (GR2), and the sixth layout cell (CB1) has an eleventh and a twelfth via area which overlap with the fourth gate area (GR5). [19] System (700) according to claim 18, wherein The arrangement of the first to sixth layout cells is a first layout cell arrangement of a plurality of identical layout cell arrangements, and the non-volatile, computer-readable storage medium (704) and the computer program code (706) are configured, together with the processor (702), to cause the system (700) to connect each of the layout cell arrangements of the plurality of identical layout cell arrangements to at least two additional layout cell arrangements of the plurality of identical layout cell arrangements, thereby forming an antifuse arrangement (300C). [20] System (700) according to any one of claims 16 to 19, wherein the second via area (V12) is located between the first and third active areas (AA1, AA2), and / or the third via area (V18) is located between the second and the third active area (AA3, AA2).

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