Semiconductor device and its manufacturing process

Abstract

Semiconductor device (240, 440) comprising: a first dielectric layer (212, 412) arranged over a substrate (200, 400) and a conductive feature (202, 402); a second dielectric layer (214, 414) arranged over the first dielectric layer (212); a doped dielectric layer (224, 424) arranged over the first dielectric layer (212, 412) and in the second dielectric layer (214); a first metal section (220-1, 420-1) arranged in the first dielectric layer (212, 412) and in contact with the conductive feature (202, 402);and a doped metal section (222, 422) arranged above the first metal section (220-1, 420-1), wherein the doped dielectric layer (224) and the doped metal section (222) are aligned, wherein the doped metal section (222) is separated from an upper surface of the first metal section (220) and the doped dielectric layer (224) is separated from the upper surface (210t) of the second dielectric layer (214); wherein the first metal section (220-1, 420-1) and the doped metal section (222, 422) contain the same noble metal material, wherein the doped dielectric layer (224, 424) and the doped metal section (222, 422) contain the same dopants, wherein the dopants are bonded to the noble metal material in the doped metal section (222, 422).

Description

The invention relates to a semiconductor device and manufacturing method. A semiconductor device is known from US 2019 / 0 305 107 A1. A further semiconductor device and a production method are known from DE 10 2019 112 264 A1.BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have led to continuous improvements over generations of ICs. Circuits have become smaller and more complex from generation to generation. However, these advances have also increased the complexity of processing and manufacturing ICs.Generally, as IC evolution proceeds, the functional density (i.e., the number of interconnected devices per chip area) has increased, while the geometric size (i.e., the smallest device (or line) that can be fabricated by a fabrication process) has decreased. This downsizing process generally offers advantages because production efficiency is increased and the costs associated therewith are decreased.However, as feature sizes become smaller and smaller, execution of manufacturing processes becomes more and more difficult. Therefore, there is a challenge to form reliable semiconductor devices with smaller and smaller sizes.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 is a fragmentary cross-sectional view of a semiconductor structure. FIG. 2 is a flow diagram of a method of manufacturing a semiconductor device according to various aspects of the present disclosure. FIGS. 3A to 3F are schematic views of various stages in a method of manufacturing a semiconductor device according to aspects of one or more embodiments of the present disclosure. FIGS. 4A to 4E are schematic views of various stages in a method of manufacturing a semiconductor device according to aspects of one or more embodiments of the present disclosure. FIG. 5 is an illustration of a semiconductor device in accordance with aspects of one or more embodiments of the present disclosure. FIGS. 6A to 6D are schematic drawings of various stages in a method of manufacturing a semiconductor device according to aspects of one or more embodiments of the present disclosure. FIG. 7 is a schematic drawing of a semiconductor device according to various aspects of the present disclosure. FIG. 8 is a flow diagram of a method of manufacturing a semiconductor device according to various aspects of the present disclosure. FIGS. 9A to 9F are schematic drawings of various stages in a method of manufacturing a semiconductor device according to aspects of one or more embodiments of the present disclosure. FIGS. 10A to 10C are schematic drawings of various stages in a method of manufacturing a semiconductor device according to aspects of one or more embodiments of the present disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments and examples for implementing different features of the provided subject matter. In order to simplify the present disclosure, specific examples of elements and arrangements will be described below. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated in the various examples of the present disclosure. This repetition is for convenience and clarity and does not fundamentally dictate a relationship between the various embodiments and / or configurations discussed.Further, for convenience of description herein, spatially relative terms such as "below," "below," "below," over," "on," "above," "below," and the like may be used to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative terms used herein may also be interpreted accordingly.As used herein, the terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or portion from another. As used herein, the terms "first," "second," and "third" do not imply an order or order unless clearly understood from the context.The process flow in IC fabrication can typically be divided into three categories: front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL). The FEOL generally includes processes related to the fabrication of IC devices such as transistors. FEOL processes may include, for example, forming isolation structures for isolating IC devices, gate structures, and source and drain structures (also referred to as source / drain structures) that form a transistor. MEOL processes generally include processes related to the fabrication of interconnect structures (also referred to as contacts or plugs) that are connected to conductive features (or conductive regions) of the IC devices. MEOL processes may include, for example, forming interconnect structures connected to the gate structures and interconnect structures connected to the source / drain structures. The BEOL generally includes processes related to the fabrication of multilayer interconnect (MLI) structures that electrically connect the IC devices and the interconnect structures fabricated by the FEOL and the MEOL. Thus, the operation of the IC devices can be enabled. As mentioned above, the scale down processes have led to an increase in the complexity of processing and manufacturing ICs. In some comparable approaches, for example, ruthenium (Ru) having a lower resistivity is used to form the interconnect structures formed by MEOL to reduce contact resistance of the plugs.Embodiments as discussed herein provide a semiconductor device having an interconnect structure and a method of manufacturing a semiconductor device to alleviate a low metal loss problem that may occur through metal diffusion from a lower metal layer during an anneal process. In some embodiments, after depositing the metal layer, an implantation is performed to form a barrier layer within the conductive material. In some embodiments, ions implanted into the conductive material are combined with the conductive material to form the diffusion barrier layer, such that metal diffusion may be obstructed or reduced by the diffusion barrier layer. Thus, the problem of lower metal loss caused by metal diffusion can be alleviated or reduced.FIG. 1 is a fragmentary cross-sectional view of a semiconductor structure 100, in part or as a whole, in accordance with various aspects of some embodiments of the present disclosure. The semiconductor structure 100 may be included in a microprocessor, memory, and / or other IC device. In some embodiments, the semiconductor structure 100 is a portion of an IC chip, a SoC (Systemon chip), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor transistors (CMOS), bipolar junction transistors (BJTs), lateral diffused MOS transistors (LDMOS), high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The transistors may be planar transistors or multi-gate transistors such as fin-type FETs (FinFETs). FIG. 1 has been simplified for clarity to better illustrate the inventive concepts of the present disclosure. Additional features may be added to the semiconductor structure 100, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor structure 100.In some embodiments, the semiconductor structure 100 includes a substrate (wafer) 102. In some embodiments, the substrate 102 includes silicon. Alternatively or additionally, the substrate 102 includes another elemental semiconductor such as germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, the substrate 102 includes one or more Group III-V materials, one or more Group II-IV materials, or combinations thereof. In some implementations, the substrate 102 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates may be fabricated by oxygen implantation (SIMOX) separation, wafer bonding, and / or other suitable methods. The substrate 102 may include various doped regions (not shown) configured according to device design requirements, such as p-doped regions, n-doped regions, or combinations thereof. P-doped regions (e.g., p-wells) include p-dopants such as boron, indium, another p-dopant, or combinations thereof. N-doped regions (e.g., n-wells) include n-dopants such as phosphorus, arsenic, another n-dopant, or combinations thereof. In some implementations, the substrate 102 includes doped regions formed with a combination of p-type dopants and n-type dopants. The differently doped regions may be formed directly on and / or in the substrate 102, for example, thereby providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and / or another suitable doping process may be performed to form the various doped regions.Isolations (not shown) may be formed over and / or in the substrate 102 to electrically isolate different regions, such as different device regions, of the semiconductor structure 100 from each other. For example, the isolations may define active device regions and / or passive device regions and electrically isolate them from each other. The isolations may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material, or combinations thereof. The isolation features may include various structures, for example shallow trench isolation (STI) structures, deep trench isolation (DTI) structures and / or local oxidation of silicon (LOCOS) structures.Various gate structures, such as gate structures 110, 112, and 114, may be disposed over the substrate 102. In some embodiments, one or more gate structures 110, 112, and 114 may include a source region and a drain region, wherein a channel region is defined between the source region and the drain region. In some embodiments, gate structures 110, 112, and 114 are formed over a fin structure. In some embodiments, the gate structures 110, 112, and 114 include a metal gate structure. In some embodiments, the metal gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer may be disposed over the substrate 102 and the gate electrode is disposed on the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, high-k dielectric, another suitable dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials having a high dielectric constant, for example a dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, another suitable constituent, or combinations thereof. In some embodiments, the gate dielectric layer includes a multilayer structure, such as an interfacial layer (IL) including, for example, silicon oxide, and a high-k dielectric layer including, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfNbO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, another suitable high-k dielectric material, or combinations thereof.The gate electrode contains an electrically conductive material. In some implementations, the gate electrode includes multiple layers, for example, one or more work function metal layers and gap-filling metal layers. The work function metal layer includes a conductive material, such as n-type work function materials and / or p-type work function materials, configured to have a desired work function (e.g., an n-type work function or a p-type work function). P-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, another p-type work function material, or combinations thereof. N-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, another n-type work function material, or combinations thereof. The gap-filling metal layer may contain a suitable conductive material such as Al, W and / or Cu.The gate structures 110, 112, and 114 may further include spacers 116 disposed adjacent to the gate structures 110, 112, and 114 (e.g., along the sidewalls). The spacers 116 may be formed by any suitable method and include a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some embodiments, the spacers 116 may have a multilayer structure, for example, a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one group of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent gate structures 110, 112, and 114.Implantation, diffusion, and / or anneal processes may be performed to form lightly doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features in the substrate 102 before and / or after the formation of the spacers 116.In some embodiments, the source / drain regions S / D of the device may include epitaxial structures 118. For example, a semiconductor material is epitaxially grown on the substrate 102, thereby forming epitaxial source / drain structures 118 over a source region and a drain region of the substrate 102. Thus, the gate structure 110, the epitaxial source / drain structure 118, and a channel region defined between the epitaxial source / drain structures 118 form a device such as a transistor. In some embodiments, the epitaxial source / drain structures 180 may surround source / drain regions of a fin structure. In some embodiments, the epitaxial source / drain structures 180 may replace portions of the fin structure. The epitaxial source / drain structures 180 are doped with n-type dopants and / or p-type dopants. In some embodiments where the transistor is configured as an n-type device (e.g., having an n-channel), the epitaxial source / drain structure 180 may include silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers doped with phosphorus, another n-type dopant, or combinations thereof (e.g., forming Si:P epitaxial layers or Si:C:P epitaxial layers). In alternative embodiments where the transistor is configured as a p-type device (e.g., having a p-channel), the epitaxial source / drain structures 180 may include silicon- and germanium-containing epitaxial layers doped with boron, another p-type dopant, or combinations thereof (e.g., forming Si:Ge:B epitaxial layers). In some embodiments, the epitaxial source / drain structures 180 include materials and / or dopants that generate a desired tensile stress and / or compressive stress in the channel region.As shown in FIG. 1, a plurality of dielectric layers 120, 122, and 124 may be disposed over the substrate 102. The dielectric layers 120, 122, and 124 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon doped silicon oxide, Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLKTM(Dow Chemical, Midland, Mich.), polyimide, another low-k dielectric material, or combinations thereof. As shown in FIG. 1, the dielectric layer 120 may cover the source / drain region S / D, the spacers 116, and the gate structures 110, 112, and 114. In some embodiments, the dielectric layer 120 may be referred to as an interlayer dielectric layer (ILD) layer. In some embodiments, dielectric layers 122 and 124 may be referred to as an ILD layer or an inter-metal dielectric layer (IMD) layer.In some embodiments, one or more interconnect structures 130, 132 may be formed over the source / drain region S / D and the gate structure 110, as shown in FIG. 1. The interconnect structure 130 is disposed on the gate structure 110 such that the gate structure 130 may be connected to a back-end-of-line (BEOL) connection (not shown) via the interconnect structure 130. The interconnect structure 132 may be referred to as an MD (metal-to-device) contact or an MD (metal-to-drain) contact, which generally refer to contact to the source / drain regions S / D. As shown in FIG. 1, the interconnect structures 132 may be disposed on the epitaxial source / drain structures 118 such that the epitaxial source / drain structures 118 may be connected to the BEOL interconnect via the interconnect structures 132. Thus, the FEOL structures may be electrically connected to the BEOL connection via the interconnect structures 130, 132, which may also be referred to as MEOL interconnect structures.As shown in FIG. 1, interconnect structures 140, 142 may be formed on the interconnect structures 130, 132 and conductive features 150 may be formed on the interconnect structures 140, 142. The interconnect structures 140, 142 electrically connect the interconnect structure 130, 132 to the conductive features 150. In some embodiments, the interconnect structures 140, 142 are referred to as vias (V) and the conductive features 150 are referred to as metal lines (M) in the BEOL interconnect. In some embodiments, the BEOL connection includes a dielectric layer stack 122, and vias and metal lines are formed in the dielectric layer stack.FIG. 2 is a flow diagram illustrating a method of manufacturing a semiconductor device 10 in accordance with aspects of the present disclosure. In some embodiments, the method of manufacturing the semiconductor device 10 includes a number of operations (11, 12, 13, and 14). The methods of manufacturing the semiconductor device 10 are further described according to one or more embodiments. It should be appreciated that the operations of the method of manufacturing the semiconductor device 10 may be rearranged or otherwise modified within the scope of the various aspects. It is further noted that additional operations may be provided before, during, and after method 10, and that some other operations may be outlined only briefly herein. In some embodiments, the method of manufacturing the semiconductor device 10 may be used to form the interconnect structure 130, 132 in the MEOL structure. In other embodiments, the method of manufacturing the semiconductor device 10 may be used to form the interconnect structure 140, 142 in the BEOL interconnect.FIGS. 3A to 3F are schematic drawings showing various stages of the method of manufacturing the semiconductor device 10 according to aspects of one or more embodiments of the present disclosure. In some embodiments, a substrate 200 may be obtained. The substrate 200 may be the substrate 102 shown in FIG. 1, but the disclosure is not limited thereto. In some embodiments, the substrate 200 may include a semiconductor device, for example, the transistor as illustrated in FIG. 1, but the disclosure is not limited thereto. As shown in FIG. 3A, the substrate 200 may include a conductive feature 202 disposed therein. In some embodiments, the conductive feature 202 may be an FEOL feature similar to the metal gate 110 or the source / drain region S / D as shown in FIG. 1. In some embodiments, the conductive feature 202 may be a MEOL feature, such as a device level cobalt-containing contact, similar to the interconnect structure 130, 132 as shown in FIG. 1. Additionally, the substrate 200 may include one or more dielectric layers. In some embodiments, the conductive feature 202 may be, for example, a BEOL feature, such as a cobalt-containing line of a metal line feature (M) 150 as shown in FIG. 1.At operation 11, a dielectric structure 210 is formed over the substrate 200 and the conductive feature 202. In some embodiments, the dielectric structure 210 may include a single layer. In some embodiments, the dielectric structure may comprise a multilayer structure. For example, as shown in FIG. 3A, the dielectric structure 210 may include at least a first dielectric layer 212 and a second dielectric layer 214 that are sequentially stacked over the substrate 200 and the conductive feature 202. The first dielectric layer 212 and the second dielectric layer 214 may include different dielectric materials. For example, the first dielectric layer 212 may be a contact etch stop (CESL) layer, and the second dielectric layer may be an ILD layer or an IMD layer. In some embodiments, the CESL may include silicon nitride, silicon oxynitride, and the like. The ILD layer or the IMD layer may include materials as mentioned above.Referring further to FIG. 3A, at operation 11, an opening 215 may be formed in the dielectric structure 210. In some embodiments, the opening 215 penetrates the dielectric structure 210 from a top surface 210 tto a bottom of the dielectric structure 210. Thus, a portion of the conductive feature 202 is exposed through the opening 215. The opening 215 may be formed by a lithographic method using masking technologies and an anisotropic etching method (e.g., plasma etching or reactive ion etching), but the disclosure is not limited thereto.Referring to FIG. 3B, at operation 12, a metal layer 220, such as a noble metal layer, may be formed to fill the opening 215, but the disclosure is not limited thereto. The noble metal layer may contain rhenium (Re), rhodium (Rh) and ruthenium (Ru). The metal layer 220 extends from the top surface 210 tof the dielectric structure 210 to the bottom of the dielectric structure 210. The metal layer 220 penetrates the second dielectric layer 214 and the first dielectric layer 212 to contact the exposed portion of the conductive feature 202. Further, the metal layer 220 covers the top surface 210 tof the dielectric structure 210. In some embodiments, the thickness of the metal layer 220 covering the top surface 210 tof the dielectric structure 210 may be about 1 nanometer to about 50 nanometers, but the disclosure is not limited thereto.It should be appreciated that in some embodiments, the metal layer 220 may be formed without a liner, barrier, seed layer, or other intervening layer. Therefore, in such embodiments, the metal layer 220 may be in contact with the dielectric structure 210, but the disclosure is not limited thereto.Referring to FIG. 3C, in operation 13, a doped metal portion 222 is formed in the metal layer 220. In some embodiments, the doped metal portion 222 includes phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In), but the disclosure is not limited thereto. The formation of the doped metal portion 222 includes ion implantation. In some embodiments, a dose of ion implantation may be about 1E13 cm -2 to about 1E16 cm -2 an angle of ion implantation may be about 0 degrees to about 60 degrees, and a temperature of ion implantation may be about -100° C. to about 500° C. Note that a depth or a location at which the doped metal portion 222 is formed may be determined by an implantation energy of the ion implantation. For example, when the implantation energy of the ion implantation is about 500 eV to about 50 keV, the doped metal portion 222 may be formed in an upper portion of the metal layer 220. In some embodiments, as shown in FIG. 3C, the doped metal portion 222 is formed to cover the top surface 210 tof the dielectric structure 210. A distribution of dopants in the doped metal portion 222 is depicted as curve A in FIG. 3C. In some embodiments, a peak of the distribution curve may be near the center of the doped metal portion 222 overlying the second dielectric layer 214, but the disclosure is not limited thereto. In some embodiments, the thickness of the doped metal portion 222 may be about 1 nanometer to about 50 nanometers, but the disclosure is not limited thereto.Referring to FIG. 3D, in some embodiments, an anneal is performed to improve gap fill results, reduce plug resistance, and attach an interface between the dielectric structure 210 and the metal layer 220. In some embodiments, the temperature for the annealing may be about 100° C. to about 500° C., but the disclosure is not limited thereto. The pressure for the anneal may be about 13.3 Pa (about 100 mTorr) to about 101.3 Pa (about 760 mTorr), but the disclosure is not limited thereto. The duration of the anneal may be from about 10 minutes to about 120 minutes, but the disclosure is not limited thereto. Further, a gas such as nitrogen (N2), hydrogen (H2), helium (He), and / or argon (Ar) may be used for the annealing. During the anneal, metal diffusion may occur and metal ions may move from the conductive feature 202 to an upper portion of the metal layer 220, along the interface between the dielectric structure 210 and the metal layer 220, or within the metal layer 220. Note that the doped metal portion 222 serves as a barrier layer that helps impede or reduce metal diffusion, as shown in FIG. 3E. Therefore, the problem of metal loss can be alleviated or reduced.Referring to FIG. 3E, at operation 14, a portion of the metal layer 220 is removed to expose the top surface 210 tof the dielectric structure 210 and form a connection structure 240. In some embodiments, at operation 14, the doped metal portion 222 and a portion of the dielectric structure 210, such as a portion of the second dielectric layer 214, may be removed. In some embodiments, the removal of the portion of the metal layer 220, the doped metal portion 222, and the portion of the dielectric structure 210 may be performed using a chemical mechanical polishing (CMP) process.Referring to FIG. 3F, in some embodiments, another dielectric structure 250 may be formed over the dielectric structure 210 and the interconnect structure 240. Another conductive feature 260 may be formed in the dielectric structure 250. The conductive feature 260 may be coupled to the interconnect structure 240. In some embodiments, the conductive feature 260 may be referred to as the interconnect structures 140, 142 in FIG. 1. In some embodiments, the conductive feature 260 may be referred to as the metal line 150 in FIG. 1.According to the method of manufacturing the semiconductor device 10, the doped metal portion 222 may be formed before removing the part of the metal layer 220 and the part of the dielectric structure 210. The doped metal portion 222 contains the ions that can be bonded to Ru. Thus, the doped metal portion 222 may include ruthenium phosphides, ruthenium boride and ruthenium arsenide, and serve as a diffusion barrier layer. Thus, the metal diffusion can be hindered by the diffusion barrier layer, and the problem of metal loss can be alleviated. As mentioned above, the thickness of the doped metal portion 222 may be about 1 nanometer to about 50 nanometers. If the thickness of the doped metal portion 222 is less than about 1 nanometer, the doped metal portion 222 may be too thin to impede metal diffusion. In some alternative approaches, if the thickness of the doped metal portion 222 is greater than about 50 nanometers, such a thickness may result in greater cost for forming the doped metal portion 222.FIGS. 4A to 4E, 5 and 6A to 6D are schematic drawings illustrating various stages of the method of manufacturing the semiconductor device 10 according to aspects of various embodiments of the present disclosure. It is to be understood that like elements in FIGS. 3A to 3F and FIGS. 4A to 4E are denoted by like reference numerals, and repetition of details is omitted for brevity.In some embodiments, a substrate 200 may be obtained. As shown in FIG. 4A, the substrate 200 may include a conductive feature 202 disposed therein. At operation 11, a dielectric structure 210 is formed over the substrate 200 and the conductive feature 202, and an opening may be formed in the dielectric structure 210. At operation 12, a metal layer 220, such as a noble metal layer, may be formed to fill the opening 215. As shown in FIG. 4A, the metal layer 220 extends from the top surface 210 tof the dielectric structure 210 to the bottom of the dielectric structure 210. The metal layer 220 penetrates the second dielectric layer 214 and the first dielectric layer 212 to contact the exposed portion of the conductive feature 202. Further, the metal layer 220 covers the top surface 210 tof the dielectric structure 210. As mentioned above, in some embodiments, the metal layer 220 may be formed without a liner, barrier, seed layer, or other intervening layer. Therefore, in such embodiments, the metal layer 220 may be in contact with the dielectric structure 210, but the disclosure is not limited thereto.Referring to FIG. 4B, in operation 13, a doped metal portion 222 is formed in the metal layer 220. In some embodiments, the doped metal portion 222 includes phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In), but the disclosure is not limited thereto. In some embodiments, the formation of the doped metal portion 222 includes ion implantation. A dose, an angle, and a temperature used in ion implantation may be similar to those described above; therefore, details are omitted for brevity. Note that the depth of a location where the doped metal portion 222 is formed may be determined by an implantation energy of the ion implantation. For example, when the implantation energy of the ion implantation is greater than 50 keV, the doped metal portion 222 may be formed in a lower portion of the metal layer 220, as shown in FIG. 4B. However, it should be appreciated that by controlling or adjusting the implantation energy of the ion implantation, the doped metal portion 222 may be separated from the conductive feature 202. When the doped metal portion 222 is in contact with the conductive feature 202, the resistance of the conductive feature 202 may be negatively affected. In some embodiments, a doped dielectric layer 224 may be formed in the dielectric structure 210 simultaneously with the formation of the doped metal portion 222. Further, the doped dielectric layer 224 and the doped metal portion 222 are substantially aligned (aligned) with each other as shown in FIG. 4B. Thus, the doped metal portion 222 is separated from a top surface of the metal layer 220, and the doped dielectric layer 224 is separated from the top surface 210 tof the dielectric structure 210. A distribution of the dopants in the doped metal portion 222 and the doped dielectric layer 224 is illustrated as curve A in FIG. 4B. In some embodiments, a peak of the distribution curve may be near the center of the doped metal portion 222, but the disclosure is not limited thereto. In some embodiments, a thickness of the doped metal portion 222 and a thickness of the doped dielectric layer 224 may be about 1 nanometer to about 50 nanometers, but the disclosure is not limited thereto.In some embodiments, the doped dielectric layer 224 is formed in the second dielectric layer 214, and thus a top surface and a bottom surface of the doped dielectric layer 224 are in contact with the second dielectric layer 214, as shown in FIG. 4B. In some embodiments, by adjusting the implantation energy, the doped dielectric layer 224 may be formed in the second dielectric layer 214 and the first dielectric layer 212. Thus, a top surface of the doped dielectric layer 224 is in contact with the second dielectric layer 214, while a bottom surface of the doped dielectric layer 224 is in contact with the first dielectric layer 212, as shown in FIG. 6A.Referring to FIGS. 4C and 6B, in some embodiments, an anneal is performed to improve gap fill results, reduce plug resistance, and attach the interface between the dielectric structure 210 and the metal layer 220. During the anneal, metal diffusion may occur and metal ions may move from the conductive feature 202 to an upper portion of the metal layer 220, along the interface between the dielectric structure 210 and the metal layer 220, or within the metal layer 220. Note that the doped metal portion 222 and the doped dielectric layer 224 serve as a barrier layer that helps impede or reduce metal diffusion, as shown in FIGS. 4C and 6B. Therefore, the problem of metal loss can be alleviated or reduced.Referring to FIGS. 4D and 6C, at operation 14, a portion of the metal layer 220 is removed to expose the top surface 210 tof the dielectric structure 210 and form a connection structure 240. In some embodiments, a portion of the dielectric structure 210, such as a portion of the second dielectric layer 214, may be removed at operation 14. In some embodiments, the removal of the portion of the metal layer 220, the doped metal portion 222, and the portion of the dielectric structure 210 may be performed using a CMP process.This results in a connecting structure 240. As shown in FIG. 4D, the interconnect structure 240 includes the dielectric structure 210 having the first dielectric layer 212 and the second dielectric layer 214 over the substrate 200 and the conductive feature 202, the metal layer 220 disposed in the dielectric structure 210, the doped metal portion 222, and the doped dielectric layer 224 disposed over the first dielectric layer 212. As mentioned above, the first dielectric layer 212 and the second dielectric layer 214 may include different dielectric materials. In some embodiments, the metal layer may be divided into two parts by the doped metal portion 222. For example, the metal layer 220 includes a first metal portion 220- 1 in contact with the conductive feature 202 and a second metal portion 220- 2 disposed over the first metal portion 220- 1. Further, the doped metal portion 222 is disposed between the first metal portion 220- 1 and the second metal portion 220- 2. As mentioned above, the first metal portion 220- 1, the second metal portion 220- 2, and the doped metal portion 222 include a same noble metal material. The doped dielectric layer 224 and the second dielectric layer 214 include a same dielectric material. Further, the doped dielectric layer 224 and the doped metal portion 222 include like dopants.As mentioned above, the doped dielectric layer 224 and the doped metal portion 222 are substantially aligned (aligned) with each other. In some embodiments, the thickness of the doped dielectric layer 224 may be similar to the thickness of the doped metal portion 222, but the disclosure is not limited thereto. Further, a thickness of the first metal portion 220- 1 may be greater than a thickness of the first dielectric layer 212 as shown in FIG. 4D, but the disclosure is not limited thereto. In some embodiments, a top surface of the doped metal portion 222 is in contact with the second metal portion 220- 2, and a bottom surface of the doped metal portion 222 is in contact with the first metal portion 220- 1. In some embodiments, both the top surface and the bottom surface of the doped dielectric layer 224 are in contact with the second dielectric layer 214. In other words, a portion of the second dielectric layer 214 is arranged between the doped dielectric layer 224 and the first dielectric layer 212. As shown in FIG. 4D, the top surface of the doped dielectric layer 224 is separated from the top surface 210 tof the dielectric structure 210.In some embodiments, the top surface of the doped metal portion 222 and the top surface of the doped dielectric layer 224 may be exposed by removing a portion of the metal layer 220 and a portion of the second dielectric layer 214 at operation 14, as shown in FIG. 5. In such embodiments, the interconnect structure 240 may include the doped metal portion 222 disposed over the first metal portion 220- 1 and the doped dielectric layer 224 disposed over the second dielectric layer 214 and the first dielectric layer 212. In some embodiments, the peak of the distribution curve of the dopants in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222 as shown in FIG. 5, but the disclosure is not limited thereto. For example, in some embodiments, the peak of the distribution curve of the dopants in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222.Referring to FIG. 6C, in some embodiments, a connection structure 240 may be obtained at operation 14. In such embodiments, the doped dielectric layer 224 is disposed between the first dielectric layer 212 and the second dielectric layer 214. A top surface of the doped dielectric layer 224 is in contact with the second dielectric layer 214, and a bottom surface of the doped dielectric layer 224 is in contact with the first dielectric layer 212. As shown in FIG. 6C, the top surface of the doped dielectric layer 224 is separated from the top surface 210 tof the dielectric structure 210. Further, a thickness of the first metal portion 220- 1 may be substantially equal to a thickness of the first dielectric layer 212 underlying the doped dielectric layer 224, as shown in FIG. 6C.In some embodiments, the top surface of the doped metal portion 222 and the top surface of the doped dielectric layer 224 may be exposed by removing a portion of the metal layer 220 and a portion of the second dielectric layer 214 at operation 14, as shown in FIG. 7. In such embodiments, the interconnect structure 240 may include the doped metal portion 222 disposed over the first metal portion 220- 1 and the doped dielectric layer 224 disposed over the first dielectric layer 212. In some embodiments, the peak of the distribution curve of the dopants in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222 as shown in FIG. 7, but the disclosure is not limited thereto. For example, in some embodiments, the peak of the distribution curve of the dopants in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222.Referring to FIGS. 4E, 5, 6D, and 7, in some embodiments, another dielectric structure 250 may be formed over the dielectric structure 210 and the interconnect structure 240. Another conductive feature 260 may be formed in the dielectric structure 250. The conductive feature 260 may be coupled to the interconnect structure 240. In some embodiments, the conductive feature 260 may be referred to as the interconnect structures 140, 142 in FIG. 1. In some embodiments, the conductive feature 260 may be referred to as the metal line 150 in FIG. 1.According to the method of manufacturing the semiconductor device 10, the doped metal portion 222 is formed before removing the part of the metal layer 220 and the part of the dielectric structure 210. The doped metal portion 222 with the dopants bonded to the metal material serves as a diffusion barrier layer, so that metal diffusion can be obstructed or reduced and the metal loss problem can be alleviated or reduced. In some embodiments, as shown in FIGS. 4E, 5, 6D, and 7, the doped dielectric layer 224 may be formed to serve as a diffusion barrier layer to alleviate the metal loss problem. As mentioned above, the thickness of the doped metal portion 222 and the doped dielectric layer 224 may be between about 1 nanometer and about 50 nanometers. If the thickness of the doped metal portion 222 and the thickness of the doped dielectric layer 224 is less than about 1 nanometer, the diffusion barrier layer may be too thin to impede metal diffusion. In some alternative approaches, if the thickness of the doped metal portion 222 and the thickness of the doped dielectric layer 224 are greater than about 50 nanometers, such thickness may cause greater costs for removing the doped metal portion 222 and the doped dielectric layer 224.FIG. 8 is a flow diagram illustrating a method 30 of manufacturing a semiconductor device in accordance with aspects of the present disclosure. In some embodiments, the method of manufacturing the semiconductor device 30 includes a number of operations ( 31, 32, 33, and 34). The method of manufacturing the semiconductor device 30 will be further described according to one or more embodiments. It should be appreciated that the operations of the method of manufacturing the semiconductor device 30 may be rearranged or otherwise modified within the scope of the various aspects. It is further noted that additional processes may be provided before, during, and after method 30, and that some other processes may be outlined herein only briefly.FIGS. 9A to 9F are schematic drawings of various stages of the method of manufacturing the semiconductor device 30, in accordance with aspects of one or more embodiments of the present disclosure. Note that like elements in FIGS. 3A to 3F and FIGS. 9A to 9F may include like materials, and repetition of the details may be omitted for brevity. In some embodiments, a substrate 400 may be obtained. The substrate 400 may be the substrate 102 shown in FIG. 1, but the disclosure is not limited thereto. In some embodiments, the substrate 400 may include a semiconductor device such as the transistor as illustrated in FIG. 1, but the disclosure is not limited thereto. As shown in FIG. 9A, the substrate 400 may include a conductive feature 402 disposed therein. In some embodiments, the conductive feature 402 may be an FEOL feature similar to the metal gate 110 or the source / drain region S / D as shown in FIG. 1. In some embodiments, the conductive feature 402 may be a MEOL feature, such as a cobalt-containing device level contact, similar to the interconnect structures 130, 132 shown in FIG. 1. In other embodiments, the conductive feature 402 may be a BEOL feature, such as the cobalt-containing line of an M feature (metal line feature) 150 as shown in FIG. 1.At operation 31, a dielectric structure 410 is formed over the substrate 400 and the conductive feature 402. In some embodiments, the dielectric structure 410 may include a single layer. In some embodiments, the dielectric structure may include a multilayer structure. For example, as shown in FIG. 9A, the dielectric structure 410 may include at least a first dielectric layer 412 and a second dielectric layer 414 that are sequentially stacked over the substrate 400 and the conductive feature 402. The first dielectric layer 412 and the second dielectric layer 414 may include different dielectric materials.Referring further to FIG. 9A, at operation 31, an opening 415 may be formed in the dielectric structure 410. In some embodiments, the opening 415 penetrates the dielectric structure 410 from a top surface 410 tto a bottom of the dielectric structure 410. Thus, a portion of the conductive feature 402 is exposed through the opening 415.Referring to FIG. 9B, at operation 32, a metal layer 420, for example a noble metal layer, may be formed to fill the opening 415. The metal layer 420 extends from the top surface 410 tof the dielectric structure 410 to the bottom of the dielectric structure 410. The metal layer 420 penetrates the second dielectric layer 414 and the first dielectric layer 412 to contact the exposed portion of the conductive feature 402. the metal layer 420 further covers the top surface 410 tof the dielectric structure 410. It should be noted that in some embodiments, the metal layer 420 may be formed in the absence of a liner, barrier, seed layer, or any intervening layer. Therefore, in such embodiments, the metal layer 420 may be in contact with the dielectric structure 410, but the disclosure is not limited thereto.Referring to FIG. 9C, at operation 33, a portion of the metal layer 420 is removed to expose the top surface 410 tof the dielectric structure 410 and form a connection structure 440. In some embodiments, a portion of the dielectric structure 410, for example a portion of the second dielectric layer 414, may be removed at operation 33. In some embodiments, the removal of the portion of the metal layer 420 and the portion of the dielectric structure 410 may be performed by a CMP method.Referring to FIG. 9D, in operation 34, a doped metal portion 422 is formed in the metal layer 420 and a doped dielectric layer 424 is formed in the second dielectric layer 414 of the dielectric structure 410. In some embodiments, the doped metal portion 422 and the doped dielectric layer 424 are aligned (aligned) with each other, but the disclosure is not limited thereto. In some embodiments, the doped metal portion 422 and the doped dielectric layer 424 include phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In), but the disclosure is not limited thereto. In some embodiments, forming the doped metal portion 422 and the doped dielectric layer 424 includes ion implantation. A dose of ion implantation may be about 1E13 cm -2 to about 1E16 cm -2. An angle of ion implantation may be about 0 degrees to about 60 degrees. In some embodiments, the temperature of ion implantation may be about -100° C. to about 500° C. Note that the depth or the location where the doped metal portion 422 is formed may be determined by the implantation energy of the ion implantation. For example, when the implantation energy of the ion implantation is about 500 eV to about 50 keV, the doped metal portion 422 may be formed in an upper portion of the metal layer 420, and the doped dielectric layer 424 may be formed in an upper portion of the second dielectric layer 414. In some embodiments, as shown in FIG. 9D, a top surface of the doped metal portion 422 and a top surface of the doped dielectric layer 424 are exposed. A distribution of the dopants in the doped metal portion 422 in the doped dielectric layer 424 is depicted as curve A in FIG. 9D. In some embodiments, a peak of the distribution curve may be near the center of the doped metal portion 422 and the center of the doped dielectric layer 424, but the disclosure is not limited thereto. In some embodiments, the thickness of the doped metal portion 422 may be about 1 nanometer to about 30 nanometers, but the disclosure is not limited thereto. Further, the thickness of the doped dielectric layer 424 may be about 1 nanometer to about 50 nanometers, but the disclosure is not limited thereto.Referring to FIG. 9E, in some embodiments, an anneal is performed to improve the gap fill results, reduce the plug resistance, and attach an interface between the dielectric structure 410 and the metal layer 420. During the anneal, metal diffusion may occur and metal ions may move from the conductive feature 402 to a top portion of the metal layer 420, along the interface between the dielectric structure 410 and the metal layer 420, or within the metal layer 420. Note that the doped metal portion 422 together with the doped dielectric layer 424 serves as a barrier layer that helps impede or reduce metal diffusion, as shown in FIG. 9E. Therefore, the metal loss problem can be alleviated or reduced.According to the method of manufacturing the semiconductor device 30, the doped metal portion 422 and the doped dielectric layer 424 may be formed after removing the part of the metal layer 420 and the part of the second dielectric layer 414. The doped metal portion 422 contains the ions, for example Ru, that can be bonded to the metal layer. Therefore, the doped metal portion 422 may include ruthenium phosphides, ruthenium boride and ruthenium arsenide, and serve as a diffusion barrier layer. Thus, metal diffusion can be obstructed by the diffusion barrier layer, and the metal loss problem can be alleviated. As mentioned above, the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 may be about 1 nanometer to about 30 nanometers. If the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 are less than about 1 nanometer, the diffusion barrier layer may be too thin to impede metal diffusion. In some alternative approaches, if the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 are greater than about 50 nanometers, such thickness may negatively affect the resistance of the conductive feature 402.FIGS. 10A to 10C are schematic drawings of various stages of the method of manufacturing the semiconductor device 30, in accordance with aspects of one or more embodiments of the present disclosure. The steps shown in FIGS. 10A to 10C may be performed after performing the steps associated with FIGS. 9A to 9C. It is to be understood that like elements in FIGS. 9A to 9F and FIGS. 10A to 10C are denoted by like reference numerals, and repetition of the details may be omitted for brevity.In some embodiments, a substrate 400 may be obtained. As shown in FIG. 10A, the substrate 400 may include a conductive feature 402 disposed therein. At operation 31, a dielectric structure 410 is formed over the substrate 400 and the conductive feature 402, and an opening may be formed in the dielectric structure 410. At operation 32, a metal layer 420, such as a noble metal layer, may be formed to fill the opening. As mentioned above, in some embodiments, the metal layer 420 may be formed without a liner, barrier, seed layer, or intervening layer. Therefore, in such embodiments, the metal layer 420 may be in contact with the dielectric structure 410, but the disclosure is not limited thereto.Referring to FIG. 10A, at operation 33, a portion of the metal layer 420 is removed to expose the top surface 410 tof the dielectric structure 410 and form a connection structure 440. In some embodiments, a portion of the dielectric structure 410, for example a portion of the second dielectric layer 414, may be removed at operation 33. In some embodiments, the removal of the portion of the metal layer 420 and the portion of the dielectric structure 410 may be performed by a CMP method.At operation 34, a doped metal portion 422 is formed in the metal layer 420 and a doped dielectric layer 424 is formed in the dielectric structure 410. In some embodiments, forming the doped metal portion includes ion implantation. A dose, an angle, and a temperature used in ion implantation may be similar to those described above; therefore, details are omitted for brevity. Note that the depths or positions of the doped metal portion 422 and the doped dielectric layer 424 may be determined by an implantation energy of ion implantation. For example, by adjusting the implantation energy, the doped metal portion 422 and the doped dielectric layer 424 may be formed away from the top surface 410 tof the dielectric structure 410 or in a bottom portion of the second dielectric layer 414. In some embodiments, the doped dielectric layer 424 may be formed by adjusting the implantation energy in both the first dielectric layer 412 and the second dielectric layer 414, as shown in FIG. 10A. However, it should be appreciated that by controlling or adjusting the implant energy of the ion implantation, the doped metal portion 422 and the doped dielectric layer 424 are separated from the conductive feature 402. In some comparable approaches, the resistance of the conductive feature 402 may be negatively affected when the doped metal portion 422 is in contact with the conductive feature 402.Referring to FIG. 10B, in some embodiments, an anneal is performed to improve the gap filling results, reduce the plug resistance, and attach an interface between the dielectric structure 410 and the metal layer 420. During the anneal, metal diffusion may occur and metal ions may move from the conductive feature 402 to a top portion of the metal layer 420, along the interface between the dielectric structure 410 and the metal layer 420, or within the metal layer 420. Note that the doped metal portion 422 and the doped dielectric layer 424 serve as a barrier layer that helps impede or reduce metal diffusion, as shown in FIG. 10B. Therefore, the metal loss problem can be alleviated or reduced.Referring to FIGS. 9F and 10C, in some embodiments, another dielectric structure 450 may be formed over the dielectric structure 410 and the interconnect structure 440. Another conductive feature 460 may be formed in the dielectric structure 450. The conductive feature 460 may be coupled to the interconnect structure 440. In some embodiments, the conductive feature 460 may be referred to as the interconnect structures 140, 142 in FIG. 1. In some embodiments, the conductive feature 460 may be referred to as the metal line 150 in FIG. 1.Thus, a connection structure 440 as shown in FIG. 9E or 10B is obtained. The interconnect structure 440 includes the dielectric structure 410 including the first dielectric layer 412 and the second dielectric layer 414 over the substrate 400 and the conductive feature 402, the metal layer 420 disposed in the dielectric structure 410, the doped metal portion 422 and the doped dielectric layer 424. In some embodiments, the top surface of the doped metal portion 422 and the top surface of the doped dielectric layer 424 form a top surface of the interconnect structure 440, as shown in FIG. 9E. In such embodiments, the second dielectric layer 414 may be disposed between the doped dielectric layer 424 and the first dielectric layer 412. Therefore, a lower surface of the doped dielectric layer 424 is in contact with the second dielectric layer 414. Further, the doped metal portion 422 is separated from the conductive feature 402 by the metal layer 420.In other embodiments, as mentioned above, the metal layer 420 may be divided into two parts by the doped metal portion 422. For example, the metal layer includes a first metal portion 420- 1 in contact with the conductive feature 402 and a second metal portion 420- 2 disposed over the first metal portion 420- 1. Further, the doped metal portion 422 including dopants bonded to the metal material is disposed between the first metal portion 420- 1 and the second metal portion 420- 2. In such embodiments, the doped dielectric layer 424 is disposed between the first dielectric layer 412 and the second dielectric layer 414. In some embodiments, the thickness of the first metal portion 420- 1 may be greater than the thickness of the first dielectric layer 412, as shown in FIG. 9E. In other embodiments, the thickness of the first metal portion 420- 1 may be substantially equal to the thickness of the first dielectric layer 412 underlying the doped dielectric layer 414, as shown in FIG. 10B. In some embodiments, the top surface of the doped metal portion 422 is separated from the top surface of the interconnect structure 440 by the second metal portion 420- 2, and the top surface of the doped dielectric layer 424 is separated from the top surface 410 tof the dielectric structure 410 and the top surface of the interconnect structure 440 by the second dielectric layer 414, as shown in FIG. 10B. In such embodiments, the top surface of the doped metal portion 422 is in contact with the second metal portion 420- 2, and a bottom surface of the doped metal portion 422 is in contact with the first metal portion 420- 1. The upper surface of the doped dielectric layer 424 is in contact with the second dielectric layer 424 and a lower surface of the doped dielectric layer 424 is in contact with the first dielectric layer 412.As mentioned above, the doped dielectric layer 424 and the doped metal portion 422 are substantially aligned (aligned) with each other. In some embodiments, the thickness of the doped dielectric layer 424 may be similar to the thickness of the doped metal portion 422, but the disclosure is not limited thereto.According to the method of manufacturing the semiconductor device 30, the doped metal portion 422 and the doped dielectric layer 424 may be formed after removing the part of the metal layer 420 and the part of the second dielectric layer 414. The doped metal portion 422 having the dopants bonded to the metal material serves as a diffusion barrier layer, so that the metal diffusion can be hindered and the metal loss problem can be alleviated. As mentioned above, the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 may be about 1 nanometer to about 30 nanometers. If the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 are less than about 1 nanometer, the diffusion barrier layer may be too thin to impede metal diffusion. In some alternative approaches, if the thickness of the doped metal portion 422 and the thickness of the doped dielectric layer 424 are greater than about 50 nanometers, such thickness may negatively affect the resistance of the conductive feature 402.In short, embodiments of the present disclosure provide a semiconductor device having an interconnect structure and a method of manufacturing a semiconductor device to counteract the problem of low metal loss. In some embodiments, ion implantation is performed after depositing the metal layer to form a barrier layer in the conductive material. The ion implantation may be performed before or after the removal of the unnecessary metal layer. In some embodiments, ions implanted into the conductive material are combined with the conductive material to form the diffusion barrier layer, so that metal diffusion may be obstructed by the barrier layer. Thus, the problem of lower metal loss caused by metal diffusion can be alleviated.The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are set forth in the dependent claims.

Claims

A semiconductor device (240, 440) comprising: a first dielectric layer (212, 412) disposed over a substrate (200, 400) and a conductive feature (202, 402); a second dielectric layer (214, 414) disposed over the first dielectric layer (212), a doped dielectric layer (224, 424) disposed over the first dielectric layer (212, 412) and in the second dielectric layer (214); a first metal portion (220-1, 420-1) disposed in the first dielectric layer (212, 412) and in contact with the conductive feature (202, 402); and a doped metal portion (222, 422) disposed over the first metal portion (220-1, 420-1), wherein the doped dielectric layer (224) and the doped metal portion (222) are aligned with each other, wherein the doped metal portion (222) is separated from a top surface of the first metal portion (220) and the doped dielectric layer (224) is separated from the top surface (210t) of the second dielectric layer (214); wherein the first metal portion (220-1, 420-1) and the doped metal portion (222, 422) include a same noble metal material, wherein the doped dielectric layer (224, 424) and the doped metal portion (222, 422) include same dopants, wherein the dopants are bonded to the noble metal material in the doped metal portion (222, 422).The semiconductor device (220, 420) of claim 1, wherein the doped dielectric layer (224, 424) is in contact with the first dielectric layer (212, 412).The semiconductor device (220, 420) of any preceding claim, wherein the first dielectric layer (212, 412) includes a first dielectric material, wherein the second dielectric layer (214, 414) and the doped dielectric layer (224, 424) include a second dielectric material, wherein the first dielectric material and the second dielectric material are different from each other.The semiconductor device (220, 420) according to any one of the preceding claims, further comprising: a second metal portion (220-2, 420-2) disposed over the substrate (200, 400), wherein the second metal portion (220-2, 420-2) includes a same noble metal material as the first metal portion (220-1, 420-1).The semiconductor device (220, 420) of claim 4, wherein the doped metal portion (222, 422) is disposed between the second metal portion (220-2, 402-2) and the first metal portion (220-1, 420-1).The semiconductor device (220, 420) of any preceding claim, wherein the dopants include phosphorus, boron, arsenic, gallium, or indium.The semiconductor device of any preceding claim, wherein the noble metal material includes rhenium, rhodium, and ruthenium.The semiconductor device according to any one of the preceding claims, wherein a peak of a distribution curve (A) of the dopants in the doped metal portion (222) and in the doped dielectric layer (224) is near the center of the doped metal portion (222).The semiconductor device of any preceding claim, wherein a thickness of the doped metal portion (222) and a thickness of the doped dielectric layer (224) is about 1 nm to about 50 nm.A method of manufacturing a semiconductor device (10), comprising: forming a dielectric structure (210) over a conductive feature (202), the dielectric structure (210) comprising an opening (215) exposing a portion of the conductive feature (202); filling the opening (215) with a metal layer (220) containing a noble metal material; forming a doped metal portion (222) in the metal layer (220), the doped metal portion (222) containing dopants bonded to the metal material; and removing a portion of the metal layer (220) to expose a top surface (210t) of the dielectric structure (210) and form an interconnect structure (240), the method further comprising: forming a doped dielectric layer (224) in the dielectric structure (210) simultaneously with forming the doped metal portion (222), wherein the doped dielectric layer (224) and the doped metal portion (222) are substantially aligned with each other, wherein the doped metal portion (222) is separated from a top surface of the metal layer (220) and the doped dielectric layer (224) is separated from the top surface (210t) of the dielectric structure (210).The process of claim 10, wherein the precious metal material comprises rhenium, rhodium and ruthenium.The method of claim 11, wherein the dopants include phosphorus, boron, arsenic, or nitrogen.The method of any of the preceding claims 10 to 12, wherein forming the doped metal portion (222) and forming the doped dielectric layer (224) comprise ion implantation using an implant energy of greater than about 50 keV.The method of any of the preceding claims 10 to 13, wherein after forming the doped metal portion (222) in the metal layer (220), an anneal is performed.The method of any of the preceding claims 10 to 14, wherein a CMP operation is performed in the removing of the portion of the metal layer (220).The method of any of the preceding claims 10 to 15, wherein a peak of a distribution curve (A) of the dopants in the doped metal portion (222) and in the doped dielectric layer (224) is near the center of the doped metal portion (222).The method of any of the preceding claims 10 to 16, wherein a thickness of the doped metal portion (222) and a thickness of the doped dielectric layer (224) is about 1 nm to about 50 nm.A method of manufacturing a semiconductor device (30), the method comprising: forming a dielectric structure (410) over a conductive feature (402), the dielectric structure (410) having an opening (415) exposing a portion of the conductive feature (402); filling the opening (415) with a metal layer (420), the metal layer (420) covering a top surface of the dielectric structure (410); removing a portion of the metal layer (420) to expose the top surface (210t) of the dielectric structure (410); and after removing the part of the metal layer (420), forming a doped metal portion (422) in the metal layer (420) and a doped dielectric layer (424) in the dielectric structure (410), wherein the metal layer (420) and the doped metal portion (422) include a same metal material, wherein the doped metal portion (422) and the doped dielectric layer (424) include same dopants, wherein the dopants are bonded to the metal material in the doped metal portion (422).The method of claim 18, wherein the metal material includes a noble metal material.The method of claim 18 or 19, wherein the dopants include phosphorus (P), boron (B), arsenic (As), gallium (Ga), or indium (In).

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