Method for producing a silicon carbide epitaxial wafer

Abstract

A method for producing a silicon carbide epitaxial wafer (20), comprising: - an etching process for etching a surface of a silicon carbide substrate (1) at a first temperature using an etching gas comprising H2, wherein the silicon carbide substrate (1) has an angular offset inclined with respect to the (0001) plane in the <11-20> direction at an angle of approximately 5 degrees; - a process for flattening the surface etched during the etching process at a second temperature using a gas comprising H2 gas, a first Si supply gas, and a first C supply gas; and - an epitaxial layer growth process for performing epitaxial growth on the surface flattened during the flattening processing process at a third temperature using a gas comprising a second Si supply gas and a second C supply gas, wherein: - the first temperature T1, the second temperature T2, and the third temperature T3, T1 > T2>T3, - the first temperature T1 is equal to or greater than 1650 °C and equal to or less than 1750 °C, - the second temperature T2 is equal to or greater than 1550 °C and equal to or less than 1680 °C, and - the third temperature T3 is equal to or greater than 1450 °C and equal to or less than 1600 °C.

Description

Background of the inventionField of the invention

[0001] The present disclosure relates to a method for producing a silicon carbide epitaxial wafer. Description of the state of the art

[0002] Silicon carbide exhibits a wide band gap and better physical properties than silicon, such as insulation breakdown field intensity, saturated electron velocity, and thermal conductivity. Therefore, it has excellent performance as a semiconductor device material. In particular, in semiconductor devices using silicon carbide, a significant reduction in power loss and downsizing of the semiconductor device can be achieved, thus enabling energy savings at the time of energy conversion from a power source. Therefore, silicon carbide is attracting attention as a semiconductor material for achieving a low-carbon society, for example, through high performance of an electric vehicle and high functionality of a solar power system.

[0003] To manufacture a semiconductor device using silicon carbide, first, a layer in which an impurity concentration is controlled with high precision is epitaxially grown on a silicon carbide substrate using a silicon carbide substrate epitaxial growth apparatus, for example, by a chemical vapor deposition (CVD) method. A silicon carbide epitaxial layer may be an N-type layer, for example, by adding nitrogen to the epitaxial growth gas. A wafer in which a silicon carbide epitaxial layer is formed on the silicon carbide substrate is called a silicon carbide epitaxial wafer. A device in which an element region is further formed on the silicon carbide epitaxial wafer or on which various processes are additionally performed is called a silicon carbide semiconductor device.

[0004] Japanese Patent JP 60 12841 B2 discloses a method for manufacturing a silicon carbide semiconductor device. Japanese Patent JP 60 12841 B2 describes that the occurrence of a surface defect such as step bunching in a silicon carbide epitaxial layer can be suppressed by a method described in Japanese Patent JP 60 12841 B2. Summary

[0005] Examples of defects occurring in the silicon carbide epitaxial layer include a triangular defect. This surface defect can be suppressed by the method described in Japanese Patent JP 60 12841 B2, but suppressing the occurrence of a triangular defect is not specifically addressed.

[0006] JP 2013-034007 A discloses a method for producing an epitaxial SiC wafer without step bundling, i.e., a method in which step bundling is avoided over the entire surface of a wafer. Such an epitaxial SiC wafer is a wafer formed with a SiC epitaxial layer on a 4H-SiC single-crystal substrate tilted at an off-angle of 0.4° to 5° and without short-step bundling.

[0007] The document US 2017 / 0 233 893 A1 describes a SiC epitaxial wafer comprising a SiC epitaxial layer formed on a SiC substrate with an offset angle x, wherein the surface density of triangular defects, in which a distance from a starting point to an opposite side in the horizontal direction is equal to or greater than a thickness of the SiC epitaxial layer / tan(x) × 90% and equal to or less than the thickness of the SiC epitaxial layer / tan(x) × 110%, in the SiC epitaxial layer is in the range of 0.05 pieces / cm 2 up to 0.5 pieces / cm 2 lies.

[0008] The document US 2013 / 0 126 906 A1 relates to a method for producing an epitaxial silicon carbide wafer with very good surface flatness and a very low density of carrot-shaped defects and triangular defects appearing after epitaxial growth. The epitaxial silicon carbide wafer is obtained by a first step of annealing a silicon carbide bulk substrate which is inclined by less than 5 degrees from a surface <0001> from inclined, in a reducing gas-containing atmosphere at a first temperature T1 for a treatment time t, a second step of lowering the temperature of the substrate in the reducing gas atmosphere, and a third step of performing an epitaxial growth at a second temperature T2 below the annealing temperature T1 of the first step, wherein a gas is supplied which contains a gas containing silicon atoms and / or a gas containing carbon atoms.

[0009] It is an object of the present invention to provide a method for producing a silicon carbide epitaxial wafer which is suitable for suppressing a triangular defect.

[0010] The object underlying the invention is achieved in a method for producing a silicon carbide epitaxial wafer according to the invention with the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0011] In a method for manufacturing a silicon carbide epitaxial wafer according to the present disclosure, a surface of a silicon carbide substrate is etched at a first temperature, the surface etched by the etching is flattened at a second temperature, and epitaxial growth is performed at a third temperature on the surface flattened by the flattening. An etching gas containing H2 is used during the etching. A gas containing an H2 gas, a first Si supply gas, and a first C supply gas is used during the flattening. A gas containing a second Si supply gas and a second C supply gas is used during the epitaxial growth. A first temperature T1, a second temperature T2, and a third temperature T3 satisfy T1>T2>T3.

[0012] The silicon carbide substrate has an angular offset inclined at an angle of approximately 5 degrees relative to the (0001) plane in the <11-20> direction. According to the invention, the first temperature T1 is equal to or greater than 1650°C and equal to or less than 1750°C, the second temperature T2 is equal to or greater than 1550°C and equal to or less than 1680°C, and the third temperature T3 is equal to or greater than 1450°C and equal to or less than 1600°C.

[0013] The etching is carried out at the first temperature T1, the flattening is carried out at the second temperature T2, and the epitaxial growth is carried out at the third temperature T3 under a condition of T1 > T2 > T3, thus suppressing the occurrence of a triangle defect.

[0014] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Short description of the characters Fig. 1 is a schematic diagram of a silicon carbide epitaxial growth apparatus used to perform the method according to one embodiment. Fig. Figure 2 is a schematic cross-sectional view of a silicon carbide epitaxial wafer. Fig. 3 is a flowchart of a method for manufacturing the silicon carbide epitaxial wafer according to the embodiment. Fig. 4 is a diagram illustrating a triangular defect density of each silicon carbide epitaxial wafer manufactured in the embodiment and in a comparative example 1. Fig. 5 is a graph illustrating an effect of flattening processing in a case of changing a flattening processing time and a flattening processing temperature. Description of the preferred embodiments<A. Ausführungsform><A-1. Konfiguration einer Siliziumkarbid-Epitaxiewachstumsvorrichtung>

[0015] First, a configuration of a silicon carbide epitaxial growth apparatus 100, which is a silicon carbide epitaxial growth apparatus according to the present embodiment, will be described.

[0016] Fig. Figure 1 is a schematic cross-sectional view of a growth furnace 10 included in the silicon carbide epitaxial growth apparatus according to the embodiment as a main unit thereof. The growth furnace 10 will be described below.

[0017] The growth furnace 10 comprises a susceptor 5, a wafer holder 3, a rotating table 2, and an induction heating coil 4.

[0018] Gas such as a growth gas, a carrier gas, and an etching gas is provided to the susceptor 5 and from it in the form of a Fig. 1. Consequently, the susceptor 5, for example, is always filled with new growth gas, carrier gas, and etching gas.

[0019] When forming an epitaxial growth layer on a silicon carbide substrate 1, for example, a gas containing SiH4 gas comprising silicon atoms and C3H8 gas comprising carbon atoms is used as the growth gas, and a gas containing H2 is used as the carrier gas. In the silicon carbide epitaxial growth apparatus 100, a growth temperature can be set, for example, to be in a range from 1450°C to 1700°C, and a growth pressure can be set, for example, to be in a range from 1×10 3 Pa up to 5×10 4 Pa. Nitrogen gas for N-type doping can be provided along with the growth gas if necessary. An organic metal material comprising Al, B, or Be can be provided for P-type doping. In addition, HCl or dichlorosilane can be used to increase the growth rate.

[0020] The wafer holder 3 has a disk-like shape. A plurality of wafer pockets 31 are provided in a surface of the wafer holder 3 so that the silicon carbide substrate 1 can be arranged therein. The plurality of wafer pockets 31 are formed by performing a countersinking process multiple times on the surface of the wafer holder 3. The wafer holder 3 is arranged on the rotating table 2 and rotates, for example, at a constant speed together with the rotating table 2 when the epitaxial growth layer is formed on the silicon carbide substrate 1.

[0021] The induction heating coil 4 is wound around an outer edge region of the susceptor 5. The wafer holder 3, the susceptor 5, and the rotating table 2 are inductively heated when electrical power is supplied to the induction heating coil 4. When the wafer holder 3, the susceptor 5, and the rotating table 2 are inductively heated, the interior of the susceptor 5 is completely heated by heat conduction and heat radiation.

[0022] In the present embodiment, silicon carbide-coated graphite is used in the wafer holder 3, the rotating table 2, and the susceptor 5. This is because the silicon carbide substrate 1 is heated to, for example, approximately 1450°C or more when the epitaxial growth layer is formed on the silicon carbide substrate 1, so these components must be able to withstand such heat.

[0023] Consider a configuration in which the wafer holder 3, the rotating table 2, and the susceptor 5 are formed only of graphite. In this case, there is a possibility that graphite will cause dust during the formation of the epitaxial growth layer. If the epitaxial growth layer is formed in a state where microparticles of graphite in the form of dust are present on the silicon carbide substrate 1, crystals will grow abnormally from a position where the microparticles are present, and a crystal defect will occur in the epitaxial growth layer. Therefore, it is preferable to coat graphite with silicon carbide to suppress dust caused by graphite.

[0024] In graphite coated with silicon carbide, the occurrence of dust caused by graphite is suppressed due to the silicon carbide coating. Diffusion of metal impurities from graphite is also suppressed. Metal impurities cause crystal defects on the epitaxial growth layer and also affect the electrical properties of the semiconductor device; therefore, it is preferable to prevent the metal impurities from diffusing. Accordingly, graphite coated with silicon carbide is preferably used in the wafer holder 3, the rotating table 2, and the susceptor 5. A silicon carbide material produced by a CVD method or by a sintering method can be used for the silicon carbide coating. The graphite can be coated using tantalum carbide (TaC) instead of silicon carbide.Carbon coating using a CVD process can also be applied to the graphite. <A-2. Konfiguration des Siliziumkarbid-Epitaxie-Wafers>

[0025] Fig. 2 is a schematic cross-sectional view of a silicon carbide epitaxial wafer 20 manufactured by a method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment.

[0026] The silicon carbide epitaxial wafer 20 manufactured in the present embodiment includes the silicon carbide substrate 1 and a silicon carbide epitaxial layer 12 formed on the silicon carbide substrate 1.

[0027] The silicon carbide substrate 1 is an N-type silicon carbide substrate with low resistance. The conductivity type of the silicon carbide epitaxial layer 12 is the same as that of the silicon carbide substrate 1, specifically, an N-type. The silicon carbide substrate 1 is a silicon carbide substrate 1 having an angular offset inclined at an angle of approximately 5 degrees relative to the (0001) plane in the <11-20> direction.

[0028] A preferred configuration of the silicon carbide epitaxial wafer 20 is described.

[0029] A silicon carbide semiconductor device manufactured by performing various types of processing on the silicon carbide epitaxial wafer 20 is referred to as a silicon carbide semiconductor device 21. If a defect exists in the silicon carbide epitaxial wafer 20 caused by a defect in the silicon carbide substrate 1 and a defect at the time of growth of the silicon carbide epitaxial layer 12, a region in the silicon carbide semiconductor device 21 where a high voltage cannot be locally maintained occurs, and a leakage current occurs in the silicon carbide semiconductor device 21.When leakage current occurs in the silicon carbide semiconductor device 21, there is a high probability that the silicon carbide semiconductor device 21 will become a defective device. Therefore, if the density of the high-voltage-incapable region increases, the non-defect rate during the fabrication of the silicon carbide semiconductor device 21 decreases. Typical examples of defects that reduce the non-defect ratio include a lack of crystallographic uniformity in the silicon carbide epitaxial wafer 20, for example, a defect in which the periodicity of an atomic arrangement in the crystal along a crystal growth direction is locally imperfect. A carrot defect and a triangle defect, which occur due to the epitaxial growth of silicon carbide, are known as some of the defects associated with such a lamination defect and cause leakage current.

[0030] A silicon carbide crystal has a variety of crystal types (polytypes), among which the periodicity of an atomic arrangement along a c-axis varies. Although they have a stoichiometric composition in which the ratio of Si to C is 1:1, that is, the same ratio, and a crystal lattice with a hexagonal close-packed structure, physical properties are regulated depending on the periodicity. A type called 4H type is currently attracting the most attention from a device application perspective. To epitaxially grow the same crystal type, a surface of the silicon carbide substrate is usually set to be tilted with respect to a plane orientation of the crystal, and the silicon carbide substrate is processed such that a surface with respect to the (0001) plane in the <11-20> direction corresponds to an angle of 8 degrees or 4 degrees.

[0031] The silicon carbide substrate 1 is processed by cutting and lapping a silicon carbide ingot into a wafer shape, and subsequently, a process damage layer on the surface of the silicon carbide substrate 1 is removed by, for example, multi-stage mechanical polishing, chemical mechanical polishing (CMP), and H2 etching.

[0032] If the process damage layer remains on the surface of the silicon carbide substrate 1, a surface defect such as a predominantly triangular defect frequently occurs when the silicon carbide epitaxial layer is formed, and stepwise growth is also blocked. Consequently, step clustering easily occurs and surface roughness increases. Even if the surface of the silicon carbide substrate 1 is flat in a nano-scale range, in some cases, process damage, which is called a latent defect, exists near the surface of the silicon carbide substrate 1. The latent defect is not generally accompanied by a surface unevenness or an extremely small unevenness, if any; therefore, the unevenness cannot be confirmed by an optical microscope.However, if a latent defect exists near the surface of the silicon carbide substrate 1, the latent defect becomes an origin of the surface defect such as predominantly a triangular defect and a step bundling in epitaxial growth.

[0033] If a crystal growth condition deviates from a desired condition during a silicon carbide ingot manufacturing process, particles called inclusions are incorporated into the ingot. If the inclusion is located on the surface of the silicon carbide substrate 1, a surface defect, such as a predominantly triangular defect, occurs during epitaxial growth, originating from the inclusion. Consequently, the inclusion leads to a reduction in device yield.

[0034] As described above, the latent defect and the inclusion lead to the triangular defect. Therefore, the latent defect and the inclusion are removed by H2 etching, as described below in the method for manufacturing the silicon carbide epitaxial wafer according to the present embodiment. Preferably, they are completely removed. If the silicon carbide substrate 1 containing the latent defect or inclusion is etched using, for example, H2 gas, a recess is formed because the etching is promoted in the latent defect and the inclusion in which a disturbance of a crystal structure occurs, and the recess can be confirmed using an optical microscope. If the<A-3-3. Epitaxieschichtwachstumsprozess> , which is described below, is carried out directly on the surface with this depression, a triangular defect occurs starting from the depression as the origin.In the method for manufacturing the silicon carbide epitaxial wafer according to the present embodiment, a flattening processing as described below is carried out.<A-3-2. Prozess der Abflachprozessierung> to reduce the triangular defect originating from the depression, and then an epitaxial layer growth process is carried out in the<A-3-3. Epitaxieschichtwachstumsprozess> to form the silicon carbide epitaxial layer 12. <A-3. Verfahren zur Herstellung eines Siliziumkarbid-Epitaxie-Wafers>

[0035] A method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment will be described.

[0036] The silicon carbide epitaxial growth apparatus 100 is used in the method for manufacturing the silicon carbide epitaxial wafer according to the present embodiment. Fig. 3 is a flowchart of the method for manufacturing the silicon carbide epitaxial wafer according to the present embodiment.

[0037] First, the silicon carbide substrate 1 is prepared, and the silicon carbide substrate 1 is placed in the wafer pocket 31 of the wafer holder 3 outside the susceptor 5. Subsequently, the wafer holder 3, in which the silicon carbide substrate 1 is placed, is placed on the rotating table 2 provided in the susceptor 5 (a silicon carbide substrate loading process, step S1).

[0038] After step S1, an H2 gas etching process (step S2), a flattening process (step S3), and an epitaxial layer growth process (step S4) are performed sequentially. Subsequently, the silicon carbide epitaxial wafer 20, in which the silicon carbide epitaxial layer 12 was formed on the silicon carbide substrate 1 in the epitaxial layer growth process of step S4, is transported out of the susceptor 5 (a silicon carbide epitaxial wafer removal process, step S5).

[0039] The H2 gas etching process (step S2), the flattening processing process (step S3), and the epitaxial layer growth process (step S4) are described in detail below. <A-3-1. H2-Gasätzprozess>

[0040] In the H2 gas etching process in step S2, after step S1, a pressure in the susceptor 5 is reduced to a desired pressure, and then the silicon carbide substrate 1 is heated. Heating is performed by applying electrical energy to the induction heating coil 4 wound around an outer peripheral portion of the susceptor 5. The susceptor 5, the rotating table 2, and the wafer holder 3 are inductively heated when the electrical energy is applied to the induction heating coil 4. The silicon carbide substrate 1 is heated, for example, by heat radiation from an inner wall of the susceptor 5 (also from a side part of the rotating table 2 when the rotating table 2 has a U-like shape) and by heat conduction from the wafer holder 3. When the silicon carbide substrate 1 has been heated to a target temperature, an H2 gas is provided in the susceptor 5 to perform H2 gas etching.

[0041] During the H2 gas etching, gas containing H2 gas, which is preferably only H2 gas, flows into the growth furnace 10, a pressure in the growth furnace 10 is adjusted to be equal to or greater than 5×10 3 Pa and equal to or less than 5×10 4 Pa, and a temperature of the silicon carbide substrate 1 is set to be equal to or greater than 1650 °C and equal to or less than 1750 °C. In the present embodiment, the H2 gas etching is carried out at a pressure of 9×10 3 Pa and a temperature of 1670 °C.

[0042] It is preferable that the latent defect and inclusion be completely removed to reduce the surface defect such as a triangular defect that occurs during epitaxial growth. When the temperature during etching is set to be equal to or higher than 1650°C, an etching rate increases, and a time required to remove the latent defect and inclusion is shortened; thus, such a temperature is more preferable from a productivity perspective. When the temperature during etching is set to be equal to or lower than 1750°C, there is a low frequency that the etching of a silicon carbide product material adhering to a furnace wall of the growth furnace 10 continues, and silicon carbide particles fall onto the silicon carbide substrate 1.

[0043] The latent defect and inclusion located on the surface of the silicon carbide substrate 1 are accompanied by a disruption of a crystal structure and are fragile, thus they can be easily etched by heated H2 gas. A pit remains at a position where the latent defect or inclusion is located on the surface of the silicon carbide substrate 1 after etching. For example, the depth of the pit is equal to or greater than 0.05 µm and equal to or less than 0.5 µm, but this depends on the size of the latent defect and inclusion or the etching conditions.

[0044] For example, an etching processing time is equal to or longer than five minutes and equal to or shorter than 30 minutes in a case where a condition of 9×10 3Pa and 1670 °C. When the etching time is longer than five minutes, large latent defects and large inclusions can be removed more efficiently. The etching time is not too long, thus preventing excessive etching and increasing productivity.

[0045] A preferred H2 gas etching condition, particularly a preferred etching processing time and pressure, differs depending on a crystal state and a surface unevenness state of the silicon carbide substrate 1. The H2 gas etching condition is not limited to that described in the present embodiment, as long as the number of latent defects and inclusions can be reduced to a target number. <A-3-2. Prozess der Abflachprozessierung>

[0046] As described above, the latent defect and inclusion in the silicon carbide substrate 1 can be removed by the H2 gas etching process, which is carried out in<A-3-1. H2-Gasätzen> described, or preferably completely eliminated. However, the latent defect and the inclusion can be etched more easily than the wider region, thus the recess remains locally in the surface where the latent defect and the inclusion are located. If the silicon carbide epitaxial layer is formed on the surface etched by the H2 gas etching process, thereby obtaining the recess, the abnormal growth occurs from the recess as the origin and leads to the triangular defect in a case where a portion of the recess is not filled but remains in the surface during epitaxial growth.The occurrence of the triangular defect can be suppressed by performing the epitaxial layer growth process of step S4 after performing the recess flattening processing in the flattening processing process of step S3. The flattening processing process of step S3 corresponds to the same processing condition as the epitaxial layer growth process of step S4 in the present embodiment except for the processing temperature and processing time. Therefore, it is considered to have a configuration in which not only the recess is simply flattened but also epitaxial growth occurs, and the silicon carbide epitaxial layer 12 also includes the region formed by the flattening processing process of step S3.However, the flattening processing is carried out for the purpose of flattening the recess, as compared with the epitaxial layer growth process of step S4 described below, hence it is referred to as the flattening processing.

[0047] The flattening processing of step S3 is carried out under a condition that H2 gas, which is a carrier gas, SiH4 gas, which is a Si supply gas, C3H8 gas, which is a C supply gas, and N2 gas, which provides nitrogen atoms as a dopant, are provided in the growth furnace 10, and that a pressure in the growth furnace 10 is adjusted to be equal to or greater than 1×10 3 Pa and equal to or less than 5×10 4Pa, and that the silicon carbide substrate 1 is heated to a temperature equal to or greater than 1550 °C and equal to or less than 1680 °C. A preferred processing time is, for example, equal to or longer than five minutes and equal to or shorter than 50 minutes. The flattening processing is carried out for thirty minutes under a processing condition of 1×10 4 Pa and 1600 °C.

[0048] The processing temperature in the flattening processing of step S3 is lower than the processing temperature in the H2 gas etching processing of step S2, thus an effect of the H2 gas etching of the recess is suppressed.

[0049] When the processing temperature is increased during the flattening processing, energy provided to atoms of the material gas reaching the silicon carbide substrate increases, and migration of the atoms of the dissolved material gas on the surface of the silicon carbide substrate 1 is activated. When the migration is activated, the atoms of the material gas also reach the recessed portion in the surface of the silicon carbide substrate 1, and the effect of flattening the recess increases. Consequently, the flattening processing can be performed in a shorter time, and productivity is increased. Accordingly, the processing temperature in the flattening processing of step S3 is set to be higher than the growth processing temperature in the epitaxial layer growth process of step S4, and is more preferably set to be equal to or higher than 1550°C.

[0050] When the temperature is increased, migration is activated, but etching using H2 gas, which is the carrier gas, is also activated. Therefore, if the temperature is increased too much, the state in which the recess is flattened more efficiently by increasing the temperature during the flattening process does not occur. Accordingly, the processing temperature in the flattening process of step S3 is preferably set equal to or lower than 1680°C.

[0051] When the epitaxial layer growth process of step S4 is carried out after the flattening processing of step S3, the triangular defect occurring due to the recess as the origin can be suppressed compared with the case where the epitaxial layer growth process is carried out without the flattening processing (see<B. Vergleichsbeispiel 1> and<E. Ergebnisbewertung> ).

[0052] There is a possibility that the preferable flattening processing condition during the flattening processing of step S3 described in the present embodiment differs depending on, for example, the condition of H2 gas etching, the crystal state of the silicon carbide substrate 1, or the state of surface unevenness, and the flattening processing condition is not limited to that in the present embodiment. <A-3-3. Epitaxieschichtwachstumsprozess>

[0053] Next, the epitaxial layer growth process of step S4 is performed under the same gas conditions as the flattening processing of step S3, except for the processing temperature and processing time. That is, epitaxial growth is performed on the surface flattened during the flattening processing of step S3, at the same pressure and using the same type of gas as that used in the flattening processing of step S3, to form the silicon carbide epitaxial layer 12.

[0054] The processing temperature in the epitaxial layer growth process of step S4 is set lower than the processing temperature in the flattening processing of step S3, which is carried out to flatten the recess.

[0055] The processing temperature during the epitaxial layer growth process of step S4 is preferably set to be equal to or greater than 1450 °C and equal to or less than 1600 °C.

[0056] When the processing temperature is reduced during the epitaxial layer growth process of step S4, the growth processing of the epitaxial layer is not carried out too quickly. Thus, for example, the defect and unevenness remaining after the recess is flattened in the silicon carbide substrate 1 are hardly transferred to the surface of the silicon carbide epitaxial layer 12, and the occurrence of the triangular defect caused by the defect and unevenness remaining after the flattening processing can be easily suppressed. Therefore, the processing temperature in the epitaxial layer growth process of step S4 is set to be lower than the processing temperature in the flattening processing of step S3, and is preferably set to be equal to or lower than 1600°C.The unevenness remaining after the flattening process is different from the depression that occurs in the track of the latent defect or inclusion in the H2 gas etching process, but reveals a broad unevenness like step bundling.

[0057] It is preferable to increase the temperature to increase the thermal decomposition efficiency of the material gas, increase the epitaxial growth rate, and improve the fluctuation of the carrier concentration within the plane of the silicon carbide epitaxial layer 12. Therefore, the processing temperature in the epitaxial layer growth process of step S4 is preferably set to be equal to or greater than 1450°C.

[0058] In the present embodiment, the epitaxial layer growth process of step S4 is carried out for three hours at a temperature of 1500 °C.

[0059] The present embodiment focuses on a configuration in which continuity is maintained by using the same gas condition as the flattening processing except for the processing temperature as the epitaxial growth condition in step S4, and the gas flow fluctuation in the growth furnace 10 is suppressed as much as possible, thus reducing the influence of dust occurrence as much as possible. However, the epitaxial layer growth condition in step S4 is not limited to that exemplified in the present embodiment. When the processing temperature T2 in the flattening processing process of step S3 and the processing temperature T3 in the epitaxial layer growth process of step S4 satisfy T2>T3, the triangular defect can be suppressed.

[0060] As described above, the method for manufacturing the silicon carbide epitaxial wafer according to the present embodiment includes: the H2 etching process of step S2 for etching the surface of the silicon carbide substrate using the etching gas containing H2; the flattening processing of step S3 for flattening the surface etched in the etching process of step S2 using the gas containing the H2 gas, the SiH4 gas which is the Si supply gas, and the C3H8 gas which is the C supply gas; and the epitaxial layer growth process of step S4 for performing epitaxial growth on the surface flattened during the flattening processing of step S3 using the gas containing the SiH4 gas which is the Si supply gas, and the C3H8 gas which is the C supply gas.The processing temperature T1 in the H2 etching process of step S2, the processing temperature T2 in the flattening process of step S3, and the processing temperature T3 in the epitaxial layer growth process of step S4 satisfy the following conditions: T1>T2>T3. T1>T2 is satisfied, thus the latent defect and the inclusion can be efficiently removed in the H2 etching process of step S2, and the triangular defect caused by the latent defect and inclusion can be suppressed. Furthermore, the recess can be flattened in the flattening process of step S3, and the triangular defect caused by the recess can be suppressed. T2>T3 is satisfied, thus the triangular defect caused by the recess and the triangular defect caused by the defect remaining after the flattening process, as well as the unevenness, can be suppressed.As described above, the method for manufacturing the silicon carbide epitaxial wafer according to the present embodiment is the method for manufacturing the silicon carbide epitaxial wafer capable of suppressing the occurrence of the triangular defect.

[0061] The degree of shallowing of the recess in the shallowing processing of step S3 depends on the degree of migration of the atoms of the material gas, and the degree of migration depends on the temperature. In the present embodiment, the Si supply gas (the first Si supply gas) and the C supply gas (the first C supply gas) used in the shallowing processing of step S3, and the Si supply gas (the second Si supply gas) and the C supply gas (the second C supply gas) used in the epitaxial layer growth process of step S4 are the same Si supply gas and the same C supply gas, but different Si supply gases and different C supply gases may be used.Furthermore, in this case, T2>T3 is satisfied, thus controlling the degree of migration, and suppressing the triangular defect caused by the recess, the triangular defect caused by the defect, and the unevenness remaining after, for example, the flattening processing and the step bundling. The first Si supply gas and the second Si supply gas are the same Si supply gas, and the first C supply gas and the second C supply gas are the same C supply gas. Thus, the gas flow fluctuation in the growth furnace 10 at the time of advancing the process from the flattening processing of step S3 to the epitaxial layer growth process of step S4 can be suppressed, and the occurrence of dust in the growth furnace 10 can be prevented.

[0062] The Si supply gas can be, for example, any of SiH2Cl2, SiHCl3, and SiCl4. For example, hydrocarbon gas such as C2H2 other than C3H8 can be used as the C supply gas. <A-4. Effekt>

[0063] The processing temperature T1 in the H2 etching process of step S2, the processing temperature T2 in the flattening processing of step S3, and the processing temperature T3 in the epitaxial layer growth process of step S4 satisfy T1>T2>T3. As described above, the method for manufacturing the silicon carbide epitaxial wafer according to the present embodiment is the method for manufacturing the silicon carbide epitaxial wafer suitable for suppressing the occurrence of the triangular defect.

[0064] The first Si supply gas and the second Si supply gas are the same Si supply gas, and the first C supply gas and the second C supply gas are the same C supply gas. Accordingly, the gas flow fluctuation in the growth furnace 10 at the time of advancing the process from the flattening processing of step S3 to the epitaxial layer growth process of step S4 can be suppressed, and the occurrence of dust in the growth furnace 10 can be suppressed.

[0065] In the method for manufacturing the silicon carbide epitaxial wafer according to the present embodiment, the processing temperature T1 in the H2 etching process of step S2 is equal to or greater than 1650°C and equal to or less than 1750°C, the processing temperature T2 in the flattening processing of step S3 is equal to or greater than 1550°C and equal to or less than 1680°C, and the processing temperature T3 in the epitaxial layer growth process of step S4 is equal to or greater than 1450°C and equal to or less than 1600°C. According to this condition, the silicon carbide epitaxial wafer in which the triangular defect is suppressed can be manufactured more efficiently. <A-5. Modifikationsbeispiel>

[0066] It is also applicable that the silicon carbide epitaxial layer 12 is formed during the processing up to the epitaxial layer growth process of step S4, and then further epitaxial growth is performed at an elevated processing temperature to form the further epitaxial layer (referred to as silicon carbide epitaxial layer 13) on the surface of the silicon carbide epitaxial layer 12. That is, it is also applicable that the silicon carbide epitaxial layer 13 is formed, or that further epitaxial growth is further performed on the silicon carbide epitaxial layer 13 to form the silicon carbide epitaxial wafer in which the plurality of epitaxial layers are formed on the silicon carbide substrate 1.

[0067] In the epitaxial layer growth process of step S4, the epitaxial layer growth is performed at a temperature lower than a preferable temperature from a growth rate perspective. Consequently, the defect and unevenness remaining after the recess is flattened in the flattening processing of step S3 are hardly transferred to the epitaxial growth. However, the epitaxial layer growth process of step S4 is not preferable from a growth rate perspective. Therefore, from a productivity perspective, it is preferable to increase the processing temperature after the epitaxial layer growth process of step S4 to increase the growth rate.

[0068] That is, the recess is flattened during the flattening processing of step S3, the defect and unevenness remaining after the recess is flattened are reduced in the epitaxial layer growth process of step S4, and subsequently, further epitaxial growth, which is different from the epitaxial layer growth process of step S4, is carried out at the high growth rate, accordingly, the silicon carbide epitaxial wafer in which the triangular defect and unevenness are also reduced can be efficiently manufactured. <B. Vergleichsbeispiel 1>

[0069] In Comparative Example 1, the flattening processing process of step S3 is carried out in the manner shown in the flowchart in Fig. 3 illustrated processing, which in<A-3. Verfahren zur Herstellung eines Siliziumkarbid-Epitaxie-Wafers> is not performed in the embodiment, but steps S1, S2, S4, and S5 are performed in this order to manufacture the silicon carbide epitaxial wafer. The processing conditions of the H2 gas etching process of step S2 and the epitaxial layer growth process of step S4 in the present comparative example are each the same as those in the embodiment. <C. Vergleichsbeispiel 2>

[0070] In a comparative example 2, the flowchart in Fig. 3 illustrated processing, which in<A-3. Verfahren zur Herstellung eines Siliziumkarbid-Epitaxie-Wafers> is carried out in the embodiment while changing the processing temperature in the H2 gas etching process of step S2 to 1600°C, which is the same as the temperature in the flattening processing process of step S3, to manufacture the silicon carbide epitaxial wafer. The other conditions such as a gas flow amount and a pressure other than the processing temperature in the conditions of the H2 gas etching process of step S2 are the same as those of the H2 gas etching process of step S2 in the embodiment. The processing conditions of the flattening processing process of step S3 and the epitaxial layer growth process of step S4 in the present comparative example are respectively the same as those in the embodiment. <C. Vergleichsbeispiel 3>

[0071] In a comparative example 2, the flowchart in Fig. 3 illustrated processing, which in<A-3. Verfahren zur Herstellung eines Siliziumkarbid-Epitaxie-Wafers> is carried out in the embodiment, while changing the processing temperature in the epitaxial layer growth process of step S4 to 1600°C, which is the same as the processing temperature in the flattening processing process of step S3 for manufacturing the silicon carbide epitaxial wafer. Other conditions such as a gas flow rate and a pressure, which differ from the processing temperature in the epitaxial layer growth process conditions of step S2, are the same as those in the embodiment. The processing conditions of the H2 gas etching process of step S2 and the flattening processing process of step S3 in the present comparative example are each the same as those in the embodiment. <E. Ergebnisbewertung>

[0072] Each of the silicon carbide epitaxial wafers manufactured in the embodiment and Comparative Examples 1 to 3 is taken out from the growth furnace 10, and the number of triangular defects on the surface of the epitaxial growth layer (a main surface of the epitaxial growth layer on a side opposite to the silicon carbide substrate 1) of the silicon carbide epitaxial wafer is evaluated using an optical surface defect evaluation device.

[0073] Fig. 4 is a diagram for comparing the number of triangular defects on each surface of the epitaxial growth layer in the embodiment and Comparative Example 1. The plurality of silicon carbide epitaxial wafers are manufactured, and a result of each of the plurality of silicon carbide epitaxial wafers is shown as a point in Fig. 4 for each embodiment and Comparative Example 1. In Fig. 4 are an average of the number of triangular defects on the surface of the epitaxial growth layer of the plurality of silicon carbide epitaxial wafers manufactured in the embodiment and an average of the number of triangular defects on the surface of the epitaxial growth layer of the plurality of silicon carbide epitaxial wafers manufactured in Comparative Example 1, respectively, illustrated by a crossbar. On a vertical axis, the average of the number of triangular defects on the surface of the epitaxial growth layer of the plurality of silicon carbide epitaxial wafers manufactured in the embodiment is scaled to 1.

[0074] As in Fig. 4, in the embodiment, the number of triangular defects is clearly reduced by performing the flattening processing compared to that in Comparative Example 1. In the embodiment, a silicon carbide epitaxial wafer is obtained which has a low defect density in which a triangular defect density is equal to or less than 0.1 pieces / cm 2 is.

[0075] The number of triangular defects in the embodiment is smaller than those in Comparative Examples 2 and 3.

[0076] The processing temperature in the H2 gas etching of step 2 is 1600°C, which is the same as the flattening processing of step S3 in Comparative Example 2. In contrast, the processing temperature in the H2 gas etching of step 2 is higher than 1600°C, which is the same as the flattening processing of step S3 in the embodiment. Therefore, it is considered that the latent defect and the inclusion located in the surface of the silicon carbide substrate 1 can be removed more efficiently, and the triangular defect caused by the latent defect and the inclusion is reduced in the embodiment compared to Comparative Example 2.

[0077] The processing temperature in the epitaxial layer growth process of step S4 is the same as that of the flattening processing of step S3 in Comparative Example 3, and in contrast, the processing temperature in the epitaxial layer growth process of step S4 is lower than that of the flattening processing of step S3 in the embodiment. Therefore, it is considered that in the embodiment, the other defect and the unevenness remaining after the recess is flattened in the flattening processing of step S3 are hardly transferred to the epitaxial growth compared to the case in Comparative Example 3, and the triangular defect caused by the other defect and the unevenness is also reduced.That is, the processing temperature T2 in the flattening processing of step S3 and the processing temperature T3 in the epitaxial layer growth process of step S4 satisfy T2>T3, thus the triangular defect caused by the recess can be sufficiently reduced, and the triangular defect caused by an influencing factor other than the recess can also be reduced.

[0078] Fig. Figure 5 is a graph showing the trend of the reduction effect on a triangle defect in the flattening processing at the time of changing the flattening processing time and the flattening processing temperature. The reduction effect on the triangle defect expresses the degree of reduction of the triangle defect in a case where the flattening processing is performed compared to a case where the flattening processing is not performed. However, the H2 etching process and the epitaxial layer growth process are performed under the same conditions as in the cases where the flattening processing is performed or not performed, and T1>T2>T3 is satisfied.

[0079] Fig.Figure 5 shows that the processing time of the flattening process is reduced as the temperature T2 in the flattening process becomes higher, and in contrast, it is necessary to extend the flattening process when the temperature in the flattening process is low. The reason for this is considered to be that the migration of atoms of the material gas is active when the temperature is high. From an experimental result, it is recognized that the higher reduction effect on the triangle defect can be obtained in a processing time in which a flattening processing time T2 [°C] and a processing time t [minutes] satisfy T2≧-34.1In(t)+1687. A temperature T2 which is outside a range of the flattening processing temperature equal to or greater than 1550 °C and equal to or less than 1680 °C, which is in the <A-3-2.Process of flattening processing> is preferred, furthermore, has the processing time t, which satisfies T2 ≧ -34.1 In(t) + 1687. However, as in the<A-3-2. Prozess des Abflachprozessierung> described, it is more preferable that T2 is equal to or greater than 1550 °C and equal to or less than 1680 °C.

[0080] Each embodiment may be combined as desired, or each embodiment may be varied or omitted as appropriate.

Claims

[1] A method for producing a silicon carbide epitaxial wafer (20), comprising: - an etching process for etching a surface of a silicon carbide substrate (1) at a first temperature using an etching gas comprising H2, wherein the silicon carbide substrate (1) has an angular offset inclined with respect to the (0001) plane in the <11-20> direction at an angle of approximately 5 degrees; - a process for flattening the surface etched during the etching process at a second temperature using a gas comprising H2 gas, a first Si supply gas, and a first C supply gas; and - an epitaxial layer growth process for performing epitaxial growth on the surface flattened during the flattening processing process at a third temperature using a gas comprising a second Si supply gas and a second C supply gas, wherein: - the first temperature T1, the second temperature T2, and the third temperature T3, T1 > T2>T3, - the first temperature T1 is equal to or greater than 1650 °C and equal to or less than 1750 °C, - the second temperature T2 is equal to or greater than 1550 °C and equal to or less than 1680 °C, and - the third temperature T3 is equal to or greater than 1450 °C and equal to or less than 1600 °C. [2] The method of claim 1, wherein: - the first Si supply gas and the second Si supply gas are an identical Si supply gas, and - the first C supply gas and the second C supply gas are an identical C supply gas. [3] A method according to any one of the preceding claims, wherein: - the first Si supply gas is SiH4 gas, and - the first C supply gas is C3H8 gas. [4] Method according to one of the preceding claims, wherein the second temperature T2 and a processing time t of the flattening processing process satisfy T2 / °C ≧ - 34.1 In(t / minutes) + 1687. [5] A method according to any one of the preceding claims, wherein a silicon carbide epitaxial wafer (20) having a triangular defect density equal to or less than 0.1 pieces / cm 2 is manufactured. [6] A method according to any one of the preceding claims, wherein a recess formed in the etching process by etching a latent defect or an inclusion in the silicon carbide epitaxial wafer (20) prior to the etching process is flattened in the flattening process. [7] A method according to any one of the preceding claims, wherein the flattening processing process is a process of performing epitaxial growth.

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