Integrated circuit structure with avalanche transition to a doped semiconductor over a semiconductor well

Abstract

Integrated circuit structure (120) comprising: a doped well (124) in a semiconductor substrate (122), the doped well (124) comprising a first dopant type; a base region (130) within the doped well (124) and containing the first dopant type; an emitter region (136) within the doped well (124) and having a second dopant type oriented opposite to the first dopant type; a first insulator (140) within the doped well (124) located horizontally between the base region (130) and the emitter region (136); a collector region (142) within the doped well (124) and containing the second dopant type; a second insulator (146) within the doped well (124), horizontally between the collector region (142) and the emitter region (136); an insulating material (152) within the doped well (124), the insulating material (152) having a first end (S1) horizontally adjacent to the collector region (142) and a second end (S2) opposite the first end (S1); and a doped semiconductor region (154) within the doped well (124) adjacent to the second end (S2) of the insulating material (152), the doped semiconductor region (154) being of the first dopant type such that an avalanche transition (150) is defined between the collector region (142) and the doped semiconductor region (154) along the doped well (124).

Description

Technical field

[0001] Embodiments of the invention generally relate to integrated circuit (IC) structures. In particular, various embodiments of the invention provide an IC structure with an avalanche junction to a doped semiconductor over a semiconductor well. background

[0002] Integrated circuits (ICs) may incorporate elements to protect the device hardware against electrostatic discharge (ESD) voltages that can cause electrical shorts, dielectric breakdown, and / or other failure modes. Ideally, ESD devices do not affect device operation until an ESD event is detected by a pin on an IC, where the ESD event acts as a trigger voltage that turns on the ESD devices and discharges current through the ESD device to power or ground rails. ESD devices can be designed to adjust their trigger voltages to allow input voltages higher than the supply voltage without excessive leakage through the ESD devices at elevated voltages.As ICs become smaller and their scaling decreases, lower trigger voltages may be required to meet device manufacturing specifications. However, conventional approaches to reducing the trigger voltage can have the undesirable effect of increasing the ESD element's hold voltage, particularly the voltage level to which the device returns after the ESD element ceases to operate. Conventional ESD element configurations and / or other structures have been unable to deliver lower trigger voltages while maintaining or also reducing the hold voltages.

[0003] From document US 9 214 540 B2 an n-type metal oxide semiconductor transistor or NMOS for electrostatic discharge (ESD) is known. This NMOS includes a first region including a p-type well (PW) region, a first native NMOS block implant (NTN) region, and a second NTN region, a first n-type plus (NP) region over at least a portion of the first NTN region, a first p-type plus (PP) region over at least a portion of the first NTN region or the PW region, a dummy gate stack between the first NP region and the first PP region, a second NP region over at least a portion of the PW region, a second PP region over at least a portion of the second NTN region, a shallow trench isolation (STI) region over at least a portion of the PW region or the second NTN region, and a gate stack over at least a portion of the PW region.The first PP region is between the first NP region and the second NP region, the second NP region is between the first PP region and the second PP region, and the STI region is between the second NP region and the second PP region.

[0004] US Pat. No. 7,323,752 B2 describes an electrostatic discharge (ESD) protection circuit. This ESD circuit consists of at least one MOS transistor coupled to a pad of an integrated circuit to divert an ESD current from the pad during an ESD event, a substrate having a contact region, at least one floating diffusion region formed in the substrate between the MOS transistor and the substrate contact region, wherein the contact region and the at least one floating diffusion region have the same dopant type, and a first insulation structure and a second insulation structure arranged between the MOS transistor and the substrate contact region, wherein the at least one floating diffusion region is in direct contact with the first insulation structure and the second insulation structure.

[0005] US Pat. No. 7,973,386 B1 discloses a bipolar NPN device with controllable breakdown voltage, comprising a bipolar device including an n+ polysilicon emitter, a p-type base, and a collector with a subcollector. The subcollector includes an n-type sink arranged to partially overlap the p-type base to form a pn junction with a resurfacing or lightly doped region defining a finger. The n-type sink overlaps the p-type base to define an intrinsic Zener diode junction. Summary

[0006] Aspects of the present invention provide an integrated circuit (IC) structure comprising: a doped well in a semiconductor substrate, the doped well having a first dopant type; a base region within the doped well and having the first dopant type; an emitter region within the doped well and having a second dopant type oriented opposite to the first dopant type; a first insulator within the doped well, horizontally between the base region and the emitter region; a collector region within the doped well and having the second dopant type; a second insulator within the doped well, horizontally between the collector region and the emitter region; an insulating material within the doped well, the insulating material having a first end horizontally adjacent to the collector region and a second end opposite the first end;and a doped semiconductor region within the doped well adjacent the second end of the insulating material, the doped semiconductor region being of the first dopant type such that an avalanche transition is defined between the collector region and the doped semiconductor region along the doped well;

[0007] Further aspects of the present invention provide an integrated circuit (IC) structure comprising: a first doped well in a semiconductor substrate and having a first dopant type; a base region within the first doped well and having the first dopant type; a second doped well having a first end adjacent to the first doped well and a second end opposite the first end, the second doped well having a second dopant type oriented opposite to the first dopant type; a first insulator within the first doped well, horizontally between the base region and the second doped well; a third doped well adjacent to the second end of the second doped well, the third doped well having the first dopant type; an emitter region within the third doped well and having the second dopant type;a second insulator within the third doped well, horizontally between the emitter region and the second doped well; a collector region within the third doped well, comprising the second dopant type; a third insulator within the third doped well, horizontally between the emitter region and the second doped well; an insulating material within the third doped well, the insulating material having a first end horizontally adjacent to the collector region and a second end opposite the first end; and a doped semiconductor region within the third doped well adjacent to the second end of the insulating material, the doped semiconductor region being of the first dopant type, such that an avalanche transition is defined between the collector region and the doped semiconductor region along the doped well.

[0008] Another aspect of the present invention provides an integrated circuit (IC) structure comprising: a first doped well in a semiconductor substrate and having a first dopant type; a second doped well within the first doped well, the second doped well having a second dopant type oriented opposite to the first dopant type, a top surface of the second doped well being coplanar with a top surface of the first doped well; a third doped well within the first doped well and having the first dopant type, a top surface of the third doped well being coplanar with the top surface of the second doped well; a base region within the third doped well and having the first dopant type;a collector terminal within the third doped well and laterally separated from the base region by a first insulator, the collector terminal comprising a first pair of oppositely doped semiconductor regions separated by a first insulating material within the third doped well such that a first avalanche transition is defined between the first pair of oppositely doped semiconductor regions; and an emitter terminal within the third doped well and laterally separated from the collector terminal by a second insulator, the emitter terminal comprising a second pair of oppositely doped semiconductor regions separated by a second insulating material within the third doped well such that a second avalanche transition is defined between the second pair of oppositely doped semiconductor regions. Short description of the drawings

[0009] These and other features of this invention will be more readily understood from the detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings which illustrate various embodiments of the invention, in which: Fig. 1 shows a schematic view of active elements of an integrated circuit (IC) structure connected via electrostatic discharge (ESD) elements according to embodiments of the invention. Fig. 2 shows a cross-sectional view of an IC structure according to embodiments of the invention. Fig. 3 shows a cross-section through an IC structure according to further embodiments of the invention. Fig. 4 shows a cross-sectional view of an IC structure according to still further embodiments of the invention.

[0010] The drawings of the invention are not necessarily to scale. The drawings are intended to illustrate typical aspects of the invention and are therefore not to be considered limiting of the invention. In the drawings, like reference numerals represent like elements throughout the drawings. Detailed description

[0011] In this description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration certain exemplary embodiments in which the present teachings may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to utilize the present teachings, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the spirit and scope of the invention. This description, therefore, is merely illustrative.

[0012] Embodiments of the invention provide an integrated circuit (IC) structure having an avalanche junction to a doped semiconductor region above a semiconductor well. In some cases, embodiments of the invention may provide an electrostatic discharge (ESD) device in which the avalanche junction provides a bidirectional current path to provide a lower trigger voltage while maintaining substantially the same withstand voltage compared to conventional ESD devices. According to one example, embodiments of the invention may include a doped well in a semiconductor substrate and a base region in the doped well. The base region and the doped well may have the same dopant type.An emitter region of a second dopant type, oriented opposite to the first dopant type, may be located in the semiconductor well and separated from the base region by a first insulator. A second insulator in the doped well may separate the emitter region from a collector region comprising the second dopant type. An insulating material adjacent to the collector region may separate the collector region from a doped semiconductor region. A portion of the doped well below the insulating material, also between the collector and the doped semiconductor region, may provide a diode in the form of an avalanche junction for bidirectional control of the current through the IC structure. Voltages applied to the avalanche junction may influence whether current can flow between the emitter and the collector.

[0013] A diode is a two-terminal device that behaves differently than conducting or insulating materials between two electrical contact points. Specifically, a diode offers high conductivity from one contact to the other in one direction (i.e., the "forward" direction), but little or no conductivity in the opposite direction (i.e., the "reverse" direction). In the case of a PN junction, the orientation of a diode's forward and reverse conduction can depend on the type and magnitude of the voltage applied to the material composition of one or both terminals, which affects the magnitude of the potential barrier. In the case of a junction between two semiconductor materials, the potential barrier forms along the interface between the two semiconductor materials.

[0014] Embodiments of the invention utilize the unique properties of an "avalanche junction," also referred to as an "avalanche diode," to enable bidirectional control of current flow through the IC structure. Avalanche junctions differ from PN diodes in that they have a conductive material adjacent to an insulating material between two terminals. In various implementations, the materials can be sized and arranged to substantially prevent any current flow between the two terminals. Applying an electrical voltage to the materials can accelerate minority charge carriers in the insulating material to an extent that creates ionization in a crystal lattice. The accelerated minority charge carriers, in turn, create more charge carriers and more electrical ionization. This effect is referred to as "avalanche breakdown."In this scenario, an electrical path can form in both directions from one terminal to the other. Avalanche diodes differ from other diodes, for example, in that they provide a voltage drop across the two terminals that is constant and independent of the amount of current flowing through them. Embodiments of the invention exploit these properties to provide electrical protection features (e.g., ESD elements) in a device structure.

[0015] With reference to Fig. 1 is a schematic view of a device 100 according to embodiments of the invention. The device 100 represents an exemplary configuration in which embodiments of an IC structure, as further explained with reference to other drawings, may be employed. The device 100 is configured to respond to excess charges and currents resulting from an ESD event by preventing current flow into active components (e.g., internal circuitry 102) of the device 100. An input / output (I / O) pad 104 may electrically couple an input voltage and / or signal to the internal circuitry 102 via any form of wiring. The excess charge generated by an ESD event may be transferred to the device 100 via the I / O pad 104. A supply terminal 106 may be configured to short such excess charges from the power supply to ground.The supply terminal 106 may be implemented in the form of any conceivable transistor element (e.g., a field-effect transistor (FET) or a bipolar transistor (BJT)). A set of voltage nodes 108 (generally referred to as "VDD" for a supply rail or "VSS" for a ground rail, respectively) may provide a voltage (e.g., from a battery or other device driving the device 100) to operate the supply terminal 106. It should be understood that the designations "VDD" and "VSS" for supply and ground rails may be interchanged in further embodiments. The supply terminal 106 is not designed to operate under non-ESD conditions with voltage fluctuations. In particular, the supply terminal 106 remains inactive during power-on and power-off operations, where voltages may fluctuate. The supply terminal 106 selectively allows current flow upon detection of an ESD event.

[0016] A set of ESD elements 110 may be coupled between the internal circuitry 102 and the power supply / supply terminal (hereinafter simply "supply terminal") 106 to activate the supply terminal 106 during an ESD event. The ESD element(s) 110 may prevent current flow from the I / O pad 104 to the supply terminal 106 until a trigger voltage is applied to the corresponding terminal of the ESD element(s) 110. In various other examples, additional circuitry and / or current paths may be arranged between the I / O pad 104 and the ESD element(s) 110, or between the ESD element(s) 110 and the supply terminal 106, to further control the conduction of current to the supply terminal 106 during an ESD event.

[0017] With reference to Fig. 2, embodiments of the invention include an integrated circuit (IC) structure 120 capable of including one or more ESD elements 110 ( Fig. 1) or to otherwise implement similar functions. The IC structure 120 may be formed from a substrate 122, for example, comprising one or more semiconductor materials. The substrate 122 may comprise any currently known or later developed semiconductor material, which may include, without limitation, silicon, germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition represented by the formula Al X1 Ga X2 In X3 Ace Y1 P Y2 N Y3 Sb Y4, where X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions, each greater than or equal to zero, and X1+X2+X3+Y1+Y2+Y3+Y4=1 (where 1 is the total relative molar amount). Other suitable substrates include II-VI compound semiconductors having a composition Zn A1 CD A2 See B1 The B2 , where A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1+A2+B1+B2=1 (where 1 is a total molar amount). The entirety of the substrate 122 or a portion thereof may be subjected to mechanical stress.

[0018] Portions of the substrate 122 may include dopants, thus providing a first doped well 124 with a first dopant type. According to one example, the first dopant type may be a P-type dopant. When referring to dopants, P-type dopants refer to elements that are introduced into the semiconductor material to create free holes by "accepting" electrons from a semiconductor atom and consequently "releasing" the hole. The acceptor atom must have one fewer valence electron than the host semiconductor. P-type dopants suitable for use in the substrate 122 include, among others: boron (B), indium (In), and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Other alternatives are In and Ga. Ga exhibits high diffusivity in silicon dioxide (SiO2), therefore, the oxide cannot be used as a mask in Ga diffusion.The first doped well 124 may be formed within the substrate 122, e.g., by vertical ion implantation, such that a top surface of the first doped well 124 is aligned with and thus shared with the top surface of the substrate 122. Although the first doped well 124 may have the same dopant type as the substrate 122, the first doped well 124 may have a higher or lower dopant concentration than the substrate 122. The first doped well 124 may therefore differ from the substrate 122 at least in part due to its dopant concentration, dopant materials, etc., even if the first doped well 124 and the substrate 122 are of the same dopant type. The substrate 122 may have other doped wells with the same or a different dopant type, and such wells are shown in FIG. Fig. 2 only for clarity. It is also understood that the first doped well 124 may be disposed within and / or along a guard ring (not shown) to isolate the first doped well 124 from other parts of the device 100 ( Fig. 1) to separate and insulate. Such guard rings may, for example, be in the form of oppositely doped regions of a semiconductor material that border and / or surround the first doped well 124.

[0019] The IC structure 120 may be configured to direct current flow from a "collector" terminal to an "emitter" terminal and may therefore include the same or a similar arrangement of doped semiconductor materials as in a bipolar junction transistor (BJT) architecture within the first doped well 124. However, the IC structure 120 is not configured to operate like a standard forward-biased transistor (e.g., BJT) because two terminals are coupled to ground, as mentioned herein. The IC structure 120 may therefore include a base region 130 within the first doped well 124. The base region 130 may include the same dopant type (e.g., a p-type dopant) as the first doped well 124 and may also be disposed at the top surface of the first doped well 124. The base region 130 may have a higher dopant concentration than the first doped well 124 and is therefore in Fig. 2 by different cross-hatching. The base region 130 may be electrically coupled to ground ("GND / VSS") via a first contact 132 formed from a conductive material (e.g., one or more metals formed by deposition, patterning, and / or other processes) on the base region 130.

[0020] The IC structure 120 may further include an emitter region 136 within the first doped well 124. The emitter region 136 may have a second dopant type oriented opposite to the dopant type of the first doped well 124 and the base region 130 (e.g., an N-type doping). The emitter region 136 may be formed by implanting N-type dopants into the substrate 122 and / or the precursor semiconductor material by any currently known or later developed technique, e.g., by ion implantation. N-type dopants are elements introduced into semiconductor materials to create free electrons, e.g., by "donating" an electron to the semiconductor. N-type dopants must have one more valence electron than the semiconductor. Common N-type donors in silicon (Si) include, for example, E.g. phosphorus (P), arsenic (As) and / or antimony (Sb).A second contact 138, which may be formed from any conductive material (e.g., one or more metals formed by deposition, patterning, and / or other processes), is formed on the emitter region 136. The second contact 138 may electrically couple the emitter region 136 to ground GND / VSS, similar to the connection provided by the first contact 132.

[0021] A first insulator 140 may be disposed horizontally between the base region 130 and the emitter region 136 within the first doped well 124 to physically and electrically separate the base region 130 from the emitter region 136. The first insulator 140 may comprise any conceivable insulating material, such as, for example, Examples of materials include, but are not limited to, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boron phosphosilicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) having atoms of silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H), thermosetting polyarylene ethers, SiLK (a polyarylene ether available from Dow Chemical Corporation), a silicon-carbon-containing polymer material available from JSR Corporation, another low dielectric constant (< 3.9) material, or layers thereof.In one example, the first insulator 140 may take the form of a shallow trench isolation (STI) within the first doped well 124. An STI is an insulating structure formed by etching a trench into the semiconductor material (e.g., the first doped well 124) and filling the trench with an insulating material such as an oxide and / or another insulator discussed herein. An STI may be used to isolate a region of the first doped well 124 from a neighboring region, e.g., to isolate the base region 130 from the emitter region 136 as shown. Portions of the first insulator 140 may also be disposed, e.g., adjacent the opposite horizontal end of the base region 130, to further isolate the base region 130 from other materials within the doped well 124.

[0022] The IC structure 120 includes a collector region 142 within the first doped well 124. The collector region 142 has the second dopant type (e.g., N-doped) within the first doped well 124, but is separated from the base region 130 and the emitter region 136. A collector contact 144 having a conductive material similar to or different from the contact(s) 132, 138 may be located on the collector region 142 to connect the collector region 142 to one or more active elements of the device 100 ( Fig. 1), e.g., the internal circuit 102. A second insulator 146 may be located horizontally between the emitter region 136 and the collector region 142 within the first doped well 124. The second insulator 146 may be formed of the same or a similar insulating material as the first insulator 140 and, in some cases, may be an STI, as described elsewhere herein.

[0023] To control whether electrical currents can flow from an active element such as the internal circuitry 102 to ground GND / VSS through the IC structure 120, additional elements may form an avalanche junction 150 with the collector region 142. For example, the IC structure 120 may include an insulating material 152 within the first doped well 124, with a first horizontal end S1 adjacent to the collector region 142. The insulating material 152 may be formed from any conceivable insulating material and, in particular, may include one or more layers of a nitride material on the first doped well 124. In some cases, the insulating material 152 may take the form of a "silicide-blocking insulator" or "SAB" material. Such materials may include, for example, silicon nitride insulators and / or lesser silicon oxide insulators.The insulating material 152 may be formed using any technique known today or later developed for forming an insulator on a doped semiconductor material (e.g., combinations of etching and deposition, selectively and / or non-selectively). A second end S2 of the insulating material 152 may be adjacent to a doped semiconductor region 154 within the first doped well 124. The doped semiconductor region 154 may have the first dopant type (i.e., the same dopant type as the first doped well 124 and the base region 130). The first doped well 124, in an exemplary embodiment, may be a continuous doped semiconductor region beneath each of the base region 130, emitter region 136, collector region 142, and doped semiconductor region 154.

[0024] The insulating material 152 may have a depth within the first doped well 124 that is significantly less than the depth of the collector region 142, or the insulating material 152 may be a thin layer deposited over the surface of the first doped well 124. In particular, the insulating material 152 may be as thin as possible to avoid mechanical stresses and other undesirable effects beneath the material. The presence of an insulating material on the first doped well 124, as well as between the collector region 142 and the insulating material 152, may provide an avalanche junction 150 to create a bidirectional diode junction within the IC structure 120. As described elsewhere, applying a trigger voltage to the collector region 142 may selectively enable current flow across the avalanche junction 150.To electrically couple the doped semiconductor region 154 to a second active element (e.g., the supply terminal 106 in one example), a fourth contact 156 may be formed on the doped semiconductor region 154. The fourth contact 156 may be formed from the same or a similar conductive material as the contacts 132, 138, 144, or from another currently known or later developed conductive material.

[0025] In this embodiment, an electric current from the internal circuit 102 ( Fig. 1) flow through the IC structure 120 to ground GND / VSS. During operation, a trigger voltage, e.g., that of an ESD event, may be applied to the collector region 142 and / or the doped semiconductor region 154. Such a voltage may enable current to flow across the avalanche junction 150, electrically coupling two active elements (e.g., the internal circuitry 102 and the supply terminal 106) through the IC structure 120. The IC structure 120 may therefore conduct excessive currents to ground GND / VSS via the emitter region 136 and the collector region 142 in response to an ESD event. During operation, the IC structure 120 may be configured to have a trigger voltage of no more than approximately 11.0 volts (V), while having a holding voltage of no more than approximately5.0 V, whereby these trigger voltages and holding voltages can have large ranges depending on doping profiles, often between 5 V and 200 V in silicon-based devices.

[0026] With reference to Fig. 3, further embodiments of the invention may include additional elements, e.g., to change the trigger voltage and thus the sensitivity of the IC structure 120 to ESD events. The IC structure 120 may include a substrate 122 with various regions (e.g., a first doped well 124, a base region 130, an emitter region 136, a collector region 142, an avalanche junction 150, an insulating material 152, a doped semiconductor region 154, etc.) thereover, as described for other implementations of the IC structure 120. Here, a second doped well 160 may be disposed adjacent to the first doped well 124. The base region 130 and the first insulator(s) 140 may be formed in the first doped well 124, and the second doped well 160 separates these elements from other portions of the IC structure 120. The second doped well 160 may comprise the second dopant type (ie,N-doping in the case that the first doped well 124 is P-doped, or vice versa). Although in . Fig. 3, the second doped well may alternatively have various additional doped regions (e.g., N+ regions) formed therein and / or may also be connected to one of the internal circuits 102, the supply terminal 106, GND / VSS, a power supply rail (not shown), etc.

[0027] The second doped well 160 may be free of additional semiconductor regions and / or terminals therein, and in particular, may not include a base region 130, emitter region 136, collector region 142, and / or doped semiconductor region 154 therein. A first end T1 of the second doped well 160 may be disposed adjacent to the first doped well 124, and a second end T2 of the second doped well 160 may be disposed adjacent to a third doped well 162. The third doped well 162 may include the first dopant type (e.g., the same dopant type as the first doped well 124). In this embodiment, each of the emitter region 136, collector region 142, second insulator 146, insulating material 152, and doped semiconductor region 154 may be formed exclusively in the third doped well 162, rather than in the first doped well 124 or the second doped well 160.

[0028] For example, the third doped well 162 may include a second insulator 146 horizontally between the emitter region 136 and the second doped well 160, in addition to a third insulator 164 horizontally between the emitter region 136 and the collector region 142. The IC structure 120 in such a configuration may function substantially identically to other implementations discussed herein, but may have different trigger and / or holding voltages. Such differences may result from the additional electrical isolation between the base region 130 and the region(s) 136, 142 by the second doped well 160. In one example, the IC structure 120 coupled to the internal circuitry 102 and the supply terminal 106 may have a trigger voltage of at most about 9.5 V and a hold voltage of at most about 5.0 V, based on the presence and size of the second doped well 160.

[0029] With regard to Fig. 4, further embodiments of the IC structure 120 may include rearranging and / or reshaping the doped recesses 124, 160, changing the number of insulating materials 152, and / or other modifications with respect to other implementations of the IC structure 120. In such an example, the first doped well 124 may not include a base region 130 and / or other doped regions such as the emitter region 136, the collector region 142, the insulating material 152, and / or the doped semiconductor material(s) 154. However, the first doped well 124 may include at least one external doped semiconductor material 170, so named because it is located outside the third doped well 162 and connected to ground GND / VSS via a fourth contact 172 formed from any currently known or later developed conductive material.The second doped well 160 may be formed entirely within the first doped well 124, while the third doped well 162 may be formed entirely within the second doped well 160. Such an arrangement of doped wells 124, 160, 162 is known as a "triple-well" configuration. The various other regions and / or materials of the IC structure 120 may be formed exclusively within and / or on the third doped well 162.

[0030] The IC structure 120 may have multiple avalanche transitions (e.g., in the example of Fig. 4), in contrast to other implementations with only one avalanche transition 150 (e.g. as in Fig. 2, Fig. 3). For example, an avalanche junction 150 may be located between the collector region 142 and the doped semiconductor region 154, substantially as contemplated in other implementations. Together, the collector region 142 and the doped semiconductor region 154 form a pair of oppositely doped semiconductor regions with insulating material 152 therebetween, thereby defining an avalanche junction 150. The IC structure 120 may also include, for example, another region of insulating material 152 in a third doped well 162 between a doped semiconductor region 154 and the emitter region 136. The emitter region 136 and the doped semiconductor region 154 thus form another pair of oppositely doped semiconductor regions. Here, an active element (e.g., the supply terminal 106) may be electrically coupled to each of the emitter regions 136 and doped semiconductor regions 154 via one or more third contacts 156.The IC structure 120 may otherwise remain similar to other implementations. The IC structure 120 may include a first insulator 140 to electrically separate the base region 130 from other materials. Although in . Fig. 4, additional portions of the first insulator 140 and the base region 130 may be formed on the third doped well 162 (e.g., on the left and right sides adjacent to the second doped well 160 in a mirrored arrangement). The second insulator 146 may electrically isolate the emitter region 136 and the doped semiconductor region 154 of an avalanche junction 150 from other materials. The third insulator 164 may electrically isolate the collector region 142 and the doped semiconductor region 154 from other materials in the third doped well 162. During operation, such embodiments of the IC structure 120 may have a trigger voltage of at most, e.g., about 9.5 V and a holding voltage of about 5.0 V.

[0031] Embodiments of the invention may provide several technical and commercial advantages, some of which are described herein by way of example. For example, embodiments of the IC structure 120 provide a structure that can be used as an ESD element (e.g., ESD element(s) 110 ( Fig.1)) can operate with reduced trigger voltages, but with similar holding voltages as other types of ESD elements without avalanche junction(s) 150 therein. In some cases, placing a doped well contact outside of an N-well (e.g., an N-well ring or intermediate well) will increase the internal resistance of the IC structure 120, thereby further reducing the trigger voltage. The inclusion of the avalanche junction 150 also enables bipolar current flow through the IC structure 120, making it suitable for combating multiple types of ESD events and / or operational settings. Compared to conventional ESD elements and / or operationally similar IC structures, embodiments of the IC structure 120 occupy a similar area in a device such as the device 100.

Claims

[1] Integrated circuit structure (120) comprising: a doped well (124) in a semiconductor substrate (122), the doped well (124) comprising a first dopant type; a base region (130) within the doped well (124) and containing the first dopant type; an emitter region (136) within the doped well (124) and having a second dopant type oriented opposite to the first dopant type; a first insulator (140) within the doped well (124) located horizontally between the base region (130) and the emitter region (136); a collector region (142) within the doped well (124) and containing the second dopant type; a second insulator (146) within the doped well (124), horizontally between the collector region (142) and the emitter region (136); an insulating material (152) within the doped well (124), the insulating material (152) having a first end (S1) horizontally adjacent to the collector region (142) and a second end (S2) opposite the first end (S1); and a doped semiconductor region (154) within the doped well (124) adjacent to the second end (S2) of the insulating material (152), the doped semiconductor region (154) being of the first dopant type such that an avalanche transition (150) is defined between the collector region (142) and the doped semiconductor region (154) along the doped well (124). [2] The integrated circuit structure (120) of claim 1, wherein the insulating material (152) comprises a nitride having a depth below a top surface of the doped well (124) that is less than a depth of the collector region (142) and a depth of the doped semiconductor region (154) below a top surface of the doped well (124). [3] The integrated circuit structure (120) of claim 1, further comprising: a first contact (132) to the collector region (142); and a second contact (138) to the doped semiconductor region (154), wherein the base region (130) and the emitter region (136) are each coupled to ground. [4] The integrated circuit structure (120) of claim 3, further comprising: a first active element (102) coupled to the collector region (142) via the first contact (132); and a second active element (106) coupled to the doped semiconductor region (154) via the second contact (138), wherein the integrated circuit structure (120) is an electrostatic discharge element (110) between the first active element (102) and the second active element (106). [5] The integrated circuit structure (120) of claim 4, wherein a trigger voltage of the electrostatic discharge element (110) is at most about 11.0 volts. [6] The integrated circuit structure (120) of claim 5, wherein a holding voltage of the electrostatic discharge element (110) is at most about 5.0 volts. [7] The integrated circuit structure (120) of claim 1, wherein both the first insulator (140) and the second insulator (146) comprise shallow trench isolation regions within the doped well (124). [8] The integrated circuit structure (120) of claim 1, wherein the doped well (124) is a continuous doped semiconductor region (154) beneath the base region (130), the emitter region (136), the collector region (142), the insulating material (152), and the doped semiconductor region (154). [9] Integrated circuit structure (120) comprising: a first doped well (124) in a semiconductor substrate (122) and having a first dopant type; a base region (130) within the first doped well (124) and comprising the first dopant type; a second doped well (160) having a first end (T1) adjacent to the first doped well (124) and a second end (T2) opposite the first end (T1), the second doped well (160) having a second dopant type opposite to the first dopant type; a first insulator (140) within the first doped well (124), horizontally between the base region (130) and the second doped well (160); a third doped well (162) adjacent the second end (T2) of the second doped well (160), the third doped well (162) comprising the first dopant type; an emitter region (136) within the third doped well (162), the emitter region (136) comprising the second dopant type; a second insulator (146) within the third doped well (162) located horizontally between the emitter region (136) and the second doped well (160); a collector region (142) within the third doped well (162) and comprising the second dopant type; a third insulator (164) within the third doped well (162), horizontally between the emitter region (136) and the collector region (142); an insulating material (152) within the third doped well (162), the insulating material (152) having a first end (S1) horizontally adjacent to the collector region (142) and a second end (S2) opposite the first end (S1); and a doped semiconductor region (154) within the third doped well (162) adjacent to the second end (S2) of the insulating material (152), the doped semiconductor region (154) being of the first dopant type such that an avalanche transition (150) is defined between the collector region (142) and the doped semiconductor region (154) along the doped well (124). [10] The integrated circuit structure (120) of claim 9, further comprising: a first contact (132) to the collector region (142); and a second contact (138) to the doped semiconductor region (154), wherein the base region (130) and the emitter region (136) are each coupled to ground. [11] The integrated circuit structure (120) of claim 10, further comprising: a first active element (102) coupled to the collector region (142) via the first contact (132); and a second active element (106) coupled to the doped semiconductor region (154) via the second contact (138); wherein the IC structure is an electrostatic discharge element (110) between the first active element (102) and the second active element (106). [12] The integrated circuit structure (120) of claim 11, wherein a trigger voltage of the electrostatic discharge element (110) is at most about 9.5 volts, and wherein a hold voltage of the electrostatic discharge element (110) is at most about 5.0 volts. [13] The integrated circuit structure (120) of claim 9, wherein the insulating material (152) comprises a nitride having a depth below a top surface of the third doped well (162) that is less than a depth of the collector region (142) and a depth of the doped semiconductor region (154) below a top surface of the third doped well (162). [14] The integrated circuit structure (120) of claim 9, wherein the first insulator (140) has a first shallow trench isolation within the first doped well (124), and wherein the second insulator (146) and the third insulator (164) each have shallow trench isolations within the third doped well (162). [15] Integrated circuit structure (120) comprising: a first doped well (124) in a semiconductor substrate (122) and having a first dopant type; a second doped well (160) within the first doped well (124), the second doped well (160) having a second dopant type oriented opposite to the first dopant type, a top surface of the second doped well (160) being coplanar with a top surface of the first doped well (124); a third doped well (162) within the first doped well (124) and having the first dopant type, wherein a top surface of the third doped well (162) is coplanar with the top surface of the second doped well (160); a base region (130) within the third doped well (162) and having the first dopant type; a collector terminal within the third doped well (162) and laterally separated from the base region (130) by a first insulator (140), the collector terminal comprising a first pair of oppositely doped semiconductor regions separated by a first insulating material (152) within the third doped well (162) such that a first avalanche transition (150) is defined between the first pair of oppositely doped semiconductor regions; and an emitter terminal within the third doped well (162) and laterally separated from the collector terminal by a second insulator (146), the emitter terminal comprising a second pair of oppositely doped semiconductor regions separated by a second insulating material within the third doped well (162) such that a second avalanche transition (150) is defined between the second pair of oppositely doped semiconductor regions. [16] The integrated circuit structure (120) of claim 15, further comprising: a first contact (132) coupling the base region (130) to ground; a second contact (138) coupling the emitter terminal to ground; a third contact (144) to the collector terminal; and a fourth contact (156) coupling the first doped well (124) to ground. [17] The integrated circuit structure (120) of claim 15, further comprising: a first active element (102) coupled to one of the pairs of oppositely doped semiconductor regions of the collector terminal; and a second active element (106) coupled to the other of the pairs of oppositely doped semiconductor regions of the collector terminal, wherein the IC structure is an electrostatic discharge element (110) between the first active element (102) and the second active element (106). [18] The integrated circuit structure (120) of claim 15, wherein a trigger voltage of the electrostatic discharge element (110) is at most about 9.5 volts and wherein a hold voltage of the electrostatic discharge element (110) is at most about 5.0 volts. [19] The integrated circuit structure (120) of claim 15, wherein the first insulating material (152) comprises a first nitride having a depth below a top surface of the third doped well (162) that is less than a depth of the first pair of oppositely doped semiconductor regions below the top surface of the third doped well (162), and wherein the second insulating material comprises a second nitride having a depth below the top surface of the third doped well (162) that is less than a depth of the second pair of oppositely doped semiconductor regions below the top surface of the third doped well (162). [20] The integrated circuit structure (120) of claim 15, wherein the first insulator (140) comprises a first shallow trench isolation () within the third doped well (162), and wherein the second insulator (146) comprises a second shallow trench isolation within the third doped well (162).

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