Semiconductor device

Abstract

Semiconductor device comprising: - a semiconductor substrate (1) having a first and a second principal surface facing each other; - a first semiconductor layer (2) of a first conductivity type, provided between the first principal surface and the second principal surface of the semiconductor substrate (1); - a second semiconductor layer (3) of a second conductivity type, provided between the first semiconductor layer (2) and the first principal surface; - a plurality of third semiconductor layers (4) of a first conductivity type, selectively provided on a surface of the second semiconductor layer (3); - a fourth semiconductor layer (5) of a second conductivity type, provided between the first semiconductor layer (2) and the second principal surface; - a plurality of fifth semiconductor layers (6) of a first conductivity type,which is selectively provided on an area of ​​the fourth semiconductor layer (5); - a first main electrode (14) which is provided on the first main area and is connected to the second and third semiconductor layers (3, 4); - a second main electrode (15) which is provided on the second main area and is connected to the fourth and fifth semiconductor layers (5, 6); - a plurality of first control electrodes (8) which each switch conducting and non-conducting states between the first semiconductor layer (2) and the plurality of third semiconductor layers (4) in accordance with electrical signals; and - a plurality of second control electrodes (11) which each switch conducting and non-conducting states between the first semiconductor layer (2) and the plurality of fifth semiconductor layers (6) in accordance with electrical signals, wherein: - the plurality of first control electrodes (8) has strip shapes,which extend in a first direction in a top view,- the plurality of second control electrodes (11) has strip shapes which extend in a second direction in a top view,- a sum of lengths (G1W) in the first direction of boundaries between the second semiconductor layer (3) and the plurality of third semiconductor layers (4) on a surface of the semiconductor substrate (1) which faces the plurality of first control electrodes (8) is defined as a first gate total width (ZG1W),- a sum of lengths (G2W) in the second direction of boundaries between the fourth semiconductor layer (5) and the plurality of fifth semiconductor layers (6) on a surface of the semiconductor substrate (1) which faces the plurality of second control electrodes (11) is defined as a second total width (ZG2W),- a gate width ratio (∑G2W / ∑G1W) which is obtained,by dividing the second total width (G2W) by the first gate total width (G1W) is equal to or greater than 1.0, - the plurality of first control electrodes (8) has a trench-gate structure, - a region on the first main face of the semiconductor substrate (1) is divided into a plurality of mesa sections by trenches (7) of the plurality of first control electrodes (8), - the plurality of mesa sections includes cell sections containing the third semiconductor layer (4) connected to the first main electrode (14) and dummy cell sections that do not contain the third semiconductor layer (4) connected to the first main electrode (14) or that do not contain the third semiconductor layer (4), and - a distance between adjacent cell sections corresponds to 1 / 40 to 1 / 20 of a shortest distance from the second semiconductor layer (3) to the fourth semiconductor layer (5).

Description

BACKGROUND OF THE INVENTIONField of InterestThe present invention relates to a semiconductor device.BackgroundIn the IGBT, an emitter electrode (cathode) is provided on a surface, and a collector electrode (anode) is provided on a back surface. There has been proposed an IGBT having a double gate structure in which a first gate electrode is provided on a surface and a second gate electrode is provided on a back surface (see, for example, Japanese Patent Application JP S64-057 674A).In turn-off, a signal is applied to the second gate electrode to form a channel connecting an N base layer and an N collector layer in the vicinity of the second gate electrode. Moreover, a P base layer and the N base layer function as a PN diode. In this way, a current path is formed from an emitter electrode including an emitter layer, the P base layer, the N base layer, a back channel region, the N collector layer, and a collector electrode to the collector electrode. Excess electrons accumulated in the N base layer are discharged through this path, so that it is possible to significantly reduce turn-off switching loss without sacrificing an ON voltage.If a parasitic diode integrated in this IGBT having the double gate structure can be provided with a sufficient excitation function, the parasitic diode operates in a similar manner to a free wheeling diode connected in antiparallel with the IGBT. As a result, it is possible to make the capacitance of the free wheel diode smaller or to eliminate the free wheel diode.US 2018 / 0 083 129 A1 relates to a semiconductor device comprising a first electrode, a first semiconductor region arranged on the first electrode and electrically connected thereto, a second semiconductor region arranged on the first semiconductor region and having a lower carrier concentration than the first semiconductor region, a third semiconductor region arranged on the second semiconductor region, a fourth semiconductor region arranged on the third semiconductor region, a fifth semiconductor region arranged on the second semiconductor region and separated in one direction from the third semiconductor region, a gate electrode arranged on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode arranged on the fourth semiconductor region and electrically connected thereto, a third electrode disposed on the fifth semiconductor region is separated from the second electrode and electrically connected to the fifth semiconductor region.US 2020 / 0 303 526 A1 shows a semiconductor device having first and second electrodes, first and second gate electrodes and a semiconductor layer having first and second levels, wherein the semiconductor layer comprises a first semiconductor region of a first conductivity type having a first portion, a second portion having a higher carrier concentration than the first portion and a third portion having a lower carrier concentration than the second portion; facing a second semiconductor region of a second conductivity type between the first semiconductor region and the first level and the first gate electrode; facing a third semiconductor region of a first conductivity type between the second semiconductor region and the first level and in contact with the first electrode; facing a fourth semiconductor region of a second conductivity type between the first semiconductor region and the second level and the second gate electrode; and a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the second plane.US 2017 / 0 117 383 A1 describes a method for forming a semiconductor device, comprising forming an electrical structure on a main surface of a semiconductor substrate and performing an anodic oxidation of a back surface region of a back surface of the semiconductor substrate to form an oxide layer on the back surface of the semiconductor substrate.US 4 980 743 A relates to MIS field effect transistors and improved conductivity modulation MOSFETs. Such a MOSFET comprises a semiconducting drain layer, an N-type base layer (N-base layer) formed on a buffer layer, and a P-type base layer (P-base layer). The P base layer is formed by diffusion in an N-type semiconductor layer serving as the N base layer. An N-type (N+) highly doped layer is formed on the P base layer to define a channel region of the MOSFET. A gate electrode layer covers "insulative" the N base layer and the channel region, and a source electrode layer shorts the P base layer and the N+ source layer. When a positive voltage is applied to the gate electrode, the channel region is inverted, so that carriers (electrons) are injected from the N +- source layer into the N base layer. When the electrons enter the drain layer through the buffer layer, the PN junction of the MOSFET is forward biased and as a result the MOSFET is turned on. When a zero or negative voltage is applied to the gate electrode, the inverted layer in the channel region disappears and thus the channel disappears. As a result, the MOSFET is turned off.US 2014 / 0 339 600 A1 discloses a trench gate MOS structure in a semiconductor device that is formed on a main surface of a semiconductor substrate that is formed as an n-drift region. An n-type well region is provided in the n-type drift region so as to come into contact with a surface of a p-type base region in the vicinity of the n-type drift region constituting the trench gate MOS structure. The n-type shell region has a higher dopant concentration than the n-type drift region. The effective dose of n-type dopants in the n-type shell region is equal to or less than 5.0×1012cm-2. The n-type drift region has a resistance that prevents a depletion layer, which propagates from a p-type collector region on the other main surface when a reverse rated voltage is applied with an emitter as a positive electrode, from reaching either the n-type shell region or the bottom of a first trench depending on which / r is closer to the p-type collector region than the other / s.SummaryHowever, the IGBT having the double gate structure in the related art is focused on reducing turn-off loss of the IGBT and is not focused on fully utilizing functions of the parasitic diode. Consequently, an excitation capability of the parasitic diode is not high. Moreover, it is necessary to make the N base layer thicker as a withstand voltage becomes higher. Thicknesses of N-base layers of an IGBT on the order of 1000 V, an IGBT on the order of 3000 V, and an IGBT on the order of 6000 V correspond to, for example, about 120 micrometers, about 350 micrometers, and about 650 micrometers, respectively. As a result, a current path becomes longer as the withstand voltage becomes higher, and thus the diode has lower excitation power. Therefore, it was not possible to make the capacitance of the free wheeling diode connected in antiparallel to the IGBT smaller or to eliminate the free wheeling diode.The present invention has been implemented to solve the above-described problems, and is directed to provide a semiconductor device capable of improving an excitation power of a parasitic diode.The object on which the invention is based is achieved in a semiconductor device according to the invention with the features of claim 1. Advantageous refinements are the subject matter of the respective dependent claims.A semiconductor device according to the present disclosure includes: a semiconductor substrate having first and second main surfaces facing each other; a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first main surface; a plurality of third semiconductor layers of a first conductivity type selectively provided on a surface of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second main surface; a plurality of fifth semiconductor layers of a first conductivity type selectively provided on a surface of the fourth semiconductor layer; a first main electrode provided on the first main surface and connected to the second and third semiconductor layers; a second main electrode provided on the second main surface and connected to the fourth and fifth semiconductor layers; a plurality of first control electrodes that respectively switch conductive states and non-conductive states between the first semiconductor layer and the plurality of third semiconductor layers in accordance with electric signals; a plurality of second control electrodes that respectively switch conductive states and non-conductive states between the first semiconductor layer and the plurality of fifth semiconductor layers in accordance with electric signals, the plurality of first control electrodes having stripe shapes that extend in a first direction in a plan view, the plurality of second control electrodes having stripe shapes that extend in a second direction in a plan view, a sum of lengths in the first direction of boundaries between the second semiconductor layer and the plurality of third semiconductor layers on a surface of the semiconductor substrate, which faces the plurality of first control electrodes is set to a first gate total width, a sum of lengths in the second direction of boundaries between the fourth semiconductor layer and the plurality of fifth semiconductor layers on a surface of the semiconductor substrate which faces the plurality of second control electrodes is set to a second gate total width, and a gate width ratio obtained by dividing the second gate total width by the first gate total width is equal to or greater than 1.0. According to the invention, the plurality of first control electrodes have a trench gate structure. A region on the first main surface side of the semiconductor substrate is divided into a plurality of mesa portions by trenches of the plurality of first control electrodes. The plurality of mesa portions include cell portions including the third semiconductor layer connected to the first main electrode and dummy cell portions that do not include the third semiconductor layer connected to the first main electrode or that do not include the third semiconductor layer. A distance between adjacent cell portions corresponds to 1 / 40 to 1 / 20 of a shortest distance from the second semiconductor layer to the fourth semiconductor layer.In the present disclosure, the plurality of first control electrodes extends in a first direction in a plan view, the plurality of second control electrodes extends in a second direction in a plan view. A sum of lengths in the first direction of boundaries between the second semiconductor layer and the plurality of third semiconductor layers on a surface of the semiconductor substrate facing the surfaces of the plurality of first control electrodes is set as a first gate total width. A sum of lengths in the second direction of boundaries between the fourth semiconductor layer and the plurality of fifth semiconductor layers on a surface of the semiconductor substrate facing the plurality of second control electrodes is set as a second gate total width. A gate width ratio obtained by dividing the second gate total width by the first gate total width is equal to or greater than 1.0. Therefore, it is possible to improve an excitation power of the parasitic diode.Other and further objects, features and advantages of the invention will become more apparent from the following description.Brief Description of the FiguresFIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. FIG. 2 is a plan view of the semiconductor device according to the first embodiment as viewed from the emitter side. FIG. 3 is a plan view of the semiconductor device according to the first embodiment as viewed from the collector side. FIG. 4 is an enlarged plan view of a region enclosed by a broken line in FIG. 2. Fig. 5 is a cross-sectional view of a portion around the emitter layer, taken along I-I' in Fig. 4. FIG. 6 is an enlarged plan view of a region enclosed by a dashed line in FIG. 3. FIG. 7 is an enlarged plan view of a region enclosed by a broken line in FIG. 6. FIG. 8 is a view illustrating a simulation result of a relationship between a gate width ratio of the IGBT having the double gate structure whose withstand voltage is on the order of 1 kV and a forward voltage drop of a parasitic diode. FIG. 9 is a view illustrating a simulation result of a relationship between a gate width ratio of the IGBT having the double gate structure whose withstand voltage is on the order of 3 kV and a forward voltage drop. FIG. 10 is a view illustrating an inverter for motor control, which is a typical example of a load application of an inductor (L). FIG. 11 is a view illustrating a simulation result of an ON voltage of the IGBT having the double gate structure including a trench gate structure on the front side and on the back side, and whose withstand voltage is on the order of 3 kV. FIG. 12 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. FIG. 13 is a plan view of a part of the semiconductor device according to the second embodiment as viewed from the emitter side. FIG. 14 is a plan view of a part of the semiconductor device according to the second embodiment as viewed from the collector side. Fig. 15 is a cross-sectional view of a portion around the collector layer, taken along II-II' in Fig. 14. FIG. 16 is a plan view of a part of a semiconductor device according to a third embodiment as viewed from the collector side. Fig. 17 is a cross-sectional view of a portion around the collector layer, taken along I-I' in Fig. 16.DESCRIPTION OF EMBODIMENTSA semiconductor device according to embodiments of the present disclosure will be described with reference to the figures. The same components are denoted by identical reference numerals, and repeated description thereof may be omitted.First EmbodimentFIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. The semiconductor device is an IGBT having a dual gate structure in which a front side has a trench gate structure and a back side has a planar gate structure. In FIG. 1, a lateral direction is set as an X direction and a vertical direction is set as a Y direction to clarify a positional relationship among respective components.A semiconductor substrate 1 has a surface and a back surface facing each other. An N-type base layer 2 is provided between the front surface and the back surface of the semiconductor substrate 1. A P base layer 3 is provided between the N base layer 2 and the surface of the semiconductor substrate 1. A plurality of N-type emitter layers 4 are selectively provided on one surface of the P-type base layer 3. A plurality of P collector layers 5 are provided between the N base layer 2 and the back surface of the semiconductor substrate 1. A plurality of N collector layers 6 are selectively provided on surfaces of the P collector layers 5.A plurality of trenches 7 are formed on the front surface of the semiconductor substrate 1 so as to pass through the N-type emitter layers 4 and the P-type base layer 3 and reach the N-type base layer 2. Front-side gate electrodes 8 are formed within a plurality of trenches 7 via front-side gate insulating films 9. Front-side intermediate layers 10 cover the front-side gate electrodes 8, and back-side gate electrodes 11 are formed on the back surface of the semiconductor substrate 1 via back-side gate insulating layers 12 so as to face the N base layer 2, the P collector layers 5, and the N collector layers 6. Back side intermediate layers 13 cover the back side gate electrodes 11.An emitter electrode 14 is provided on the surface of the semiconductor substrate 1 and connected to the P base layer 3 and the N emitter layers 4. A collector electrode 15 is provided on the back surface of the semiconductor substrate 1 and connected to the P collector layers 5 and the N collector layers 6.A region on the front side of the semiconductor substrate 1 is divided into a plurality of mesa portions by the trenches 7 of the plurality of front-side gate electrodes 8. The plurality of mesa portions include cell portions that have the N-type emitter layers 4 connected to the emitter electrode 14 and dummy cell portions that do not have the N-type emitter layers 4 connected to the emitter electrode 14 or that do not have the N-type emitter layers 4. The cell portions and the dummy cell portions form an emitter-side IGBT region. A distance between adjacent cell portions is referred to as a cell distance CP. A shortest distance from the P base layer 3 to the P collector layers 5, that is, a thickness Tn of the N base layer 2, determines a withstand voltage property.If electrical signals are applied to the front-side gate electrodes 8, front-side gate channels 16 are formed in regions of the P base layer 3 facing the front-side gate electrodes 8 via the front-side gate insulating films 9. The N-type emitter layers 4 are electrically conductive to the N-type base layer 2 through the front-side gate channels 16, and thus the plurality of front-side gate electrodes 8 switch conductive states and non-conductive states between the N-type base layer 2 and the plurality of emitter layers 4, respectively, in accordance with electric signals.If electrical signals are applied to the back gate electrodes 11, back gate channels 17 are formed in regions of the P collector layers 5 facing the back gate electrodes 11 via the back gate insulating films 12. The N collector layers 6 are electrically conductive to the N base layer 2 through the back gate channels 17, and thus the back gate electrodes 11 switch conductive states and non-conductive states between the N base layer 2 and the plurality of N collector layers 6, respectively, in accordance with electric signals.FIG. 2 is a plan view of the semiconductor device according to the first embodiment as viewed from the emitter side. FIG. 2 illustrates a direction in which the front-side gate electrodes 8 extend as a Z direction. The plurality of front-side gate electrodes 8 have strip shapes that extend in the Z direction in a plan view perpendicular to the surface of the semiconductor substrate 1 and are arranged parallel to each other. A front-side gate wiring 18 is connected to the front-side gate electrodes 8. The front-side gate wiring 18 is connected to a front-side gate electrode pad 19. An outer edge region including an outer edge electrode 20 and an N+ layer 21 for satisfying the withstand voltage characteristics is provided in an outer edge region of the emitter-side IGBT region. The outer edge region is covered with a protective layer of the outer edge region.FIG. 3 is a plan view of the semiconductor device according to the first embodiment as viewed from the collector side. The plurality of back-side gate electrodes 11 have stripe shapes extending in the Z direction in a plan view perpendicular to the back side of the semiconductor substrate 1 and arranged parallel to each other. A back gate wiring 22 is connected to the back gate electrodes 11. The back gate wiring 22 is connected to a back gate electrode pad 23. Portions of the back gate wiring 22 and the back gate electrode pad 23 are covered with a protective layer 24.The front-side gate insulating films 9 and the back-side gate insulating films 12 are normally formed of an oxide film such as SiO 2. The front-side gate electrodes 8 and the back-side gate electrodes 11 are formed of polysilicon doped with N-type impurities. The front-side intermediate layers 10 and the back-side intermediate layers 13 are formed by silicate glass (BPSG) containing boron and phosphorus. The emitter electrode 14, the collector electrode 15, the front-side gate wiring 18, the front-side gate electrode pad 19, the back-side gate wiring 22, and the back-side gate electrode pad 23 are formed by aluminum containing silicon.FIG. 4 is an enlarged plan view of a region enclosed by a broken line in FIG. 2. FIG. 5 is a cross-sectional view of a portion around the emitter layer 4, taken along I-I' in FIG. 4. A length G 1W in the Z direction of a boundary between the P base layer 3 and the N emitter layer 4 on the surface (Y-Z plane) of the semiconductor substrate 1 facing the front-side gate electrode 8 is a width of the front-side gate channel 16.FIG. 6 is an enlarged plan view of a region enclosed by a dashed line in FIG. 3. FIG. 7 is an enlarged plan view of a region surrounded by a broken line in FIG. 6. FIG. 1 corresponds to a cross-sectional view taken along II-II' in FIGS. 4 and 6, and the back-side gate electrodes 11, the back-side gate insulating films 12, the back-side intermediate films 13, and the collector electrode 15 are omitted. A length G 2W in the Z direction of a boundary between the P collector layer 5 and the N collector layer 6 on the front surface (X-Z plane) of the semiconductor substrate 1 facing the back gate electrode 11 is a width of the back gate channel 17.In the present embodiment, the semiconductor device is configured such that a gate width ratio (ΣG 2W / ΣG 1VW) obtained by dividing the second gate total width ΣG 2W by the first gate total width ΣG 1W becomes equal to or greater than 1.0. Note that the gate width ratio (ΣG2W / ΣG1VW) is about 10.A rated withstand voltage of a front-side gate and a back-side gate is ±7 V, similarly to a rated withstand voltage of gates of a scaling IGBT whose scaling factor (k) corresponds to 3. A threshold voltage of the front-side gate and the back-side gate is approximately +1.7 V, similarly to a threshold voltage of the scaling IGBT. A gate voltage applied to the front-side gate and the back-side gate to cause a gate channel to stably operate by reducing the resistance is +5 V, which is about three times the threshold voltage in a similar manner to a gate voltage of the scaling IGBT.Table 1 gives an aspect of voltage blocking and current excitation of operation of such an IGBT having the double gate structure. A positive or negative collector voltage is applied with respect to a ground potential of the emitter electrode 14. A gate voltage positive with respect to the ground potential of the emitter electrode 14 is applied to the front-side gate electrodes 8. A gate voltage that is positive with respect to a potential of the collector electrode 15 is applied to the back-side gate electrodes 11. The operating aspect is one of voltage blocking, forward current excitation, and reverse current excitation, and does not include either an aspect of leakage current or an aspect of junction breakdown. During voltage blocking, current does not flow from the collector electrode 15 to the emitter electrode 14. In forward current excitation, current flows from the collector electrode 15 to the emitter electrode 14. [Table 1] Table 1] [Table 1] Table 1]1positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive positive 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negative negative negative negative negative negative negative negative negative negativeabuttingabuttingReverse current excitation (large resistance when excitation)8negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative 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negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negative negativeNot abuttingabuttingReverse current excitationNext, a switching operation will be described. First, an ON state (operation mode 2 in Table 1) in which a large current flows from the collector electrode 15 to the emitter electrode 14 at a low collector voltage V CE will be described. A predefined collector voltage V CE is present between emitter electrode 14 and collector electrode 15. A gate voltage is not applied between the collector electrode 15 and the back gate electrodes 11, or a voltage (reverse bias voltage) negative with respect to the collector electrode 15 is applied to the back gate electrodes 11. A voltage V G1E( forward bias voltage) positive with respect to the emitter electrode 14 is applied to the front-side gate electrodes 8, in which case the first front-side gate channels 16 are formed as a result of regions in the vicinity of the front-side gate electrodes 8 in the P base layer 3 inverted to an N type. A current path is formed in the N emitter layer 4, the front-side gate channels 16, and the N base layer 2. Electrons having negative charges are injected from the emitter electrode 14 into the N base layer 2 through this path. The injected electrons charge the N base layer 2 negatively and forwardly bias the PN junction of the P collector layer 5 and the N base layer 2. Thus, holes having positive charges are injected from the collector electrode 15 through the P collector layer 5 into the N base layer 2. This results in an increase in density of the holes existing in the N base layer 2, causes conductivity modulation, and drastically reduces resistance components of the N base layer 2. As a result, even when the collector voltage V CE is low, a large collector current flows from the collector electrode 15 to the emitter electrode 14, and a voltage drop at this time between the collector and the emitter of the IGBT having the double-gate structure is an ON voltage V CEsat.Next, a turn-off operation in which a state of the IGBT having the double gate structure transitions from an ON state to an OFF state will be described. A zero potential or a negative potential is applied to the front-side gate electrodes 8, and provision of a positive voltage to the emitter electrode 14 is stopped. As a result, the regions near the front-side gate electrodes 8 in the P base layer 3 inverted to the N type return to a P type. Due to the disappearance of the first N channel, a path through which electrons flow from the N emitter layer 4 to the N base layer 2 disappears. As a result, injection of electrons from the emitter electrode 14 into the N base layer 2 is stopped, forward bias of the PN junction of the collector layer 5 and the N base layer 2 is canceled, and injection of holes from the collector electrode 15 into the N base layer 2 through the collector layer 5 is stopped. Conductivity modulation of the N base layer 2 is canceled, and a resistance of the N base layer 2 returns to a state before the occurrence of the conductivity modulation. The PN junction of the P base layer 3 and the N base layer 2 becomes a depletion layer and has voltage blocking properties. As a result, a state transitions to an OFF state (voltage blocking) in which no current flows from the collector electrode 15 to the emitter electrode 14.During the turn-off operation, a voltage V G2C, which is positive with respect to the collector electrode 15, is applied to the back-side gate electrodes 11 immediately before or substantially at the same time as the application of a voltage, which is positive with respect to the emitter electrode 14, is stopped at the front-side gate electrodes 8. As a result, the back gate channels 17 are formed as a result of regions near the back gate electrodes 11 inverted to an N type. A current path composed of the N base layer 2, the back gate channels 17, and the N collector layer 6 is formed. As a result, electrons are discharged from the N base layer 2 to the collector electrode 15 through this path, a density of electrons in the N base layer 2 starts to decrease. This decrease in the density of electrons weakens the forward bias of the PN junction of the P collector layer 5 and the N base layer 2, and reduces the injection of holes from the P collector layer 5 into the N base layer 2. In this situation, if the positive gate voltage V G1E, which is applied to the front-side gate electrodes 8, is switched to a zero-volt voltage or a reverse bias, the front-side gate channels 16, which are inverted to the N type, return to a P type, and injection of electrons from the emitter electrode 14 is terminated. The electrons accumulated in the N base layer 2 are discharged to the collector electrode 15 through the back gate channels 17 and the N collector layer 6. The holes accumulated in the N base layer 2 are discharged to the emitter electrode 14 through the P base layer 3. A depletion electric field occurring due to a result of the PN junction of the P base layer 3 and the N base layer 2 becoming a depletion layer rapidly discharges the electrons accumulated in the N base layer 2 to the collector electrode 15 and rapidly discharges the holes to the emitter electrodes 14.Immediately before application of a voltage positive with respect to the emitter electrode 14 to the front-side gate electrodes 8 is stopped, a voltage V G2C, positive with respect to the collector layer 15, is applied to the back-side gate electrodes 11. This reduces accumulation of electrons in the N base layer 2 and also reduces a density of holes so that charge neutrality is satisfied. As a result, a time period from when an excessive charge accumulated in the N base layer 2 disappears is shortened, and turn-off loss is further reduced.FIG. 8 is a view illustrating a simulation result of a relationship between a gate width ratio of the IGBT having the double gate structure whose withstand voltage is on the order of 1 kV and a forward voltage drop of a parasitic diode. FIG. 8 indicates the gate width ratio (ΣG 2W / ΣG 1W) on a horizontal axis. FIG. 8 indicates a relative value of the forward voltage drop @150 A / cm 2 of the parasitic diode on a vertical axis. Scaling design technology is applied to the front-side gate structure. A distance from the P collector layer 5 to the P base layers 3, that is, a thickness of the N base layer 2, is set to 115 micrometers. The cell distance CP is set to 12 micrometers. A depth of the front side trenches 7 is set to 2.5 micrometers. A gate rated voltage of the front-side gate and the back-side gate is set to ±7 V, and a threshold voltage is set from 1.6 V to 1.8 V. 0 V abuts the front-side gate electrodes 8, and 5 V abuts the back-side gate electrodes 11. A temperature is 150° C., which is a typical rated temperature of the IGBT. A current to be flowed is converted into a current density to eliminate factors depending on a size of the IGBT having the double gate structure.It can be observed that when the gate width ratio (ΣG2W / ΣG1W) falls below 1.0, a forward voltage drop of the parasitic diode significantly increases beyond an error level, and an excitation capability of the diode deteriorates. Here, if the gate width ratio is small, a gate width G 2W of the back side gate electrodes 11 which become current passage becomes narrower, and the back side gate channel 17 becomes narrower. This increases a resistance of the back gate channels 17 and makes the forward voltage drop of the parasitic diode steeply rise.FIG. 9 is a view illustrating a simulation result of a relationship between a gate width ratio of the IGBT having the double gate structure whose withstand voltage is on the order of 3 kV and a forward voltage drop. FIG. 9 indicates the gate width ratio (ΣG 2W / ΣG 1W) on a horizontal axis. FIG. 9 indicates a relative value of the forward voltage drop @50 A / cm 2 of the parasitic diode on a vertical axis. A distance from the P collector layer 5 to the P base layer 3, that is, a thickness of the N base layer 2, is set to 350 micrometers. The cell distance CP is set to 12 micrometers. A depth of the front side trenches 7 is set to 6 micrometers. Thicknesses of the front-side gate insulating films 9 and the back-side gate insulating films 12 are formed thicker, a gate rated voltage of the front-side gate and the back-side gate is set to ±20 V, and a threshold voltage is set from +5 V to +6 V. An applied voltage for driving is +15 V.0 V is applied to the front-side gate electrodes 8, and 15 V is applied to the back-side gate electrodes 11. A temperature is 150° C., which is a typical rated temperature of the IGBT. A current to be flowed is converted into a current density to eliminate factors depending on a size of the IGBT having the double gate structure.It can be observed that when the gate width ratio (ΣG2W / ΣG1W) falls below 1.0, the forward voltage drop of the parasitic diode significantly increases beyond an error level, in a similar manner to the IGBT having the double gate structure on the order of 1 kV, and an excitation capability as a diode deteriorates. It has therefore been confirmed that an excitation capability of the parasitic diode can be improved by setting the gate width ratio (ΣG2W / ΣG1W) to be equal to or greater than 1.0 having different ratings and characteristics even in the IGBT having the double gate structure.As described above, the present embodiment is an IGBT having a double gate structure in which the back-side gate electrodes 11 are provided to reduce turn-off switching loss while maintaining a structure design of the emitter-side IGBT region to achieve a low ON voltage of the IGBT. Further, the semiconductor device is configured such that the gate width ratio (ΣG2W / ΣG1W) becomes equal to or greater than 1.0 by adjusting the second gate total width ΣG2W on the back side while forming the first gate total width ΣG1W on the front side identically to that of the IGBT having the double gate structure in the related art. This can improve the excitation capability of the parasitic diode integrated in the IGBT in a reverse direction.FIG. 10 is a view illustrating an inverter for motor control, which is a typical example of a load application of an inductor (L). Two IGBT units 26 are connected in series at each of three phases of a DC-AC inverter that drives a motor 25 so as to form an arm. Each IGBT unit 26 includes an IGBT 27 and a free wheeling diode (FWD) 28 connected in antiparallel with the IGBT 27.A driving power is supplied from a series connection portion of the IGBT unit 26 to the motor 25. The IGBT 27 whose cathode is connected to the series connection portion is called a P-side (high-side) IGBT. The IGBT 27 whose anode is connected to the series connection portion is called an N-side (low-side) IGBT. The P-side IGBT and the N-side IGBT connected in series to form the arm are driven such that the IGBTs are not simultaneously placed in an ON state (arm short circuit). The IGBT 27 constituting the arm provides driving power to the motor by repeating ON / OFF while adjusting and controlling an ON / OFF period. Energy accumulates in an L load by a current flowing through the IGBT 27. When the IGBT 27 is turned off, the FWD causes a reverse current (which is a reverse current of the IGBT 27 but a forward current of the FWD) to flow and consume the power.The IGBT having the double gate structure according to the present embodiment is applied to the IGBT 27 of this inverter. In the IGBT having the double gate structure, the N base layer 2 may be electrically conductive to the collector electrode 15 by turning on the back gate, and electric conduction between the N base layer 2 and the collector electrode 15 allows the PN junction composed of the P base layer 3 and the N base layer 2 to function as a diode. By achieving electrical conduction between the N base layer 2 and the emitter electrode 14 by turning on the front-side gate while turning on the back-side gate, it is possible to cause a reverse current to flow while achieving electrical conduction between the emitter electrode 14 and the collector electrode 15. Therefore, it is also possible to provide the IGBT having the double gate structure with functions that integrate the FWD by the driving of the back gate. As a result, it is possible to make a capacitance of the free wheeling diode 28 smaller or to eliminate the free wheeling diode 28. As a result, it is possible to achieve an inverter whose size is drastically reduced.In the present embodiment, the back side gate electrodes 11 have a planar gate structure. Accordingly, it is possible to omit a trench forming process, which makes manufacturing simple and improves productivity.In the scaling IGBT, there is also an optimum relationship between the thickness Tnof the N base layer 2 and the cell distance CP. FIG. 11 is a view illustrating a simulation result of an ON voltage of the IGBT having the double gate structure having a trench gate structure on the front side and on the back side, and whose withstand voltage is on the order of 3 kV. FIG. 11 indicates a ratio CP / Tn of the cell distance CP with respect to Tn on a horizontal axis. FIG. 11 indicates an ON voltage standardized while a minimum value on a vertical axis is set to 1. The gate width ratio (ΣG2W / ΣG1W) is set to 1.0. A rated gate voltage of the front-side gate and the back-side gate is set to ±20 V, and a threshold voltage is set from 5 V to 6 V. 15V are applied to the front-side gate electrodes 8, and 0V are applied to the back-side gate electrodes 11. A temperature is 150° C., which is a typical rated temperature of the IGBT. As a result of the simulation, it can be seen that a change in the ON voltage is small in a region in which CP / Tn ranges from 1 / 40 to 1 / 20 and falls within a level of an error of +1.0%. Thus, the semiconductor device in the present embodiment is configured such that CP / Tn falls within a range of 1 / 40 to 1 / 20. By specifying the cell pitch on the front side in accordance with the thickness of the N base layer 2 in this manner, it is possible to reduce an ON voltage of the IGBT.Second EmbodimentFIG. 12 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. FIG. 13 is a plan view of a part of the semiconductor device according to the second embodiment as viewed from the emitter side. The emitter electrode 14 and the front side intermediate layers 10 are omitted. FIG. 14 is a plan view of a part of the semiconductor device according to the second embodiment as viewed from the collector side. The collector electrode 15 and the back side intermediate layers 13 are omitted. Note that FIG. 12 corresponds to a cross-sectional view along I-I' in FIGS. 13 and 14. Fig. 15 is a cross-sectional view of a portion around the collector layer, taken along II-II' in Fig. 14.The present embodiment has a structure on the emitter side similar to that in the first embodiment and has a structure on the collector side different from that of the first embodiment. A plurality of trenches 29 are formed on the back surface of the semiconductor substrate 1 so as to pass through the N collector layers 6 and the P collector layer 5 and reach the N base layer 2. The back gate electrodes 11 are formed within the plurality of trenches 29 via the back gate insulating films 12. The back side intermediate layers 13 cover the back side gate electrodes 11.The back side gate electrodes 11 have a trench gate structure in this manner, so that it is possible to design a pitch of the back side gate electrodes 11 to be about 6 micrometers. This allows the back-side gate electrodes 11 to be arranged at a higher density by making a pitch of the back-side gate electrodes 11 narrower than that of a planar gate structure having a pitch of about 12 micrometers.Moreover, an electron injection improving effect is typically used to improve an ON voltage of the IGBT. Consequently, the cell pitch of the front-side gate electrodes 8 cannot be made smaller even if a trench structure is used. The trenches 7 do not have N emitter layers 4 and are provided with dummy cell portions that are not connected to the emitter electrode 14 to make the cell pitch larger because the trenches 7 are desired to be formed at identical pitches. Meanwhile, such a limitation is not imposed on the back-side gate electrodes 11, and thus the N collector layers 6 may be positioned at all mesa portions between the trenches 29.Accordingly, as a result of the back-side gate electrodes 11 having the trench gate structure, it is possible to increase the second gate total width ΣG 2W on the back side. Consequently, the gate width ratio (ΣG2W / ΣG1W) can be easily made equal to or greater than 1.0. Therefore, it is possible to improve an excitation power of the parasitic diode and reduce the forward voltage drop of the parasitic diode.Third EmbodimentFIG. 16 is a plan view of a part of a semiconductor device according to a third embodiment as viewed from the collector side. The collector electrode 15 and the back side intermediate layers 13 are omitted. FIG. 17 is a cross-sectional view of a portion around the collector layer, taken along I-I' in FIG. 16; a structure on the emitter side of the present embodiment is similar to that in the first embodiment, and a longitudinal direction of the front-side gate electrode 8 is a direction of a Z axis. Meanwhile, a longitudinal direction of the back side gate electrodes 11 is a direction of an X axis and is deviated from the longitudinal direction of the front side gate electrodes 8.Here, in a case where the front-side gate electrodes 8 have the trench gate structure, a JFET resistance region does not exist in an electron injection path from the N emitter layer 4 to the N base layer 2. electrons injected into the N base layer 2 increase by an amount corresponding to the decrease in resistance in the electron injection path. This increases an amount of electrons accumulated in the N base layer 2 and makes the amount of electrons nonuniform. As a result of a portion in which the front-side gate electrodes 8 injecting electrons overlap with the back-side gate electrodes 11 discharging electrons and a portion in which the front-side gate electrodes 8 locally do not overlap with the back-side gate electrodes 11, a non-uniform increase in the distribution of the electrons in the N base layer 2 may occur during the transient turn-off operation, whereby currents may converge and cause destruction.In contrast, in the present embodiment, a direction in which the back side gate electrodes 11 extend is formed differently from a direction in which the front side gate electrodes 8 extend. This prevents a portion into which electrons are likely to be injected from the front-side gate electrodes 8 and accumulate from locally overlapping with a portion separated from the back-side gate electrodes 11 and from which electrons are slowly discharged. It is therefore possible to improve uniformity of operation in a transient operation such as switching. Further, the direction in which the back side gate electrodes 11 extend is preferably orthogonal to the direction in which the front side gate electrodes 8 extend. This makes power variation within the plane of the IGBT cell region even smaller.Note that the semiconductor substrate 1 may be formed of both a wide band gap semiconductor having a larger band gap than that of silicon and silicon. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. A semiconductor device formed of such a wide band gap semiconductor has high withstand voltage characteristics and a high allowable current density, so that the semiconductor device can be made smaller. Use of this semiconductor device made smaller can also make a semiconductor module including this semiconductor device smaller and higher integrated. Further, the semiconductor device has high heat resistance, which can make a cooling fin of a heat sink smaller and can convert a water cooled part to an air cooled part, so that it is possible to make the semiconductor module even smaller. Moreover, the semiconductor device has a low power loss and a high efficiency, so that it is possible to increase an efficiency of the semiconductor module.

Claims

A semiconductor device comprising: a semiconductor substrate (1) having first and second main surfaces facing each other; a first semiconductor layer (2) of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate (1); a second semiconductor layer (3) of a second conductivity type provided between the first semiconductor layer (2) and the first main surface; a plurality of third semiconductor layers (4) of a first conductivity type selectively provided on a surface of the second semiconductor layer (3); a fourth semiconductor layer (5) of a second conductivity type provided between the first semiconductor layer (2) and the second main surface; a plurality of fifth semiconductor layers (6) of a first conductivity type selectively provided on a surface of the fourth semiconductor layer (5); a first main electrode (14) provided on the first main surface and connected to the second and third semiconductor layers (3, 4); a second main electrode (15) provided on the second main surface and connected to the fourth and fifth semiconductor layers (5, 6); a plurality of first control electrodes (8) that respectively switch conductive states and non-conductive states between the first semiconductor layer (2) and the plurality of third semiconductor layers (4) in accordance with electrical signals; and a plurality of second control electrodes (11) that respectively switch conductive states and non-conductive states between the first semiconductor layer (2) and the plurality of fifth semiconductor layers (6) in accordance with electrical signals, wherein: the plurality of first control electrodes (8) have stripe shapes that extend in a first direction in a plan view, the plurality of second control electrodes (11) have stripe shapes extending in a second direction in a plan view, a sum of lengths (G1W) in the first direction of boundaries between the second semiconductor layer (3) and the plurality of third semiconductor layers (4) on a surface of the semiconductor substrate (1) facing the plurality of first control electrodes (8) is set as a first gate total width (ZG1W), a sum of lengths (G2W) in the second direction of boundaries between the fourth semiconductor layer (5) and the plurality of fifth semiconductor layers (6) on a surface of the semiconductor substrate (1) facing the plurality of second control electrodes (11) is set as a second total width (ZG2W), a gate width ratio (∑G2W / ∑G1W) obtained by dividing the second total width (ΣG2W by the first gate total width (ΣG1W) is equal to or higher than 1.0, the plurality of first control electrodes (8) has a trench gate structure, a region on the first main surface side of the semiconductor substrate (1) is divided into a plurality of mesa portions by trenches (7) of the plurality of first control electrodes (8), the plurality of mesa portions include cell portions including the third semiconductor layer (4) connected to the first main electrode (14) and dummy cell portions, which do not contain the third semiconductor layer (4) connected to the first main electrode (14) or which do not contain the third semiconductor layer (4), and - a distance between adjacent cell sections corresponds to 1 / 40 to 1 / 20 of a shortest distance from the second semiconductor layer (3) to the fourth semiconductor layer (5).The semiconductor device according to claim 1, wherein the second control electrodes (11) have a planar gate structure.The semiconductor device according to claim 1, wherein the second control electrodes (11) have a trench gate structure.The semiconductor device according to any one of the preceding claims, wherein: - the first control electrodes (8) have a trench gate structure, and - the second direction is different from the first direction.The semiconductor device of claim 4, wherein the second direction is orthogonal to the first direction.The semiconductor device according to any one of the preceding claims, wherein the semiconductor substrate (1) is formed by a wide band gap semiconductor.

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