Frequency converter

Abstract

Frequency converter (100), comprising: - a first fieldbus connection (1) and a second fieldbus connection (2), and - a Field Programmable Gate Array (FPGA) (3) with n IP cores (4a, 4b), with n > 1, - wherein a respective one of the n IP cores (4a, 4b) implements a fieldbus node, and - wherein the n IP cores (4a, 4b) are looped in series between the first fieldbus connection (1) and the second fieldbus connection (2), characterized in that - each of the n IP cores (4a, 4b) can be assigned a power electronics unit (5a, 5b) which can be controlled by means of the assignable IP core (4a, 4b) via a fieldbus (6).

Description

The invention relates to a frequency converter which can be configured as flexibly as possible.DE 10 2017 131 314 A1 discloses a frequency converter according to the preamble of claim 1.The publication EtherCAT® Slave Controller IP Core for Xilinx® FPGAs Release 3.00k. Datasheet. Beckhoff Automation GmbH & Co. KG, 2015, s.i-2, 81th URL: https: / / download.beckhoff. com / download / document / io / ethercat-development-products / ethercat_ipcore_xilinx_v3_00k_datasheet_v1i0.pdf [retrieved on 11.02.2022] discloses a realization of an EtherCAT IP core.The frequency converter has a conventional first field bus connection and a conventional second field bus connection. The first field bus connection forms, for example, a bidirectional incoming field bus connection and the second field bus connection forms, for example, a bidirectional outgoing field bus connection, so that a plurality of frequency converters linked to one another via their first or second field bus connections form a so-called daisy chain. In this respect, reference is also made to the relevant technical literature, for example to EtherCAT fieldbuses, in particular with respect to their connections and their topology.The frequency converter has a conventional field programmable gate array (FPGA), the FPGA has n IP cores, where n>1. For the rest, reference is made to the relevant technical literature in this respect.Each IP core realizes a fieldbus node. With regard to the basic properties of field bus nodes, reference is made to the relevant technical literature.The n IP cores are connected in series between the first field bus connection and the second field bus connection, specifically exclusively within the FPGA, i.e. without FPGA-external detours or paths.In one embodiment, the associated fieldbus is an EtherCAT fieldbus and the fieldbus nodes are respectively EtherCAT fieldbus nodes.In one embodiment, the frequency converter is designed in a first operating mode to link only m IP cores in series in a data flow between the first fieldbus connection and the second fieldbus connection for data exchange with one another, wherein m<n. In other words, fieldbus data between the first fieldbus connection and the second fieldbus connection are passed through bidirectionally, sequentially only between the m IP cores, the remaining n-m IP cores are bridged with respect to the data flow. In the first operating mode, there are, for example, two IP cores, wherein only one of the two IP cores is located in the bidirectional data flow between the first field bus connection and the second field bus connection, i.e. n=2 and m=1.In one embodiment, the frequency converter is designed in a second operating mode to link all n IP cores in series with one another in the bidirectional data flow between the first field bus connection and the second field bus connection. The data is then received, for example, by the IP core which is connected to the first or second fieldbus connection, and is then passed through or streamed sequentially to the respective next IP core of the row.Each of the n IP cores is allocatable or assigned power electronics. The power electronics can be controlled by means of the allocatable or assigned IP core via a field bus. The power electronics can have, for example, a three-phase inverter.In one embodiment, each of the n IP cores has a first connection side and a second connection side, wherein, in the series connection of the IP cores, for example, the second connection side of an IP core is always connected to the first connection side of a subsequent IP core. The first port side and the second port side each include a port for receiving data, a port for transmitting data, and a reception clock port.In one embodiment, the frequency converter further comprises: a first physical layer transceiver connected to the first fieldbus connection and a second physical layer transceiver connected to the second fieldbus connection. The n IP cores are then looped in series between the first physical layer transceiver and the second physical layer transceiver.In an embodiment, the port for receiving data of the first port side of a first IP core is connected to a corresponding port of the first physical layer transceiver, the port for transmitting data of the first port side of the first IP core is connected to a corresponding port of the first physical layer transceiver, and the receive clock port of the first port side of the first IP core is connected to a corresponding port of the first physical layer transceiver.Frequency converters are typically differentiated according to whether they can actuate a single axis, i.e. a single electric motor, or a multi-axis, i.e. a plurality of electric motors. An individual axis of a multi-axis converter is actuated / parameterized differently here than the individual axis of an individual-axis converter.The invention now provides a frequency converter in which each axis can be parameterized and controlled in the same way via the field bus, independently of its available number. In other words, the individual axis of an individual-axis converter is controlled and parameterized via the fieldbus in the same way as a respective individual axis of a multi-axis converter.The invention will be described in detail below with reference to the drawings. The following shows: FIG. 1 is a high-level schematic block diagram of an internal structure of a frequency converter according to the invention.FIG. 1 shows a block diagram of a frequency converter 100, comprising: a first EtherCAT fieldbus connection 1, a second EtherCAT fieldbus connection 2, a first physical layer transceiver 7, also referred to as PHY, which is connected to the first fieldbus connection 1, a second physical layer transceiver 8 which is connected to the second fieldbus connection 2, and a field programmable gate array (FPGA) 3 having two IP cores 4 aand 4 b. Each IP core 4a and 4b implements an EtherCAT Fieldbus node. The IP cores 4 aand 4 bare connected in series between the first fieldbus connection 1 and the second fieldbus connection 2 or the first physical layer transceiver 7 and the second physical layer transceiver 8.In a first operating mode, the frequency converter 100 is designed to only include the IP core 4 ain a data flow between the first fieldbus connection 1 and the second fieldbus connection 2, i.e. the IP core 4 bis bridged. In the first operating mode, therefore, only the fieldbus node 4 ais visible and addressable on a fieldbus 6, to which the frequency converter 100 is connected.In a second operating mode, the frequency converter 100 is designed to include both IP cores 4 aand 4 bin the data flow between the first field bus connection 1 and the second field bus connection 2. In the second operating mode, therefore, both fieldbus nodes 4 aand 4 bare visible and addressable on the fieldbus 6.Power electronics 5 aof the frequency converter 100 are assigned to the IP core 4 aand power electronics 5 bof the frequency converter 100 are assigned to the IP core 4 b. The power electronics 5 aand 5 bcan be controlled by means of their associated IP core 4 aand 4 b, respectively, via the field bus 6, for example by a higher-order controller.Each IP core 4 aand 4 bhas a first and left terminal side and a second and right terminal side, respectively, the first terminal side and the second terminal side each including: a terminal RX_DATA for receiving data, a terminal TX_DATA for transmitting data, and a reception clock terminal RX_CLK. Further, each IP core 4a and 4b is supplied with a base clock of 25 MHz.The terminal RX_DATA of the first terminal side of the IP core 4 ais connected to a corresponding terminal of the first physical layer transceiver 7, the terminal TX_DATA of the first terminal side of the IP core 4 ais connected to a corresponding terminal of the first physical layer transceiver 7, and the reception clock terminal RX_CLK of the first terminal side of the IP core 4 ais connected to a corresponding terminal of the first physical layer transceiver 7.The terminal TX_DATA of the second terminal side of the IP core 4a is connected to the terminal RX_DATA of the first terminal side of the IP core 4b and is connected to an input of a multiplexer 11. The terminal RX_DATA of the second terminal side of the IP core 4a is connected to an output of a multiplexer 10. The terminal RX_CLK of the second terminal side of the IP core 4a is connected to an output of a multiplexer 9.One input of the multiplexer 9 is connected to a 25 MHz clock signal. A further input of the multiplexer 9 is connected to a corresponding terminal of the second physical layer transceiver 8.One input of the multiplexer 10 is connected to the terminal TX_DATA of the first terminal side of the IP core 4 band another input of the multiplexer 10 is connected to a corresponding terminal of the second physical layer transceiver 8.The terminal RX_CLK of the first terminal side of the IP core 4b is connected to a 25 MHz clock signal. The terminal RX_CLK of the second terminal side of the IP core 4 bis connected to a corresponding terminal of the second physical layer transceiver 8. The terminal RX_DATA of the second terminal side of the IP core 4 bis connected to a corresponding terminal of the second physical layer transceiver 8. The terminal TX_DATA of the second terminal side of the IP core 4 bis connected to a further input of the multiplexer 11.An output of the multiplexer 11 is connected to a corresponding terminal of the second physical layer transceiver 8.As already explained above, the frequency converter 100 in the first operating mode is designed to only include the IP core 4 ain a data flow between the first field bus connection 1 and the second field bus connection 2. For this purpose, the multiplexers 9, 10 and 11 bridge the IP core 4 b. The switching position of the multiplexers 9, 10 and 11 is then such that the connection TX_DATA of the second connection side of the IP core 4 ais in data connection with the corresponding connection of the second physical layer transceiver 8, that the connection RX_DATA of the second connection side of the IP core 4 ais in data connection with the corresponding connection of the second physical layer transceiver 8, and the connection RX_CLK is in data connection with the corresponding connection of the second physical layer transceiver 8.As already explained above, the frequency converter 100 is designed in the second operating mode to include both IP cores 4 aand 4 bin the data flow. The switching position of the multiplexers 9, 10 and 11 is then such that the terminal TX_DATA of the second terminal side of the IP core 4 bis in data connection with the corresponding terminal of the second physical layer transceiver 8, that the terminal RX_DATA of the second terminal side of the IP core 4 ais in data connection with the terminal TX_DATA of the first terminal side of the IP core 4 band the terminal RX_CLK of the second terminal side of the IP core 4 ais supplied with the 25 MHz clock signal.The embodiment shown in Figure 1 illustrates two IP cores 4a and 4b. It is understood that according to the invention, more than two IP cores may also be present, which may be operated in a first operating mode or a second operating mode based on the principle shown above.

Claims

Frequency converter (100), having: - a first field bus connection (1) and a second field bus connection (2), and - a field programmable gate array (FPGA) (3) having n IP cores (4a, 4b), where n > 1, - wherein a respective one of the n IP cores (4a, 4b) implements a field bus node, and - wherein the n IP cores (4a, 4b) are looped in series between the first field bus connection (1) and the second field bus connection (2), characterized in that - each of the n IP cores (4a, 4b) can be assigned power electronics (5a, 5b) which can be assigned by means of the IP core (4a, 4b) which can be assigned, 4b) can be controlled via a field bus (6).Frequency converter (100) according to Claim 1, characterized in that - the field bus nodes (4a, 4b) are EtherCAT field bus nodes.Frequency converter (100) according to one of the preceding claims, characterized in that - the frequency converter (100) is designed in a first operating mode to link only m IP cores (4a) of the n IP cores (4a, 4b) in series with one another into a data flow between the first field bus connection (1) and the second field bus connection (2), wherein m < n.Frequency converter (100) according to claim 3, characterised in that - n = 2 and m = 1.Frequency converter (100) according to Claim 3 or 4, characterized in that - the frequency converter (100) is designed, in a second operating mode, to link all n IP cores (4a, 4b) to one another in series in a data flow between the first field bus connection (1) and the second field bus connection (2).Frequency converter (100) according to one of the preceding claims, characterized in that - each of the n IP cores (4a, 4b) has a first connection side and a second connection side, the first connection side and the second connection side each having: - a connection (RX_DATA) for receiving data, - a connection (TX_DATA) for transmitting data, and - a reception clock connection (RX_CLK).Frequency converter (100) according to one of the preceding claims, characterized in that the frequency converter (100) further comprises: - a first physical layer transceiver (7) which is connected to the first field bus connection (1), and - a second physical layer transceiver (8) which is connected to the second field bus connection (2).Frequency converter (100) according to claim 7, characterised in that - the connection (RX_DATA) for receiving data of the first connection side of a first IP core (4a) is connected to a corresponding connection of the first physical layer transceiver (7), - the connection (TX_DATA) for transmitting data of the first connection side of the first IP core (4a) is connected to a corresponding connection of the first physical layer transceiver (7), and - the reception clock connection (RX_CLK) of the first connection side of the first IP core (4a) is connected to a corresponding connection of the first physical layer transceiver (7).

Images