SILICON CONTACTS AND METHOD FOR THEIR MANUFACTURE

Abstract

Procedure with the following steps: Providing a substrate (202) comprising a semiconductor device (204) arranged on the substrate (202); Producing a multilayer interconnect structure (208, 804) over the substrate (202), wherein the multilayer interconnect structure (208, 804) has an enclosure structure (212, 810), the enclosure structure (212, 810) being formed by metal-containing structural elements (706A, 706B, 808A, 808B); Etching an opening (904, 1502, 2602, 3102, 3302) in the enclosure structure (212, 810), wherein the etching of the opening (904, 1502, 2602, 3102, 3302) includes lateral etching of end regions of the metal-containing structural elements (706A, 706B, 808A, 808B); Deposition of a protective layer (1002, 2702) on side walls of the opening (904, 1502, 2602, 3102, 3302); and Producing a substrate via (214, 1302, 1802, 2802, 2902, 3202) such that it extends into the substrate (202) within the enclosure structure (212, 810) of the multilayer interconnect structure (208, 804), wherein the protective layer (1002, 2702) is arranged between the substrate via (214, 1302, 1802, 2802, 2902, 3202) and the enclosure structure (212, 810).

Description

background

[0001] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Throughout IC evolution, feature density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while feature size (i.e., the smallest component or trace that can be produced using a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production output and reducing associated costs.

[0002] This miniaturization has also increased the complexity of IC processing and manufacturing, and similar advancements in IC processing and manufacturing are needed to realize these progress. As part of semiconductor manufacturing, conductive elements can be created to provide electrical connections for various components within an IC. For example, metal traces and vias transmit signals from one component to another. While these metal traces and vias have been satisfactory in some respects, improvements in manufacturability, performance, and reliability are desirable.

[0003] A method and a device are known from DE 10 2019 130 124 A1. A method and a structure are known from US 2019 / 0079166 A1. Brief description of the drawings

[0004] The present invention is best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale and are for illustrative purposes only. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a flowchart showing an embodiment of a method for producing a conductive through-hole of a semiconductor device according to various aspects of the present invention. Fig. Figure 2A is a sectional view of an embodiment of a semiconductor device having a through-hole with an enclosure structure according to various aspects of the present invention, and which Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E and Fig. 2F are embodiments of a top view of a through-hole with an enclosure structure according to various aspects of the present invention. Fig. Figure 3 is a flowchart illustrating an embodiment of a method for manufacturing a semiconductor device with a multilayer interconnect (MLI) providing an enclosure structure, according to various aspects of the present invention. Fig. Figure 4 is a flowchart illustrating the steps of an exemplary method for fabricating a silicon through-hole (TSV) in an enclosure structure according to various aspects of the present invention, continuing the method of Fig. 3 shows. Fig. Figure 5 is a flowchart illustrating further steps of an exemplary method for fabricating a backside silicon through-hole (BSHD) in an enclosure structure according to various aspects of the present invention, continuing the method of Fig. 3 shows. The Fig. Figures 6 to 8 are schematic partial views of a partial or complete integrated circuit device at various manufacturing stages associated with the manufacture of an MLI with an enclosure structure according to various aspects of the present invention, which is related to the method of Fig. 3 correspond. The Fig. Figures 9 to 14 are schematic partial views of a partial or complete integrated circuit device at various manufacturing stages associated with the fabrication of a TSV in an enclosure structure according to various aspects of the present invention, which is related to the method of Fig. 4 correspond. The Fig. Figures 15 to 18 are schematic partial views of a partial or complete integrated circuit device at various manufacturing stages associated with the manufacture of a further TSV in an enclosure structure according to various aspects of the present invention, which is related to the method of Fig. 4 correspond. The Fig. Figures 19 to 28 are schematic partial views of a partial or complete integrated circuit device at various manufacturing stages associated with the manufacture of a TSV according to various aspects of the present invention, which is related to the method of Fig. 5 correspond. Fig. Figure 29 is a schematic partial view of a partial or complete integrated circuit device, designed according to various aspects of the present invention, including those which Fig. 5 correspond, is manufactured. The Fig. Figures 30 to 32 are schematic partial views of a partial or complete integrated circuit device at various manufacturing stages associated with the manufacture of a further TSV according to various aspects of the present invention, which is related to the method of Fig. 5 correspond. The Fig. 33 and Fig. Figure 34 are schematic partial views of another partial or complete integrated circuit device at various manufacturing stages associated with the manufacture of a TSV according to various aspects of the present invention, which is related to the method of Fig. 5 correspond. Fig. Figure 35 is a schematic partial view of a partial or complete integrated circuit device comprising a TSV or a BTSV according to one or more aspects of the present invention. Detailed description

[0005] The present invention relates generally to integrated circuit devices and in particular to interconnect structures for integrated circuit devices.

[0006] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact.

[0007] Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed. Moreover, the fabrication of an element on and / or in connection with another element in the present invention described below may include embodiments in which the elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the elements, so that the elements are not in direct contact.Furthermore, to simplify the description of the relationship between one element and another, spatially relative terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "under", "upwards", "downwards", "above", "below", etc., as well as their derivatives (e.g., the adverbs "horizontal", "downwards", "upwards", etc.) are used. These spatially relative terms are intended to cover different orientations of the device that the elements have.

[0008] An MLI element electrically connects various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or source / drain elements) so that the various devices and / or components can operate as specified by the design requirements. The MLI element has a combination of dielectric and conductive layers configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect elements, such as device-level contacts and / or vias, and / or horizontal interconnect elements, such as conductive traces, also referred to as metal layers. Vertical interconnect elements typically connect horizontal interconnect elements in different layers (or different levels) of the MLI element.A typical semiconductor device can have multiple conductive layers, such as multiple layers (or levels) that provide a multi-layer interconnect (MLI). For example, in some implementations, semiconductor devices have a dozen or more levels of horizontal interconnects, metal traces with vertically extending interconnects between them, and vias. During operation of the IC device, the interconnect structures transmit signals between the devices and / or components of the IC, and / or they distribute signals (for example, clock signals, voltage signals, and / or ground signals) to the devices and / or components. An MLI is fabricated in a back-end-of-line (BEOL) process, usually after active devices, such as transistors, have been fabricated on a substrate using a front-end-of-line (FEOL) process.The BEOL process can begin with an initial interconnect over the active device (e.g., an initial via Vo or a first metal conductor M1), or one or more layers can be fabricated over the active device before the BEOL process is carried out.

[0009] In some implementations of semiconductor devices, it is desirable to provide a vertical interconnect that extends through different layers and / or the substrate of the semiconductor device. Such a vertical interconnect may be referred to as a silicon or substrate through-hole (TSV) because it extends completely or partially through the semiconductor substrate (which is typically, though not exclusively, silicon). In some implementations, TSVs are made from a back side of the device (and are referred to as backside TSVs or BTSVs). The term “TSV” in the present invention broadly encompasses electrical connections made from both the front and back sides of the substrate.

[0010] A TSV (transistor-type interconnect) can establish an electrical connection that offers an alternative to other connection methods (e.g., wire bonding). In some implementations, 3D packages or integrated circuits can be fabricated using a TSV, enabling devices on different substrates to be interconnected. A TSV provides a robust connection, allowing for higher device density and shorter connection paths. Integrating a TSV can improve device performance, for example, by reducing RC delay. Various semiconductor devices are suitable for TSVs such as those of the present invention, including CMOS image sensors (CISs; CMOS: complementary metal oxide semiconductor), 3D packages, 3D ICs, MEMS devices (MEMS: microelectromechanical system), RF devices, wafer-on-wafer (WoW) devices, and the like.

[0011] However, due to the methods and structures used to fabricate TSVs, which can extend over relatively large distances, problems can arise during TSV fabrication, for example, during the etching of openings / holes and the filling of these openings. In some implementations, the TSV must traverse dielectric materials that can be damaged by etching and deposition processes. For example, extremely low k dielectric materials (ELK materials) can be implemented in an MLI to provide mechanical stability and electrical insulation for conductive traces and vias. However, the ELK materials can be damaged by the etching and deposition processes used to fabricate TSVs that extend through some or all of the ELK materials in the MLI.For example, etching openings or holes for TSVs can lead to layer delamination and / or other damage to the dielectric materials, such as the ELK materials, in which the TSVs are manufactured. Furthermore, the conductive material (e.g., copper) intended for manufacturing the TSVs can undesirably diffuse into the dielectric materials, resulting in contamination and / or an undesirable modification of the material's conductivity.

[0012] In embodiments of the present invention, a TSV is enclosed by a containment structure. The containment structure is positioned between the TSV and enclosing materials (e.g., dielectrics such as ILD layers). The containment structure is fabricated in conjunction with the conductive layers (vias and metal layers) of the MLI. Thus, the containment structures are fabricated coplanar with the vias and metal layers in the MLI, and they can comprise the same materials (e.g., metals). In some implementations, the containment structures reduce layer delamination or damage to dielectric materials, providing a protective enclosure, also referred to as a ring or sleeve, around the area where etching is performed to fabricate a TSV.In some implementations, a reduction and / or elimination of metal (e.g., Cu) diffusion can be achieved by creating a protective barrier layer (e.g., a dielectric) between the TSV and the enclosure structure. In some implementations, the protective barrier layer (e.g., the dielectric) between the TSV sidewalls and the enclosure structure (both of which are metals) acts in such a way as to reduce the stress caused by metallization. Different embodiments may have different advantages, and no single embodiment requires a specific advantage.

[0013] Fig. Figure 1 is a flowchart showing a method 100 for producing a conductive through-hole, such as a TSV, according to various aspects of the present invention. Fig. Figure 2A is a schematic partial sectional view of a partial or complete integrated circuit device 200 according to various aspects of the present invention. The integrated circuit device 200 may be contained in a microprocessor, a memory, and / or another integrated circuit device.In some implementations, the integrated circuit device 200 is part of an IC chip, a system-on-chip (SoC), or a part thereof, which incorporates various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), CMOS transistors (complementary metal-oxide-semiconductor), bipolar junction transistors (BJTs), low-density MOS transistors (LDMOS transistors), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The transistors can be planar transistors or multi-gate transistors, such as fin FETs (FinFETs) or gate-all-around transistors (GAA transistors).GAA transistors can have channel regions with various shapes, such as nanowires, nanorods, or nanolayers, which are collectively referred to as nanostructures. Fig. For the sake of clarity, Figure 2A has been simplified to better illustrate the inventive concepts of the present invention. Further elements can be added to the integrated circuit device 200, and some of the elements described below can be replaced, modified, or omitted in other embodiments of the integrated circuit device 200.

[0014] Procedure 100 begins with a block 102 in which a substrate is provided. In the example of Fig. In 2A, the integrated circuit device 200 comprises a substrate (wafer) 202. In one embodiment, the substrate 202 comprises silicon. Alternatively or additionally, the substrate 202 comprises: another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Alternatively, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.Semiconductor-on-insulator substrates can be fabricated by separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the integrated circuit device, the substrate 202 can have 200 different doped regions (not shown). In some implementations, the substrate 202 has n-doped regions (e.g., n-wells) doped with n-doped elements such as phosphorus, arsenic, other n-doped elements, or combinations thereof. In some embodiments, the substrate 202 has doped regions fabricated with a combination of p- and n-doped elements. The various doped regions can be created directly on and / or within the substrate 202, resulting, for example, in a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof.To create the different doped areas, an implantation process, a diffusion process and / or other suitable doping processes can be carried out.

[0015] One or more insulating elements 203 are formed on and / or within the substrate 202 to isolate different areas, such as different component areas, of the integrated circuit device 200. For example, the insulating elements 203 define active and / or passive device areas and electrically isolate them from one another. The insulating elements 203 contain silicon oxide, silicon nitride, silicon oxide nitride, other suitable insulating materials (such as silicon, oxygen, nitrogen, carbon, or other suitable insulating components), or combinations thereof. The insulating elements 203 can have different structures, such as STI structures (STI: shallow trench insulation), DTI structures (DTI: deep trench insulation), and / or LOCOS structures (LOCOS: local oxidation of silicon).In some implementations, the insulating elements 203 are produced by creating a trench in the substrate 202 (for example, using a dry and / or wet etching process) and then filling the trench with an insulating material, for example, using a CVD (chemical vapor deposition) or spin-on-glass process. A CMP (chemical-mechanical polishing) process can be performed to remove excess insulating material and / or to planarize the top surface of the insulating elements 203. In some implementations, the insulating elements 203 can be produced by depositing an insulating material over the substrate after fins have been produced (in some implementations, such that the insulating material fills gaps or trenches between the fins) and then back-etching the layer of insulating material.In some implementations, the insulating elements 203 have a multilayer structure that fills the trenches, such as a solid dielectric layer arranged over a dielectric coating layer, wherein the solid dielectric layer and the dielectric coating layer comprise materials that depend on the design requirements (for example, the solid dielectric layer comprises silicon nitride and is arranged over a dielectric coating layer of thermal oxide). In some implementations, the insulating elements 203 have a dielectric layer arranged over a doped coating layer containing, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG). In the representation of . Fig. In 2A, the insulating elements 203 are arranged between a TSV 214 (which will be discussed later) and an active device 204 (which will also be discussed later), but other configurations are also possible, including those in which the TSV 214 passes through the insulating elements 203 (see e.g. Fig. 15 to 18).

[0016] The device 204 is arranged on the substrate 202. The device 204 can be an n- or p-type field-effect transistor (n- or p-FET). The device 204 has a gate structure 204A arranged over the substrate 202. The gate structure is located between a source region 204B and a drain region 204B, with a channel region defined between the source region 204B and the drain region 204B. The gate structure 204A extends into the channel region, allowing current to flow between the source / drain regions during operation. In some embodiments, the gate structure 204A is manufactured over a fin structure, such that the gate structure 204A encloses part of the fin structure. For example, the gate structure 204A encloses a channel region of the fin structure, thus placing it between a source region and a drain region of the fin structure.In some implementations, the gate structure 204A is fabricated over a plurality of nanostructures such that it encloses them, specifically each of the nanostructures located between a source region and a drain region, forming the channel regions within the nanostructures. The gate structure 204A features a gate stack configured to provide desired functionality according to the design requirements of the integrated circuit device 200. In some implementations, the gate stack includes a gate dielectric (for example, a dielectric gate layer) and a gate electrode (for example, a discharge layer and / or a solid conductive layer). The gate stack may also include numerous other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof.In some implementations, the dielectric gate layer is positioned over an interface layer (which incorporates a dielectric material such as silicon dioxide), and the gate electrode is positioned over the dielectric gate layer. The dielectric gate layer may contain a dielectric material such as silicon dioxide, a high-k dielectric material, another suitable dielectric material, or combinations thereof. Examples of high-k dielectric materials include hafnium oxide (HfO₂), HfSiO₂, HfSiON₄, HfTaO₂, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃ alloy), other suitable high-k dielectric materials, or combinations thereof. In some implementations, the dielectric gate layer of gate structure 204A is a high-k dielectric layer.The gate electrode of the 204A gate structure contains a conductive material such as polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some implementations, the work function layer is a conductive layer adapted to have a desired work function (such as an n-type or p-type work function), and the conductive solid layer is a conductive layer fabricated above the work function layer. In some implementations, the exit layer features n exit materials, such as Ti, silver (Ag), TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, manganese (Mn), zirconium (Zr), other suitable n exit materials, or combinations thereof.In some implementations, the exit layer comprises p-exit materials, such as TiN, TaN, ruthenium (Ru), Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-exit materials, or combinations thereof. The solid conductive layer (or conductive filler layer) comprises a suitable conductive material, such as Al, W, and / or Cu. The solid conductive layer may additionally or collectively comprise polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof. The present invention also considers embodiments in which the dielectric gate layer, the exit layer, the solid conductive layer, and / or other layers of the gate stack have a multilayer structure.

[0017] The gate structure 204A is fabricated using deposition processes, lithography, etching, other suitable processes, or combinations thereof. Deposition processes include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma-ceramic (HDP-CVD), metal-organic CVD (MOCVD), remote plasma plated CVD (RPCVD), plasma-assisted CVD (PECVD), low-pressure gravure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable processes, or combinations thereof. Lithographic structuring processes include resist coating (e.g., spin coating), pre-curing, mask adjustment, exposure, post-exposure curing, resist development, rinsing, drying (e.g., post-curing), other suitable processes, or combinations thereof.Alternatively, the lithographic exposure process is supported, implemented, or replaced by other methods, such as maskless lithography, electron beam writing, or ion beam writing. Etching processes include dry etching, wet etching, other etching processes, or combinations thereof. The 204A gate structure is fabricated using a gate-last process, a gate-first process, or a gate-last / gate-first hybrid process.

[0018] The gate structure 204A also features gate spacers, each arranged adjacent to the gate stack (e.g., along its sidewalls). The gate spacers are fabricated using a suitable method and comprise a dielectric material. The dielectric material can be silicon, oxygen, carbon, nitrogen, another suitable dielectric material, or a combination thereof (for example, silicon oxide, silicon nitride, silicon oxide nitride, or silicon carbide). After deposition of the dielectric material, it can be anisotropically etched to fabricate the gate spacers. In some implementations, the gate spacers have a multilayer structure. In some implementations, more than one group of spacers, such as gasket spacers, offset spacers, sacrificial spacers, dummy spacers, and / or principal spacers, are fabricated adjacent to the gate stack.Depending on the design requirements of the integrated circuit device, 200 source / drain regions 204B with lightly doped source and drain elements (LDD elements) and / or heavily doped source and drain elements (HDD elements) can be produced on the substrate 202 (e.g., in the substrate, on or in a fin extending from the substrate, or the like) using epitaxial growth, implantation, diffusion, and / or annealing processes. For an epitaxial process, CVD deposition methods [e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD], molecular beam epitaxy, other suitable SEG (selective epitaxial growth) methods, or combinations thereof can be implemented. The source / drain elements 204B are doped with n- and / or p-type dopants. If a transistor is, for example, an n-device (which is, for example,In another example, where the transistor is configured as a p-device (which has, for example, a p-channel), the source / drain elements can be 204B epitaxial layers containing silicon and / or carbon, with silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers being doped with phosphorus, another n-doped element, or combinations thereof (resulting, for example, in a Si:P epitaxial layer or a Si:C:P epitaxial layer). In another example, where the transistor is configured as a p-device (which has, for example, a p-channel), the source / drain elements are 204B epitaxial layers containing silicon and germanium, with the silicon-germanium-containing epitaxial layers being doped with boron, another p-doped element, or combinations thereof (resulting, for example, in a Si:Ge:B epitaxial layer).

[0019] Method 100 then proceeds to a block 104, in which an MLI is fabricated over the substrate. The MLI is fabricated in a BEOL process, typically after active devices, such as a transistor 204, have been fabricated on the substrate 202 in a FEOL process. As outlined above, an MLI is fabricated using BEOL processes, such as fabricating conductive layers that allow tracing and interconnection between devices fabricated on the substrate. In addition to fabricating the electrical connections to / from the device by means of horizontally extending metal traces and vertically extending vias or contacts, as described above in block 102, the fabrication of the MLI in block 104 includes defining and fabricating a structure to enclose a via.This structure can be described here as an enclosure or enclosing structure, or as a ring or sleeve. The enclosure structure is described in more detail below.

[0020] During the fabrication of MLI, a plurality of interlayer dielectric layers (ILD layers) are produced over the substrate. The ILD layers can have the same or different compositions. A metal element, e.g., a metal conductor and / or via, is fabricated in each ILD layer. In the example of Fig. Figure 2 shows that ILD layers are collectively represented as an ILD layer 206 fabricated over substrate 202, wherein the ILD layer 206 contains dielectric materials such as silicon oxide, silicon nitride, silicon oxide nitride, TEOS oxide (TEOS: tetraethyl orthosilicate), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), a low-k dielectric material, another suitable dielectric material, or combinations thereof. Examples of low-k dielectric materials include fluorosilicate glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (bisbenzocyclobutene), polyimides, other low-k dielectric materials, or combinations thereof. In some implementations, the ILD layer 206 has a multilayer structure with several dielectric materials.In some implementations, for example, etch stop layers (ESLs), such as a contact etch stop layer (CESL), are arranged between portions of the ILD layer 206 and / or between the ILD layer 206 and the device 204 or the substrate 202. The ESL / CESL may be made of a different material than other parts of the ILD layer 206. In one embodiment, the ILD layer 206 has one or more parts made of dielectric low-k material, and an ESL / CESL part has silicon and nitrogen (e.g., silicon nitride or silicon oxide nitride). The ILD layer 206 is produced over the substrate 202, for example, by a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof).In some implementations, the ILD layer 206 is fabricated using a flowable CVD process (FCVD), which includes, for example, depositing a flowable material (such as a liquid compound) onto the substrate 202 and converting the flowable material into a solid using a suitable method, such as thermal annealing and / or UV irradiation. The ILD layer 206 can be fabricated as follows: performing several deposition steps; subsequently structuring the ILD layer 206 to define conductive structural elements to be fabricated within the ILD layer 206; fabricating the conductive structural elements; and performing planarization and / or other suitable processes.

[0021] As proposed above, fabricating the MLI involves defining and fabricating conductive traces 208A and vias 208B embedded in the ILD layer 206. The conductive layers are configured to form vertical interconnect elements, such as device-level contacts 208B (contacting a source / drain 204B) and / or the vias 208B, and / or horizontal interconnect elements, such as the conductive traces 208A. The vertical interconnect elements 208B typically connect horizontal interconnect elements in different layers (or different levels) of an MLI element 120.The interconnect structures 208A and 208B are configured to transmit signals between the devices, including device 204, and / or the components of the integrated circuit device 200 during operation, and / or to distribute signals (for example, clock signals, voltage signals, and / or ground signals) to the devices and / or the components of the integrated circuit device 200. In some implementations, the conductive traces or vias are created by depositing conductive material such as copper, aluminum, tungsten, and / or other suitable conductive materials into channels or openings created in a respective layer of ILD material, as described above.In some implementations, the conductive interconnect elements have a multilayer structure, which includes, for example, seed layers, adhesion accelerator layers, barrier layers, and the like. The MLI structure, MLI 208, is one example. Fig. 2A, has the conductive structural elements 208A and 208B and the surrounding dielectric 206.

[0022] In method 100, fabricating the MLI further comprises defining an enclosure structure for enclosing a (subsequently fabricated) via (e.g., a silicon via or TSV) according to one or more aspects of the present invention. The enclosure structure is fabricated simultaneously with the conductive traces and vias. The enclosure structure is fabricated from a plurality of layers, each of which is fabricated in the same plane as the vias and metal traces of the MLI. All layers of the enclosure structure can be fabricated simultaneously, and they can comprise the same materials (e.g., a conductive material such as copper, aluminum, tungsten, and / or other suitable conductive materials) as the corresponding via and / or metal trace of that layer.All layers of the enclosure structure together form a continuous metal-containing structure (e.g., a ring or a sleeve) that extends up to the height of the MLI.

[0023] In the example of Fig. 2A is an enclosure structure 212 of the MLI 208 shown. The enclosure structure 212 is an element that has a metal-containing material and extends through the ILD layer 206 in pretty much the same way as the conductive lines 208A and the vias 208B that have been discussed above and will be described again later.

[0024] The MLI 208 can, for example, be fabricated in successive layers, as described above. In some implementations, after the deposition of a portion of the ILD layer 206, the ILD layer 206 is structured to create openings in that portion, where the openings correspond to the conductive traces and / or vias, and one opening corresponds to a portion of the encapsulation structure 212. The fabrication of the conductive parts of the MLI 208 can be performed using a single- or a dual-damascene process.

[0025] In one embodiment, the structuring process for the ILD layer 206 or its layers comprises lithography processes and / or etching processes. For example, creating openings comprises performing a lithography process to create a structured resist layer over a portion of the ILD layer 206 and performing an etching process to transfer a structure defined in the structured resist layer to the ILD layer 206. The lithography process may include: creating a resist layer on the ILD layer 206 (for example, by spin coating); performing a pre-curing process; performing an exposure process using a mask; performing a post-curing process; and performing a development process.During the exposure process, the resist layer is irradiated with radiation energy, such as UV light, deep UV light (DUV light), or extreme UV light (EUV light). Depending on its structure and / or type (e.g., binary mask, phase-shift mask, or EUV mask), the mask blocks, transmits, and / or reflects radiation to the resist layer, projecting an image onto the resist layer that corresponds to the mask structure. Because the resist layer is sensitive to radiation energy, exposed portions of the resist layer undergo chemical changes, and exposed (or unexposed) portions of the resist layer dissolve during the development process, depending on the properties of the resist layer and the properties of the developer solution used. After development, the structured photoresist layer exhibits a resist structure that corresponds to the mask.In the etching process, the structured resist layer is used as an etching mask to remove portions of the ILD layer 206, creating openings or channels. These channels may correspond to a conductive path from the device 204 and may also include channels corresponding to the enclosure structure 212. The etching process can be a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. After the etching process, the structured resist layer is removed from the ILD layer 206, for example, by a resist removal process.

[0026] The process continues with the deposition of one or more conductive materials in the etched channels of the ILD layer 206. In one implementation, a first via is defined using the structuring and etching processes, and a first metal conductor is defined in an ILD layer using a subsequent structuring and etching process, creating a through-hole that defines the via and the metal conductor (e.g., using a dual-damascene process). In this process, the defined first via and the defined first metal conductor are filled simultaneously. The portion of the encapsulation structure 212 that is coplanar with the individual conductive structural elements (e.g., via and conductor) is fabricated concurrently with the respective structural element (e.g., via or conductor). In other implementations, a single layer of a conductive structural element (e.g.,The conductive structural element (via or via) and the corresponding layer of the enclosure structure 212 are fabricated independently of the adjacent metallization layer using a single-damascene process. Here too, the portion of the enclosure structure 212 that is coplanar with the conductive structural element and enables the transmission of electrical signals from the device 204 (e.g., via or via) is fabricated simultaneously with the conductive structural element.

[0027] The filling of channels in the ILD layer (e.g., to create vias, metal conductors, and layers of the enclosure structure 212) can be achieved by depositing one or more conductive materials. The one or more conductive materials can be deposited using a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable processes, or combinations thereof). The conductive structural elements can be multilayered and can incorporate a suitable conductive material such as Ta, Ti, Al, Cu, Co, TaN, TiN, TaN, and / or other suitable conductive materials. In some implementations, for example, a coating or barrier layer (e.g., TiN, TaN, or WN) is deposited (e.g., by PVD or ALD), followed by the deposition of a seed layer and a conductive filler material (e.g., copper).A CMP step removes excess metal to complete the interconnect layer. In some implementations, a capping layer or ESL (e.g., SiCN) is fabricated over the planarized surface. These processes are repeated until each MLI layer is fabricated.

[0028] The enclosure structure 212, which in some implementations is fabricated with the MLI 208, is a continuous structure extending from a bottom surface of the ILD layer 206 to its top surface. That is, in some implementations, the MLI 208 has x via layers (e.g., V0, V1, V2, etc.) and y metal layers (e.g., M1, M2, M3, etc.). In one embodiment, the enclosure structure 212 has parts / layers fabricated on each of the x via layers and each of the y metal layers. In another embodiment, the enclosure structure 212 has parts fabricated on each of (x - 1) via layers and each of the y metal layers.The enclosure structure 212, for example, cannot extend coplanarly with a first-contact-plane interconnect, such as a vertically extending contact that extends from the source / drain 204B upwards to a first metallization element of the MLI 208 (e.g., a bottom via 208B).

[0029] The enclosure structure 212 provides a covering or ring that encloses a subsequently fabricated through-hole (e.g., a TSV). The term "ring" used here does not require a structure with an inner and an outer rim that are ring-shaped and thus curvilinear. Rather, the enclosure structure can have various shapes that, in plan view, enclose the through-hole (which can also have various shapes). Fig. Figure 2B is an embodiment of the enclosure structure 212 in a top view, showing that the enclosure structure 212 is essentially annular. However, for example, due to lithographic limitations and / or processes (e.g., metal filling), it may be desirable or necessary to provide edges of the enclosure structure 212 that form a different shape. Fig. 2C, Fig. 2D, Fig. 2E and Fig. Figure 2F shows top views of embodiments of the enclosure structure 212, which are essentially polygonal. The shape of the enclosure structure 212 is determined by the structuring discussed above. For example, the channels in the ILD layer 206, corresponding to a given layer of the enclosure structure 212, are defined by the lithography process.

[0030] Method 100 then proceeds to a block 108, in which a conductive via is fabricated within the via enclosure structure created using the MLI in block 104. The conductive via can be defined as providing an electrical path from an exposed top surface of the device to and / or through the substrate. For example, it provides an electrical path from the top surface of the device to its back surface. This type of via can be referred to as a substrate via or a silicon via (TSV). In the example of Fig. In 2A, the via 214 extends from a top surface of the device 200, in particular the top surface of the ILD 206, to the back surface of the substrate 202. The via 214 is referred to as a TSV 214. The TSV 214 is provided within the enclosure structure 212. Therefore, in some implementations, the TSV 214 itself does not contact the ILD 206, but is largely separated from the ILD 206 by the enclosure structure 212. In some implementations, the TSV 214 is directly adjacent to the enclosure structure 212, and in other embodiments, which will be discussed later, a protective layer is created between the enclosure structure 212 and the ILD 206. The ILD 206 may be completely absent from the enclosure structure 212.

[0031] In one embodiment, the TSV 214 is produced by structuring, etching an opening, and filling the opening with one or more conductive materials. The etching process may include lithography and / or etching processes. For example, the opening for the TSV 214 can be created by performing a lithography process to produce a structured resist layer over the ILD layer 206 and an etching process to transfer a structure defined in the structured resist layer to the ILD layer 206 and underlying layers and / or to the substrate 202. The lithography process may include: producing a resist layer on the ILD layer 206 (e.g., by spin coating), performing a pre-curing process, performing an exposure process using a mask, performing a post-curing process, and performing a development process.During the exposure process, the resist layer is irradiated with radiation energy such as UV, DUV, or EUV light. Depending on its structure and / or type (e.g., binary mask, phase-shift mask, or EUV mask), the mask blocks, transmits, and / or reflects radiation to the resist layer, projecting an image onto the resist layer that corresponds to the mask structure. Because the resist layer is sensitive to radiation energy, exposed portions of the resist layer undergo chemical changes. These exposed (or unexposed) portions dissolve during the development process, depending on the properties of the resist layer and the developer solution used. After development, the structured photoresist layer exhibits a resist structure that corresponds to the mask.In the etching process, the structured resist layer is used as an etching mask to remove portions of the ILD layer 206 and the underlying substrate 202. The etching process can be a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. After the etching process, the structured resist layer is removed from the ILD layer 206, for example, by a resist removal process.

[0032] The opening etched for the TSV 214 is then filled with various layers, including protective layers, barrier layers, and one or more conductive filler materials. These layers will be discussed in more detail later. After filling the TSV 214 with the one or more conductive materials, excess material can be removed using a planarization process. In some implementations, the substrate 202 is then thinned from the back side to expose one end of the TSV 214.

[0033] It should be noted that although the TSV is manufactured within the enclosure structure 212, the TSV 214 does not need to be positioned centrally (e.g., its central axis does not need to coincide with that of the enclosure structure 212). As in Fig. As shown in Figure 2E, the TSV 214 can be displaced to one side of the enclosure structure 212. In another embodiment, which is shown in Figure 2E, the TSV 214 can be displaced to one side of the enclosure structure 212. Fig. As shown in Figure 2F, the TSV 214 is manufactured within the enclosure structure 212. However, a portion of the ILD layer 206, designated ILD 206', remains between the TSV 214 and the enclosure structure 212. It should be noted that the ILD 206' is separated from the rest of the ILD 206 by the enclosure structure 212. In some embodiments, a protective layer is manufactured between the TSV 214 and the enclosure structure 212.

[0034] Connections to other conductive structural elements, such as other metal conductors, bond pads, conductive contact bumps or other input / output elements, and / or other suitable connections can be made on the top and / or bottom of the TSV 214.

[0035] Exemplary apparatus 200 and exemplary method 100 provide embodiments in which, during the fabrication of the TSV (e.g., TSV 214), the dielectric layer (e.g., the ILD 206) is protected against damage, such as layer delamination, by the enclosing structure (e.g., the enclosing structure 212). The enclosing structure provides a covering for the TSV, thus reducing damage to the enclosing materials (e.g., the ILD layer) during etching and / or filling of the TSV. The enclosing structure offers advantages such as reduced ILD layer delamination. Advantages of the structural elements of apparatus 200 and / or method 100 include a reduction in the diffusion of conductive material (e.g., copper) in the TSV into the enclosing areas (e.g., the ILD layer).The methods and / or devices also allow for performance improvements, such as RC enhancement. By preventing damage to the ILD layer in some embodiments, the extremely low k-dielectric materials suitable for use in the ILD layer, but easily damaged by processes such as etching the opening for the TSV, can be protected.

[0036] Now let's move on to... Fig. Figure 3, in which a method 300 for manufacturing an MLI with an enclosure structure is described. The manufactured enclosure structure surrounds an area of ​​the device in which a through-hole connection, such as a TSV, is subsequently manufactured. Method 300 represents an exemplary embodiment of method 100 of Fig. 1. The enclosure structure produced in process 300 is essentially similar to the enclosure structure 212 discussed above. Process 300 is only an example and may include steps other than those listed.

[0037] Process 300 begins with a block 302 in which a substrate is provided. Block 302 may be substantially similar to block 102 described above in Process 100. Fig. 1 has been discussed. The provided substrate can essentially be compared to substrate 202 of Fig. 2A may be similar. In one embodiment, the substrate is, for example, a silicon substrate (or a wafer). In the example of Fig. Figure 6 includes a device 600 that holds the substrate 202. The device 600 can be substantially similar to the device 200 discussed above.

[0038] Method 300 then proceeds to a block 304 in which a device (e.g., an active device) is fabricated on the substrate. The device may be an n-type or a p-type field-effect transistor (FET). In one embodiment, the device may be a fin-type field-effect transistor (FinFET), a gate-all-around transistor (GAA transistor), and / or another type of semiconductor device, including, but not limited to, a capacitor, a resistor, a storage element, a junction, an image component, and / or another element. In the example of Fig. 6. A device 204 (e.g., a FET) has a gate structure 204A and corresponding source / drain regions 204B, and it is fabricated on the substrate 202. The device 204 with the gate structure 204A and the source / drain regions 204B can be substantially as described above.

[0039] The process 300 then proceeds to a block 306, in which a first dielectric layer is deposited over the substrate. The first dielectric layer can be a first ILD layer. In the example of Fig. In section 6, a dielectric layer 602 is produced over the substrate 202. The dielectric layer 602 can be substantially similar to a portion of the dielectric layer 206 described above with reference to Fig. 2A has been discussed. In one embodiment, the dielectric layer 602 comprises a dielectric material such as silicon oxide, silicon nitride, silicon oxide nitride, TEOS oxide, PSG, BPSG, a low-k dielectric material, another suitable dielectric material, or combinations thereof. Examples of low-k dielectric materials include FSG, carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB, polyimides, other low-k dielectric materials, or combinations thereof. In some implementations, the dielectric layer 602 has a multilayer structure with several dielectric materials, such as a contact etch stop layer (CESL). In one embodiment, the dielectric layer 602 comprises a low-k dielectric material and a silicon-nitrogen CESL (for example, silicon nitride or silicon oxide nitride).The dielectric layer 602 is produced, for example, by a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof) over the substrate 202. In one embodiment, the material of the dielectric layer 602 differs from that of the ILD layers (e.g., 702) located above it. The dielectric layer 602 can, for example, have a composition that exhibits a different etch selectivity than the dielectric layer 702 located above it.

[0040] The process 300 then proceeds to a block 308, in which a first contact structure is produced in the first dielectric layer. The first contact structure can establish an electrical connection with the device produced in block 304 and / or a part thereof. In the example of Fig. In one embodiment, a first contact structure 604 is manufactured such that it extends through the dielectric layer 602 to the source / drain element 204B of the device 204. The first contact element 604 comprises a conductive material such as titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), tantalum nitride (TaN), and / or other suitable materials. In some implementations, the contact element 604 comprises a coating layer (e.g., a barrier layer) such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN), tantalum nitride (TaN), and / or other materials. The contact element 604 can be produced by structuring the dielectric layer 602 to create a trench or opening which is subsequently filled with a conductive material as described above for the MLI 208.In some implementations, a silicide layer is produced between the first contact element 604 and the source / drain 204B. The contact element 604 can be essentially similar to the lower via 208B of the device 200, which is described above with reference to... Fig. 2A has been discussed.

[0041] The process 300 then proceeds to a block 310 in which another dielectric layer is produced. The additional dielectric layer can be a dielectric ILD layer, which has been discussed above. In the example of Fig. In 7, a dielectric layer 702 is produced over the substrate 202. The dielectric layer 702 can be substantially similar to a portion of the dielectric layer 206 described above with reference to Fig. 2A has been discussed. In one embodiment, the dielectric layer 702 comprises a dielectric material such as silicon oxide, silicon nitride, silicon oxide nitride, TEOS oxide, PSG, BPSG, a low-k dielectric material, another suitable dielectric material, or combinations thereof. Examples of low-k dielectric materials include FSG, carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB, polyimides, other low-k dielectric materials, or combinations thereof. In some implementations, the dielectric layer 702 has a multilayer structure. The dielectric layer 702 is produced, for example, by a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof) over the substrate 202.

[0042] The process 300 then proceeds to a block 312 in which a metallization layer of the MLI is fabricated. The metallization layer may include a vertically extending via (e.g., V0) and / or a horizontally extending metal conductor (e.g., M1) of an MLI, enabling electrical signals to and from the device 200 to be transmitted. According to aspects of the present invention, fabricating the metallization layer of the MLI further comprises fabricating an element that provides a component (or part or layer) of an enclosure structure for a TSV. The metallization layer of the MLI can be fabricated substantially as described above, such as by lithography, etching, and deposition processes to create channels in the dielectric layer, which are then filled with one or more conductive materials in a single- or dual-damascene process.

[0043] In the example of Fig. In the dielectric layer 702, a first conductive structural element 704 is fabricated. The first conductive structural element 704 has a conductive via 704A and a conductive metal conductor 704B. The conductive via 704A and the conductive metal conductor 704B can be fabricated in a dual-damascene process. In one embodiment, the conductive via 704A and the conductive metal conductor 704B are each fabricated separately in a single-damascene process. The conductive via 704A and the conductive metal conductor 704B form conductive structural elements that enable transmission to and from the device 204.

[0044] As in Fig. As shown in Figure 7, a second structural element 706 is fabricated in the metallization layer of the MLI structure. The second structural element 706 has a first part 706A, which is fabricated coplanarly with the first via 704A, and a second part 706B, which is fabricated coplanarly with the first metal conductor 704B. The first and second structural elements 704 and 706 can be fabricated simultaneously with the first via 704A and the first metal conductor 704B, respectively, for example, in a dual or a single damascene process. The second structural element 706 provides a first layer or part of an enclosure structure that is essentially similar to the enclosure structure 212 discussed above. That is, the second structural element 706 encloses a region of the dielectric 702 in which a via (e.g., a TSV) is subsequently fabricated.As shown in the inset image of the top view, the second structural element 706 can be ring-shaped with parts 706A and 706B, but other configurations of a ring enclosing the via area are also possible, which are described above with reference to the . Fig. 2B to 2F have been discussed. It should also be noted that in the second structural element 706, which forms part of the enclosure structure, the first part 706A has a width that is smaller than that of the second part 706B, wherein the first part 706A is fabricated on the via plane of the MLI and the second part 706B is fabricated on the metal layer plane of the MLI. In other embodiments, the width of the first part 706A may differ from the width of the second part 706B. For example, the width of part 706B may be smaller than the width of part 706A.

[0045] The first structural element 704 and the second structural element 706 of the MLI can consist of a metal or a conductive material. The first structural element 704 and / or the second structural element 706 can each be a multilayer structure, for example with coating layers and / or metallization layers, as described above for the conductive layers 208A and 208B and the enclosing structure 212 of Fig. 2A have been discussed. Examples of conductive materials are titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), tantalum nitride (TaN), iridium (Ir), rhenium (Re), aluminum (Al), silver (Ag) and / or other suitable materials.

[0046] The process 300 then proceeds to block 314, where it is decided whether to fabricate further layers of the MLI in the BEOL processes to create the intended semiconductor device. The MLI can have multiple layers or levels, for example, a dozen or more conductive layers or levels that allow horizontal tracing (metal conductors M1, M2, M3, etc.). If further layers are to be fabricated, the process 300 returns to block 310, where another dielectric layer is deposited (and, in some implementations, planarized), and the process 300 then proceeds to block 312, where another metallization layer (e.g., a via and / or a metal conductor) is fabricated in the dielectric layer. The further layers have a tracing component that is connected to the device 204 (e.g.,vias and metal traces), and a corresponding part or layer of the encapsulation structure. These steps are continued until an upper metallization layer is produced.

[0047] In the example of Fig. 8 Blocks 310 and 312 are repeated to produce a plurality of metallization layers and intermediate vias with a corresponding part of the enclosure structure at each level, providing vias and metal leads of the MLI. Fig. Figure 8 shows an MLI structure 804, which has a path providing electrical signals for the device 204, which has the first via 704A, the first metal conductor 704B, and subsequent vias 802A and metal conductors 802B. The vias 802A and the metal conductors 802B are made in dielectric layers 806. The dielectric layers 806 can be substantially similar to layer 702. The vias 802A and the metal conductors 802B can be substantially similar to the first via 704A and the first metal conductor 704B, respectively. The device of Fig. Figure 8 shows six (6) additional metallization layers in addition to the first via 704A and the first metal conductor 704B to produce an MLI with seven (7) metallization layers (with seven vias in between), but this is only an example and any number of layers can be produced.

[0048] For each layer of the MLI structure 804 that provides a conductive via 802A or a conductive metal conductor 802B, there is a part of the enclosure structure coplanar with the respective via 802A or metal conductor 802B, designated as a part or layer 808A corresponding to the plane of the vias 802A, and a part or layer 808B corresponding to the plane of the metal conductors 802B. In some embodiments, parts 808A and 808B are substantially similar to part 706A and part 706B, respectively. For example, the Fig. The top view shown in Figure 7 applies similarly to each of the parts 808A and 808B. In other embodiments, the parts 808A and 808B may have different configurations. However, in some embodiments, the parts 706A, 706B, 808A, and 808B together form an enclosure structure 810 of continuous conductive material that encloses a central region of the dielectric 806 or 702, respectively, in which a via (e.g., a TSV) may be made. The enclosure structure 810 may also be referred to as a ring or a sleeve. In some implementations, the parts 706A, 706B, 808A, and 808B of the enclosure structure 810 may be aligned with each other, while in other implementations, the parts 706A, 706B, 808A, and 808B may be vertically offset, as shown in Figure 7. Fig. Figure 35 shows that in some implementations a continuous metal-containing enclosure structure 810 is provided, which extends vertically and in a ring shape around part of the dielectric layer 806.

[0049] Procedure 300, which is in Fig. 3 is shown and with the device 600 of the Fig. 6, Fig. 7 and Fig. Figure 8 illustrates that the device can be used in different embodiments to create a through-hole connection through the enclosure structure produced by method 300. In particular, the TSV can be produced in the enclosure structure 810 in different ways. Some of these embodiments are discussed below.

[0050] In Fig. Figure 4 shows a method 400 which, in some embodiments, is adapted from method 300 for producing a TSV in the enclosure structure 810 produced by method 300. Fig. 3 can be connected (e.g., from B to B1). An embodiment of method 400 is described using the example of a device 600b in the Fig. Explained in sections 9 to 14. Device 600b is an embodiment of device 600 which has a TSV.

[0051] In block 402 of process 400, an opening is created such that it extends through dielectric layers of an MLI in a region within an enclosure structure. In the example of Fig. 9 creates an opening 904 in the enclosure structure 810.

[0052] To create the opening 904, a masking layer 902 is produced over the substrate 202 and the MLI 804. The masking layer 902 can be structured using the photolithography methods discussed above to define an opening in the masking layer 902. The masking layer 902 can comprise a suitable material, such as a photoresist, hard mask materials (e.g., SiN or SiON), and / or other materials. In one embodiment, the masking element 902 has an opening with a width w1 that is larger than a width w2 of the enclosure structure 810 formed by parts 706A, 706B, 808A, and 808B (see the labeling in Figure 1). Fig. 8).

[0053] Using the masking layer 902 as a masking element during etching, an opening 904 is etched in the dielectric layers 806 and 702 within the enclosure structure 810. The opening 904 extends to a top surface of the first dielectric layer 602. In one embodiment, an end portion of one or more of the structural elements 706A, 706B, 808A, and 808B is etched. The extent of any lateral back-etching of the structural elements 706A, 706B, 808A, and 808B depends on the width of the opening in the masking element 902. In particular, the extent of the etching back of the structural elements 706A, 706B, 808A and 808B can depend on the width w1 of the opening in the masking element 902, which is greater than the width w2 between opposing parts of the enclosure structure 810 formed by the structural elements 706A, 706B, 808A and 808B.By reducing the width of one or more of the structural elements 706A, 706B, 808A, and 808B, the opening 904 can be widened, thus improving gap filling. However, a sufficient width of the structural elements 706A, 706B, 808A, and 808B should be maintained to protect the dielectric layers 806 and 702 from the etching process. In one embodiment, the opening 904 is defined by conductive sidewalls of the structural elements 706A, 706B, 808A, and 808B.

[0054] The etching process used to create the opening 904 may include dry etching, such as reactive ion etching or another plasma-assisted etching process, wet etching, or one or more other suitable etching processes. In some embodiments, the first dielectric layer 602 has a composition that enables etch selectivity, particularly for the dielectric layers 702 and 806, thereby providing an etch stop for the process. It should be noted that during the etching of the opening 904, remaining portions of the dielectric layers 806 and / or 702, including the portion adjacent to the vias 704A and 802A and the metal conductors 704B and 802B, are largely protected from the etching agent by the enclosure structure 810 formed by the metal-containing structural elements 706A, 706B, 808A, and 808B.In some implementations, the etching is terminated at the dielectric layer 602, which advantageously avoids exposing the substrate 202 during the etching of the opening 904, thus preventing contamination, among other things, from the etching of the metal-containing material of the structural elements 706A, 706B, 808A and 808B.

[0055] As above with reference to the Fig. As explained in sections 2B to 2F, the opening 904 can be annular (but does not have to be) and it can (but does not have to be) be centrally located in the enclosure structure 810. As further explained in Fig. As shown in Figure 2F, in some implementations a residual amount of the dielectric 806 may remain in the opening 904 after etching. After the opening 904 has been created, the masking element 902 can be removed (e.g., detached) from the substrate 202.

[0056] The process 400 then proceeds to a block 404, in which a protective layer is produced on the side walls of the opening created in block 402. In the example of Fig. In section 10, a protective layer 1002 is produced on the side walls of the opening 904. In some implementations, the protective layer 1002 is produced such that it directly abuts the structural elements 706A, 706B, 808A, and 808B. Thus, in some implementations, the protective layer 1002 covers the exposed side walls of the metal-containing material of the structural elements 706A, 706B, 808A, and 808B.

[0057] The protective layer 1002 may comprise: an oxide, such as silicon oxide; a nitride, such as silicon nitride; an oxide nitride, such as silicon nitride oxide; combinations thereof; and / or other suitable materials. The protective layer 1002 may have a different composition than the dielectric layers 806 and 702. The protective layer 1002 may be deposited by a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof). In one embodiment, the protective layer 1002 is produced by depositing a dielectric material by one or more CVD processes and performing an etching (e.g., a dry etch) to remove the dielectric material so that it remains only on the sidewalls of the opening 904.In some implementations, the protective layer 1002 serves to protect the enclosure structure 810, formed by the structural elements 706A, 706B, 808A, and 808B, against contamination and / or diffusion of metals during subsequent processes (e.g., during the etching of the dielectric layer 602 and / or the substrate 202). In some implementations, the thickness of the protective layer 1002 can range from approximately 3 nm (about 30 Å) to approximately 300 nm (about 3000 Å). In one embodiment, the thickness of the protective layer 1002 can be substantially equal to the extent of the lateral back-etching of the structural elements 706A, 706B, 808A, and 808B discussed above.

[0058] The process 400 then proceeds to a block 406, in which the opening through one or more dielectric layers of the MLI is extended into the substrate. In the example of Fig. 11 a masking layer 1102 is applied over the side walls of the in Fig. The opening 904 shown in Figure 10 is produced, for example, on the sidewalls of the protective layer 1002. The masking layer 1102 can be produced with a first thickness t1. In some implementations, the sum of the thickness t1 and the thickness of the protective layer 1002 results in a difference between the width of the upper part of the via and the width of its lower part, as will be explained later.

[0059] By means of an etching process, the opening (previously the opening 904) can be extended through the dielectric layer 602 and into at least part of the substrate 202, resulting in an extended opening 1104. The etching of the dielectric layer 602 and the substrate 202 can be carried out in the same or in different etching steps. As shown in Fig. As shown in Figure 11, an opening 1104 is created that extends into the substrate 202. The etching process used to create the opening 1104 can include dry etching, such as reactive ion etching or another plasma-assisted etching process, wet etching, or one or more other suitable etching processes. After etching the opening 1104, the masking layer 1102 can be removed (e.g., peeled off).

[0060] After removal of the masking layer 1102, the aperture 1104 has a first width w3 at its lower part in the substrate 202 and / or in the dielectric layer 602. At its upper part in the dielectric layers 806 of the MLI 804, the aperture 1102 has a second width w4. The second width w4 is larger than the first width w3. In some implementations, the first width w3 is approximately 0% to approximately 40% smaller than the second width w4.

[0061] Procedure 400 then proceeds to block 408, in which a barrier layer is fabricated to cover the opening. Exemplary compositions include metal nitrides such as TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, or combinations thereof. In some implementations, the barrier layer can be omitted. In some implementations, other dielectric materials can be used. In the example of Fig. 12 a barrier layer 1202 is applied to the side walls of the opening 1104 of Fig. 11. In some implementations, the barrier layer 1202 has a thickness of about 3 nm (about 30 Å) to about 300 nm (about 3000 Å).

[0062] The process 400 then continues to a block 410, in which a conductive filler metal is deposited in the opening to create the conductive via. In the example of Fig. 12 a conductive filler metal 1204 is placed in the opening 1104 ( Fig. 11) and deposited over the barrier layer 1202 (if present). In one embodiment, the conductive filler metal 1204 is copper. However, other conductive materials are also possible, such as Ta, Ti, Al, Cu alloys, Co, TaN, TiN, W or Zr, and / or other suitable conductive materials. After deposition of the conductive filler metal, a planarization process (e.g., a CMP) can be carried out so that, by removing excess material from the top of the dielectric layer 602, a planar top surface is created, as shown in Fig. 13 is shown.

[0063] As also in Fig. As shown in Figure 13, a conductive via 1302 is fabricated, which incorporates the conductive filler metal 1204. The width w5 of the upper part of the conductive via 1302 is greater than the width w6 of its lower part. In some implementations, the width w6 is 0% to 40% smaller than the width w5. The width w6 can be adjusted depending on the thickness of the protective layer 1102. A difference between the width w5 and the width w6 can facilitate gap filling with the conductive material 1204.

[0064] The process 400 then proceeds to a block 412, in which the fabrication can be continued with further steps. In some implementations, an interconnect structure 1402 (e.g., metal conductors and vias with surrounding dielectrics) can be fabricated on a front face of the device, creating a connection with a top face of the via 1302, as shown in Fig. Figure 14 shows that in some implementations, the substrate 202 can be thinned (e.g., from the back side of the substrate 202) to expose a lower portion of the via 1302. During subsequent machining, an interconnect structure can be fabricated on the back side of the device, thus creating a connection with a bottom side of the via 1302. In some implementations, one or more interconnect structures can be connected to or provided on another device on the top or bottom side of the device.

[0065] Thus, the method 400, which is based on the device 600b of the Fig. As explained in Sections 9 to 14, an example of fabricating a conductive via 1302 extends from the top side of an MLI 804 fabricated over a semiconductor substrate 202 to the back side of the substrate 202. The conductive via 1302 can be referred to as a TSV 1302. The TSV 1302 is provided within the enclosure structure 810, which is formed by the structural elements 706A, 706B, 808A, and 808B, such that the enclosure structure 810 completely encloses or encloses the portion of the TSV 1302 that extends through the dielectric layers 806. The enclosure structure 810 encloses the upper portion of the TSV 1302, which has an increased width (e.g., width w5). In some implementations, the dielectric layer 806 is an extremely low k material, and the enclosure structure 810 protects the extremely low k material against an etching process that would create an opening (e.g.in the dielectric material) in which the TSV 1302 is manufactured. In one embodiment, the enclosure structure 810 is not provided on a second part of the TSV (e.g., with width w6) that is enclosed by the dielectric layer 602 and / or the substrate 202.

[0066] Let us now turn to examples of Procedure 400 from Fig. 4, which are in the Fig. Figures 15 to 18 show a further embodiment of method 400, which is based on method 300 of Fig. 3 can connect (e.g., from B to B1) and includes the manufacture of a TSV in an enclosure structure. The embodiment of a device 600c, which is located in the Fig. The device shown in Figures 15 to 18 has many similarities to the device 600b discussed above, but the substrate 202 has an insulating element, such as an insulating element 203, in the area where a TSV is produced.

[0067] In block 402 of the embodiment of method 400, an opening is created such that it extends through the dielectric layers of the MLI in a region within an enclosure structure. However, due to the insulating element 203 arranged beneath the enclosure structure, etching can continue without the risk of introducing contaminants into the substrate. In the example of Fig. In 15, an opening 1502 is created in the enclosure structure 810, formed by the structural elements 706A, 706B, 808A, and 808B, by an etching process, wherein the opening 1502 is defined by the masking layer 902 discussed above. The etching process used to create the opening 1502 may include one or more dry etching processes, such as reactive ion etching or another plasma-assisted etching process, wet etching, or other suitable etching processes. In some embodiments, the material of the insulating element 203 has a composition that provides etch selectivity for the dielectric layers 602, 702, and / or 806 and provides an etch stop. In another implementation, over-etching is performed, so that part of the insulating element 203 is etched.It should be noted that (as explained above in the embodiment of device 600b) during the etching of the opening 1502, areas of the dielectric layers 806 and / or 702 outside the enclosure structure 810 are largely protected against etching agents and / or impurities by the enclosure structure 810. As explained above, end parts of the structural elements 7064, 706B, 808A and 808B can be etched together with the dielectric layers 806 and 702 in the enclosure structure 810.

[0068] The process 400 then proceeds to block 404, in which a protective layer is produced on the side walls of the opening created in block 402. In the example of Fig. 16. A protective layer 1002 is fabricated on the sidewalls of the opening 1502. In some implementations, the protective layer 1002 is fabricated to be directly adjacent to the structural elements 706A, 706B, 808A, and 808B, directly adjacent to the dielectric layer 602, and / or directly adjacent to the insulating element 203. The protective layer 1002 may be substantially similar to the protective layer discussed above, for example, in some implementations, and the thickness of the protective layer 1002 may be from about 3 nm (about 30 Å) to about 300 nm (about 3000 Å).

[0069] Method 400 then proceeds to block 406, in which the first opening (e.g., the opening extending through one or more dielectric layers of the MLI, as described in block 402) is extended into the substrate. In the example of Fig. 17 A masking layer 1102 is applied over the side walls of the in Fig. The opening 904 shown in Figure 16 is produced, as is the case, for example, on the side walls of the protective layer 1002. The masking layer 1102 can be essentially similar to the one described above using the example of Fig. 11 has been discussed.

[0070] An etching process can extend the opening (previously opening 1502) through the insulating element 203 and into at least part of the substrate 202, creating an extended opening 1702. The etching of a lower portion of the insulating element 203 and the substrate 202 can be performed in the same or separate etching steps. The etching process used to create opening 1702 can include dry etching, such as reactive ion etching or another plasma-assisted etching process, wet etching, or other suitable etching processes. After etching opening 1702, the masking layer 1102 can be removed (e.g., peeled off).

[0071] The opening 1702 has a first width w8 in the substrate 202 and / or in the lower part of the insulating element 203. The opening 1702 has a second width w7 in the dielectric layers 806 of the MLI 804, in the dielectric layer 602 and / or in an upper part (e.g., above the etched area) of the insulating structure 204. In some implementations, the first width w8 can be approximately 0% to approximately 40% smaller than the second width w7.

[0072] Method 400 then proceeds to blocks 408 and 410, in which a barrier layer and a conductive filling are produced in the opening essentially as described above for device 600b. In the example of Fig. In step 18, the barrier layer 1202 and the conductive filler metal 1204 are deposited in the opening 1702. As in Fig. As shown in Figure 18, a conductive via 1802 is fabricated with the conductive filler metal 1204. The width w9 of the upper part of the conductive via 1802 is greater than the width w10 of its lower part. In some implementations, the width w10 is 0% to 40% smaller than the width w9. The width w10 can be adjusted depending on the thickness of the protective layer 1002. The difference between the width w10 and the width w9 allows the gap-filling capacity during the deposition of the conductive filler metal 1204 to be adjusted.

[0073] Thus, using method 400, which is based on the device 600c of the Fig. As explained in sections 15 to 18, a conductive via 1802 is provided, extending from the top of an MLI 804 fabricated over the semiconductor substrate 202 to a back side of the substrate 202. The conductive via 1802 can be referred to as a TSV 1802. The TSV 1802 is provided within the enclosure structure 810, which is formed by the structural elements 706A, 706B, 808A, and 808B, such that the enclosure structure 810 completely encloses or encloses the portion of the TSV 1802 that extends through the dielectric layers 806. The enclosure structure 810, formed by the structural elements 706A, 706B, 808A and 808B, encloses a part of the TSV 1802 that has a reduced width (e.g. the width w9).In some implementations, the dielectric layer 806 is an extremely low k material, and the enclosure structure 810 protects the extremely low k material outside the enclosure structure 810 from an etching process used to create the opening for the TSV 1802. However, the enclosure structure 810 is not provided on a second part of the TSV that is enclosed by the dielectric layer 602, the insulating element 203, and / or the substrate 202.

[0074] In Fig. Figure 5 shows a method 500 which, in some embodiments, is adapted from method 300 for producing a TSV in the enclosure structure produced by method 300. Fig. 3 can be connected (e.g., from B to B2). In particular, the TSV is produced from a rear side of the device, and it can therefore be referred to as a rear-side TSV or BTSV. An embodiment of method 500 is described with reference to the example of a device 600d in the Fig. Explained in sections 19 to 28.

[0075] Process 500 is based on Process 300, in which an MLI is produced over a substrate, the MLI having an enclosing structure. Fig. 19 A device 600d is provided which is substantially similar to the device described with reference to Fig. As discussed in section 8, the device 600d has an enclosure structure 810 formed by the structural elements 706A, 706B, 808A and 808B, which are coplanar with the vias 704A and the conductors 704B of the MLI 804 in the dielectric layers 806. The active device 204 is arranged in a first dielectric layer 602 above the substrate 202.

[0076] The device 600d also has a bonding area located on a top surface of the device 600d. The bonding area has a conductive structural element 1902 that is positioned over and connected to the vias and metal traces (704A and 704B), thus establishing a connection with the active device 204 of the device 600d. The bonding area also has a conductive structural element 1904 that is positioned over the enclosure structure 810. The conductive structural elements 1902 and 1904 are only examples and can have other configurations. In one embodiment, the conductive structural element 1904 extends from a position over a first side of the enclosure structure 810 to a position over a second, opposite side of the enclosure structure 810 (e.g., in the x-direction and / or the y-direction). In some embodiments, the conductive structural element is 1904 (e.g.B. in the z-direction) thicker than the MLI's 704B metal conduits.

[0077] In block 502 of process 500, a second device is provided, which is fabricated on a second substrate. The second device is bonded to a first device, such as the first device fabricated by process 300. Fig. 3 is manufactured and has an enclosure structure manufactured in an MLI. In the example of Fig. Figure 20 shows a second device 2002. The second device 2002 is shown wholly or partially as an integrated circuit device 2002. The integrated circuit device 2002 may be contained within a microprocessor, a memory, and / or another integrated circuit device. In some implementations, the integrated circuit device 2002 is part of an IC chip, a SoC, or a portion thereof, which incorporates various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The transistors may be planar transistors or multi-gate transistors, such as finned FinFETs or GAA transistors. In other embodiments, the second device 2002 is part of a MEMS device.For the sake of simplicity, the device 2002 is shown with an active device 2004, such as a transistor, and an MLI structure 2006 fabricated over the active device 2004, the MLI 2006 comprising a plurality of metal conductors and vias located between them. The MLI 2006 has a dielectric contact plane layer 2006a in which conductive contacts 2006b extend to a terminal of the active device 2004. The device 2002 comprises a substrate (a wafer) 2008. The substrate 2008 can be substantially similar to the substrate 202. In one embodiment, for example, the substrate 2008 comprises silicon.

[0078] As in the Fig. 20 and Fig. As shown in Figure 21, the device 2002 is inverted and bonded to the device 600d. Bonding can be performed by fusion bonding, hybrid bonding, and / or another suitable bonding method. In some implementations, bonding is performed completely or partially between the conductive structural elements 1902 and 1904 of the device 600d and a corresponding conductive element of the MLI 2006 of the device 2002. In some implementations, eutectic bonding is performed between conductive components of the device 2002 and the device 600d. After bonding, the structure can be inverted as shown in Figure 21. Fig. 22 is shown.

[0079] The process 500 then proceeds to a block 504, in which the first and / or the second substrate is diluted. In the example of Fig. In step 23, substrate 202 is thinned. The one or more substrates can be thinned by mechanical grinding, chemical-mechanical polishing and / or other suitable methods.

[0080] Method 500 then proceeds to a block 506 in which an opening is created in the substrate of a device. In one embodiment, the opening is created in the substrate of the first device. In the example of Fig. 24 An opening 2402 is created in the substrate 202 of the device 600d.

[0081] To create the opening 2402, a masking layer 2404 is applied to the substrate 202 (e.g., on a back side of the substrate 202, which in the example of Fig. 24 is oriented upwards). The masking layer 2404 can be structured using the photolithography methods discussed above for defining an opening in the masking layer 2404. The masking layer 2404 can comprise a suitable material, such as a photoresist, hard mask materials (e.g., SiN or SiON), and / or other materials. In one embodiment, the masking element 2404 has an opening with a width w11 that is larger than the width w12 of the enclosure structure 810 formed by parts 706A, 706B, 808A, and 808B.

[0082] Using the masking layer 2404 as a masking element during etching, the opening 2404 is etched into the substrate 202. In one embodiment, the dielectric layer 602 is used as an etch stop layer for etching the substrate 202. In some implementations, the etching includes slight over-etching into the dielectric layer 602. The etching process for creating the opening 2402 can include dry etching, such as reactive ion etching or another plasma-assisted etching process, wet etching, or other suitable etching processes. After etching, the masking layer 2404 is removed (e.g., peeled off) from the substrate 202.

[0083] The process 500 then proceeds to a block 508, in which a protective layer is produced on the side walls of the opening created in block 506. In the example of Fig. In this embodiment, a protective layer 2502 is produced on the sidewalls of the opening 2402. The protective layer 2502 can comprise: an oxide, such as silicon oxide; a nitride, such as silicon nitride; an oxide nitride, such as silicon nitride oxide; combinations thereof; and / or other suitable materials. The protective layer 2502 can be deposited by a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof). In one embodiment, the protective layer 2502 is produced by depositing a dielectric material by one or more CVD processes and performing an etching (e.g., a dry etch) to remove the dielectric layer so that it remains only on the sidewalls of the opening 2402.In some implementations, the protective layer 2502 provides a protective barrier for the substrate 202, thus protecting the substrate 202 against impurities (e.g., metal particles) that may arise in later processes, such as the etching of the enclosing structure 810.

[0084] Method 500 then proceeds to a block 510, in which the opening created in block 506 is extended into the device. In the example of Fig. 26 an extended opening 2602 is created in the device 600d and in particular by the dielectric layers 806 in the enclosure structure 810 of the device 600d.

[0085] In one embodiment for creating the opening 2602, a masking layer 1102 is applied over the side walls of the Fig. The opening 2402 shown in Figure 25 is produced, for example, on the sidewalls of the protective layer 2502. The masking layer 1102 can be structured using photolithography and / or etching techniques, as described above. The masking layer 1102 can be made of a suitable material, such as a photoresist or a hard mask (e.g., SiN or SiON), and / or other materials. The masking layer 1102 can be produced with a first thickness t1. In some implementations, the sum of the thickness t1 and the thickness of the protective layer 2502 provides a difference between the width of the first part of the via and the width of its second part, as will be explained later.

[0086] Using the masking layer 1102 as a masking element during etching, the opening 2602 is etched to extend into the dielectric layers 602, 702, and 806. The etching of the opening 2602 can be performed using wet etching or dry etching (such as plasma and / or RIE etching) in one or more etching processes. In one embodiment, an end portion of one or more of the structural elements 706A, 706B, 808A, and 808B is etched to create the opening 2602. The extent of removal of the end portions of the structural elements 706A, 706B, 808A, and 808B depends on the thickness of the first dielectric layer 2502. By reducing the width of one or more of the structural elements 706A, 706B, 808A and 808B, the opening 2602 can be widened, thus enabling improved gap filling.However, a sufficient width of the structural elements 706A, 706B, 808A, and 808B should be maintained to protect the dielectric layers 806 and 702, which are located in areas outside the enclosure structure 810, from the etching process. It should be noted that during the etching of the opening 2602, the dielectric layers 806 and 702 in areas outside the enclosure structure 810 are largely protected from the etching agents by the enclosure structure 810 formed by the structural elements 706A, 706B, 808A, and 808B.

[0087] As above with reference to the Fig. As explained in sections 2B to 2F, the opening 2602 can be annular like the opening 2402 (but it does not have to be), and it can (but does not have to be) arranged centrally in the enclosure structure 810. As further explained in Fig. As shown in Figure 2F, in some implementations a residual amount of dielectric 806 may remain in the opening 2602 after etching. After etching the opening 2602, the masking layer 1102 can be removed (e.g., peeled off).

[0088] After removal of the masking layer 1102, the opening 2602 has a first width w13 at a portion of the opening 2602 in the substrate 202 and a second width w14 at a portion of the opening 2602 in the dielectric layer 602 and / or in the enclosure structure 810. The second width w14 is smaller than the first width w13. In some implementations, the second width w14 can be approximately 0% to approximately 40% smaller than the first width w13.

[0089] The process 500 then continues to a block 512, in which a second protective layer is produced in such a way that it covers the opening. In the example of Fig. 27 A second protective layer 2702 is produced such that it covers the opening 2602. The protective layer 2702 can comprise: an oxide, such as silicon oxide; a nitride, such as silicon nitride; an oxide nitride, such as silicon oxide nitride; combinations thereof; and / or other suitable materials. The protective layer 2702 can be deposited by a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof). In one embodiment, the protective layer 2702 is produced by depositing a dielectric material by one or more CVD processes and performing an etching (e.g., a dry etching) to remove the dielectric material so that it remains only on the sidewalls of the opening 2602.

[0090] The process 500 then proceeds to a block 514, in which one or more conductive materials are deposited in the opening to create the conductive via. In the example of Fig. 28 a metal layer 1204 in the opening 2602 ( Fig. 27) produced. In one embodiment, the conductive filler metal 1204 is copper. However, other conductive materials are also possible, such as Ta, Ti, Al, Cu alloys, Co, TaN or TiN, and / or other suitable conductive materials. After deposition of the conductive filler metal, a planarization process (e.g., a CMP) can be carried out so that, by removing excess material from the top of the substrate 202, a planar top surface is created, as in Fig. Figure 28 shows that in some implementations, a barrier layer, such as one made of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN or a combination thereof, can also be created in opening 2602.

[0091] As also in Fig. As shown in Figure 28, a conductive via 2802 is fabricated, which incorporates the conductive filler metal 1204. The width w15 of an upper part of the conductive via 2802 is greater than the width w16 of its lower part. In some implementations, the width w15 is 0% to 40% greater than the width w16. The width w16 can be adjusted depending on the thickness of the protective layer 2702. By varying the widths w15 and w16, the gap-filling capacity during fabrication of the conductive via 2802 can be adjusted. In one embodiment, the width w15 of the TSV 2802 is approximately 1 µm to approximately 10 µm. In another embodiment, the width w16 of the TSV 2802 is approximately 0.5 µm to approximately 2.8 µm.

[0092] In some embodiments, the dielectric layer 2502 and / or the dielectric layer 2702 are arranged between the TSV 2802 and the enclosure structure 810, which offers the advantage of balancing any stress caused by the metal composition of the TSV 2802.

[0093] Method 500 then proceeds to a block 516, in which the fabrication can continue. In some implementations, an interconnect structure (e.g., metal conductors and vias with surrounding dielectrics) can be fabricated on an exposed surface of the device, creating a connection with a top surface of the via 2802. In some implementations, an interconnect structure, such as a metallic contact bump or bond pad, can be connected to the via 2802. Thus, Method 500, which is described using the device 600d, Fig. As explained in paragraphs 19 to 28, a conductive via 2802 is produced which extends from the back of the substrate 202 to a conductive structural element 1904 of the device 600d which can be connected to the MLI of the second structure 2002.

[0094] The conductive via 2802 can be referred to as a backside TSV or BTSV 2802. The BTSV 2802 is provided within the enclosure structure 810, which is formed by the structural elements 706A, 706B, 808A, and 808B, such that the enclosure structure 810 completely encloses or encloses a portion of the BTSV 2802 that extends through the dielectric layers 806. The enclosure structure 810 encloses the lower portion of the BTSV 2802, which has a reduced width (e.g., width w16). In some implementations, the dielectric layer 806 is an extremely low k material, and the enclosure structure 810 formed by the structural elements 706A, 706B, 808A, and 808B protects the extremely low k material from an etching process used to create an opening (e.g., in the dielectric material) in which the BTSV 2802 is fabricated. However, the enclosure structure 810 is not applied to a second part of the BTSV 2802 (e.g.,with the width w15) provided, which is enclosed by the dielectric layer 602 and / or the substrate 202.

[0095] Now let's move on to... Fig. 29, in which an embodiment of a device 600e is shown, which is equipped with one or more of the steps discussed above, as described, for example, for method 500 of Fig. The device 600e is essentially similar to the device 600d discussed above. The substrate 202 has an insulating element 203 by which a BTSV 2902 is produced. The BTSV 2902 can be essentially similar to the BTSV 2802. The insulating element 203 borders a surface of the dielectric layer 602. Due to the presence of the insulating element 203, the first etching process, such as the one described above in Block 506 of Method 500 and based on Fig. As explained in section 24, an opening is created that terminates in the substrate 202 and, in particular, in the insulating element 203. This eliminates the need for over-etching into the dielectric layer 602, which has been discussed above, in some implementations.

[0096] In a further embodiment of method 500 of Fig. 5. The TSV can be produced with further etching steps, and / or a TSV can be provided that has at least three different widths. Fig. Figures 30 to 32 show a device 600f as an example. In one embodiment of the method 500, the method 500 proceeds through the block 508 discussed above, in which a protective layer is produced over a first opening. In one embodiment, an exemplary device at this stage of the method 500 is shown in Fig. Figure 25 shows that the dielectric protective layer 2502 has a protective layer. In one embodiment, the thickness of the dielectric protective layer 2502 is approximately 3 nm (about 30 Å) to about 300 nm (about 3000 Å).

[0097] In one embodiment, the embodiment of method 500 then comprises an intermediate etching step in which the opening in the substrate 202 is extended so that it extends through the dielectric layer 602, as shown in Fig. 30 is shown, and an extended opening 3002 is created.

[0098] In one embodiment of generating the opening 3002, a masking layer 1102 is applied over the side walls of the opening. Fig. The opening 2402 shown in Figure 25 is produced, for example, on the side walls of the protective layer 2502. The masking layer 1102 can be structured using photolithography and / or etching processes, as described above. The masking layer 1102 can comprise a suitable material, such as a photoresist or a hard mask (e.g., SiN or SiON), and / or other materials.

[0099] Using the masking layer 1102 as a masking element during etching, the opening 3002 is created such that it extends into and / or through the dielectric layer 602. The etching of the opening 3002 can be carried out using wet etching or dry etching (such as plasma and / or RIE etching) in one or more etching processes. In one embodiment, the dielectric layer 806 has a different composition than the dielectric layer 602, thus creating an etch stop for the creation of the opening 3002. In another embodiment, the enclosing structure 810 provides an etch stop for the creation of the opening 3002. After etching, the masking layer 1102 can be removed.

[0100] In one embodiment, the process 500 then continues to a block 510 in which a further etching step is carried out to extend the opening further into the device. In the example of Fig. 31 provides an opening 3102 which enlarges the opening through the dielectric layers 702 and 806 in the enclosure structure 810, as shown in Fig. 31 is shown.

[0101] In one embodiment of creating the opening 3102, a masking layer 1102 is again applied over the side walls of the opening. Fig. The opening 3002 shown in Figure 30 is produced, for example, on the sidewalls of the protective layer 2502 and the sidewalls of the etched dielectric layer 602. The masking layer 1102 can be structured using photolithography and / or etching processes, as described above. The masking layer 1102 can comprise a suitable material, such as a photoresist or a hard mask (e.g., SiN or SiON), and / or other materials.

[0102] Using the masking layer 1102 as a masking element during etching, the opening 3102 is etched in the dielectric layers 702 and 806, which are arranged in the enclosure structure 810. The etching of the opening 3102 can be carried out by wet etching or dry etching (such as plasma and / or RIE etching) in one or more etching processes. In one embodiment, the etching terminates at the conductive structural element 1904.

[0103] In some embodiments, the etching process also removes the ends of the structural elements 706A, 706B, 808A, and 808B, as described above. In one embodiment, the protective layer 2502 serves to protect the substrate 202 against unwanted contamination resulting from the etching of the metal-containing material at the ends of the structural elements 706A, 706B, 808A, and 808B. After etching, the masking layer 1102 can be removed.

[0104] The process 500 then continues to a block 512, in which a second protective layer is produced in such a way that it covers the opening. In the example of Fig. 32 A second dielectric protective layer 2702 is produced such that it covers the opening 3102. The protective layer 2702 can comprise: an oxide, such as silicon oxide; a nitride, such as silicon nitride; an oxide nitride, such as silicon oxide nitride; combinations thereof; and / or other suitable materials. The protective layer 2702 can be deposited by a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof). In one embodiment, the protective layer 2702 is produced by depositing a dielectric material by one or more CVD processes and performing an etching (e.g., a dry etching) to remove the dielectric material so that it remains only on the sidewalls of the opening 3102.In one embodiment, the thickness of the dielectric layer 2702 is approximately 3 nm (about 30 Å) to about 300 nm (about 3000 Å).

[0105] The process 500 then proceeds to a block 514, in which one or more conductive materials are deposited in the opening to create the conductive via. In the example of Fig. 32 a metal layer 1204 in the opening 3102 ( Fig. 31) produced. In one embodiment, the conductive filler metal 1204 is copper. However, other conductive materials are also possible, such as Ta, Ti, Al, Cu alloys, Co, TaN or TiN, and / or other suitable conductive materials. After deposition of the conductive filler metal, a planarization process (e.g., a CMP) can be carried out so that, by removing excess material from the top of the substrate 202, a planar top surface is created, as in Fig. Figure 31 shows that in some implementations, a barrier layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN or a combination thereof can also be created in opening 3102.

[0106] As also in Fig. As shown in Figure 32, a conductive via 3202 is fabricated, which incorporates the conductive filler metal 1204. The width w17 of an upper part of the conductive via 3202 is greater than the width w18 of its lower part. A region with a width w19 is located between two parts of the conductive via 2802. In some implementations, the width w17 of the TSV 3202 is approximately 1 µm to approximately 10 µm. In other implementations, the width w18 of the TSV 3202 is approximately 0.5 µm to approximately 2 µm. The TSV 3202, which has a three-part configuration, can provide a stepped profile that facilitates gap filling.

[0107] In some embodiments, the dielectric layers 2502 and 2702 are arranged between the TSV 3202 and the enclosure structure 810 to compensate for stress caused by the metal composition of the TSV 3202. The TSV 3202, which has a three-stage profile, can also allow for a smaller size (critical dimension; CD) of the TSV 3202 within the enclosure structure 810, thereby improving device density.

[0108] Method 500 then proceeds to block 516, where fabrication can continue. In some implementations, an interconnect structure (e.g., metal conductors and vias with surrounding dielectrics) can be fabricated on a front face of the device, creating a connection with a top face of the via 3202. In some implementations, an interconnect structure, such as a metallic contact mound or a metallic bond pad, can be connected to the via 3202. Thus, Method 500, which is described using device 600f, Fig. As explained in sections 30 to 32, a conductive via 3202 is produced which extends from the back of the substrate 202 to a conductive structural element 1904 of the device 600f which can be connected to the MLI of the second structure 2002.

[0109] The conductive via 3202 can be referred to as a backside TSV 3202 or BTSV 3202. The BTSV 3202 is provided within the enclosure structure 810, which is formed by the structural elements 706A, 706B, 808A and 808B, such that the enclosure structure 810 completely encloses or encases a portion of the BTSV 3202 that extends through the dielectric layers 806.

[0110] Now let's move on to the Fig. 33 and Fig. 34, in which an exemplary device 600g is illustrated, which is carried out by one or more steps of the method 500 of Fig. 5 can be produced. Device 600g differs from the preceding description in that a through-hole with only one width can be produced in a single etching step. In one embodiment, according to block 504 of method 500, a device can be provided which has an enclosure structure in which a TSV can be produced. The device of Fig. 23 is explanatory for this stage in the manufacturing process.

[0111] In one embodiment of method 500, an opening is created in the substrate in block 506. In the example of Fig. 33 an opening 3302 is created such that it extends through the substrate 202, the dielectric layer 602 and the enclosure structure 810.

[0112] In one embodiment of generating the opening 3302, a masking layer is produced over the substrate 202. Using the masking layer as a masking element during etching, the opening 3302 is etched. The etching of the opening 3302 can be performed using wet etching or dry etching (such as plasma and / or RIE etching) in one or more etching processes. In one embodiment, the etching terminates at the structural element 1904. In some embodiments, the ends of the structural elements 706A, 706B, 808A, and 808B are also removed by the etching, as described above.

[0113] Skipping blocks 508 and 510, process 500 then proceeds to block 512, in which a barrier layer is produced to cover the opening. In the example of Fig. In this embodiment, a barrier layer 3402 is produced to cover the opening 3302. The barrier layer 3402 can comprise: an oxide, such as silicon oxide; a nitride, such as silicon nitride; an oxide nitride, such as silicon oxide nitride; combinations thereof; and / or other suitable materials. The barrier layer 3402 can be deposited by a deposition process (such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof). In one embodiment, the barrier layer 3402 is produced by depositing a dielectric material by one or more CVD processes and performing an etching (e.g., a dry etch) to remove the dielectric material so that it remains only on the sidewalls of the opening 3302. In one embodiment, the thickness of the barrier layer 3402 is approximately 3 nm (about 30 Å) to about 300 nm (about 3000 Å).

[0114] The process 500 then proceeds to block 514, in which one or more conductive materials are deposited in the opening to create the conductive via. In the example of Fig. 34 a metal layer 1204 in the opening 3302 ( Fig. 33) produced. In one embodiment, the conductive filler metal 1204 is copper. However, other conductive materials are also possible, such as Ta, Ti, Al, Cu alloys, Co, TaN or TiN, and / or other suitable conductive materials. After deposition of the conductive filler metal, a planarization process (e.g., a CMP) can be carried out so that, by removing excess material from the top of the substrate 202, a planar top surface is created, as in Fig. Figure 34 shows that in some implementations, a barrier layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN or a combination thereof can also be created in opening 3302.

[0115] As also in Fig. As shown in Figure 34, a conductive via 3404 is produced, which has the conductive filler metal 1204. A width w20 of the conductive via 3404 can be substantially constant over the entire via 3404. In one embodiment, the width w20 of the TSV 3404 is approximately 0.5 µm to approximately 10 µm. The method 500 can then proceed to the block 516, in which the production can be continued as described above. Thus, with the method 500, which is based on the apparatus 600g of the Fig. 33 and Fig. As explained in Figure 34, a conductive via 3404 is produced which extends from the back of the substrate 202 to a conductive structural element 1904 of the device 600g which can be connected to the MLI of the second structure 2002.

[0116] Now let's move on to... Fig. 35, in which an exemplary device 600h is shown, which is essentially similar to the device 600b discussed above. The device 600h serves to illustrate an embodiment of an enclosure structure 810'. The enclosure structure 810' is essentially similar to the enclosure structure 810 discussed above, but shows a special configuration of layers 706A, 706B, 808A and 808B that are not vertically oriented. Due to the vertically offset orientation, a residual dielectric material 802' can remain in the enclosure structure 810', which is similar to the residual dielectric material 206' discussed above. Fig.2F is similar. Although the layers 706A, 706B, 808A, and 808B of the enclosure structure 810' are not aligned, in some embodiments a portion of each layer abuts the layers above and below it, forming a continuous vertical enclosure structure. The enclosure structure 810' can be provided in any of the embodiments discussed above.

[0117] The present invention provides many different embodiments. Interconnect structures, such as TSVs, and corresponding methods for their fabrication are disclosed here. The TSVs are fabricated in an enclosure structure that encloses them. In some embodiments, the fabrication of the enclosure structure limits the exposure of adjacent layers (e.g., ILD and dielectric low-k layers) for the etching and deposition processes used to fabricate the TSVs.

[0118] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Procedure with the following steps: Providing a substrate (202) comprising a semiconductor device (204) arranged on the substrate (202); Producing a multilayer interconnect structure (208, 804) over the substrate (202), wherein the multilayer interconnect structure (208, 804) has an enclosure structure (212, 810), the enclosure structure (212, 810) being formed by metal-containing structural elements (706A, 706B, 808A, 808B); Etching an opening (904, 1502, 2602, 3102, 3302) in the enclosure structure (212, 810), wherein the etching of the opening (904, 1502, 2602, 3102, 3302) includes lateral etching of end regions of the metal-containing structural elements (706A, 706B, 808A, 808B); Deposition of a protective layer (1002, 2702) on side walls of the opening (904, 1502, 2602, 3102, 3302); and Producing a substrate via (214, 1302, 1802, 2802, 2902, 3202) such that it extends into the substrate (202) within the enclosure structure (212, 810) of the multilayer interconnect structure (208, 804), wherein the protective layer (1002, 2702) is arranged between the substrate via (214, 1302, 1802, 2802, 2902, 3202) and the enclosure structure (212, 810). [2] Method according to claim 1, wherein the deposition of the protective layer (1002, 2702) comprises the deposition of a dielectric material directly onto the etched end regions of the metal-containing structural elements (706A, 706B, 808A, 808B) of the enclosure structure (212, 810). [3] Method according to claim 1 or 2, wherein the deposition of the protective layer (1002, 2702) comprises the deposition of the protective layer (1002, 2702) with a thickness that is substantially equal to the extent of the lateral etching of the end regions of the metal-containing structural elements (706A, 706B, 808A, 808B) of the enclosure structure (212, 810). [4] Method according to claim 3, wherein the enclosure structure (212, 810) is annular in a top view. [5] Method according to any of the preceding claims, wherein the enclosure structure (212, 810) encloses the substrate via (214, 1302, 1802, 2802, 2902, 3202). [6] Method according to any of the preceding claims, wherein the production of the substrate through-hole (214, 1302, 1802, 2802, 2902, 3202) comprises: Etching out the dielectric material from the interior of the enclosure structure (212, 810) to create the opening (904, 1104, 1502, 2602, 3102, 3302); and Filling the opening (904, 1104, 1502, 2602, 3102, 3302) with conductive material (1204). [7] The method of claim 6, further comprising: Creating a barrier layer (1202) in the opening (1104) before filling the opening (904, 1104, 1502, 2602, 3102, 3302) with conductive material (1204), wherein the barrier layer (1202) is physically adjacent to the protective layer (1002, 2702). [8] Method according to claim 8, wherein the barrier layer (1202) comprises TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN or combinations thereof. [9] Method according to one of the preceding claims, wherein the thickness of the protective layer (1002, 2702) is between 3 nm and 300 nm. [10] Procedure with the following steps: Providing a semiconductor substrate (202) comprising a semiconductor device (204) arranged above the semiconductor substrate; Deposition of a first dielectric layer (702) over the semiconductor device (204); Producing, in the first dielectric layer (702), a first via (704A), a first metal conductor (704B) over the first via (704A), a first metal ring (706A) so that it is coplanar with the first via (704A), and a second metal ring (706B) on the first metal ring (706A) such that the second metal ring (706B) is coplanar with the first metal conductor (704B); Deposition of a second dielectric layer (806) over the first metal conductor (704B); Producing, in the second dielectric layer (806), a second via (802A), a second metal conductor (802B) above the second via (802A), a third metal ring (808A) on the second metal ring (806B) such that the third metal ring (808A) is coplanar with the second via (802A), and a fourth metal ring (808B) on the third metal ring (808A) such that the fourth metal ring (808B) is coplanar with the second metal conductor (802B); and Producing a further via (1302) through a part of the semiconductor substrate (202), wherein the production of the further via (1302) comprises etching the first and second dielectric layers (702, 806) to create an opening (904, 1502, 2602, 3102, 3302) such that it extends through a central region of the first, second, third and fourth metal rings (706A, 706B, 808A, 808B), wherein the first, second, third and / or fourth metal rings (706A, 706B, 808A, 808B) are laterally etched during the etching to create the opening (904, 1502, 2602, 3102, 3302). [11] Method according to claim 10, wherein the first via (704A), the first metal conductor (704B), the second via (802A) and the second metal conductor (802B) are electrically connected to a source / drain region (204B) of the semiconductor device (204). [12] Method according to claim 10 or 11, wherein the first and second dielectric layer (702, 806) are dielectric low-k materials. [13] Method according to any one of claims 10 to 12, wherein the production of the further via (1302) comprises depositing a protective layer (1002, 2702) between the first metal ring (706A) and the further via (1302). [14] Method according to any one of claims 10 to 13, wherein the production of the first metal ring (706A) comprises depositing a conductive material with curvilinear edges. [15] Method according to any one of claims 10 to 14, wherein the production of the first and second metal ring (706A, 706B) is carried out using a dual damascene process. [16] Method according to any one of claims 10 to 15, further comprising thinning the semiconductor substrate (202) after making the further through-hole plating (1302). [17] Integrated circuit device comprising: an active device (204) arranged on a substrate (202); a multilayer interconnect (208, 804) over the substrate (202), wherein the multilayer interconnect (208, 804) comprises a plurality of metal conductors (208A, 208B) and enclosing dielectric material (206) with a first composition; a substrate through-hole (214, 1302, 1802, 2802, 2902, 3202) extending through the substrate (202) and the dielectric material (206) of the multilayer interconnect (208, 804); a metal-containing enclosure structure (212, 810) that encloses the substrate via (214, 1302, 1802, 2802, 2902, 3202) and is formed from metal-containing structural elements (706A, 706B, 808A, 808B), wherein the metal-containing enclosure structure (212, 810) is arranged between the substrate via (214, 1302, 1802, 2802, 2902, 3202) and the dielectric material (206) of the multilayer interconnect (208, 804); and a protective layer (1002, 2702) having a second composition and arranged between the metal-containing enclosure structure (212, 810) and the substrate via (214, 1302, 1802, 2802, 2902, 3202), wherein the metal-containing enclosure structure (212, 810) physically contacts the protective layer (1002, 2702). [18] Integrated circuit device according to claim 17, wherein the metal-containing enclosure structure (212, 810) is approximately circular in a top view. [19] Integrated circuit device according to claim 17 or 18, wherein the metal-containing enclosure structure (212, 810) is made of the same material as the majority of metal conductors (208A, 208B). [20] Circuit device according to one of claims 17 to 19, which further comprises a metal nitride barrier layer (1202) arranged between the protective layer (1002, 2702) and the substrate via (214, 1302, 1802, 2802, 2902, 3202).

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