Operating voltage and signal line arrangement in integrated circuits with stacked transistors

Abstract

Integrated circuit device comprising: an active region semiconductor structure of a first type (50p) extending in a first direction; a first gate conductor (150p) extending in a second direction perpendicular to the first direction and intersecting the active region semiconductor structure of a first type (5op) at a channel region of a transistor of a first type; an active region semiconductor structure of a second type (50n) extending in the first direction, stacked with the active region semiconductor structure of a first type (50p) and displaced by the active region semiconductor structure of a first type (50p) along a third direction perpendicular to both the first and second directions; a second gate conductor (150n) extending in the second direction and intersecting the active region semiconductor structure of a second type (50n) at a channel region of a transistor of a second type; a front-side conductive layer, in a plane with a normal vector oriented in the third direction and positioned above the first type (50n) active region semiconductor structure and the second type (50n) active region semiconductor structure; a backside conductive layer, in a plane with a normal vector oriented in the third direction and positioned below the first type (50p) active region semiconductor structure and the second type (50n) active region semiconductor structure; a front-side operating voltage line (30F) extending in the first direction in the front-side conductive layer and configured to maintain a first supply voltage; a rear operating voltage line (30B) extending in the first direction in the rear conductive layer and configured to maintain a second supply voltage; a front-side signal line (140F) extending in the first direction in the front-side conductive layer; a rear-side signal line (140B) extending in the first direction in the rear-side conductive layer; a first conductive source segment (132p) extending in the second direction, intersecting the active region semiconductor structure of a first type (50p) at a source region of the transistor of a first type, and being conductively connected to the front supply voltage line (30F) at the intersection of the first conductive source segment (132p) and the front supply voltage line (30F) via a first via connector (VT); a second conductive source segment (132n) extending in the second direction, intersecting the active region semiconductor structure of a second type (50n) at a source region of the transistor of a second type, and conductively connected to the rear supply voltage line (30B) at the intersection of the second conductive source segment and the rear supply voltage line (30B) via a second via connector (VB); and a conductive drain segment (134n) extending in the second direction, intersecting one or both of the active region semiconductor structure of a first type (50p) and the active region semiconductor structure of a second type (50n), and being conductively connected to the front signal line (140F) at the intersection of the conductive drain segment (134n) and the front signal line (140F) via a third via connector (VBT, VB, VT) or at the intersection of the conductive drain segment (134n) and the rear signal line (140B) via a third via connector.

Description

BACKGROUND

[0001] An integrated circuit (IC) typically contains a number of IC devices, which are manufactured according to one or more IC layout diagrams. IC devices sometimes include complementary field-effect transistor (CFET) devices. A CFET device generally has an upper FET stacked on top of a lower FET. Both the upper and lower FETs in a CFET device are positioned above the leads in a backside conductive layer, but below the leads in a frontside conductive layer.

[0002] Configurations with stacked field-effect transistors, especially complementary ones, are known from US 2020 / 0 235 013 A1, US 2020 / 0 211 905 A1, US 2018 / 0 315 838 A1, and US 2020 / 0 328 212 A1. Providing conductors for this purpose in both a front-side layer and a back-side layer of the stacked configuration is described, for example, in US 2020 / 0 328 212 A1 or US 2020 / 0 235 013 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1A is a diagram of an inverter circuit with operating voltage lines and signal lines in both a front conductive layer and a rear conductive layer according to some embodiments. Fig. 1B are layout diagrams of the in Fig. 1A of the inverter circuit shown according to some embodiments. Fig. 1C are cross-sectional views of the inverter circuit of Fig. 1A according to some embodiments. Fig. 1D is a cross-sectional view of the inverter circuit of Fig. 1A according to some embodiments. Fig. 2A is a modification of the inverter circuit in Fig. 1A according to some embodiments. Fig. 2B are layout diagrams of the inverter circuit in Fig. 2A according to some embodiments. Fig. 2C are cross-sectional views of the inverter circuit of Fig. 2A according to some embodiments. Fig. 3A is a further modification of the inverter circuit in Fig. 1A according to some embodiments. Fig. 3B are layout diagrams of the inverter circuit in Fig. 3A according to some embodiments. Fig. 3C are cross-sectional views of the inverter circuit of Fig. 3A according to some embodiments. Fig. 4A is a modification of the inverter circuit in Fig. 3A according to some embodiments. Fig. 4B are layout diagrams of the inverter circuit in Fig. 4A according to some embodiments. Fig. 4C are cross-sectional views of the inverter circuit of Fig. 4A according to some embodiments. Fig. 5A is a modification of the inverter circuit in Fig. 4A according to some embodiments. Fig. 5B are layout diagrams of the inverter circuit in Fig. 5A according to some embodiments. Fig. 5C are cross-sectional views of the inverter circuit of Fig. 5A according to some embodiments. Fig. 5D are cross-sectional views of the inverter circuit of Fig. 5A according to some embodiments. Fig. 6A is a modification of the inverter circuit in Fig. 5A according to some embodiments. Fig. 6B are layout diagrams of the inverter circuit in Fig. 6A according to some embodiments. Fig. 6C are cross-sectional views of the inverter circuit of Fig. 6A according to some embodiments. Fig. Figures 7A-7B are circuit diagrams of an inverter circuit and a sub-circuit according to some embodiments. Fig. 8A is a diagram of a sub-circuit in Fig. 7B, which is implemented with a CFET, according to some embodiments. Fig. 8B are layout diagrams of the subcircuit in Fig. 8A according to some embodiments. Fig. 8C are cross-sectional views of the sub-circuit of Fig. 8A according to some embodiments. Fig. Figure 9A shows layout diagrams of an AOI logic circuit according to some embodiments. Fig. 9B is a circuit diagram of the AOI logic circuit in Fig. 9A according to some embodiments. Fig. 9C is a transistor table according to the positions of the transistors in the layout diagram of Fig. 9A according to some embodiments. Fig. Figure 10A shows layout diagrams of a Scan-D flip-flop circuit (SDF circuit) according to some embodiments. Fig. 10B is a circuit diagram of the SDF circuit according to the specification by the layout diagrams in Fig. 10A according to some embodiments. Fig. 10C is a transistor table according to the positions of the transistors in the layout diagram of Fig. 10A according to some embodiments. Fig. 11A is an equivalent circuit diagram of the SDF circuit in Fig. 10B according to some embodiments. Fig. Figure 11B is a circuit diagram of the SDF circuit, shown in functional blocks, according to some embodiments. Fig. Figures 12A and FIG. are the upper section and lower section, respectively, of a layout diagram of a multi-cell circuit according to some embodiments. Fig. Figure 13 shows layout diagrams of a circuit cell with labeled dimensions according to some embodiments. Fig. Figure 14 is a flowchart of a method for generating a layout diagram of an integrated circuit (IC) according to some embodiments. Fig. Figure 15 is a flowchart of a method 1500 for manufacturing an integrated circuit (IC) with CFET devices according to some embodiments. Fig. Figure 16 is a block diagram of a system for Electronic Design Automation (EDA) according to some embodiments. Fig. Figure 17 is a block diagram of a manufacturing system for integrated circuits (ICs) and an associated IC manufacturing flow according to some embodiments. DETAILED DESCRIPTION

[0004] The present invention is given according to the respective subject matter of the attached independent claims. Particular embodiments are given by the additional features of the dependent claims. The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components, materials, values, steps, operations, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples. Other components, values, operations, materials, arrangements, or the like are also considered.For example, forming a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0006] A complementary field-effect transistor (CFET transistor) generally has a first-type transistor stacked with a second-type transistor. The first-type transistor has a channel region in a first-type active-region semiconductor structure, and the second-type transistor has a channel region in a second-type active-region semiconductor structure. An integrated circuit (IC) device containing CFET transistors often has a front-side conductive layer over the CFET transistors and a back-side conductive layer beneath them. In at least some embodiments, the device performance of the IC device containing CFET transistors depends on the positioning of the supply voltage lines and the signal lines.In some embodiments, when a cell circuit in the IC device is powered by a first supply voltage maintained on a front-side power supply line in the front-side conductive layer, and by a second supply voltage maintained on a back-side power supply line in the back-side conductive layer, the current connections to the cell circuit are improved with reduced resistance between the cell circuit and the power supply lines. Furthermore, in some embodiments, when both the front-side signal lines and the back-side signal lines are available in the front-side conductive layer for connecting the CFET transistors in the IC device, some limitations regarding the width extents of the active-region semiconductor structures are eliminated.Furthermore, in some embodiments, when the front-side operating voltage lines are interleaved with the front-side signal lines in the IC device, and the rear-side operating voltage lines are interleaved with the rear-side signal lines in the IC device, the shielding of the signals between the cells for the front-side signal lines is improved by the front-side operating voltage lines, and the shielding of the signals between the cells for the rear-side signal lines is improved by the rear-side operating voltage lines.

[0007] Fig. Figure 1A is a diagram of an inverter circuit 100 implemented with a CFET and having operating voltage lines and signal lines in both a front-side conductive layer and a back-side conductive layer, according to some embodiments. The circuit diagram of an inverter circuit is shown in Fig. 7A shown. The inverter circuit in Fig. 7A features a PMOS device and an NMOS device. The gate terminals of the PMOS and NMOS devices are connected together, serving as one input terminal of the inverter. The drain terminals of the PMOS and NMOS devices are connected together, serving as one output terminal of the inverter. The source terminals of the PMOS and NMOS devices are held at the supply voltages VDD and VSS, respectively.

[0008] In Fig. In 1A, the inverter circuit 100 has a p-active region semiconductor structure 50p extending in the X direction and an n-active region semiconductor structure 50n extending in the X direction. The X direction, the Y direction, and the Z direction in Fig. The 1A lines are orthogonal to each other and form an orthogonal coordinate frame. The p-active-region semiconductor structure 50p is stacked with the n-active-region semiconductor structure 50n and shifted by the n-active-region semiconductor structure along the Z-direction. A gate conductor 150, extending in the Y-direction, intersects both the p-active-region semiconductor structure 50p and the n-active-region semiconductor structure 50n. The gate conductor 150 functions as two stacked gate conductors conductively connected to each other: one of the two gate conductors intersects the p-active-region semiconductor structure 50p at a channel region of a PMOS transistor T1p, and the other of the two gate conductors intersects the n-active-region semiconductor structure 50n at a channel region of an NMOS transistor T1n. The gate conductor 150 is conductively connected to the gate terminals of the PMOS transistor T1p and the NMOS transistor T1n.In some embodiments, both the p-active-region semiconductor structure 50p and the n-active-region semiconductor structure 50n have one or more nanolayers, and consequently, both the PMOS transistor T1p and the NMOS transistor T1n are nanolayer transistors. In some embodiments, both the p-active-region semiconductor structure 50p and the n-active-region semiconductor structure 50n have one or more nanowires, and consequently, both the PMOS transistor T1p and the NMOS transistor T1n are nanowire transistors.

[0009] Inverter circuit 100 also features conductive segments 132p, 134p, 132n, and 134n. Each of the conductive segments 132p and 134p, extending in the Y direction, intersects the p-active-region semiconductor structure 50p at one of the terminal regions of the PMOS transistor T1p. Each of the conductive segments 132n and 134n, extending in the Y direction, intersects the n-active-region semiconductor structure 50n at one of the terminal regions of the NMOS transistor T1n. A terminal region of a transistor is either a source region or a drain region of the transistor. The conductive segment 132p, as a conductive source segment, forms a source terminal of the PMOS transistor T1p. The conductive segment 132n forms – as a conductive source segment – ​​a source terminal of the NMOS transistor T1n. The conductive segment 134p forms – as a conductive drain segment – ​​a drain terminal of the PMOS transistor T1p.The conductive segment 134n forms a drain terminal of the NMOS transistor T1n as a conductive drain segment. The conductive segments 134p and 134n are conductively connected via a conductive segment interconnect (VMD). While the drain terminals of the PMOS transistor T1p and the NMOS transistor T1n are conductively connected to each other via the conductive segment interconnect (VMD), the source terminal of the PMOS transistor T1p is conductively connected to a front-side supply voltage line 30F via an upper via connector (VT), and the source terminal of the NMOS transistor T2n is conductively connected to a rear-side supply voltage line 30B via a lower via connector (VB).The front operating voltage line 30F is configured to be maintained at a first supply voltage VDD, and the rear operating voltage line 30B is configured to be maintained at a second supply voltage VSS.

[0010] The front-side operating voltage line 30F, extending in the X direction, is located in a front-side conductive layer. The rear-side operating voltage line 30B, also extending in the X direction, is located in a rear-side conductive layer. Both the front-side and rear-side conductive layers lie in a plane whose normal vector is oriented in the Z direction. The front-side conductive layer is located above both the p-active-region semiconductor structure and the n-active-region semiconductor structure 50n. The rear-side conductive layer is located below both the p-active-region semiconductor structure 50p and the n-active-region semiconductor structure 50n. In some embodiments, the rear-side conductive layer is fabricated on a substrate as a buried conductive layer, and then the n-active-region semiconductor structure 50n is fabricated above the buried conductive layer.Subsequently, the p-active-region semiconductor structure 50p is fabricated over the n-active-region semiconductor structure 50n, and the front-side conductive layer is fabricated over the p-active-region semiconductor structure 50p. Other arrangements of the back-side conductive layer are also within the considered scope of this disclosure.

[0011] In Fig. In 1A, the inverter circuit 100 has front-side signal lines 120F and 140F in the front-side conductive layer and also rear-side signal lines 120B and 140B in the rear-side conductive layer. The front-side signal line 120F is conductively connected to the gate conductor 150 via an upper gate via VG and is configured as an input signal line of the inverter circuit. The front-side signal line 140F is conductively connected to the conductive segment 134n via a bottom-to-top via VD1 and is configured as an output signal line of the inverter circuit. In some embodiments, the rear-side signal lines 120B and 140B are also connected in Fig. 1A is not directly connected to circuit nodes in the inverter circuit 100, but the rear signal lines 120B and 140B are configured to route signals between adjacent cells on opposite sides of the inverter circuit. For example, in some embodiments, a signal from an adjacent cell next to conductive segments 132p and 132n is coupled—via one of the rear signal lines 120B and 140B—into another adjacent cell next to conductive segments 134p and 134n.

[0012] Fig. 1B are layout diagrams of the in Fig. 1A of the inverter circuit 100 shown according to some embodiments. The layout diagrams in Fig. 1B contains an upper section of the layout and a lower section of the layout. The upper section of the layout features the layout structures for specifying the p-active region semiconductor structure 50p, the gate conductor 150, the conductive segments 132p and 134p, the front signal lines 120F and 140F, the front power supply line 30F, the conductive segment interconnect connector VMD, and various via connectors. The lower section of the layout features the layout structures for specifying the n active region semiconductor structure 50n, the gate conductor 150, the conductive segments 132n and 134n, the rear signal lines 120B and 140B, the rear power supply line 30B, the conductive segment interconnect connector VMD, and various via connectors.

[0013] As described in the upper section of Fig. As indicated in Figure 1B, the p-active region semiconductor structure 50p, the front signal lines 120F and 140F, and the front supply voltage line 30F extend in the X direction. The gate conductor 150, extending in the Y direction, intersects the p-active region semiconductor structure 50p at the channel region of a PMOS transistor. The conductive segment 132p, extending in the Y direction, intersects the p-active region semiconductor structure 50p at the source region of the PMOS transistor. The conductive segment 134p, extending in the Y direction, intersects the p-active region semiconductor structure 50p at the drain region of the PMOS transistor.

[0014] The via connector structure VT at the intersection between the conductive segment 132p and the front-side power supply line 30F specifies that the conductive segment 132p and the front-side power supply line 30F are conductively connected via an upper via connector VT. The gate via connector structure VG at the intersection between the gate conductor 150 and the front-side signal lines 120F specifies that the gate conductor 150 and the front-side signal lines 120F are conductively connected via an upper gate via connector VG.

[0015] As described in the lower section of Fig. As indicated by 1B, the n-active-region semiconductor structure 50n, the rear-side signal lines 120B and 140B, and the rear-side power supply line 30B extend in the X direction. The gate conductor 150, extending in the Y direction, intersects the n-active-region semiconductor structure 50n at the channel region of an NMOS transistor. The conductive segment 132n, extending in the Y direction, intersects the n-active-region semiconductor structure 50n at the source region of the NMOS transistor. The conductive segment 134n, extending in the Y direction, intersects the n-active-region semiconductor structure 50n at the drain region of the NMOS transistor.The via connector structure VB at the intersection between the conductive segment 132n and the rear operating voltage line 30B specifies that in the inverter circuit 100 the conductive segment 132n and the rear operating voltage line 30B are conductively connected by a lower via connector VB.

[0016] In Fig. 1B are the bottom-to-top via-hole connector VBT, located above the front signal lines 140F in the upper section, and the bottom-to-top via-hole connector VBT, located above the rear signal lines 140B in the lower section, aligned in identical shapes and positions in the XY coordinate. The aligned bottom-to-top via-hole connectors VBT in the layout diagrams specify that the front signal lines 140F and the rear signal lines 140B in the inverter circuit 100 are conductively connected along the Z-direction via a bottom-to-top via-hole connector VBT. The bottom-to-top via-hole connectors VBT appear in the upper and lower sections of Fig. 1B as a matched pair. In Fig. In Figure 1B, the interconnect structure VMD located above the conductive segment 134p in the upper section and the interconnect structure VMD located above the conductive segment 134n in the lower section are aligned in identical shapes and positions in the XY coordinate. The aligned interconnect structures VMD in the layout diagrams specify that the conductive segment 134p and the conductive segment 134n in the inverter circuit 100 are conductively connected via a conductive segment interconnect structure VMD. The interconnect structures VMD appear in the upper and lower sections of the diagram. Fig. 1B as a coordinated pair.

[0017] In Fig. In 1B, the upper and lower sections of the layout also include dummy gate strip structures 110 for specifying the dummy gate strips at the edges of the inverter cell. In some embodiments, the intersections between the dummy gate strip structures 110 and the layout structure of the p-active region semiconductor structure 50p specify the isolation regions in the p-active region semiconductor structure 50p to isolate the p-active region in the inverter cell from the active regions in the adjacent cells. In some embodiments, the intersections between the dummy gate strip structures 110 and the layout structure of the n-active region semiconductor structure 50n specify the isolation regions in the n-active region semiconductor structure 50n to isolate the n-active region in the inverter cell from the active regions in the adjacent cells.In some embodiments, the isolation regions in the active-region semiconductor structures (50p or 50n) are generated based on the "Poly on Oxide Definition Edge" technology (PODE technology) or on the basis of the "Continuous Poly on Oxide Definition" technology (CPODE technology). Other suitable technologies for generating the isolation regions in the active-region semiconductor structures (50p or 50n) are also within the considered scope of this disclosure.

[0018] Fig. 1C are cross-sectional views of the inverter circuit 100 of Fig. 1A in cutting planes that pass through the line PP' and the line QQ' in Fig. 1B can be specified according to some embodiments. Fig. 1D are cross-sectional views of the inverter circuit 100 of Fig. 1A in section planes that pass through the line RR' in Fig. 1B can be specified, according to some embodiments. In Fig. 1C and Fig. 1D consists of the p-type active-region semiconductor structure 50p stacked with the n-type active-region semiconductor structure 50n. The front signal lines 120F and 140F and the front operating voltage line 30F are located in the front conductive layer above the p-type active-region semiconductor structure 50p and the n-type active-region semiconductor structure 50n. The back signal lines 120B and 140B and the back operating voltage line 30B are located in the back conductive layer below the p-type active-region semiconductor structure 50p and the n-type active-region semiconductor structure 50n.

[0019] In Fig. As shown in the cross-sectional view of the cutting plane PP', conductive segment 132p intersects the p-active-region semiconductor structure 50p at a source region of the PMOS transistor, and conductive segment 132n intersects the n-active-region semiconductor structure 50n at a source region of the NMOS transistor. Conductive segment 132p is conductively connected to the front-side power supply line 30F via an upper via connector VT, and conductive segment 132n is conductively connected to the rear-side power supply line 30B via a lower via connector VB.

[0020] In Fig. As shown in the cross-sectional view of section plane QQ', conductive segment 134p intersects the p-active-region semiconductor structure 50p at a drain region of the PMOS transistor, and conductive segment 134n intersects the n-active-region semiconductor structure 50n at a drain region of the NMOS transistor. Conductive segment 134n is conductively connected to the front-facing signal line 140F via a bottom-to-top via VBT. Conductive segment 134p is conductively connected to conductive segment 134n via a conductive segment interconnect VMD.

[0021] In Fig. As shown in the cross-sectional view of the section plane RR', the gate conductor 150 intersects the p-active-region semiconductor structure 50p at a channel region of the PMOS transistor and the n-active-region semiconductor structure 50n at a channel region of the NMOS transistor. The front-side signal line 140F is conductively connected to the gate conductor 150 via an upper gate via-connector structure VG.

[0022] In addition to the exemplary design and implementation of the inverter circuit 100, as in Fig. As shown in Figure 1A, there are other designs and implementations of the inverter circuit. Each of the diagrams in Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A and Fig. Figure 6A is a diagram of an inverter circuit implemented with a CFET and having operating voltage lines and signal lines in both a front-side conductive layer and a back-side conductive layer, according to some embodiments.

[0023] The inverter circuit 200 in Fig. 2A is a modification of the inverter circuit 100 in Fig. 1A. The bottom-to-top via-hole connector VBT in Fig. 1A is connected via a bottom-to-top via connector VB in Fig. 2A replaced. The lower via connector VB connects the conductive segment 134n to the rear signal line 140B. In Fig. 2A, the rear signal line 140B is configured as an output signal line of the inverter circuit. For comparison, in Fig. 1A, the front-side signal line 140F is configured as the output signal line of the inverter circuit.

[0024] Fig. 2B are layout diagrams of the inverter circuit 200 in Fig. 2A according to some embodiments. The layout diagrams in Fig. 2B are almost the same as the layout diagrams in Fig. 1B, except that the pair of matched bottom-to-top via-hole connector structures VBT in the upper section and the lower section of Fig. 1B is removed and a lower via connector structure VB is installed in the lower section of Fig. 2B is added at the intersection between the conductive segment 134n and the rear signal line 140B, specifying that the conductive segment 134n is conductively connected to the rear signal line 140B via a lower via connector VB.

[0025] Fig. 2C are cross-sectional views of the inverter circuit 200 in Fig. 2A in cutting planes that pass through line PP' and line QQ' in Fig. 2B can be specified, according to some embodiments. The cross-section of the cutting plane PP' in Fig. 2C is identical to the cross-section of the cutting plane PP' in Fig. 1C. The cross-section of the cutting plane QQ' in Fig. 2C is almost the same as the cross-section of the cutting plane QQ' in Fig. 1C, except that the bottom-to-top via-connector structures VBT, which connect the front-side signal line 140F to the conductive segment 134n in Fig. 1C is connected, replaced by the lower via connector VB, which connects the rear signal line 140B to the conductive segment 134n.

[0026] The inverter circuit 300 in Fig. 3A is a further modification of the 100 inverter circuit from 1A. The modification involves removing the Conductive Segment Interconnect (VMD) connector. Fig. 1A and changing the connection functions of the conductive segments 132p and 134p. The conductive segment 134p in Fig. 3A acts as a source terminal of the PMOS transistor, while the conductive segment 134p in Fig. 1A acts as a drain terminal of the PMOS transistor. The conductive segment 132p in Fig. 3A acts as a drain terminal of the PMOS transistor, while the conductive segment 132p in Fig. 1A functions as a source terminal of the PMOS transistor. In Fig. 3A The source terminal of the PMOS transistor is configured to receive the supply voltage VDD from the front-side power supply line 30F via an upper via connector VT at a position on the front-side power supply line 30F near the conductive segment 134p. Fig. 3A The drain terminal of the PMOS transistor and the drain terminal of the PMOS transistor are conductively connected via the conductive connection from conductive segment 132p to conductive segment 134n. The conductive segment 132p is conductively connected to the front signal line 140F via an upper via connector VT, and the front signal line 140F is conductively connected to the conductive segment 134n via a bottom-to-top via connector VBT.

[0027] Fig. 3B are layout diagrams of the inverter circuit 300 in Fig. 3A according to some embodiments. The layout diagrams in Fig. 3B are a modification of the layout diagrams in Fig. 1B. The modification involves removing the pair of matched interconnect connector structures VMD in the upper section and in the lower section of Fig. 1B, moving the upper via connector structure VT on the front-side power supply line 30F to a new position at the intersection between the conductive segment 134p and the front-side power supply line 30F, and adding a new upper via connector structure VT at the intersection between the conductive segment 132p and the front-side signal line 140F.

[0028] Fig. 3C are cross-sectional views of the inverter circuit 300 in Fig. 3A in cutting planes defined by line PP' and line QQ' in Fig. 3B can be specified, according to some embodiments. The cross-section of the cutting plane PP' in Fig. 3C is almost the same as the cross-section of the cutting plane PP' in Fig. 1C, except that the upper via connector VT in Fig. 1C, which connects the front-side operating voltage line 30F to the conductive segment 132p, through an upper via connector VT in Fig. 3C is replaced, which connects the front signal line 140F to the conductive segment 132p. The cross-section of the cutting plane QQ' in Fig. 3C is almost the same as the cross-section of the cutting plane QQ' in Fig. 1C, except that the Conductive Segment Interconnect Connector VMD in Fig. 1C, which connects the conductive segments 134p and 134n, is removed and in Fig. 3C adds an upper via connector VT, which connects the front-side operating voltage line 30F to the conductive segment 134p.

[0029] The inverter circuit 400 in Fig. 4A is a modification of the 300 inverter circuit in Fig. 3A. The modification involves changing the conductive connection from conductive segment 132p to conductive segment 134n. In Fig. 4A, the conductive segment 132p is conductively connected to the rear signal line 140B via a top-to-bottom via connector VTB, and the rear signal line 140B is conductively connected to the conductive segment 134n via a bottom via connector VB. The rear signal line 140B is configured as the output signal line of the inverter circuit 400.

[0030] Fig. 4B are layout diagrams of the inverter circuit 400 in Fig. 4A according to some embodiments. The layout diagrams in Fig. 4B are a modification of the layout diagrams in Fig. 3B. In Fig. 4B specifies the pair of matched, top-to-bottom via-connector structures VTB in the upper and lower sections of Fig. 1B, that the conductive segment 132p is conductively connected to the rear signal line 140B via a top-to-bottom via connector VTB. The lower via connector structure VB at the intersection of the conductive segment 134n and the rear signal line 140B specifies the lower via connector structure VB that connects the conductive segment 134n to the rear signal line 140B.

[0031] Fig. 4C are cross-sectional views of the inverter circuit 400 in Fig. 4A in cutting planes defined by line PP' and line QQ' in Fig. 4B can be specified, according to some embodiments. The cross-section of the cutting plane PP' in Fig. 4C is almost the same as the cross-section of the cutting plane PP' in Fig. 3C, except that the upper via connector VT in Fig. 3C, which connects the front signal line 140F to the conductive segment 134p, is replaced by the top-to-bottom via connector VTB, which connects the conductive segment 134p to the rear signal line 140B. The cross-section of the cutting plane QQ' in Fig. 4C is almost the same as the cross-section of the cutting plane QQ' in Fig. 3C, except that in Fig. 4C a lower via connector VB is added, which connects the conductive segment 134n to the rear signal line 140B.

[0032] The inverter circuit 500 in Fig. 5A is a modification of the 400 inverter circuit in Fig. 4A. In the inverter circuit 500 of Fig. In the 5A circuit, the front-mounted signal line 140F is configured as the input signal line, and the front-mounted signal line 120F is configured as the output signal line. For comparison, in the inverter circuit 400 of Fig. 4A, the front signal line 120F is configured as the input signal line, and the rear signal line 140B is configured as the output signal line. Fig. 5A the gate conductor 150 is conductively connected to the front signal line 140F via an upper gate via-connector VG, and the front signal line 120F is conductively connected to the front signal line 120F via an upper via-connector VT.

[0033] Fig. 5B are layout diagrams of the inverter circuit 500 in Fig. 5A according to some embodiments. The lower section of Fig. 5B is identical to the lower section of Fig. 4B. The upper section of Fig. 5B is a modification of the upper section of Fig. 4B. The upper gate via connector structure VG in Fig. 4B, which lies above the layout structure of the gate conductor 150, is moved to a new position that lies above the layout structure of the front signal line 140F. At the intersection between the conductive segment 132p and the front signal line 120F, an upper via connector structure VT is added.

[0034] Fig. 5C are cross-sectional views of the inverter circuit 500 in Fig. 5A in cutting planes that pass through line PP' and line QQ' in Fig. 5B can be specified, according to some embodiments. The cross-section of the cutting plane QQ' in Fig. 5C is identical to the cross-section of the cutting plane QQ' in Fig. 4C. The cross-section of the cutting plane PP' in Fig. 4C is almost the same as the cross-section of the cutting plane PP' in FIG. Fig. 4C, except that in Fig. 5C an upper via connector VT is added, which connects the front signal line 120F to the conductive segment 132p.

[0035] Fig. 5D are cross-sectional views of the inverter circuit 500 in Fig. 5A in cutting planes that pass through the line RR' in Fig. 5B can be specified, according to some embodiments. The cross-sectional view in Fig. 5D is a modification of the cross-sectional view in Fig. 1D. The upper via connector VT in Fig. 5D connects the front signal line 140F conductively to the gate conductor 150, while the upper via connector VT in Fig. 1D connects the front signal line 120F conductively to the gate conductor 150.

[0036] The inverter circuit 600 in Fig. 6A is a modification of the 500 inverter circuit in Fig. 5A. The inverter circuit 600 from Fig. 6A uses the rear signal line 120B as the input signal line, while the inverter circuit 500 of Fig. 5A uses the front signal line 140 as the input signal line. Fig. 6A the gate conductor 150 is conductively connected to the rear signal line 120B via a lower gate via-connector VG.

[0037] Fig. 6B are layout diagrams of the inverter circuit 600 in Fig. 6A according to some embodiments. The layout diagrams in Fig. 6B are a modification of the layout diagrams in Fig. 5B. The upper gate via connector structure VG (which lies above the layout structure of the front signal line 140F) in the upper section of Fig. 5B is connected via a lower gate via connector structure VG (which lies above the layout structure of the rear signal line 140B) in the lower section of Fig. Replaced by 5B.

[0038] Fig. 6C are cross-sectional views of the inverter circuit 600 in Fig. 6A in section planes that pass through the line RR' in Fig. 6B can be specified, according to some embodiments. The cross-sectional view in Fig. 6C is a modification of the cross-sectional view in Fig. 5D. In Fig. 6C, the gate conductor 150 is conductively connected to the rear signal line 120B via the lower gate via connector VG. For comparison, in Fig. 5D of the gate conductor 150 is conductively connected to the front signal line 140F via the upper gate via-connector VG.

[0039] The inverter circuit in each of the diagrams in Fig. 1A, Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A and Fig. 6A has a gate conductor 150 that connects the gate terminal of the PMOS transistor T1p to the gate terminal of the NMOS transistor T1n. In each inverter circuit, the gate terminal of the PMOS transistor T1p and the gate terminal of the NMOS transistor T1n receive the same logic input signal “IN”, as in Fig. Figure 7A shows that in some configurations of a sub-circuit, the gate terminal of the PMOS transistor T1p and the gate terminal of the NMOS transistor T1n receive different logic input signals. For example, in the sub-circuit of Fig. 7B The gate terminal of the PMOS transistor T1p and the gate terminal of the NMOS transistor T1n carry the logic input signal “IN-A” or the logic input signal “IN-B” if the gate terminals of the PMOS transistor and the NMOS transistor in a CFET receive different input signals. The gate conductor of the PMOS transistor is separated from the gate conductor of the NMOS transistor by a gate stack insulator.

[0040] Fig. 8A is a diagram of a partial circuit 800 in Fig. 7B, which is implemented with a CFET, according to some embodiments. The sub-circuit 800 in Fig. 8A is in comparison to the inverter circuit 600 in Fig. 6A modified by adding a gate conductor 150 in Fig. 6A is replaced by two gate conductors, 150P and 150n, which are electrically isolated from each other. Fig. 8A. The gate conductors 150P, extending in the Y direction, intersect the p-active-region semiconductor structure 50p at a channel region of a PMOS transistor T1p. The gate conductors 150n, extending in the Y direction, intersect the n-active-region semiconductor structure 50n at a channel region of an NMOS transistor T1n. The gate conductors 150P and 150P are separated along the Z direction by the gate stack insulator 815, which extends in the Y direction. The gate conductor 150P is conductively connected to the front signal line 120F via an upper gate via connector VG, and the gate conductor 150n is conductively connected to the rear signal line 120B via a lower gate via connector VG.

[0041] Fig. 8B are layout diagrams of subcircuit 800 in Fig. 8A according to some embodiments. The layout diagrams in Fig. 8B are almost identical to the layout diagrams in Fig. 6B, except that the triangle symbols at each end of the layout structure for the gate conductor 150n of Fig. 8B specifies that the gate conductor structure 150n is separated from the gate conductor 150p by a gate stack isolator 815. There are various embodiments of layout designs that specify the separation of two stacked gate conductors by a gate stack isolator 815. The layout diagram in Fig. 8B belongs to one of the specific embodiments in which one or more special symbols 885 (such as the triangle symbols) are placed on at least one of the two stacked gate conductor structures (for example, the structure for gate conductor 150n or the structure for gate conductor 150n). In alternative embodiments, the comparison between the structure for gate conductor 150n and the structure for gate conductor 150n specifies whether the gate conductor 150n and the gate conductor 150n are separated by a gate stack isolator 815. For example, if in some embodiments the structure for gate conductor 150n and the structure for gate conductor 150n are different, the layout diagram indicates that the gate conductor 150n and the gate conductor 150n are separated by a gate stack isolator 815.However, if in some embodiments the structure for gate conductor 150n and the structure for gate conductor 150n are the same, the layout diagram indicates that gate conductor 150n and gate conductor 150n are conductively connected to each other.

[0042] Fig. 8C is a cross-sectional view of sub-circuit 800 in Fig. 8A in cutting planes that pass through the line RR' in Fig. 8B can be specified, according to some embodiments. In the cross-section of the cutting plane PP' in Fig. In 8C, the gate conductor 150n and the gate conductor 150n are separated by the gate stack insulator 815. The gate conductor 150p is conductively connected to the front signal line 120F via an upper gate via connector VG, and the gate conductor 150n is conductively connected to the rear signal line 120B via a lower gate via connector VG.

[0043] Fig. Figure 9A shows layout diagrams of an AOI logic circuit 900 according to some embodiments. Fig. 9B is a circuit diagram of the AOI logic circuit 900 in Fig. 9A according to some embodiments. The layout diagram in Fig. 9A contains an upper section of the layout and a lower section of the layout. The upper section of the layout contains the layout structures for specifying the p-active region semiconductor structure 50p, the gate conductors (gB2, gB1, gA1 and gA2), the conductive segments (932p, 934P, 935P, 936p and 938p), the front signal lines (920F, 942F, 944F and 946F), the front power supply line 30F and various via connectors. The lower section of the layout contains the layout structures for specifying the n active region semiconductor structure 50n, the gate conductors (gB2, gB1, gA1 and gA2), the conductive segments (932n, 934n, 935n, 936n and 938n), the rear signal lines (922B, 924B, 942B and 944B), the rear power supply line 30B and various via connectors.

[0044] As described in the upper section of Fig. As specified in 9A, each of the gate conductors gB2, gB1, gA1, and gA2 intersects the p-active region semiconductor structure 50p at the channel region of a PMOS transistor, forming the gate terminals of the p-transistors pB2, pB1, pA1, and pA2, respectively. As shown in the lower section of Fig. Specified as 9A, each of the gate conductors gB2, gB1, gA1, and gA2 intersects the n-active-region semiconductor structure 50n at the channel region of an NMOS transistor, forming the gate terminals of the n-transistors nB2, nB1, nA1, and nA2, respectively. Each of the p-transistors pB2, pB1, pA1, and pA2 is stacked with a corresponding n-transistor nB2, nB1, nA1, and nA2. The p-transistors and the n-transistors are listed in the transistor table in Fig. 9C is listed according to the positions of the transistors in the upper or lower section of the layout diagram. The p-transistors and the n-transistors are also shown in the circuit diagram of Fig. 9B according to the positions of the transistors in the upper section and the lower section of the layout diagram.

[0045] In the layout diagram of Fig. According to some embodiments, if the structures for a pair of stacked gate conductors are identical in the upper and lower sections of the layout diagram, the layout diagram indicates that the gate conductors in the pair of stacked gate conductors are conductively connected to each other. Consequently, as in Fig. 9A and Fig. Figure 9B shows that the gate terminals of transistors pB2 and nB2 are conductively connected to each other via the gate conductor gB2, the gate terminals of transistors pB1 and nB1 are conductively connected to each other via the gate conductor gB1, the gate terminals of transistors pA1 and nA1 are conductively connected to each other via the gate conductor gA1, and the gate terminals of transistors pA2 and nA2 are conductively connected to each other via the gate conductor gA2. Furthermore, in the Fig. Gate conductors gB2 and gB1 on pins 9A-9B are connected to the front signal lines 942F and 944F, respectively, via a corresponding upper gate via connector VG. Gate conductors gA1 and gA2 are connected to the rear signal lines 922B and 924B, respectively, via a corresponding lower gate via connector VG.

[0046] Furthermore - as shown by the layout diagram of Fig. 9A specified and as shown in the circuit diagram of Fig. Figure 9B shows that each of the conductive segments intersects one of the active-region semiconductor structures. Each of the conductive segments 932p, 934P, 935P, 936p, and 938p intersects the p-active-region semiconductor structure 50p at a terminal region of a p-type transistor. Each of the conductive segments 932n, 934n, 935n, 936n, and 938n intersects the n-active-region semiconductor structure 50n at a terminal region of an n-type transistor. The terminal region of a transistor (which is either p-type or n-type) is either a source region or a drain region of the transistor.

[0047] In the Fig. In segments 9A-9B, the conductive segment 934p is conductively connected to the front-side power supply line 30F via an upper via connector VT, and the front-side power supply line 30F is configured to maintain a first supply voltage VDD. Each of the conductive segments 932n and 938n is conductively connected to the rear-side power supply line 30B via a corresponding lower via connector VB, and the rear-side power supply line 30B is configured to maintain a second supply voltage VSS. Each of the conductive segments 932p, 935p, and 938p is conductively connected to the front-side signal lines 920F via a corresponding upper via connector VT. The conductive segment 935n is conductively connected to the rear-side signal line 844B via a corresponding lower via connector VB.The rear signal line 844B is in turn conductively connected to the conductive segments 936p via a corresponding upper via connector VTB. The top-to-bottom via connector VTB is connected by a pair of corresponding via connector structures in the upper and lower sections of the [unclear text]. Fig. 9A specified.

[0048] Fig. Figure 10A shows layout diagrams of a Scan-D flip-flop circuit (SDF circuit) 1000 according to some embodiments. Fig. 10B is a circuit diagram of the SDF circuit 1000 according to the specification by the layout diagrams in Fig. 10A according to some embodiments. Fig. 11A is an equivalent circuit diagram of the SDF circuit in Fig. 10B according to some embodiments. The circuit diagram in Fig. 10B precisely follows the physical positions of various elements (such as the p-transistors, the n-transistors, the front-side signal lines, the rear-side signal lines, and the via connectors) in the layout diagram of Fig. 10A, while the circuit diagram in Fig. 11A the transistors in Fig. 10A grouped into different functional blocks.

[0049] Fig. Figure 11B is a circuit diagram of the SDF circuit 1000, shown in functional blocks, according to some embodiments. Fig. In diagram 11B, the SDF circuit 1000 comprises a dual-input multiplexer 1110, a master latch 1120, a transmission gate 1130, a slave latch 1140, and an inverter 1150. The dual-input multiplexer 1110 receives a data signal D at a first input 1111 and a sample input signal SI at a second input 1112. The dual-input multiplexer 1110, the master latch 1120, and the slave latch 1140 are each clocked by clock signals synchronized with the clock signal CP. Depending on the logic levels of the selection activation signal SE, either the data signal D or the sample input signal SI is generated as an inverted signal at the output 1119 of the dual-input multiplexer 1110.In some embodiments, the inverse of the data signal is generated at output 1119 when the selection activation signal SE is logic HIGH, and the inverse of the sample input signal SI is generated at output 1119 when the selection activation signal SE is logic LOW. Output 1119 of the dual-input multiplexer 1110 is connected to the input of the master latch 1120. The transfer gate 1130 is connected between the master latch 1120 and the slave latch 1140. The output of the slave latch 1140 is connected to the input of the inverter 1150. The output of the SDF circuit 1000 is provided by the output of the inverter 1150.

[0050] In Fig. 10A specifies various elements for forming the SDF circuit 1000 through the corresponding layout structures. The layout diagram in Fig. 10A contains an upper section of the layout and a lower section of the layout. The elements that are defined by the upper section of Fig. 10A, which are specified, feature a first p-active-region semiconductor structure 52p and a second p-active-region semiconductor structure 54p. The elements specified by the lower section of Fig. 10A specified, they feature a first n-active-region semiconductor structure 52n and a second n-active-region semiconductor structure 54n. In the SDF circuit 1000, which is represented by the layout diagram of Fig. Specified to 10A, various transistors are formed in the active region semiconductor structures. The p-transistors and n-transistors in the SDF 1000 circuit are listed in the transistor table in Fig. 10C according to the positions of the transistors in the layout diagram of Fig. Listed in 10A. The transistors in the first p-active-region semiconductor structure 52p include the p-transistors pQB, pSL_a, pSE_o, pSL_bx, pCK_SL, pCKb_TX, pML_ax, and pCP. The transistors in the second p-active-region semiconductor structure 54p include the p-transistors pSI, pSEB, pD, pSE, pCK_MX, pCKb_ML, pML_b, and pCKb_o. The transistors in the first n-active-region semiconductor structure 52p include the n-transistors nQB, nSL_a, nSE_o, nSL_bx, nCKb_SL, nCK_TX, nML_ax, and nCP. The transistors in the second n-active-region semiconductor structure 54p include the n-transistors nSI, nSEB, nD, nSE, nCKb_MX, pCK_ML, nML_b and nCKb_o.

[0051] In the upper section of Fig. At 10A, each of the gate conductors gQB, gSL_a, gSE, gSL_bx, gpCKbb, gpCKb, gML_ax, and gCP cuts the first p-active-region semiconductor structure 52p at the channel region of a PMOS transistor and accordingly forms the gate terminal of one of the p-transistors pQB, pSL_a, pSE_o, pSL_bx, pCK_SL, pCKb_TX, pML_ax, and pCP. In the lower section of Fig. At 10A, each of the gate conductors gQB, gSL_a, gSE, gSL_bx, gnCKb, gnCKbb, gML_ax and gCP cuts the first n active region semiconductor structure 52n at the channel region of an NMOS transistor and accordingly forms the gate terminal of one of the n transistors nQB, nSL_a, nSE_o, nSL_bx, nCKb_SL, nCK_TX, nML_ax and nCP. Each of the p-transistors pQB, pSL_a, pSE_o, pSL_bx, pCK_SL, pCKb_TX, pML_ax and pCP is stacked accordingly with one of the n-transistors nQB, nSL_a, nSE_o, nSL_bx, nCKb_SL, nCK_TX, nML_ax and nCP.

[0052] In the upper section of Fig. At 10A, each of the gate conductors gSI, gSEB, gD, gSE, gpCKbb, gpCKb, gML_b and gCKb_o cuts the second p-active-region semiconductor structure 54p at the channel region of a PMOS transistor and accordingly forms the gate terminal of one of the p-transistors pSI, pSEB, pD, pSE, pCK_MX, pCKb_ML, pML_b and pCKb_o. In the lower section of Fig. At 10A, each of the gate conductors gSI, gSEB, gD, gSE, gnCKb, gnCKbb, gML_b and gCKb_o cuts the second n-active-region semiconductor structure 54n at the channel region of an NMOS transistor and accordingly forms the gate terminal of one of the n-transistors nSI, nSEB, nD, nSE, nCKb_MX, nCK_ML, nML_b and nCKb_o. Each of the p-transistors pSI, pSEB, pD, pSE, pCK_MX, pCKb_ML, pML_b and pCKb_o is stacked accordingly with one of the n-transistors nSI, nSEB, nD, nSE, nCKb_MX, nCK_ML, nML_b and nCKb_o.

[0053] In the SDF circuit 1000, which is represented by the layout diagram of Fig. As specified in 10A, the gate terminals of the PMOS and NMOS in each pair of stacked transistors are conductively connected by the same gate conductor shared by the PMOS and NMOS, except for the PMOS and NMOS in four pairs of stacked transistors, which are assigned to the gate conductors gpCKbb, gnCKb, gpCKb, and gnCKbb. The special symbols 885 (such as the triangle symbols) at the ends of the layout structure for the gate conductor bnCKb specify that the stacked gate conductors gpCKbb and gnCKb are separated by a gate stack insulator. The special symbols 885 (such as the triangle symbols) at the ends of the layout structure for the gate conductors gnCKbb specify that the stacked gate conductors gpCKb and gnCKbb are separated by a gate stack isolator.The gate terminals of each of the following four stacked transistor pairs are not directly connected because of the gate stack insulators: a first stacked transistor pair pCK_SL and nCKb_SL, a second stacked transistor pair pCKb_TX and nCK_TX, a third stacked transistor pair pCK_MX and nCKb_MX, and a fourth stacked transistor pair pCKb_ML and nCK_ML. In alternative embodiments, distinguishable layout structures for the stacked gate conductors gpCKbb and gnCKb are used to specify the separation of the stacked gate conductors gpCKbb and gnCKb by a gate stack isolator, and distinguishable layout structures for the stacked gate conductors gpCKb and gnCKbb are used to specify the separation of the stacked gate conductors gpCKb and gnCKbb by a gate stack isolator.

[0054] Furthermore, the layout diagram shows in Fig. 10A also includes dummy gate strip structures 110 within the cell of the SDF cell and at the edges of the SDF cell. The intersections between the dummy gate strip structures 110 and the layout structure of the p-active region semiconductor structures (52p and 54p) specify the isolation regions in the p-active region semiconductor structure. The intersections between the dummy gate strip structures 110 and the layout structure of the n-active region semiconductor structures (52n and 54n) specify the isolation regions in the n-active region semiconductor structure. The isolation regions at the edges of the SDF cell electrically isolate the active regions in the SDF cell from the active regions in the neighboring cells.Within the SDF cell, the dummy gate strip structure 110, which cuts the p active region semiconductor structure 32p, specifies an isolation region between the p transistors pSL_a and pSE_o, and the dummy gate strip structure 110, which cuts the p active region semiconductor structure 34p, specifies an isolation region between the p transistors pSE and pCK_MX. Within the SDF cell, the dummy gate strip structure 110, which intersects the n active-region semiconductor structure 32n, specifies an isolation region between the n transistors nSL_a and nSE_o, and the dummy gate strip structure 110, which intersects the n active-region semiconductor structure 34n, specifies an isolation region between the n transistors nSE and nCKb_MX. Each of the isolation regions in the active-region semiconductor structures (52p, 54p, 52n, or 54n) is listed in the transistor table of . Fig. 10C identified as a CPODE. The CPODE in the transistor table of Fig. Reference 10C indicates that the "Continuous Poly on Oxide Definition" technology (Continuous Poly on Oxide Definition, CPODE technology) is a possible technology for generating the insulation regions in the active region semiconductor structures (52p, 54p, 52n or 54n). Other suitable technologies, such as the "Poly on Oxide Definition Edge" technology (PODE technology), are also within the considered scope of this disclosure.

[0055] In the upper section of Fig. 10A each of the conductive segments C31p-C39p and C30p cuts the first p-active-region semiconductor structure 52p at a connection region of at least one of the p-transistors pQB, pSL_a, pSE_o, pSL_bx, pCK_SL, pCKb_TX, pML_ax, and pCP. Each of the conductive segments C71p-C79p and C70p cuts the second p-active-region semiconductor structure 54p at a connection region of at least one of the p-transistors pSI, pSEB, pD, pSE, pCK_MX, pCKb_ML, pML_b, and pCKb_o. In addition to the gate conductors and the conductive segments that cut the p-active-region semiconductor structures (52p and 54p), as in the section above. Fig. Specified to 10A, the SDF 1000 circuit also features front-side signal lines (F22, F24, F26, F28, F42, F44, F62, F64, F66, F68, F82, F84 and F86) and front-side operating voltage lines (32F and 34F).

[0056] In the lower section of Fig. At 10A, each of the conductive segments C31n-C39n and C30n cuts the first n-active-region semiconductor structure 52n at a connection region of at least one of the n-transistors nQB, nSL_a, nSE_o, nSL_bx, nCKb_SL, nCK_TX, nML_ax, and nCP. Each of the conductive segments C71n-C79n and C70n cuts the second n-active-region semiconductor structure 54n at a connection region of at least one of the n-transistors nSI, nSEB, nD, nSE, nCKb_MX, nCK_ML, nML_b, and nCKb_o. In addition to the gate conductors and the conductive segments that intersect the n-active-region semiconductor structures (52n and 54n), as shown in the lower section of Fig. Specified to 10A, the SDF circuit 1000 also features the rear signal lines (B22, B24, B26, B42, B44, B46, B62, B64, B66, B82, B84 and B86) and the rear operating voltage lines (32B and 34B).

[0057] The conductive connections between the various elements of the SDF 1000 circuit are shown in the layout diagram of Fig. 10A as also shown in the circuit diagrams of the Fig. Figures 11A-11B show each conductive segment C32p, C35p, and C39p connected to the first front-side power supply line 32F via a corresponding upper via connector VT. Each conductive segment C71p, C75p, and C79p connected to the second front-side power supply line 34F via a corresponding upper via connector VT. Each conductive segment B32n, B35n, and B39n connected to the first rear-side power supply line 32B via a corresponding lower via connector VB. Each conductive segment B72n and B79n connected to the second rear-side power supply line 34B via a corresponding lower via connector VB.

[0058] In Fig. In section 10A, the stacked conductive segments C31p and C31n are conductively connected via a corresponding conductive segment interconnect (VMD) and form a signal output node oQB. The stacked conductive segments C33p and C33n are conductively connected via a corresponding conductive segment interconnect (VMD) and form a signal output node oSL_a. The stacked conductive segments C34p and C34n are conductively connected via a corresponding conductive segment interconnect (VMD) and form a signal output node oSE_o. The stacked conductive segments C37p and C37n are conductively connected via a corresponding conductive segment interconnect (VMD) and form a signal output node oCK_SL.The stacked conductive segments C77p and C77n are conductively connected via a corresponding conductive segment interconnect (VMD) and form a signal output node oCK_MX and a signal output node oCK_ML, respectively. The stacked conductive segments C38p and C38n are conductively connected via a corresponding conductive segment interconnect (VMD) and form a signal output node oML_ax. The stacked conductive segments C30p and C30n are conductively connected via a corresponding conductive segment interconnect (VMD) and form a signal output node oCP. The stacked conductive segments C70p and C70n are conductively connected via a corresponding conductive segment interconnect (VMD) and form a signal output node oCKb_o. The signal output nodes (oQB, oSL_a, oSE_o, oCK_SL, oCK_MX, oCK_ML, oML_ax, oCP and oCKb_o) in the layout diagram of . Fig. 10A are also shown in the circuit diagrams of Fig. 10B and Fig. 11A identified and labeled.

[0059] The elements that are defined by the layout diagram of Fig. Different via connectors are available for 10A ratings. When an upper gate via connector (VG) is placed at the intersection of a front signal line and a gate conductor, the upper gate via connector (VG) specifies that the front signal line is directly connected to the gate conductor. When a via connector (VT) is placed at the intersection of a front signal line and a conductive segment, the VT via connector (VT) specifies that the front signal line is directly connected to the conductive segment. When a lower gate via connector (VG) is placed at the intersection of a back signal line and a gate conductor, the lower gate via connector (VG) specifies that the back signal line is directly connected to the gate conductor.When a via connector VB is placed at an intersection of a backside signal line and a conductive segment, the via connector VB specifies that the backside signal line is directly connected to the conductive segment.

[0060] In the Fig. On components 10A-10B, the front-side signal line F42 is directly connected to the gate conductors gQB and gSL_bx, as well as to the conductive segment C33p. The front-side signal line F64 is directly connected to each of the conductive segments C73p and C76p. To transmit an inverted clock signal ckb to the gate conductor gpCKb from the signal output node oCP, the front-side signal line F44 is directly connected to the gate conductor gpCKb and the conductive segment C30p. To transmit a clock signal ckbb to the gate conductor gpCKbb from the signal output node oCKb_o, the front-side signal line F86 is directly connected to the gate conductor gpCKbb and the conductive segment C70P.To connect the signal output node oSE_o to the gate conductor gSEB, the front-side signal line F22 is directly connected to the conductive segment C34p, and the front-side signal line F82 is directly connected to the gate conductor gSEB, while the front-side signal lines F22 and F82 are conductively connected to each other via a conductor trace Mi1_1 running in the Y direction. To connect the signal output nodes oCK_MX and oCK_ML to the gate conductor gML_ax, the front-side signal line F26 is directly connected to the gate conductor gML_ax, and the front-side signal line F66 is directly connected to the conductive segment C77p, while the front-side signal lines F26 and F66 are conductively connected to each other via a conductor trace M1_2 running in the Y direction.

[0061] In the IC device, which is shown in the layout diagram of Fig. As specified for 10A, the conductors M1_1 and M1_2 are conductors in a conductive layer (such as an M1 layer) that is separated from the front-side conductive layer by an insulating layer. Each of the front-side signal lines F22 and F82 is directly connected to conductor M1_1 via a corresponding via VIIAo connector that passes through the insulating layer. Each of the front-side signal lines F26 and F66 is directly connected to conductor M1_2 via a corresponding via VIIAo connector that passes through the insulating layer. In the layout diagram in Fig. Although the via connectors VIIAo are represented by corresponding layout structures in 10A, the conductor tracks M1_1 and M1_2 are only represented by "bar" lines to improve the readability of the layout diagram. In alternative embodiments of the layout diagram in Fig. In addition to the via connectors VIIAo, 10A also represents each of the conductor tracks M1_1 and M1_2 by a corresponding layout structure, which specifies not only the position but also the geometry (such as the width and length) of the represented conductor track.

[0062] In the Fig. For nodes 10A-10B, the rear signal line B24 is directly connected to the gate conductor gSL_a and the conductive segment C37n. The rear signal line B64 is directly connected to the conductive segments C74n and C76n. The rear signal line B82 is directly connected to the conductive segments C71n and C75n. To transmit an inverted clock signal ckb to the gate conductor gnCKb from the signal output node oCP, the rear signal line B46 is directly connected to the gate conductor gnCKb and the conductive segment C3on. To transmit a clock signal ckbb to the gate conductor gnCKbb from the signal output node oCKb_o, the rear signal line B66 is directly connected to the gate conductor gnCKbb and the conductive segment C70n.To connect the signal output node oML_ax to the gate conductor gML_b, the rear signal line B26 is directly connected to the conductive segment C38n, and the rear signal line B84 is directly connected to the gate conductor gML_b, while the rear signal lines B26 and B84 are conductively connected to each other via a conductor N1_1 running in the Y direction. To connect the signal output node oCP to the gate conductor gCKb_o, the rear signal line B86 is directly connected to the gate conductor gCKb_o, while the rear signal line B86 is conductively connected to the rear signal line B46 via a conductor N1_2 extending in the Y direction.

[0063] In the IC device, which is shown in the layout diagram of Fig. As specified for 10A, traces N1_1 and N1_2 are located in a separate backside conductive layer, separated from the backside conductive layer by insulating materials. Each of the backside signal lines B26 and B84 is directly connected to trace N1_1 via a corresponding backside via VIAo that passes through the insulating materials. Each of the backside signal lines B46 and B86 is directly connected to trace N1_2 via a corresponding backside via VIAo that passes through the insulating materials. This is shown in the layout diagram in Fig. In 10A, the rear via connectors VIIAo are represented by corresponding layout structures, but the conductor tracks N1_1 and N1_2 are only represented by "bar" lines to improve the readability of the layout diagram. In alternative embodiments of the layout diagram in Fig. In addition to the rear via connectors VIIAo, 10A also represents each of the conductor tracks N1_1 and N1_2 by a corresponding layout structure, which specifies not only the position but also the geometry (such as the width and length) of the represented conductor track.

[0064] Furthermore, in the Fig. On components 10A-10B, the front-side signal line F62 is directly connected to the gate conductor gSI and functions as an input signal line for the sampling input signal "SI". The front-side signal line F84 is directly connected to the gate conductor gD and functions as an input signal line for the input data "D" of the SDF 1000 circuit. The front-side signal line F28 is directly connected to the gate conductor gCP and functions as an input signal line for the clock signal "CP". The rear-side signal line B44 is directly connected to the gate conductor gSE and functions as an input signal line for the sampling activation signal "SE". The rear-side signal line B22 is directly connected to the conductive segments C31n and functions as an output signal line for the output data "Q" of the SDF 1000 circuit.

[0065] The circuit diagram in Fig. 10B precisely follows the physical positions of various elements (such as the transistors, conductor tracks, and via connectors) in the layout diagram of Fig. 10A, while the circuit diagram in Fig. 11A the transistors in Fig. 10B is grouped into different functional blocks.

[0066] In Fig. 11A and Fig. In 10B, five p-transistors (pSI, pSEB, pSE, pD and pCK_MX) and five n-transistors (nSI, nSE, nSEB, nD and nCK_MX) are used to form the dual-input multiplexer 1110 (as shown in Fig. 11B shown). The p-transistor pML_ax and the n-transistor nML_ax form an inverter 1122 in the master latch 1120. Two p-transistors (pML_b and pCKb_ML) and two n-transistors (nML_b and nCK_ML) form a clocked inverter 1124 in the master latch 1120. The p-transistor pCKb_TX and the n-transistor nCK_TX form the transmission gate 1130. The p-transistor pSL_a and the n-transistor nSL_a form an inverter 1142 in the slave latch 1120. Two p-transistors (pSL_bx and pCK_SL) and two n-transistors (nSL_bx and nCKb_SL) form a clocked inverter 1144 in the master latch. 1120. The p-transistor pQB and the n-transistor nQB form the inverter 1150.

[0067] In Fig. 11A and Fig. In component 10B, the p-transistor pSE_o and the n-transistor nSE_o form an inverter 1170 for generating an inverted selection activation signal SEB from the selection activation signal SE. The selection activation signal SE is coupled into the gate terminals of the p-transistor pSE and the n-transistor nSE. The p-transistor pCP and the n-transistor nCP form an inverter 1180 for generating an inverted clock signal ckb from the clock signal CP. The p-transistor pCKb_o and the n-transistor nCKb_o form an inverter 1190 for generating a clock signal ckbb from the inverted clock signal ckb. The inverted clock signal ckb is coupled into the gate terminals of the p-transistors pCKb_TX and pCKb_ML and the gate terminals of the n-transistors nCKb_SL and nCKb_MX. The clock signal ckbb is coupled into the gate terminals of the p-transistors pCK_SL and pCK_MX and the gate terminals of the n-transistors nCK_TX and nCK_ML.

[0068] The various IC devices (such as 100-600 and 800-1000) described in this disclosure have improved current connections from the source terminals of the PMOS and NMOS transistors to the corresponding supply voltages compared to some alternatives in other implementations of the supply voltage lines. In general, it is possible to connect the source terminals of PMOS and NMOS transistors to the corresponding supply voltages with reduced source resistance if the first supply voltage, VDD, is provided by the front supply voltage line 30F in the front conductive layer, and the second supply voltage, VSS, is provided by the back supply voltage line 30B in the back conductive layer.More precisely, if the first supply voltage VDD is provided by the front-side power supply line 30F, the source terminal of the PMOS transistor is connected to the first supply voltage VDD by connecting the conductive source segment of the PMOS transistor to the front-side power supply line 30F via an upper via connector VT. If the second supply voltage VSS is provided by the rear-side power supply line 30B, the source terminal of the NMOS transistor is connected to the second supply voltage VSS by connecting the conductive source segment of the NMOS transistor to the rear-side power supply line 30B via a lower via connector VB.

[0069] In contrast, in some alternative implementations, where both the first supply voltage VDD and the second supply voltage VSS are provided in the backside conductive layer, the conductive source segment of the PMOS transistor must be connected to the supply voltage line for VDD via a top-to-bottom via-connector VTB.Because the electrical resistance of the top-to-bottom via connector VTB is greater than the electrical resistance of the top via connector VT (mainly due to the length difference), the connection from the source terminal of the PMOS transistor to a supply voltage line in the backside conductive layer (as in the alternative implementations) has a higher specific resistance than the connection from the source terminal of the PMOS transistor to the frontside supply voltage line 30F (as described in the present disclosure).Similarly, in some alternative implementations, if both the first supply voltage VDD and the second supply voltage VSS are provided on the front side of the conductive layer, the conductive source segment of the NMOS transistor must be connected to the supply voltage line for VSS via a bottom-to-top via-connector VBT.Because the electrical resistance of the bottom-to-top via connector VBT is greater than the electrical resistance of the bottom via connector VB (mainly due to the length difference), the connection from the source terminal of the NMOS transistor to a supply voltage line in the front conductive layer (as in the alternative implementations) has a greater specific resistance than the connection from the source terminal of the NMOS transistor to the rear supply voltage line 30B (as described in the present disclosure).

[0070] In addition to improving power connections for both PMOS and NMOS transistors, the front-side power supply lines also provide signal shielding between the cells for the front-side signal lines, and the rear-side power supply lines also provide signal shielding between the cells for the rear-side signal lines when multiple IC cells are arranged in a column (extending in the Y direction). Fig. 12A and Fig. Figures 12B represent the upper and lower sections of a layout diagram of a multi-cell integrated circuit 1200 according to some embodiments. The multi-cell integrated circuit 1200 has at least three IC cells (for example, cell A, cell B, and cell C) arranged side by side in a column extending in the Y direction. Cell A and cell B share a common cell boundary 129oAB, and cell B and cell C share a common cell boundary 129oBC. Each of cell A, cell B, and cell C has a p-active-region semiconductor structure that is 50p(1), 50p(2), and 50p(3), respectively, as shown in Figure 12B. Fig. 12A shown. Each of cell A, cell B and cell C has an n-active-region semiconductor structure that is 50n(1), 50n(2) and 50n(3) respectively, as shown in Fig. 12B shown.

[0071] In the Fig. In the 1200 multi-cell circuit, each IC cell (12A-12B) is connected to a corresponding front-side power supply line to provide the first power supply, VDD. For example, each of cells A, B, and C is connected to one of the front-side power supply lines 30F(1), 30F(2), and 30F(3), respectively. Each of the IC cells in the 1200 multi-cell circuit is also connected to a corresponding rear-side power supply line to provide the second power supply, VSS. For example, each of cells A, B, and C is connected to one of the rear-side power supply lines 30B(1), 30B(2), and 30B(3), respectively.

[0072] Each of the front-side power supply lines 30F(1), 30F(2), and 30F(3) effectively acts as a "signal ground" when each is held at a constant supply voltage VDD. Consequently, each front-side power supply line reduces the capacitive leakage coupling between the front-side signal lines in adjacent IC cells. For example, the capacitive leakage coupling between the front-side signal lines 120F(1) / 140F(1) in cell A and the front-side signal lines 120F(2) / 140F(2) in cell B is reduced by the front-side power supply line 30F(2). The capacitive leakage couplings between the front signal lines 120F(2) / 140F(2) in cell B and the front signal lines 120F(3) / 140F(3) in cell C are reduced by the front operating voltage line 30F(3).Similarly, each of the rear-side power supply lines 30B(1), 30B(2), and 30B(3) effectively acts as a "signal ground" when each is held at a constant supply voltage VSS. Consequently, each rear-side power supply line reduces the capacitive leakage coupling between the rear-side signal lines in adjacent IC cells. For example, the capacitive leakage coupling between the rear-side signal lines 120B(1) / 140B(1) in cell A and the rear-side signal lines 120B(2) / 140B(2) in cell B is reduced by the rear-side power supply line 30B(2). The capacitive stray couplings between the rear signal lines 120B(2) / 140B(2) in cell B and the rear signal lines 120B(3) / 140B(3) in cell C are reduced by the rear operating voltage line 30B(3).

[0073] In the various IC devices (such as 100-600, 800-1000, and 1200) described in this disclosure, each IC cell is powered by a front-side power supply line and a rear-side power supply line, and each IC cell is also provided with both a front-side and a rear-side signal line for signal routing. The maximum allowable widths (along the Y-direction) of the active-region semiconductor structures in the various IC devices (such as 100-600, 800-1000, and 1200, as described in this disclosure) are larger than the maximum allowable widths in some alternative implementations of the signal and power supply lines.

[0074] For example, in every embodiment of the Inverter 100-600, at least because both the front signal line 120F and the rear signal line 120B are available in a stacked position, it is possible that the width of the p-active region semiconductor structure 50p extends along the negative Y direction beyond the edges of the front signal lines 120F, and it is possible that the width of the n-active region semiconductor structure 50n extends along the negative Y direction beyond the edges of the rear signal lines 120B. More precisely, the width of the p-active region semiconductor structure 50p is not limited by a bottom-to-top via VBT for connecting a source / drain terminal of the NMOS to the front signal line 120F.The width of the n-active region semiconductor structure 50n is not limited by a top-to-bottom via connector VTB for connecting a source / drain terminal of the PMOS to the rear signal line 120B.

[0075] If we consider cell B in Fig. Taking 12A as an example, it is possible to extend the width of the p-active region semiconductor structure 50p(2) such that the two edges of the front signal line 12oF(2) are positioned parallel between the first edge 1251p and the second edge 1259p of the p-active region semiconductor structure 50p(2). It is practically possible to extend the width of the p-active region semiconductor structure 50p(2) until the first edge 1251p of the active region semiconductor structure 50p(2) reaches an edge VBT_e1 of the bottom-up via connector VBT. The bottom-up via connector VBT in cell B conductively connects the front signal line 140F(2) to a conductive segment (such as 136n in cell B). Fig. 12B), which intersects the n-active-region semiconductor structure 50n(2).

[0076] If we consider cell B in Fig. Taking 12B as an example, it is possible to extend the width of the n-active-region semiconductor structure 50n(2) such that the two edges of the front-facing signal line 12oB(2) are positioned parallel between the first edge 1251n and the second edge 1259n of the n-active-region semiconductor structure 50n(2). It is practically possible to extend the width of the n-active-region semiconductor structure 50n(2) until the first edge 1251n of the active-region semiconductor structure 50n(2) reaches an edge VBT_e1 of the top-down via connector VTB. The top-down via connector VTB in cell B conductively connects the front-facing signal line 140B(2) to a conductive segment (such as 138p in cell B). Fig. 12A), which intersects the p-active region semiconductor structure 50p(2).

[0077] Furthermore, in every embodiment of the Inverter 100-600, there is no bottom-to-top via VBT for connecting a source terminal of the NMOS to a supply voltage line in the front conductive layer. Consequently, the width of the active region semiconductor structure 50p along the positive Y direction may extend beyond the edges of the supply voltage line in the front conductive layer, unless its width is limited by other factors (such as design rules relating to the adjacent cell). Likewise, in every embodiment of the Inverter 100-600, there is no top-to-bottom via VTB for connecting a source terminal of the PMOS to a supply voltage line in the back conductive layer.Consequently, it is possible that the width of the active region semiconductor structure 50n extends along the positive Y direction beyond the edges of the operating voltage line in the backside conductive layer if the width extension of the active region semiconductor structure 50p along the positive Y direction is not limited by other factors (such as design rules relating to neighboring cells).

[0078] If we consider cell B in Fig. Taking 12A-12B as an example, it is possible to extend the width of the p-active region semiconductor structure 50p(2) such that the two edges of the front-side operating voltage line 30F(2) are both positioned parallel between the first edge 1251p and the second edge 1259p of the p-active region semiconductor structure 50p(2), because there is no bottom-to-top via connector VBT below the front-side operating voltage line 30F(2). Similarly, it is possible to extend the width of the n active region semiconductor structure 50n(2) such that the two edges of the front operating voltage line 30B(2) are both positioned parallel between the first edge 1251n and the second edge 1259n of the n active region semiconductor structure 50n(2) because there is no top-to-bottom via connector VTB positioned over the back operating voltage line 30B(2).

[0079] In some alternative embodiments, even when two or more front-side signal lines (not shown in the figure) are implemented between the front-side power supply line 30F(2) and the front-side signal line 140F(2), the top-to-bottom via connectors VBT in cell B are still implemented only for the front-side signal line 140F(2) to make the front-side signal line 140F(2) conductive with a conductive segment (such as 136n in Fig. 12B), which intersects the n-active-region semiconductor structure 50n(2). In the alternative embodiments, no bottom-up via connector VBT is implemented for the other two or more front-side signal lines located between the front-side power supply line 30F(2) and the front-side signal line 140F(2), and no bottom-up via connector VBT is implemented to conductively connect the other two or more front-side signal lines to the conductive segment (such as 136n in Fig. 12B), which intersects the n-active-region semiconductor structure 50n(2). That is, in the alternative embodiments, the distance between each bottom-to-top via connector VBT to the cell boundary 129oBC is minimized to maximize the width of the p-active-region semiconductor structure 50p(2), and bottom-to-top via connectors VBT are implemented only for the front-facing signal line, such as 140F(2), which is adjacent to the cell boundary running in the X direction.

[0080] In some alternative embodiments, even when two or more rear signal lines (not shown in the figure) are implemented between the rear power supply line 30B(2) and the rear signal line 140B(2), the top-to-bottom via connectors VTB in cell B are still implemented only for the rear signal line 140B(2) to make the rear signal line 140B(2) conductive with a conductive segment (such as, for example, 136p in Fig. 12A), which intersects the p-active region semiconductor structure 50p(2). In the alternative embodiments, no top-down via connector VTB is implemented for the other two or more rear signal lines located between the rear power supply line 30B(2) and the rear signal line 140B(2), and no top-down via connector VTB is implemented to conductively connect the other two or more rear signal lines to the conductive segment (such as 136p in Fig. 12A), which intersects the n-active-region semiconductor structure 50p(2). That is, in the alternative embodiments, the distance between each top-down via connector VTB to the cell boundary 129oBC is minimized to maximize the width of the n-active-region semiconductor structure 50n(2), and top-down via connectors VTB are implemented only for the rear-side signal line, such as 140B(2), which is adjacent to the cell boundary running in the X direction.

[0081] Fig. Figure 13 shows layout diagrams of a circuit cell with labeled dimensions according to some embodiments. The dimensions of the front-side power supply line, the front-side signal line, and the top via connectors are shown in the upper section of Figure 13. Fig. 13 labeled. The dimensions of the rear power supply line, the rear signal line, and the lower via connectors are shown in the lower section of Fig. 13 specified. The dimensions of the bottom-to-top via connector and the top-to-bottom via connector are specified in both the upper and lower sections of Fig. 13 labeled.

[0082] In the upper section of Fig. 13. The width Wa of the front-facing signal line 120F is in the range of 1.0 to 1.5 times the minimum metal width in the wafer. The width Wb of the front-facing power supply line 30F is in the range of 0.8 to 5.0 times the width Wa. The width Wc of the front-facing signal line 140F is in the range of 0.8 to 1.5 times the width Wa. The width We of the front-facing signal line 160F is in the range of 0.8 to 2.0 times the width Wa. In some embodiments, the lower limit of the width Wa is usually determined by the photolithography capability at the technology node of interest. In some embodiments, the upper limit of the width Wa is usually determined by the required number of conductor tracks. Increasing the width Wa reduces the number of conductor tracks available for each cell, thereby increasing the cell areas in some embodiments.

[0083] In the upper section of Fig. 13. The upper via connector VT1 connects the front-side operating voltage line 30F to a conductive segment, the upper via connector VT2 connects the front-side signal line 120F to a conductive segment, and the upper via connector VT3 connects the front-side signal line 160F to a conductive segment. The width “(a)” of the upper via connector VT2 is in the range of 1.0 to 1.5 times the minimum via width in the wafer, and the length “(b)” of the upper via connector VT2 is in the range of 1.0 to 1.5 times the minimum via length in the wafer. The width “(c)” of the upper via connector VT1 is in a range of 0.8 to 2.0 times the width “(a)”, and the length “(d)” of the upper via connector VT1 is in a range of 0.8 to 5.0 times the length “(b)”.The width “(1)” of the upper via connector VT1 is in a range of 0.8 to 2.0 times the width “(a)”, and the length “(j)” of the upper via connector VT1 is in a range of 0.8 to 2.0 times the length “(b)”.

[0084] In the upper section of Fig. 13. The bottom-to-top via connector VBT connects the front signal line 140F to a conductive segment for the transistor in the lower section of a CFET transistor stack, and the top-to-bottom via connector VTB connects the conductive segment for the transistor in the upper section of a CFET transistor stack to the rear signal line 140B (which is located in the lower section of Fig. 13 is shown).

[0085] The upper end of the bottom-to-top via connector VBT is in contact with the front-side signal line 140F. The upper end of the top-to-bottom via connector VTB is in contact with a conductive segment. The width “(e)” of the bottom-to-top via connector VBT at the upper end is in the range of 0.8 to 1.5 times the width “(a)”, and the length “(g)” of the bottom-to-top via connector VBT at the upper end is in the range of 0.8 to 1.5 times the length “(b)”. The width “(f)” of the top-to-bottom via connector VTB at the top end is in a range of 0.8 to 1.5 times the width “(a)”, and the length “(h)” of the top-to-bottom via connector VTB at the top end is in a range of 0.8 to 1.5 times the length “(b)”.

[0086] In some embodiments, the lower limits of width “(a)” and length “(b)” are usually determined by the reliability requirements and IR drop requirements at the technology node of interest. If the width “(a)” or length “(b)” becomes too small, the failure rates of the via holes during fabrication increase because the probability rises that some of the via holes will not fully open to receive the top via connectors. Furthermore, if the width “(a)” or length “(b)” becomes too small, the IR drop of the top via connectors increases, which can affect the reliability and performance of the fabricated integrated circuits.If the width “(a)” or the length “(b)” becomes too large, in some embodiments the number of available via connectors or the number of available conductor tracks for each cell is reduced, thereby increasing the cell areas.

[0087] In the lower section of Fig. 13. The width Wa' of the backside signal line 120B lies in a range of 1.0 to 1.5 times the minimum metal width of the wafer. The width Wb' of the backside power supply line 30B lies in a range of 0.8 to 5.0 times the width Wa'. The width Wc' of the backside signal line 140B lies in a range of 0.8 to 1.5 times the width Wa'. The width We of the backside signal line 160B lies in a range of 0.8 to 2.0 times the width Wa'. In some embodiments, the lower limit of the width Wa' is determined by the photolithography capability at the technology node of interest. In some embodiments, the upper limit of the width Wa' is determined by the required number of conductor tracks. In some embodiments, increasing the width Wa' reduces the number of conductor tracks available for each cell, thereby increasing the cell areas.

[0088] In the lower section of Fig. 13. The upper via connector VB1 connects the rear-side power supply line 30B to a conductive segment, the upper via connector VB2 connects the rear-side signal line 120B to a conductive segment, and the upper via connector VB3 connects the rear-side signal line 160B to a conductive segment. The width “(a')” of the upper via connector VB2 is in the range of 1.0 to 1.5 times the minimum via width in the wafer, and the length “(b')” of the upper via connector VB2 is in the range of 1.0 to 1.5 times the minimum via length in the wafer. The width “(c')” of the upper via connector VB1 is in a range of 0.8 to 2.0 times the width “(a')”, and the length “(d')” of the upper via connector VB1 is in a range of 0.8 to 5.0 times the length “(b')”.The width “(i')” of the upper via connector VB1 is in a range of 0.8 to 2.0 times the width “(a')”, and the length “(j')” of the upper via connector VB1 is in a range of 0.8 to 2.0 times the length “(b')”.

[0089] In the lower section of Fig. 13 The lower end of the bottom-to-top via connector VBT is in contact with a conductive segment, and the lower end of the top-to-bottom via connector VTB is in contact with the rear signal line 140B. The width “(e')” of the bottom-to-top via connector VBT at the lower end is in the range of 0.8 to 1.5 times the width “(a')”, and the length “(g')” of the bottom-to-top via connector VBT at the lower end is in the range of 0.8 to 1.5 times the length “(b')”. The width “(f)” of the top-to-bottom via connector VTB at the lower end is in a range of 0.8 to 1.5 times the width “(a')”, and the length “(h')” of the top-to-bottom via connector VTB at the lower end is in a range of 0.8 to 1.5 times the length “(b')”.

[0090] In some embodiments, the lower limits of the width “(a')” and the length “(b')” are determined by the reliability requirements and the IR drop requirements at the technology node of interest. If the width “(a')” or the length “(b')” becomes too small, the failure rates of the via holes during fabrication increase because the probability rises that some of the via holes will not fully open to receive the top via connectors. Furthermore, if the width “(a')” or the length “(b')” becomes too small, the IR drop of the top via connectors also increases in some embodiments, affecting the reliability and performance of the fabricated integrated circuits.If the width “(a')” or the length “(b')” becomes too large, in some embodiments the number of available via connectors or the number of available conductor tracks for each cell decreases, thereby increasing the cell areas.

[0091] Fig. Figure 14 is a flowchart of a method 1400 for generating a layout diagram of an integrated circuit (IC) according to some embodiments. It is understood that additional operations may be performed before, during, and / or after the process described in Figure 1400. Fig. The processes shown in section 1400 can be carried out, and some other processes may only be briefly described in this text. In some embodiments, the process 1400 can be used to generate one or more layout designs, such as the layout designs in [reference to relevant section]. Fig. 10A or in the Fig. 12A-12B. In some embodiments, Method 1400 can be used to form integrated circuits that exhibit similar structural relationships to one or more of the semiconductor structures based on the layout designs in Fig. 10A or in the Fig. 12A-12B are formed. In some embodiments, the method 1400 is performed by a processing device (for example, the processor 1602 in Fig. 16) carried out, which is set up to execute instructions for generating one or more layout designs, such as the layout designs in Fig. 10A or in the Fig. 12A-12B.

[0092] In Operation 1402 of Procedure 1400, an array of front-facing power supply line structures is generated. Each of the front-facing power supply line structures specifies a front-facing power supply line in a front-facing conductive layer. In the exemplary layout designs of the Fig. 12A-12B shows the arrangement of front-side power supply line structures, specifically the layout structures for front-side power supply lines 30F(1), 30F(2), and 34F(3). After operation 1402, the process proceeds to operation 1404.

[0093] In operation 1402 of procedure 1400, an array of first-type active zone structures is generated. The first-type active zone structures are positioned parallel to the front-side operating voltage line structures. Each of the first-type active zone structures specifies a first-type active region semiconductor structure. In the exemplary layout designs of the Fig. In 12A-12B, the arrangement of active zone structures of the first type includes the layout structures for the p-active region semiconductor structures 50p(1), 50p(2), and 50p(3). These layout structures are positioned in parallel between the layout structures for the front-side operating voltage lines 30F(1), 30F(2), and 34F(3). After operation 1404, the process proceeds to operation 1406.

[0094] In Operation 1406 of Procedure 1400, an array of backside power supply line structures is generated. Each backside power supply line structure specifies a backside power supply line in a backside conductive layer. In the exemplary layout designs of the Fig. 12A-12B shows the arrangement of rear-side power supply line structures, specifically the layout structures for rear-side power supply lines 30B(1), 30B(2), and 34B(3). After operation 1406, the process proceeds to operation 1408.

[0095] In Operation 1406 of Procedure 1400, an array of second-type active zone structures is generated. The second-type active zone structures are positioned parallel to the rear-side operating voltage line structures. Each second-type active zone structure specifies a second-type active region semiconductor structure stacked with a corresponding first-type active region semiconductor structure. In the exemplary layout designs of the Fig. 12A-12B features the arrangement of active region structures of a second type, the layout structures for the n-active region semiconductor structures 50n(1), 50n(2), and 50n(3). In the integrated circuit, which is designed according to the layout structures of Fig. In operation 12A-12B, the n-active-region semiconductor structures 50n(1) are stacked with the p-active-region semiconductor structures 50p(1), the n-active-region semiconductor structures 50n(2) are stacked with the p-active-region semiconductor structures 50p(2), and the n-active-region semiconductor structures 50n(3) are stacked with the p-active-region semiconductor structures 50p(3). After operation 1408, the process proceeds to operation 1410.

[0096] In Operation 1410 of Procedure 1400, at least one front-facing signal line structure is generated between a pair of adjacent front-facing power supply line structures. The at least one front-facing signal line structure specifies a front-facing signal line in the front-facing conductive layer over both the active-region semiconductor structure of a first type and the active-region semiconductor structure of a second type. In the exemplary layout designs of the Fig. In sections 12A-12B, the layout structures for the front-side signal lines 120F(1) and 140F(1) are positioned between the layout structures for the front-side power supply lines 30F(1) and 30F(2). The layout structures for the front-side signal lines 120F(2) and 140F(2) are positioned between the layout structures for the front-side power supply lines 30F(2) and 30F(3). After operation 1410, the process continues to operation 1412.

[0097] In Operation 1412 of Procedure 1400, at least one backside signal trace structure is generated between a pair of adjacent backside power supply trace structures. The at least one backside signal trace structure specifies a backside signal trace in the backside conductive layer under both the active-region semiconductor structure of a first type and the active-region semiconductor structure of a second type. In the exemplary layout designs of the Fig. Layout structures 12A-12B for the rear signal lines 120B(1) and 140B(1) are positioned between the layout structures for the rear power supply lines 30B(1) and 30B(2). Layout structures 120B(2) and 140B(2) for the rear signal lines are positioned between the layout structures for the rear power supply lines 30B(2) and 30B(3).

[0098] Fig. Figure 15 is a flowchart of a method 1500 for fabricating an integrated circuit (IC) with CFET devices according to some embodiments. It is understood that additional operations may be performed before, during, and / or after the process described in Figure 15. Fig. The 15 procedures shown can be carried out in 1500 and some other processes may only be briefly described in the present text.

[0099] In operation 1510 of procedure 1500, a second-type active-region semiconductor structure is fabricated on a substrate. Then, in operation 1512 of procedure 1500, a second gate conductor is fabricated, and the second gate conductor cleaves the second-type active-region semiconductor structure. In the Fig. 1A and the Fig. In the embodiments shown in Figure 1C-1E, the n-active-region semiconductor structure 50n is fabricated on a substrate in Operation 1510. The lower section of the gate conductor 150 is fabricated in Operation 1512, and the lower section of the gate conductor 150 intersects the n-active-region semiconductor structure 50n. In the embodiments shown in Fig. 8A and Fig. In embodiments shown in 8C, the gate conductor 150n is manufactured in operation 1512, and the gate conductor 150n intersects the n-active region semiconductor structure 50n.

[0100] In addition to Operation 1512, another operation following Operation 1510 is Operation 1514. A second conductive source segment is fabricated in Operation 1514, and this second conductive source segment intersects the active region semiconductor structure of a second type. Fig. 1A and the Fig. In the embodiments shown in Figure 1C-1E, the conductive segment 132n is fabricated, and the conductive segment 132n (as a conductive source segment) intersects the n-active-region semiconductor structure 50n and forms a source terminal of the NMOS transistor T1n. In the process flow of Method 1500, both Operation 1512 and Operation 1514 are performed after Operation 1510. In some embodiments, Operation 1512 is performed before Operation 1514. In some alternative embodiments, Operation 1512 is performed after Operation 1514. After Operations 1510, 1512, and 1514, the process flow proceeds to 1520.

[0101] In operation 1520 of process 1500, a layer of dielectric material is deposited and covers at least the active-region semiconductor structure of a second type, and in operation 1530 of process 1500, an active-region semiconductor structure of a first type is fabricated on the layer of dielectric material. In the Fig. 1A and the one in Fig. In embodiments shown in Figure 1C-1E, the p-active-region semiconductor structure 50p is fabricated on the layer of dielectric material located above the n-active-region semiconductor structure 50n. Then, in operation 1532 of procedure 1500, a first gate conductor is fabricated and cleaves the active-region semiconductor structure of a first type. In the embodiments shown in Fig. 1A and in the Fig. In embodiments 1C-1E shown, the upper section of the gate conductor 150 is manufactured, and the upper section of the gate conductor 150 intersects the p-active region semiconductor structure 50p.

[0102] In some embodiments, the lower and upper sections of the gate conductor 150 are fabricated separately in corresponding operations 1512 and 1532. In some embodiments, the integrated gate conductor 150 is formed from the lower and upper sections of the gate conductor. More precisely, prior to the fabrication of the upper section of the gate conductor 150, a gate interconnect connector is fabricated that passes through the layer of dielectric material over the n-active-region semiconductor structure 50n, and the gate interconnect connector directly connects the lower section of the gate conductor 150 to the upper section of the gate conductor 150 to form the integrated gate conductor 150. In some alternative embodiments, the first gate conductor fabricated in operation 1532 and the second gate conductor fabricated in operation 1512 are not directly connected by a gate interconnect connector. For example, in the Fig. 8A and Fig. In the embodiments shown in Figure 8C, the gate conductor 150p is manufactured in Operation 1532, and the gate conductor 150n is manufactured in Operation 1512. The gate conductor 150p and the gate conductor 150n are not directly connected.

[0103] A first conductive source segment is fabricated in Operation 1534, and the first conductive source segment intersects the active region semiconductor structure of a first type. In the Fig. 1A and in the Fig. In the embodiments shown in 1C-1E, the conductive segment 132p is fabricated, and the conductive segment 132p (as a conductive source segment) intersects the p-active-region semiconductor structure 50p and forms a source terminal of the PMOS transistor T1p. In the process flow of method 1500, both operation 1532 and operation 1534 are performed after operation 1530. In some embodiments, operation 1532 is performed before operation 1534. In some alternative embodiments, operation 1532 is performed after operation 1534. After operations 1530, 1532, and 1534, the process flow proceeds to 1540.

[0104] In Operation 1540 of Procedure 1500, a first insulating material is deposited and covers the first gate conductor and the first conductive source segment. Following Operation 1540, in Operation 1550 of Procedure 1500, a front-facing metal layer is deposited over the first insulating material. Then, in Operation 1555 of Procedure 1500, the front-facing metal layer is structured to form a front-facing power supply line and a front-facing signal line. The front-facing power supply line is conductively connected to the first conductive source segment via a first via connector, and the front-facing signal line is conductively connected to the first gate conductor via a front-facing gate via connector. In the Fig. 1A and the Fig. In the embodiments shown in Figure 1C-1E, the front-side operating voltage line 30F and the front-side signal lines (120F and 140F) are fabricated in the front-side metal layer that lies above the insulating material covering the gate conductor 150 and the conductive segment 132p. The front-side operating voltage line 30F is conductively connected to the conductive segment 132p via an upper via connector VT, and the front-side signal line 120F is conductively connected to the gate conductor 150 via an upper gate via connector VG.

[0105] After operations 1540, 1550, and 1555, the wafer containing the substrate is flipped in operation 1560. The process flow then continues to 1570. In operation 1570 of process 1500, a backside metal layer is formed on one side of the substrate. Following operation 1570, in operation 1575 of process 1500, the backside metal layer is structured to form a backside power supply line and a backside signal line. The backside power supply line is conductively connected to the second conductive source segment via a second via connector, and the backside signal line is conductively connected to the second gate conductor via a backside gate via connector. In the Fig. 1A and in the Fig. In the embodiments shown in Figures 1C-1E, the rear operating voltage line 30B and the rear signal lines (120B and 140B) are manufactured in a rear metal layer on the back of the substrate. The rear operating voltage line 30B is conductively connected to the conductive segment 132n via a lower via connector VB.

[0106] Fig. Figure 16 is a block diagram of a System 1600 for Electronic Design Automation (EDA) according to some embodiments.

[0107] In some embodiments, the EDA system 1600 includes an APR system. The methods described in this text for designing layout diagrams representing wire routing arrangements according to one or more embodiments can, for example, be implemented using the EDA system 1600 according to some embodiments.

[0108] In some embodiments, the EDA system 1600 is a general-purpose computing device comprising a hardware processor 1602 and a non-volatile, computer-readable storage medium 1604. The storage medium 1604 is encoded, i.e., stored, with computer program code 1606, i.e., a set of executable instructions. The execution of instructions 1606 by the hardware processor 1602 constitutes (at least partially) an EDA tool that implements some or all of the methods described herein according to one or more embodiments (hereinafter referred to as the “named processes and / or methods”).

[0109] The processor 1602 is electrically coupled to the computer-readable storage medium 1604 via a bus 1608. The processor 1602 is also electrically coupled to an I / O interface 1610 via the bus 1608. A network interface 1612 is also electrically connected to the processor 1602 via the bus 1608. The network interface 1612 is connected to a network 1614, enabling the processor 1602 and the computer-readable storage medium 1604 to connect to external elements via the network 1614. The processor 1602 is configured to execute the computer program code 1606, which is encoded in the computer-readable storage medium 1604, in order to make the system 1600 usable for the complete or partial execution of the aforementioned processes and / or procedures.In one or more embodiments, the 1602 processor is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0110] In one or more embodiments, the computer-readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or such device or apparatus). For example, the computer-readable storage medium 1604 comprises a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments operating with optical disks, the computer-readable storage medium 1604 includes a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disc (DVD).

[0111] In one or more embodiments, the storage medium 1604 stores computer program code 1606 configured to instruct the system 1600 to be usable for the complete or partial execution (if such execution (at least partially) constitutes the EDA tool) of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1604 also stores information enabling the complete or partial execution of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1604 stores a library 1607 of standard cells, including such standard cells as disclosed herein. In one or more embodiments, the storage medium 1604 stores one or more layout diagrams 1609 corresponding to one or more layouts disclosed herein.

[0112] The EDA system 1600 features the I / O interface 1610. The I / O interface 1610 is coupled to external circuitry. In one or more embodiments, the I / O interface 1610 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or arrow keys for transmitting information and commands to the processor 1602.

[0113] The EDA system 1600 also features the network interface 1612, which is coupled to the processor 1602. The network interface 1612 enables the system 1600 to communicate with the network 1614, to which one or more other computer systems are connected. The network interface 1612 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or wired network interfaces such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the aforementioned processes and / or procedures are implemented in two or more systems 1600.

[0114] The System 1600 is configured to receive information via the I / O interface 1610. The information received via the I / O interface 1610 contains one or more instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by the Processor 1602. The information is transmitted to the Processor 1602 via the bus 1608. The EDA System 1600 is also configured to receive information regarding a user interface (UI) via the I / O interface 1610. This information is stored on the computer-readable medium 1604 as the User Interface (UI) 1642.

[0115] In some embodiments, some or all of the processes and / or methods mentioned are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a software application used by the EDA System 1600. In some embodiments, a layout diagram containing standard cells is processed using a tool such as VIRTUOSO.® created by CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0116] In some embodiments, the processes are implemented as functions of a program stored on a non-transitory, computer-readable recording medium. Examples of non-transitory, computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in mass or working memory units, such as one or more from an optical disc, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, RAM, memory card, and the like.

[0117] Fig. Figure 17 is a block diagram of a 1700 fabrication system for integrated circuits (ICs) and an associated IC fabrication flow according to some embodiments. In some embodiments, based on a layout diagram, (A) one or more semiconductor masks and / or (B) at least one component in a layer of an integrated semiconductor circuit are fabricated using the 1700 fabrication system.

[0118] In Fig. The IC manufacturing system 1700 comprises entities, such as a design house 1720, a mask house 1730, and an IC manufacturer / fabricator (“Fab”) 1750, which interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 1760. The entities in the system 1700 are connected via a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a multitude of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from them.In some embodiments, two or more of the Design House 1720, the Mask House 1730, and the IC-Fab 1750 are owned by a single larger company. In some embodiments, two or more of the Design House 1720, the Mask House 1730, and the IC-Fab 1750 exist side-by-side in a shared facility and utilize common resources.

[0119] Design House (or Design Team) 1720 generates an IC design layout diagram 1722. The IC design layout diagram 1722 contains various geometric structures designed for an IC device 1760. These geometric structures correspond to structures of metal, oxide, or semiconductor layers that comprise the various components of the IC device 1760 to be manufactured. The different layers combine to form various IC structural elements. For example, a section of the IC design layout diagram 1722 contains various IC structural elements, such as an active region, a gate electrode, source and drain, metal traces or vias of an interlayer interconnect connection, and openings for bonding pads, which are to be formed in a semiconductor substrate (for example, a silicon wafer) and various material layers arranged on the semiconductor substrate.Design House 1720 implements a suitable design procedure to create the IC design layout diagram 1722. The design procedure includes one or more steps of logical design, physical design, and placement and routing. The IC design layout diagram 1722 is presented in one or more files containing information about the geometric structures. For example, the IC design layout diagram 1722 can be expressed in a GDSII file format or a DFII file format.

[0120] The mask house 1730 comprises the data preparation 1732 and the mask fabrication 1744. The mask house 1730 uses the IC design layout diagram 1722 to fabricate one or more masks 1745, which are to be used in fabricating the various layers of the IC device 1760 according to the IC design layout diagram 1722. The mask house 1730 performs the mask data preparation 1732, in which the IC design layout diagram 1722 is translated into a representative data file (RDF). The mask data preparation 1732 transmits the RDF to the mask fabrication 1744. The mask fabrication 1744 comprises a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticule) 1745 or a semiconductor wafer 1753.The design layout diagram 1722 is processed by the mask data preparation 1732 so that it is compatible with certain properties of the mask writer and / or requirements of the IC-Fab 1750. Fig. Figure 17 illustrates the mask data preparation 1732 and the mask manufacturing 1744 as separate elements. In some embodiments, the mask data preparation 1732 and the mask manufacturing 1744 can be referred to together as the mask data preparation.

[0121] In some embodiments, the mask data preparation 1732 includes optical proximity correction (OPC), which uses lithography optimization techniques to compensate for image defects, such as those caused by diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout diagram 1722. In some embodiments, the mask data preparation 1732 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0122] In some embodiments, the mask data preparation 1732 includes a mask rule checker (MRC) that verifies the IC design layout diagram 1722, which has undergone processes in OPC, against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 1722 to compensate for constraints during mask manufacturing 1744 that may undo some of the modifications made by OPC to satisfy mask generation rules.

[0123] In some embodiments, the mask data preparation 1732 includes a lithography process checking (LPC) that simulates processing implemented by the IC-Fab 1750 to manufacture the IC fixture 1760. The LPC simulates this processing using the IC design layout diagram 1722 to generate a simulated manufactured fixture, such as an IC fixture 1760. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as intermediate image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated fabricated device has been formed by the LPC, if the simulated device does not have the shape accurately enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout diagram 1722.

[0124] It is understood that the above description of the mask data preparation 1732 has been simplified for clarity. In some embodiments, the mask data preparation 1732 includes additional features, such as a logic operation (LOP) for modifying the IC design layout diagram 1722 according to manufacturing rules. Furthermore, the processes applied to the IC design layout diagram 1722 during the mask data preparation 1732 can be performed in a variety of different sequences.

[0125] Following mask data preparation 1732 and during mask fabrication 1744, a mask 1745 or a group of masks 1745 are fabricated based on the modified IC design layout 1722. In some embodiments, mask fabrication 1744 includes the execution of one or more lithographic exposures based on the IC design layout diagram 1722. In some embodiments, an electron beam (E-beam) or a mechanism consisting of multiple E-beams is used to form a structure on a mask (photomask 1745 or reticule) 845 based on the modified IC design layout 1722. The mask 1745 can be formed using various technologies. In some embodiments, the mask 1745 is formed using binary technology. In some embodiments, a mask structure includes opaque regions and transparent regions.A beam, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., the photoresist) deposited on a wafer, is blocked by the opaque region and transmitted through the transparent regions. In one example, a binary mask 1745 contains a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) deposited in the opaque regions of the mask. In another example, the mask 1745 is formed using a phase-shift technology. In a phase-shift mask (PSM) version of the mask 1745, various elements in the structure formed on the phase-shift mask are configured to have the correct phase difference to increase resolution and image quality.In various examples, the phase-shift mask can be a damped PSM or an alternating PSM. The one or more masks generated by the 1744 mask fabrication process are used in a variety of different processes. For example, these one or more masks are used in an ion implantation process to create different doped regions in the 1753 semiconductor wafer, in an etching process to create different etched regions in the 1753 semiconductor wafer, and / or in other suitable processes.

[0126] The IC-Fab 1750 is an IC manufacturing company that comprises one or more production sites for manufacturing a wide variety of different IC products. In some configurations, the IC-Fab 1750 is a semiconductor foundry. For example, there might be one production site for the front-end manufacturing of several IC products (front-end-of-line (FEOL) manufacturing), while a second production site is responsible for the back-end manufacturing of interconnect connections and encapsulation of the IC products (back-end-of-line (BEOL) manufacturing), and a third production site might provide other services to the foundry company.

[0127] The IC-Fab 1750 comprises manufacturing tools 1752 configured to perform various manufacturing operations on the semiconductor wafer 1753, such that the IC component 1760 is manufactured according to one or more masks, for example, mask 1745. In various embodiments, the manufacturing tools 1752 comprise one or more wafer steppers, ion implanters, photoresist coaters, process chambers (for example, CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed in this text.

[0128] The IC Fab 1750 uses the one or more masks 1745 produced by the mask house 1730 to fabricate an IC device 1760. Thus, the IC Fab 1750 uses, at least indirectly, the IC design layout diagram 1722 to fabricate the IC device 1760. In some embodiments, a semiconductor wafer 1753 is fabricated by the IC Fab 1750 using the one or more masks 1745 to form the IC device 1760. In some embodiments, the IC fabrication includes the execution of one or more lithographic exposures based, at least indirectly, on the IC design layout diagram 1722. The semiconductor wafer 1753 comprises a silicon substrate or other suitable substrate on which layers of material are formed.The semiconductor wafer 1753 further comprises one or more of different doped regions, dielectric structural elements, multi-level interconnect connections and the like (which are formed in subsequent manufacturing steps).

[0129] Details regarding a manufacturing system for integrated circuits (ICs) (for example, the System 1700 from Fig. 17) and an associated IC manufacturing flow US Patent No. US 9 256 709 B2, granted on February 9, 2016, in US Pre-Grant Publication No. US 2015 / 0 278 429 A1, published on October 1, 2015, in US Pre-Grant Publication No. US 2014 / 0 040 838 A1, published on February 6, 2014, and in US Patent No. US 7 260 442 B2, granted on August 21, 2007, to which reference is made.

[0130] Aspects of the present disclosure relate to an integrated circuit device. The integrated circuit device comprises an active-region semiconductor structure of a first type extending in a first direction and a first gate conductor extending in a second direction perpendicular to the first direction. The first gate conductor intersects the active-region semiconductor structure of a first type at a channel region of a transistor of a first type. The integrated circuit device also comprises an active-region semiconductor structure of a second type extending in the first direction and a second gate conductor extending in the second direction, intersecting the active-region semiconductor structure of a second type at a channel region of a transistor of a second type.The second type active region semiconductor structure is stacked with the first type active region semiconductor structure and is offset from the first type active region semiconductor structure along a third direction that is perpendicular to both the first and second directions. The integrated circuit device also includes a front-side conductive layer and a back-side conductive layer. The front-side conductive layer is oriented in the third direction and positioned above the first type active region semiconductor structure and the second type active region semiconductor structure. The back-side conductive layer is oriented in the third direction and positioned below the first type active region semiconductor structure and the second type active region semiconductor structure.The integrated circuit device also includes a front-side power supply line, a rear-side power supply line, a front-side signal line, and a rear-side signal line. The front-side power supply line extends in the first direction within the front-side conductive layer and is configured to maintain a first supply voltage. The rear-side power supply line extends in the first direction within the rear-side conductive layer and is configured to maintain a second supply voltage. The front-side signal line extends in the first direction within the front-side conductive layer. The rear-side signal line extends in the first direction within the rear-side conductive layer.The integrated circuit device also comprises a first conductive source segment, a second conductive source segment, and a conductive drain segment. The first conductive source segment extends in the second direction and intersects the active-region semiconductor structure of a first type at a source region of the transistor of a first type, and the first conductive source segment is conductively connected to the front-side supply voltage line via a first via. The second conductive source segment extends in the second direction and intersects the active-region semiconductor structure of a second type at a source region of the transistor of a second type, and is conductively connected to the rear-side supply voltage line via a second via.The conductive drain segment extends in the second direction and intersects one or both of the active region semiconductor structure of a first type and the active region semiconductor structure of a second type and is conductively connected to the front signal line or the rear signal line via a third via connector.

[0131] Another aspect of the present disclosure relates to an integrated circuit device. The integrated circuit device comprises an active-region semiconductor structure of a first type, an active-region semiconductor structure of a second type, a front-side conductive layer, a back-side conductive layer, multiple gate conductors, multiple conductive segments, a front-side signal line, and a back-side operating voltage line. The active-region semiconductor structure of a first type extends in a first direction. The active-region semiconductor structure of a second type, which extends in the first direction, is stacked with the active-region semiconductor structure of a first type. The front-side conductive layer is located above the active-region semiconductor structure of a first type and the active-region semiconductor structure of a second type.The backside conductive layer is located beneath the first-type active-region semiconductor structure and the second-type active-region semiconductor structure. Multiple gate conductors extend in a second direction perpendicular to the first. Each gate conductor intersects one or both of the first-type active-region semiconductor structures and the second-type active-region semiconductor structures, forming a gate terminal of at least one transistor. Multiple conductive segments extend in the second direction. Each conductive segment intersects one or both of the first-type active-region semiconductor structures and the second-type active-region semiconductor structures, forming a source or drain terminal of at least one transistor.The multiple conductive segments comprise a first conductive segment and a third conductive segment that intersect the active-region semiconductor structure of a first type, and a second conductive segment and a fourth conductive segment that intersect the active-region semiconductor structure of a second type. The front-side signal line extends in the first direction within the front-side conductive layer and is configured to transmit a first voltage change at the first conductive segment to one or more of the gate conductors or to one or more of the conductive segments. The back-side signal line extends in the first direction within the back-side conductive layer and is configured to transmit a second voltage change at the second conductive segment to one or more of the gate conductors or to one or more of the conductive segments.The front-side operating voltage line extends in the first direction within the front-side conductive layer and is configured to maintain a first supply voltage. It is conductively connected to the third conductive segment via a first via connector. The rear-side operating voltage line extends in the first direction within the rear-side conductive layer and is configured to maintain a second supply voltage. It is conductively connected to the fourth conductive segment via a second via connector.

[0132] Another aspect of the present disclosure relates to a method. The method comprises: fabricating an active-region semiconductor structure of a first type extending in a first direction on a substrate; fabricating a first gate conductor that intersects the active-region semiconductor structure of a first type at a channel region of a first transistor of a first type; and fabricating a first conductive source segment that intersects the active-region semiconductor structure of a first type at a first source region. The method further comprises: depositing a layer of dielectric material covering at least the active-region semiconductor structure of a first type; and fabricating an active-region semiconductor structure of a second type that extends in the first direction on the layer of dielectric material. The active-region semiconductor structure of the second type is stacked with the active-region semiconductor structure of a first type.The process comprises: fabricating a second gate conductor that intersects the active-region semiconductor structure of a second type at a channel region of a first transistor of a second type, and fabricating a second conductive source segment that intersects the active-region semiconductor structure of a second type at a second source region. The process comprises: depositing a first insulating material covering the second gate conductor and the second conductive source segment, depositing a front-side metal layer over the first insulating material, and structuring the front-side metal layer to form a front-side power supply line extending in the first direction and a front-side signal line extending in the first direction.The front-side operating voltage line is conductively connected to the second conductive source segment via a first via, and the front-side signal line is conductively connected to the second gate conductor via a front-side gate via. The method comprises: forming a back-side metal layer on the rear side of the substrate and structuring the back-side metal layer to form a back-side operating voltage line extending in the first direction and a back-side signal line extending in the first direction. The back-side operating voltage line is conductively connected to the first conductive source segment via a second via.

Claims

[1] Integrated circuit device comprising: an active region semiconductor structure of a first type (50p) extending in a first direction; a first gate conductor (150p) extending in a second direction perpendicular to the first direction and intersecting the active region semiconductor structure of a first type (5op) at a channel region of a transistor of a first type; an active region semiconductor structure of a second type (50n) extending in the first direction, stacked with the active region semiconductor structure of a first type (50p) and displaced by the active region semiconductor structure of a first type (50p) along a third direction perpendicular to both the first and second directions; a second gate conductor (150n) extending in the second direction and intersecting the active region semiconductor structure of a second type (50n) at a channel region of a transistor of a second type; a front-side conductive layer, in a plane with a normal vector oriented in the third direction and positioned above the first type (50n) active region semiconductor structure and the second type (50n) active region semiconductor structure; a backside conductive layer, in a plane with a normal vector oriented in the third direction and positioned below the first type (50p) active region semiconductor structure and the second type (50n) active region semiconductor structure; a front-side operating voltage line (30F) extending in the first direction in the front-side conductive layer and configured to maintain a first supply voltage; a rear operating voltage line (30B) extending in the first direction in the rear conductive layer and configured to maintain a second supply voltage; a front-side signal line (140F) extending in the first direction in the front-side conductive layer; a rear-side signal line (140B) extending in the first direction in the rear-side conductive layer; a first conductive source segment (132p) extending in the second direction, intersecting the active region semiconductor structure of a first type (50p) at a source region of the transistor of a first type, and being conductively connected to the front supply voltage line (30F) at the intersection of the first conductive source segment (132p) and the front supply voltage line (30F) via a first via connector (VT); a second conductive source segment (132n) extending in the second direction, intersecting the active region semiconductor structure of a second type (50n) at a source region of the transistor of a second type, and conductively connected to the rear supply voltage line (30B) at the intersection of the second conductive source segment and the rear supply voltage line (30B) via a second via connector (VB); and a conductive drain segment (134n) extending in the second direction, intersecting one or both of the active region semiconductor structure of a first type (50p) and the active region semiconductor structure of a second type (50n), and being conductively connected to the front signal line (140F) at the intersection of the conductive drain segment (134n) and the front signal line (140F) via a third via connector (VBT, VB, VT) or at the intersection of the conductive drain segment (134n) and the rear signal line (140B) via a third via connector. [2] Integrated circuit device according to claim 1, wherein the first gate conductor (150P) is connected to the second gate conductor (150n) and forms a third gate conductor (150). [3] Integrated circuit device according to claim 1, wherein the first gate conductor (150P) is separated from the second gate conductor (150n) along the third direction by a gate stack insulator (815). [4] Integrated circuit device according to any one of the preceding claims 1 to 3, wherein the front operating voltage line (30F) and the rear operating voltage line (30B) overlap each other when viewed along the third direction. [5] Integrated circuit device according to any one of the preceding claims 1 to 3, wherein the front operating voltage line (30F) and the rear operating voltage line (30B) are aligned along boundaries when viewed in the third direction. [6] Integrated circuit device comprising: an active region semiconductor structure of a first type (50p) extending in a first direction; an active region semiconductor structure of a second type (50n) extending in the first direction and stacked with the active region semiconductor structure of a first type (50p); a front-side conductive layer over the active region semiconductor structure of a first type (50p) and the active region semiconductor structure of a second type (50n); a backside conductive layer beneath the active region semiconductor structure of a first type (50p) and the active region semiconductor structure of a second type (50n); multiple gate conductors extending in a second direction perpendicular to the first direction, each of the gate conductors intersecting one or both of the active region semiconductor structure of a first type (50p) and the active region semiconductor structure of a second type (50n) while forming a gate terminal of at least one transistor; multiple conductive segments (132n, 132p, 134n, 134p) extending in the second direction, each of the conductive segments (132n, 132p, 134n, 134p) intersecting one or both of the active-region semiconductor structure of a first type (50p) and the active-region semiconductor structure of a second type (50n) while forming a source terminal or a drain terminal of at least one transistor, and wherein the multiple conductive segments (132n, 132p, 134n, 134p) include a first conductive segment (132p) and a third conductive segment (134p) intersecting the active-region semiconductor structure of a first type, and a second conductive segment (132n) and a fourth conductive segment (134n) intersecting the active-region semiconductor structure of a second type (50n) cut, exhibits; a front-side signal line (120F) extending in the first direction in the front-side conductive layer and configured to transmit a first voltage change at the first conductive segment (132p) to one or more of the gate conductors (150, 150p) or to one or more of the conductive segments (132p, 134p); a rear-side signal line (120B) extending in the first direction in the rear-side conductive layer and configured to transmit a second voltage change at the second conductive segment (132n) to one or more of the gate conductors (150, 150n) or to one or more of the conductive segments (132n, 134n); a front-side operating voltage line (30F) extending in the first direction in the front-side conductive layer and configured to maintain a first supply voltage, and conductively connected to the third conductive segment (134p) at the intersection of the front-side operating voltage line (30F) and the third conductive segment (134p) via a first via connector (VT); and a rear operating voltage line (30B) extending in the first direction in the rear conductive layer and configured to maintain a second supply voltage, and conductively connected to the fourth conductive segment (134n) at the intersection of the rear operating voltage line (30B) and the fourth conductive segment (134n) via a second via connector. [7] Integrated circuit device according to claim 6, wherein the front operating voltage line (30F) and the rear operating voltage line (30B) overlap each other when viewed in a direction perpendicular to the front conductive layer and the rear conductive layer. [8] Integrated circuit device according to claim 6, wherein the front (30F) operating voltage line and the rear operating voltage line (3oB) are aligned along boundaries - viewed in a direction perpendicular to the front conductive layer and the rear conductive layer. [9] Integrated circuit device according to any one of the preceding claims 6 to 8, wherein the active region semiconductor structure of a first type (50p) is located below the active region semiconductor structure of a second type (50n). [10] Integrated circuit device according to any one of the preceding claims 6 to 9, wherein both the active region semiconductor structure of a first type (50p) and the active region semiconductor structure of a second type comprise at least one nanolayer. [11] Integrated circuit device according to any one of the preceding claims 6 to 9, wherein both the active region semiconductor structure of a first type and the active region semiconductor structure of a second type comprise at least one nanowire. [12] Procedure that includes: Fabrication of a first-type active-region semiconductor structure (50n) extending in a first direction on a substrate; Fabricating a first gate conductor (150n) that intersects the active region semiconductor structure of a first type (50n) at a channel region of a first transistor of a first type; Fabricating a first conductive source segment (132n) that intersects the active region semiconductor structure of a first type (50n) at a first source region; Deposition of a layer of dielectric material covering at least the active region semiconductor structure of a first type (50n); Fabricating a second type (50p) active region semiconductor structure extending in the first direction on the layer of dielectric material, wherein the second type (50p) active region semiconductor structure is stacked with the first type (50n) active region semiconductor structure; Fabricating a second gate conductor (150p) that intersects the active region semiconductor structure of a second type (50p) at a channel region of a first transistor of a second type; Fabricating a second conductive source segment (132p) that intersects the active region semiconductor structure of a second type (50p) at a second source region; Deposition of a first insulating material covering the second gate conductor (150p) and the second conductive source segment (132p); Depositing a front-side metal layer over the first insulating material and structuring the front-side metal layer to form a front-side power supply line extending in the first direction and a front-side signal line (120F) extending in the first direction, wherein the front-side power supply line (30F) is conductively connected to the second conductive source segment (132p) at the intersection of the front-side power supply line (30F) and the second conductive source segment (132p) via a first via connector, and wherein the front-side signal line (120F) is conductively connected to the second gate conductor (150p) at the intersection of the front-side signal line (120F) and the second gate conductor (150p) via a front-side gate via connector; and Forming a backside metal layer on a rear side of the substrate and structuring the backside metal layer to form a backside power supply line (30B) extending in the first direction and a backside signal line (120B) extending in the first direction, wherein the backside power supply line (30B) is conductively connected to the first conductive source segment (132n) at the intersection of the backside power supply line (30B) with the first conductive source segment (132n) via a second via connector. [13] Method according to claim 12, wherein structuring the front-side metal layer comprises structuring the front-side metal layer to form a second front-side signal line (140F) extending in the first direction and is conductively connected to the second gate conductor (150p) via a front-side gate via-hole connector. [14] Method according to claim 12 or 13, wherein structuring the backside metal layer comprises structuring the backside metal layer to form a second backside signal line (140B) extending in the first direction and conductively connected to the first gate line (150n) at the intersection of the second backside signal line (140B) and the first gate line (150n) via a backside gate via-hole connector (VB). [15] Method according to any one of the preceding claims 12 to 14, further comprising: Fabricating a gate interconnect connector that passes through the layer of dielectric material to directly connect the second gate conductor (150p) to the first gate conductor (150n). [16] Method according to any one of the preceding claims 12 to 15, further comprising: Fabricating a first conductive drain segment (134n) that intersects the first type active region semiconductor structure (50n) at a first drain region; and Fabricating a second conductive drain segment (134p) that intersects the active region semiconductor structure of a second type (50n) at a second drain region. [17] The method of claim 16, which further comprises: Fabricating a conductive segment interconnect (VMD) connector passing through the layer of dielectric material to directly connect the first conductive drain segment (134n) to the second conductive drain segment (134p).

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