POWER DISTRIBUTION FOR STACKED STORAGE TANKS

Abstract

Device comprising: a memory array (170-a) of a first semiconductor chip (160-a), wherein the memory array (170-a) comprises a plurality of memory cells (205); a first interface that is connectable to a power source (180) outside the first semiconductor chip (160-a), the first interface coinciding with a first surface of the first semiconductor chip (160-a); a second interface that is electrically isolated from the first interface inside the first semiconductor chip (160-a) and connectable to the power source (180);and a third interface, electrically isolated from the first interface within the first semiconductor chip (160-a), coupled to the second interface within the first semiconductor chip (160-a) and connectable to a second semiconductor chip (160-b) in a stack of memory chips (160-a, 160-b, 160-N) comprising the first and the second semiconductor chips, wherein the second semiconductor chip (160-a) comprises a second plurality of memory cells (205) addressable via the same instruction / address bus as the first semiconductor chip (160-a), the third interface coinciding with a second surface of the first semiconductor chip (160-a) opposite the first surface of the first semiconductor chip (160-a), wherein the coupling between the second interface and the third interface comprises: a first conductor section coupled to the second interface and extending perpendicular to the first surface;a second conductor section coupled to the third interface and extending perpendicular to the second surface; and a third conductor section coupled to the first conductor section and to the second conductor section, extending in a direction parallel to the first surface, the second surface, or both.

Description

CROSS REFERENCETECHNICAL FIELDThe following relates generally to one or more systems for memories, and more particularly to power distribution for stacked memories.BACKGROUNDStorage devices are frequently used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells in a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, each of which may be stored. To access the stored information, a component may read or detect at least one stored state in the storage device. To store information, a component may write or program the state to the memory device.There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic random access memory (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and others. Memory cells may be volatile or nonvolatile. Non-volatile memories, e.g., FeRAM, may maintain their stored logic state for a longer period of time even when there is no external power source. Volatile memory devices, e.g., DRAM, may lose their stored state when disconnected from an external power source.US 2019 / 0237390 A1 relates to a semiconductor component having a plurality of memory chips stacked one on top of the other, wherein each memory chip comprises current-distributing through holes made of silicon.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 illustrates an example of a system that supports current distribution for stacked memories according to the examples disclosed herein. FIG. 2 illustrates an example of a memory chip supporting current distribution for stacked memories according to the examples disclosed herein. FIGS. 3A and 3B illustrate examples of a memory chip and a stacked memory device that support current distribution for stacked memories according to the examples disclosed herein.FIG. FIGS. 4A and 4B illustrate examples of a memory chip and a stacked memory device that support current distribution for stacked memories according to the examples disclosed herein.FIG. FIGS. 5A and 5B illustrate examples of a memory chip and a stacked memory device that support current distribution for stacked memories according to the examples disclosed herein. FIG. 6 shows a flow diagram illustrating one or more methods supporting current distribution for stacked memories according to the examples disclosed herein.DETAILED DESCRIPTIONA memory device may include one or more memory chips, wherein each memory chip may refer to a semiconductor chip configured with a corresponding memory array and a circuit for operating at least the corresponding memory array (e.g., to support read operations, write operations, memory management operations). In some examples, a memory device may include multiple discrete memory chips that are controlled or accessible by a host device over a common communication link (e.g., over a common command and address channel or bus). A stacked memory device may refer to a memory device including a plurality of discrete memory chips coupled together (e.g., bonded, soldered, welded), wherein such coupling may include providing an electrical connection between one or more electrical contacts of different memory chips (e.g., adjacent memory chips, directly adjacent memory chips). In some examples, a stacked memory device may include a current source that is common (e.g., shared) to two or more memory chips, and current may be provided to a first memory chip (e.g., a memory chip that is farther from the current source) via a conductor that passes through a second memory chip (e.g., a memory chip that is closer to the current source). In some cases, if such a conductor is configured to provide power to both the first memory chip and the second memory chip, the performance of the first memory chip or the second memory chip or both chips may degrade.For example, according to the examples disclosed herein, a memory chip may be configured with one or more conductive paths to power one or more other memory chips of a stacked memory device, wherein each conductive path may pass through the memory chip but may be electrically isolated or isolatable from a circuit for operating the memory chip. Each conductive path may be referred to as or operate as a supply conductor, such as a dedicated supply conductor through the chip, and may provide an electronic coupling between a first set of electrical contacts of the memory chip (e.g., on a first surface of the memory chip) and a second set of electrical contacts of the memory chip (e.g., on a second surface of the memory chip). Each of the first sets of contacts may be configured to be coupled to a current source, e.g., a common current source, and within the memory chip, each of the first sets of contacts may be electrically isolated from one another and each of the second sets of contacts may be electrically isolated from one another. To assist in the operation of the memory chip, one or more contacts of the first set of electrical contacts may be electrically coupled to circuitry for operating a memory array of the chip (e.g., by configuring one or more contacts of the first set of electrical contacts of the memory chip to provide current to the circuitry of the memory chip). To assist in the operation of another memory chip, one or more other contacts of the first set of electrical contacts may be electrically isolated from the circuit for operating the memory array of the chip (e.g., by configuring or determining one or more of the first set of electrical contacts or the memory chip and the associated supply conductors through the chip for providing current to another memory chip). By providing conductive paths through one memory chip that are electrically isolated from the circuits of the memory chip, another memory chip with improved characteristics such as improved voltage stability, improved temperature distribution, or reduced noise may be powered, which may improve the performance of the memory device compared to configurations where a supply conductor through the chip supports the power source for multiple memory chips.Features of the disclosure will first be described in the context of systems and chips with reference to FIGS. 1 and 2. These and other features of the disclosure are illustrated and described with reference to examples of memory chips, stacked memory devices, and fabrication techniques related to power distribution for stacked memories, as described in FIGS. 3A-6.FIG. 1 illustrates an example of a system 100 that supports current distribution for stacked memories according to the examples disclosed herein. The system 100 may include a host device 105, a storage device 110, and a plurality of channels 115 that couple the host device 105 to the storage device 110. The system 100 may include one or more storage devices 110, but aspects of the one or more storage devices 110 may be described in the context of a single storage device (e.g., the storage device 110).The system 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 may be aspects of a computer, a laptop, a tablet computer, a smartphone, a mobile phone, a wearable device, a device connected to the Internet, or the like. The storage device 110 may be a component of the system that is operable to store data for one or more other components of the system 100.At least portions of the system 100 may be examples of the host device 105. The host device 105 may be an example of a processor or other circuit within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a mobile phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or other stationary or wearable electronic device, among other examples. In some examples, the host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of an external memory controller 120. In some examples, the external memory controller 120 may be referred to as a host or host device 105.A storage device 110 may be an independent device or component that may provide physical memory addresses / storage space that may be used or referenced by the system 100. In some examples, a storage device 110 may be configured to operate with one or a different type of host device. The signaling between the host device 105 and the storage device 110 may be operated to support one or more of the following: modulation schemes for modulating the signals, different pin configurations for transmitting the signals, different form factors for physically packaging the host device 105 and the storage device 110, clock signaling and synchronization between the host device 105 and the storage device 110, time conventions, or other factors.The storage device 110 may be operable to store data for the components of the host device 105. In some examples, the memory device 110 may function as a type of slave device for the host device 105 (e.g., by responding to and executing commands provided by the host device 105 via the external memory controller 120). Such instructions may include one or more write instructions for a write operation, a read instruction for a read operation, a refresh instruction for a refresh operation, or other instructions.The host device 105 may include one or more external memory controllers 120, a processor 125, a basic input / output controller (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled together via a bus 135.The processor 125 may be operable to provide control or other functions to at least portions of the system 100 or at least portions of the host device 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or SoC, among other examples. In some examples, the external memory controller 120 may be implemented by or be part of the processor 125.The BIOS component 130 may be a software component that includes a firmware-operated BIOS that can initialize and execute various hardware components of the system 100 or the host device 105. The BIOS component 130 may also manage the flow of data between the processor 125 and the various components of the system 100 or the host device 105. The BIOS component 130 may include a program or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.The memory device 110 may include a device memory controller 155 and one or more memory chips 160 (e.g., memory chips) to support a desired capacity or a particular capacity for data storage. Each memory chip 160 may include a local memory controller 165 (e.g., local memory controller 165- a, local memory controller 165- b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170- a, memory array 170- b, memory array 170-N). A memory array 170 may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more portions) of memory cells, where each memory cell may store at least one bit of data. A memory device 110 including two or more memory chips may be referred to as multi-chip memory or multi-chip package or as multi-chip memory or multi-chip package.The memory chip 160 may be an example of a two-dimensional (2D) array of memory cells or an example of a three-dimensional (3D) array of memory cells. A 2D memory chip 160 may include a single memory array 170. A 3D memory chip 160 may include two or more memory arrays 170 that may be stacked or positioned side-by-side (e.g., relative to a substrate). In some examples, memory arrays 170 in a 3D memory chip 160 may be referred to as stacks, planes, layers, or chips. A 3D memory chip may include any set of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory chips 160, different stacks may share at least one common access line, such that some stacks may share one or more word lines, a digit line, and / or a plate line.The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include the hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute instructions, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controllers 120, the one or more memory chips 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory chip 160.In some examples, the storage device 110 may receive data or commands, or both, from the host device 105. For example, the storage device 110 may receive a write command indicating that the storage device 110 is to store data for the host device 105, or a read command indicating that the storage device 110 is to provide data stored in a memory chip 160 to the host device 105.A local memory controller 165 (e.g., local to a memory chip 160) may include circuitry, logic, or components operable to control the operation of the memory chip 160. In some examples, a local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., receive or transmit data or commands, or both). In some examples, a memory device 110 may not include a device memory controller 155, and a local memory controller 165 or the external memory controller 120 may perform various functions described herein. Thus, a local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controllers 165, or both, may include receivers for signaling (e.g., from the external memory controller 120), transmitters for transmitting signals (e.g., to the external memory controller 120), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other operable circuits or controllers to support the described operations of the device memory controller 155 or the local memory controller 165, or both.The external memory controller 120 may be operable to enable communication of one or more information, data, or commands between components of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between the host device 105 and the storage device 110. In some examples, external memory controller 120, or another component of system 100 or host device 105, or its functions described herein, may be implemented by processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by the processor 125 or another component of the system 100 or the host device 105. For example, the external memory controller 120 or its functions described herein may be implemented by one or more components of a memory device 110 (e.g., a device memory controller 155, a local memory controller 165), or vice versa, although the external memory controller 120 is shown as being external to the memory device 110.The components of the host device 105 may exchange information with the storage device 110 via one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and storage device 110. Each channel 115 may be an example of transmission media that transmits information between the host device 105 and the storage device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between ports associated with the components of the system 100. A signal path may be an example of an operable conductive path for transmitting a signal. For example, a channel 115 may include a first terminal that includes one or more pins or pads on the host device 105 and one or more pins or pads on the memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be operable to function as part of a channel.Channels 115 (and the associated signaling paths and ports) may be dedicated to the transmission of one or more types of information. For example, channels 115 may include one or more command and address (CA) channels 186 (e.g., a CA bus, a command / address bus, a C / A bus), one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling over channels 115 may be communicated using single data rate (SDR) or double data rate (DDR) signaling. In SDR signaling, a modulation symbol (e.g., the signal level) of a signal may be registered for each clock cycle (e.g., at a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., both at a rising and a falling edge of a clock signal).In some examples, a memory device 110 may include a power source that is common (e.g., shared) to multiple memory chips 160 of the memory device 110. For example, the memory device 110 may include a power source 180, which may be configured to provide power (e.g., conveying current, supply current, to each of the memory chips 160- ato 160N via a supply conductor 185). Although output conductor 185 is illustrated as being coupled to a respective local memory controller 165 of each of memory chips 160, a memory device 110 may include various configurations of output conductor 185 to additionally or alternatively couple a current source 180 to a set of memory arrays 170 or various components of a set of memory arrays 170.The current source 180 may include various components or circuits that allow the memory chips 160 to be supplied with a regulated voltage or otherwise provide a regulated voltage to each of the memory chips 160 (e.g., as a voltage source). In some examples, the current source 180 itself may include or relate to a voltage regulating circuit (e.g., the memory device 110) for providing current according to a regulated voltage, such as components or circuits configured to set a voltage level at the output conductor 185, filter noise or other voltage fluctuations from the input conductor 175 or the output conductor 185, among other components or circuits. Additionally or alternatively, the current source 180 may be configured to receive current at a regulated voltage (e.g., via an input conductor 175), and the current source 180 may or may not include additional circuitry for voltage regulation. For example, the current source 180 may refer to a through conductor of the memory device 110 (e.g., a node of the memory device 110) from or through which current is provided to each of the memory chips 160.In various examples, the input conductor 175 may include or otherwise be connected to a pin or contact of the memory device 110, which may or may not be coupled to the host device 105. The input conductor 175 may be powered by a power converter or voltage regulator (e.g., the host device 105, a device external to the host device 105), a battery, a power grid or distribution system, or other types of power sources or generators. Although a single output conductor 185 is illustrated in the memory device 110, a current source 180 may be connected to more than one output conductor 185, e.g., a pair of conductors that provide current according to a regulated voltage and a ground voltage (e.g., a package ground conductor) or another reference voltage, or to other sets of conductors that may provide current according to one or more voltage levels.In some examples, output conductor 185 may include one or more portions that pass through a memory chip 160 (e.g., through each of memory chips 160- a, 160- band 160-N, via a through silicon via (TSV) or chip via of a memory chip 160) such that power is distributed along a single, common path or bus. However, in some cases, such a configuration may be associated with reduced performance of the memory chips 160. For example, the current flowing through the output conductor 185 to assist in power consumption of the memory chips 160 may be associated with a voltage drop along a length of the output conductor 185 such that memory chips 160 relatively farther from the current source 180 may be provided with a voltage different from (e.g., relatively lower than) a voltage provided for memory chips 160 relatively closer to the current source 180. In some examples (e.g., in facilitating power consumption for multiple memory chips 160), a current or current density through a portion of the output conductor 185 that is relatively close to the power source 180 may be relatively high compared to portions of the output conductor that are relatively farther from the power source 180. In some cases, a relatively high current or current density may be associated with local heating that increases the resistance of the output conductor 185, causes local thermal stress, strain, or fatigue, or causes thermally induced material degradation or operational degradation of memory chips 160 (e.g., memory chips 160 that are relatively close to the power source 180), among other adverse behaviors. Additionally or alternatively, various operations or switching events of a memory chip 160 may cause noise, reflections or other voltage fluctuations or instabilities along the output conductor 185, and such voltage fluctuations or instabilities may affect the performance of another memory chip 160. Thus, according to these and other examples, a stacked memory device 110 configured with a common output conductor 185 that passes through a set of memory chips 160 and is shared by the set of memory chips 160 may be associated with certain performance constraints.According to the examples disclosed herein, a memory chip 160 may be configured with one or more conductive paths for providing power to one or more other memory chips 160, wherein at least some of the conductive paths may pass through the memory chip 160, but may be isolated from circuits for operating the memory chip 160 (e.g., electrically isolated from circuits for operating a memory array 170). Each conductive path may be or may be referred to as a supply conductor through the chip, a TSV, or a chip via, and provide an electronic coupling between a first set of electrical contacts of the memory chip 160 (e.g., on a first surface of the memory chip 160) and a second set of electrical contacts of the memory chip 160 (e.g., on a second surface of the memory chip 160). Each of the first sets of contacts may be configured to be coupled to a common current source 180 and, within the memory chip 160, each of the first sets of contacts may be electrically isolated from each other and each of the second sets of contacts may be electrically isolated from each other. By providing conductive paths through one memory chip 160 that are electrically isolated from the circuitry of the memory chip 160, current may be provided to another memory chip 160 with improved characteristics, such as improved voltage stability or reduced noise, favorably distributed current, current density or thermal characteristics, or other advantageous characteristics that may improve the performance of a memory device 110 compared to configurations where an output conductor 185 through the chip supports the current source for multiple memory chips 160.FIG. 2 illustrates an example of a memory chip 200 that supports current distribution for stacked memories according to the examples disclosed herein. The memory chip 200 may be an example of the memory chips 160 described with reference to FIG. 1. In some examples, the memory chip 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory chip 200 may include one or more memory cells 205, each of which may be programmed to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell 205 may be operable to store a bit of information (e.g., a logical 0 or a logical 1), respectively. In some examples, a memory cell 205 (e.g., a multilevel memory cell) may be operable to store more than one information bit simultaneously (e.g., a logic 00, a logic 01, a logic 10, a logic 11). In some examples, memory cells 205 may be arranged in an array, such as a memory array 170 described with reference to FIG. 1.A memory cell 205 may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor including a dielectric material for storing a charge representative of the programmable state. Other memory devices and components are possible in other memory architectures. For example, non-linear dielectric materials may be used. The memory cell 205 may include a logical memory component, such as the capacitor 230, and a switching component 235. The capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of capacitor 230 may be coupled to a voltage source 240, which may be the cell plate reference voltage (e.g., Vpl) or ground (e.g., Vss).The memory chip 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digit lines 215) arranged in a pattern such as a grid-like pattern. An access line may be a conductive line coupled to a memory cell 205 and may be used to perform access operations to the memory cell 205. In some examples, word lines 210 may be referred to as row lines. In some examples, digit lines 215 may also be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines or bit lines, or their analogs, are interchangeable without loss of understanding or operation. Memory cells 205 may be positioned at intersections of the word lines 210 and the digit lines 215.Operations such as reading and writing may be performed on the memory cells 205 by activating or selecting access lines such as one or more word lines 210 or a digit line 215. By biasing a word line 210 and a digit line 215 (e.g., applying a voltage to the word line 210 or the digit line 215), a single memory cell 205 may be accessed at its intersection. The intersection of a word line 210 and a digit line 215, either in a two-dimensional or three-dimensional configuration, may be referred to as an address of a memory cell 205.Access to the memory cells 205 may be controlled by a row decoder 220 and a column decoder 225. For example, a row decoder 220 may receive a row address from the local memory controller 260 and activate a word line 210 based on the received row address. A column decoder 225 may receive a column address from the local memory controller 260 and may activate a digit line 215 based on the received column address.The selection or deselection of the memory cell 205 can be effected by activating or deactivating the switching component 235 via a word line 210. Capacitor 230 may be coupled to digit line 215 using switching component 235. For example, capacitor 230 may be isolated from digit line 215 when switching component 235 is deactivated, and capacitor 230 may be coupled to digit line 215 when switching component 235 is activated.Sensing component 245 may be operable to detect a state (e.g., a charge) stored on capacitor 230 of memory cell 205 and determine a logic state of memory cell 205 based on the stored state. Sensing component 245 may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from access to memory cell 205. The sensing component 245 may compare a signal sensed by the memory cell 205 with a reference 250 (e.g., a reference voltage). The sensed logic state of the memory cell 205 may be provided as an output of the sensing component 245 (e.g., to an input / output component 255), and may indicate the sensed logic state of another component of a memory device including the memory chip 200.Local memory controller 260 may control accessing of memory cells 205 by the various components (e.g., row decoder 220, column decoder 225, sense component 245). Local memory controller 260 may be an example of local memory controller 165 described with reference to FIG. 1. In some examples, one or more of row decoder 220, column decoder 225, and sensing component 245 may be arranged together with local memory controller 260. The local memory controller 260 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 connected to a host device 105, another controller connected to the memory chip 200), translate the commands or data (or both) into information that may be used by the memory chip 200, perform one or more operations on the memory chip 200, and communicate data from the memory chip 200 to a host device 105 based on the performance of the one or more operations. Local memory controller 260 may generate row and column address signals to activate destination word line 210 and destination digit line 215. The local memory controller 260 may also generate and control various voltages or currents used during operation of the memory chip 200. Generally, the amplitude, shape, or duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory chip 200.The local memory controller 260 may be operable to perform one or more access operations to one or more memory cells 205 of the memory chip 200. Examples of access operations may include, but are not limited to, a write operation, a read operation, a refresh operation, a precharge operation, or an enable operation. In some examples, access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from a host device 105). Local memory controller 260 may be operable to perform other access operations not listed herein or other operations associated with operating memory chip 200 that are not directly associated with access to memory cells 205.The local memory controller 260 may be operable to perform a write operation (e.g., a program operation) on one or more memory cells 205 of the memory chip 200. During a write operation, a memory cell 205 of the memory chip 200 may be programmed to store a desired logic state. The local memory controller 260 may identify a target memory cell 205 on which to perform the write operation. Local memory controller 260 may identify a target word line 210 coupled to target memory cell 205 (e.g., the address of target memory cell 205) and a target digit line 215. Local memory controller 260 may activate target word line 210 and target digit line 215 (e.g., applying a voltage to word line 210 or target digit line 215) to access target memory cell 205. Local memory controller 260 may apply a particular signal (e.g., a write pulse) to target digit line 215 during the write operation to store a particular state (e.g., a charge) in capacitor 230 of memory cell 205. The pulse used as part of the write operation may include one or more voltage levels over a period of time.The local memory controller 260 may be operable to perform a read operation (e.g., a read operation) on one or more memory cells 205 of the memory chip 200. During a read operation, the logic state stored in a memory cell 205 of the memory chip 200 may be determined. The local memory controller 260 may identify a target memory cell 205 on which to perform the read operation. Local memory controller 260 may identify a target word line 210 coupled to target memory cell 205 (e.g., the address of target memory cell 205) and a target digit line 215. Local memory controller 260 may activate target word line 210 and target digit line 215 (e.g., applying a voltage to word line 210 or target digit line 215) to access target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 245 in response to biasing the access lines. The sensing component 245 may amplify the signal. Local memory controller 260 may enable sense component 245 (e.g., latch the sense component) and thereby compare the signal received from memory cell 205 to reference 250. Based on this comparison, sensing component 245 may determine a logic state stored in memory cell 205.Various components of the memory chip 200 may be coupled to a power source 180 (e.g., a memory device 110) located external to the memory chip 200 to support various operations of the memory chip 200, such as read operations, write operations, refresh operations, memory management operations, and other operations of the memory chip 200. For example, such a current source 180 may provide or transmit current to store a logical state in a memory cell 205, refresh or maintain a logical state stored in a memory cell 205, identify a logical state stored in a memory cell 205, perform memory management operations (e.g., at a local memory controller 260), or communicate information between the memory chip 200 and a device memory controller 155 or a host device 105, among other operations. To support such operations, a current source 180 may be directly or indirectly coupled to a local memory controller 260, a row decoder 220, a column decoder 225, a sense component 245, a reference 250, an input / output component 255, or various other components of a memory chip 200, or combinations thereof.According to the examples disclosed herein, the memory chip 200 may be configured with one or more conductive paths that assist in powering one or more other memory chips 200 included in a common memory device 110, wherein at least some of the conductive paths may pass through a package of the memory chip 200 (e.g., through a chip including the memory chip 200) but may be electrically isolated from the circuitry for operating the memory chip 200. By providing one or more conductive paths through a memory chip 200 that are electrically isolated from the circuits of the memory chip 200, current may be provided to one or more other memory chips 200 having improved characteristics, such as improved voltage stability or reduced noise, favorably distributed current, current density or thermal characteristics, or other advantageous characteristics that may improve the performance of a memory device 110 or its memory chips 200 compared to other configurations.FIGS. 3A and 3B illustrate examples of a memory chip 200- aand a memory device 110- a, respectively, that support current distribution for stacked memories according to the examples disclosed herein. The memory chip 200- aand the memory device 110- amay each be an example of aspects of the respective components as described with reference to FIGS. 1 and 2. For illustrative purposes, aspects of memory chip 200- aand memory device 110- amay be described with reference to an x-direction, a y-direction, and a z-direction of a coordinate system 300. In some examples, the z-direction may illustrate a direction relative to a substrate of a memory chip 200 (e.g., a height direction, a build direction) or a stacking direction for a stacked memory device 110 (e.g., a stacking direction, a direction for stacking memory chips 200), or both.The memory chip 200- amay be an example of a semiconductor chip including one or more memory arrays, such as one or more memory arrays 170 described with reference to FIG. 1. The memory chip 200- amay be connected (e.g., may have an exposed surface including or at least partially defined by a physical boundary, a volume, an extension, or a package) to a first surface 301 (e.g., surface 301- a, a bottom surface of a memory chip) and a second surface 302 (e.g., a top surface opposite the first surface 302- a, a top surface), each of which may be configured to be couplable to another component of a memory device 110 (e.g., in a stacked memory device 110).The memory chip 200- amay include a circuit 310 (e.g., the circuit 310- a), which may include various components or circuits for operating the memory chip 200- a. In some examples, the circuit 310 may include the memory cells 205 of the one or more memory arrays of the memory chip 200- a. In some examples, the circuit 310 may include various components or circuits for operating the one or more memory arrays (e.g., to support access operations to the memory cells 205 of the memory chip 200- a), such as one or more local memory controllers 260, a row decoder 220, a column decoder 225, a sensing component 245, a reference 250, an input / output component 255 as described with reference to FIG. 2, or various other components or combinations of components.The memory chip 200- amay include a set of contacts 320 (e.g., contacts 320- a- 1 to 320- a- 4). In some examples, at least some, if not all, contacts 320 may conform to surface 301- a. The memory chip 200- amay also include a set of contacts 330 (e.g., contacts 330- a- 1 to 330- a- 3). In some examples, at least some, if not all, contacts 330 may conform to surface 302- a. In some examples, contacts 320, contacts 330, or both may be included in or referred to as a ball grid array, a face grid array, or another configuration. Each of the contacts 320 and 330 may be physically, electrically, or both physically and electrically couplable to another component external to the memory chip 200- aand may include or be referred to as a bonding pad, a contact pad, a solder pad, a wire bonding pad, a wedge bonding pad, or an electrical contact, among other constructions or terms. In some examples, the contacts 320 may each be configured to be coupled to a current source 180 (e.g., for coupling to a contact of a component including the current source 180, for coupling to a contact 330 of another memory chip 200- aincluding a conductive path coupled or couplable to the current source 180). In some examples, contacts 330 may be configured to couple to another memory chip 200 (e.g., contacts 320 of another memory chip 200- a).Within a memory chip 200, each of the contacts 320 may be electrically isolated from each other, and each of the contacts 330 may be electrically isolated from each other. Accordingly, each of contacts 320- a- 2, 320- a- 3, and 320- a- 4 may be an example of an interface (e.g., an electrical interface, a conductive interface, a physical interface) isolated from contact 320- a- 1 (e.g., electrically isolated, within memory chip 200- a), and may also be electrically coupled to a current source (e.g., a same current source that may be coupled to contact 320- a- 1). Further, each of contacts 330- a- 1, 330- a- 2, and 330- a- 3 may be an example of an interface isolated from contact 320- a- 1 (e.g., electrically isolated, within memory die 200- a), coupled to a corresponding one of the other contacts 320- a(e.g., electrically coupled to one of contacts 320- a- 2, 320- a- 3, or 320- a- 4), and couplable to another semiconductor die 200- a(e.g., electrically couplable to a contact 320- aof another semiconductor die 200- a).In some examples, memory chip 200- amay include a non-coupled contact (e.g., a dummy contact, an electrically isolated contact, an electrically non-functional contact), such as contact 330- a- 4, that is not electrically coupled to other components of memory chip 200- a, but may provide a different portion of surface 302- afor bonding (e.g., soldering) to another memory chip 200- a(e.g., to a contact 320 of the other memory chip 200- a), which may improve connection strength or uniformity between memory chips 200- aor improve heat dissipation between memory chips 200- a, among other advantages. Although not illustrated in the example of memory chip 200- a, a memory chip 200 may include other contacts related to the transmission of signals to or from memory chip 200 (e.g., to or from chip circuit 310), such as signals associated with communication (e.g., for transmission, communication) between chip circuit 310 and a host device 105 via channels 115 or communication between chip circuit 310 and a device memory controller 155 of a stacked memory device 110 or communication between chip circuit 310 and chip circuit 310 of another memory chip 200, among other signals.Memory chip 200- amay include various conductive connections to contacts 320- aand contacts 330- a. For example, contact 320- a- 1 may be coupled to chip circuit 310- a(e.g., electrically coupled, directly coupled, or connected) via conductor 340- a, and accordingly contact 320- a- 1 and conductor 340- amay be operable to transfer current to operate chip circuit 310- a. Each of the other contacts 320- amay be electrically coupled to one of the contacts 330- avia a corresponding conductor 345- a(e.g., contact 320- a- 2 coupled to contact 330- a- 1 via conductor 345- a- 1, etc.). Thus, each of the conductors 345- aand the associated contact 320- aand contact 330- amay be referred to as a supply conductor or TSV of the memory chip 200- a, which is isolated from the circuit for operating the memory chip 200- a(e.g., electrically isolated from the chip circuit 310- a, not couplable to the chip circuit 310- a). Each of the chip pass conductors 345- amay be operable to provide current from a current source of one memory device 110 to another memory chip 200- aof the memory device 110 to support access operations to the memory cells of the other memory chip 200- a.In the example of memory die 200- a, each of contacts 330- amay be associated with a position on surface 302- a(e.g., with a position defined in x-direction, y-direction, or in both x- and y-directions) that coincides with or is similar to (e.g., at least partially overlaps) a position on surface 301- aof a corresponding contact 320- aelectrically isolated from contact 330- a. For example, when viewed along the z-direction (e.g., a direction between surface 301- aand surface 302- a), a cross-section (e.g., in the x-direction and the y-direction) of each of contacts 330- amay at least partially overlap or otherwise match a cross-section of a respective one of contacts 320- anot coupled or connected to the respective contact 330- aby a corresponding conductor 345- a. Moreover, a cross-section of each of the contacts 330- a, when viewed along the z-direction, may not overlap or otherwise conform to the cross-section of the respective contact 320- acoupled or connected to the respective contact 330- athrough a conductor 345- a. Such an arrangement may be referred to as a diagonal via (e.g., a via extending through memory chip 200- aalong the z-direction and the x-direction or the y-direction, or both), which may facilitate certain techniques for coupling stacked memory chips 200- a(e.g., as illustrated in memory device 110- a).The conductors 345- amay be formed according to various techniques that assist in conceptually diagonal arrangement of the chips. For example, the conductors 345- amay be formed with various combinations of one or more portions extending perpendicular to the surface 301- aor the surface 302- a(e.g., along the z-direction, in a height direction relative to a substrate, such as one or more TSV segments of the memory chip 200- a), and one or more portions extending parallel to the surface 301- aor the surface 302- a(e.g., extending in a direction perpendicular to the z-direction or in an xy-plane, such as a portion of an internal distribution or redistribution layer of the memory chip 200- a). Additionally or alternatively, in some examples, the chip pass conductors 345 may include one or more diagonal portions (e.g., portions of conductive material extending along the z-direction and one or more of the x-direction or the y-direction, portions of conductive material that are not parallel to the z-direction or parallel to an xy-plane).FIG. 3B illustrates an example of a memory device 110- aincluding a plurality of memory chips 200- a(e.g., memory chips 200- a- 1 to 200- a- 4, a stack of memory chips 200) as described with reference to FIG. 3A. The memory chips 200- a- 1 to 200- a- 4 may be stacked on (e.g., over) a base 360 (e.g., base 360- a), which may be an example of a semiconductor chip, printed circuit board (PCB), or other substrate component of the memory device 110- afor constructing or supporting a stacked memory array. In some examples, a base 360 may be referred to as a logic chip of a memory device 110 and may refer to a semiconductor chip separate from one or more memory chips 200 of a memory device 110.In various examples of a stacked memory device 110, such as the memory device 110- a, one or more memory chips 200 and a base 360 may be assembled (e.g., bonded, connected) using various techniques, such as soldering (e.g., using a reflow furnace, using an infrared radiator), bonding (e.g., thermo-sonic bonding, thermo-compression bonding, wire bonding, wedge bonding), brazing, welding (e.g., ultrasonic welding, pressure welding), or other connection techniques. The example of the memory device 110- amay include one or more bonding layers 350 (e.g., bonding layers 350- a- 1 to 350- a- 4) between the respective assembled components, as illustrated, where the bonding layers 350 may include conductive material portions 355 that contact different contacts of the assembled components to provide a corresponding electrical coupling or connection. In various examples, the conductive material portions 355 may include solder (e.g., solder balls), brazing solder, conductive paste, conductive wires, spring connectors, or other features or materials that provide an electrical connection between the assembled components of the memory device 110- a.A base 360 may include a current source 180 located outside the memory chips 200, such as the current source 180- aincluded in the base 360- a. The current source 180- amay be an example of one or more aspects of a current source 180 described with reference to FIGS. 1 and 2, and in some examples may include or be referred to as a voltage source or a voltage regulator. The power source 180- amay be powered via an input conductor 175- avia a contact 370 (e.g., contact 370- a) of the base 360- a, which may be couplable to a host device 105 (e.g., a power supply or a power supply pin of the host device 105) or another power supply. In the example of memory chip 200- a, current source 180- amay be configured to provide current for each of memory chips 200- a- 1 to 200- a- 4. In some examples, a base 360 may include other components of a memory device 110 that are not illustrated, such as a device memory controller 155 that communicates with one or more (e.g., all) of the memory chips 200 of the associated memory device 110 and may be operable for communication or other coupling or interconnection with a host device 105 (e.g., via channels 115 and associated contacts or pins of the base 360). In some examples, two or more (e.g., all) memory chips 200 of a memory device 110 (e.g., one or more memory arrays 170 of each of the memory chips 200, memory cells 205 of each of the memory chips 200) may be addressable via the same or a common communication link of the memory device 110 (not shown), such as a common command / address bus of the memory device 110 or between the memory device 110 and a host device 105.In the example of the memory device 110- a, the base 360- aincludes a respective contact 365- a, each of which is coupled to the power source 180- avia a conductor 375 (e.g., conductor 375- a) to power each of the memory chips 200- a. For example, contact 365- a- 1 may be operable to power chip circuit 310- a- 1 of memory chip 200- a- 1, contact 365- a- 2 may be operable to power chip circuit 310- a- 2 of memory chip 200- a- 2, and so forth. Thus, in the example of the memory device 110- a, each of the memory chips 200- a- 1 to 200- a- 4 may be connected to an isolated or dedicated current distribution path between the base 360- aand the respective memory chip 200- a, which may or may not include a dedicated chip pass conductor (e.g., the conductor 345) of one or more other memory chips 200- a. The example of the memory device 110- aillustrates a stacked memory device having a stack of four memory chips 200- a, but the described techniques may be applied to any number of memory chips 200- a(e.g., including fewer or more memory chips that may include various configurations of stacking or combinations of stacked elements). For example, to support a stacked memory device 110 having n memory chips 200- a, each memory chip 200- amay be configured with n contacts 320- a, at least n- 1 contacts 330- a, and at least n- 1 conductors 345- a.For example, in the memory device 110- aillustrated a diagonal arrangement of the chips, each of the memory chips 200- amay be identical (e.g., may be identically constructed) and assembled in an aligned manner (e.g., with corresponding edges aligned or flush in the x-direction, in the y-direction, or in both directions). Such a configuration may be implemented to reduce the number of component parts (e.g., individual memory chips 200, respective memory chips 200 with contacts 320 or contacts 330 at individual locations) or to facilitate component alignment during assembly with efficient use of the chip material (e.g., avoidance of portions of a memory chip 200 in the x or y direction), among other advantages.Although the memory device 110- ais illustrated as exposing the surfaces of the memory chips 200- aand the base 360- a, in some examples, one or more of the surfaces of a memory device 110 may be covered or coated by a secondary material, such as a dielectric material or a plastic coating, to protect internal components of the memory device 110. In the example of the memory device 110- a, such a material may at least partially, if not completely, cover the contacts 330- a- 5, 330- a- 6, and 330- a- 7 of the memory chip 200- a- 4, but not the contact 370- a. In some cases, it may be advantageous to avoid certain electrically floating structures in a memory chip 200, in which case one or more of the contacts 330- a- 5, 330- a- 6 or 330- a- 7 may be electrically grounded or coupled to another voltage source (e.g., a ground voltage source, a reference voltage source) without disturbing the current supply of the respective chip circuit 310- aof each memory chip 200- a. In some examples, such techniques may include providing metallization or other conductive material portion on one or more outer surfaces of memory chips 200 or base 360 (e.g., at least a portion of a top surface of memory chip 200- a- 4, one or more side surfaces of one or more memory chips 200- a- 1 to 200- a- 4, or base 360- a), which may additionally provide some degree of electromagnetic shielding for at least a portion of memory chips 200 or base 360.Although the description and illustration relates to connection to a single voltage level power source 180, a memory chip 200 or storage device 110 may include various arrangements for connection to a power source 180 supporting multiple conductive paths of a memory chip 200- afor the same voltage level, connection to one or more power sources 180 supporting multiple voltage levels, or various combinations thereof. In some examples, the conceptual arrangement of contacts 320- a, contacts 330- a, conductors 340- a, and conductors 345- a(e.g., a diagonal chip through-conductor arrangement) as applied to a voltage level in FIG. 3B may be functionally repeated for one or more other voltage levels (not illustrated). For example, such a conceptual layout may be functionally repeated to include one or more drain voltages (e.g., VDD), a source voltage (e.g., VSS, a ground voltage), a positive pump voltage (e.g., VPP), a reference voltage (e.g., VREF), a substrate voltage (e.g., VBB, a negative voltage), or various other voltages or combinations thereof that may be provided by a single current source 180 (e.g., a single voltage source, a single voltage regulator), or a combination of current sources 180 (e.g., multiple voltage sources, multiple voltage regulators). Additionally or alternatively, the conceptual arrangement of contacts 320- a, contacts 330- a, conductors 340- a, and conductors 345- a(e.g., a diagonal chip pass arrangement) as applied in FIG. 3B for a single connection to a single chip circuit 310 may be functionally repeated for multiple connections to a single chip circuit 310 of a memory chip 200, may be functionally repeated for connections to multiple chip circuits 310 of a memory chip 200, or various combinations thereof (not illustrated). In these and other examples, the respective contacts and conductors of the functionally repeating layouts may be distributed over different portions of a memory chip 200 to maintain electrical isolation between the functionally repeating layouts, e.g., by distributing the contacts and conductors over different positions in the x-direction, different positions in the y-direction, or both.FIGS. 4A and 4B illustrate examples of a memory chip 200- band a memory device 110- b, respectively, that support current distribution for stacked memories according to the examples disclosed herein. The memory chip 200- band the memory device 110- bmay each be an example of aspects of the respective components as described with reference to FIGS. 1 and 2. For illustrative purposes, aspects of memory chip 200- band memory device 110- bmay be described with reference to an x-direction, a y-direction, and a z-direction of a coordinate system 400.The memory chip 200- bmay be connected to a first surface 301 (e.g., surface 301- b) and a second surface 302 (e.g., surface 302- b), and include a chip circuit 310- b, each of which may be an example of the respective features described with reference to FIGS. 3A and 3B. Memory chip 200- bmay also include a set of contacts 320 (e.g., contacts 320- b- 1 to 320- b- 4), at least some, if not all, of which may conform to surface 301- band a set of contacts 330 (e.g., contacts 330- b- 1 to 330- b- 3), at least some, if not all, of which may conform to surface 302- b. Contact 320- b- 1 may be coupled to chip circuit 310- bvia a conductor 340- b, and at least some, if not each of the other contacts 320- bmay be electrically coupled to one of contacts 330- bvia a corresponding conductor 345- b.In the example of memory die 200- b, at least some, if not each of contacts 330- bmay be associated with a position on surface 302- b(e.g., in x and y directions) that coincides with or is similar to (e.g., at least partially overlaps) a position on surface 301- bof a corresponding contact 320- bcoupled to contact 330- b. For example, when viewed along the z-direction, a cross-section (e.g., in the x- and y-directions) of each of the contacts 330- bmay at least partially overlap or otherwise conform to a cross-section of a corresponding contact 320- bconnected to the corresponding contact 330- bby a conductor 345- b. Moreover, a cross-section of each of the contacts 330- b, when viewed along the z-direction, may not overlap or otherwise coincide with the cross-section of the respective contact 320- bcoupled or connected to the respective contact 330- bby a conductor 345- b. Such an arrangement may be referred to as a straight via (e.g., a via extending directly or predominantly along the z-direction through the memory chip 200- b), which may facilitate certain techniques for manufacturing memory chips 200- bfor a stacked memory device (e.g., as illustrated in the memory device 110- b). For example, the conductors 345- bmay be formed without one or more portions aligned in the x or y direction, and may be formed by a single TSV forming operation or by a combination of stacked, side-by-side TSV forming operations.FIG. 4B illustrates an example of a memory device 110- bincluding a plurality of memory chips 200- b(e.g., memory chips 200- b- 1 to 200- b- 4) as described with reference to FIG. 4A. The memory chips 200- b- 1 to 200- b- 4 may be stacked on (e.g., over) a base 360- b, which may be an example of aspects of a base 360 as described with reference to FIG. 3B. Base 360- bmay include a current source 180- b, which may be supplied with current via an input conductor 175- bvia a contact 370- b. In the example of the memory device 110- b, the base 360- bincludes a single contact 365- bcoupled to the current source 180- bvia a conductor 375- b. The contact 365- bmay be coupled to each of the contacts 320- bof the memory chip 200- b- 1 (e.g., a first memory chip 200- bin a stack) and may be operable to provide power to each of the memory chips 200- bof the memory device 110- b. In the example of the memory device 110- b, the contacts of the memory chips 200- band the contacts of the base 360- bmay be directly coupled or connected (e.g., without a bonding layer 350), which may be supported by bonding techniques such as thermo-sonic bonding, thermo-compression bonding, ultrasonic welding, pressure welding, or other direct bonding techniques.In the example of the memory device 110- b illustrating a direct chip pass arrangement, each of the memory chips 200- bmay be identical or not (e.g., it may be identically constructed or not). For example, to support identical memory chips 200- b, each of the memory chips 200- bmay be physically offset from one another (e.g., in the x-direction, as illustrated, in the y-direction, in both the x-direction and the y-direction), depending on the relative position of the memory chip 200- bin the stack. In a memory device 110- bwith different memory chips 200- bin each position of a stack, the memory chips 200- bmay include a corresponding padding portion 410- b, depending on the position of the memory chip 200- bin the stack, to assist in the alignment of the edges of adjacent memory chips 200- b(e.g., in the x-direction, in the y-direction). In various examples, a fill portion 410 may be formed of the same material as the memory chip 200- b(e.g., a semiconductor substrate with or without additional material on the substrate) or of another material (e.g., a dielectric material added to the edge of a memory chip 200- band planarized with the surfaces 301- band 302- b). In other examples that assist in aligning edges of memory chips 200- bwith straight chip through conductors, each memory chip 200- bmay include contacts 320- band 330- bhaving a respective position (e.g., in the x-direction, in the y-direction, on the surfaces 301- band 302- b) that is based on a relative position of the memory chip 200- bin a stack of memory chips 200- b(according to an internal staggered of the respective memory chips 200- b). According to these and other techniques, a memory device 110- bmay include a cover 405 (e.g., a dielectric cover) for protecting the internal components of the memory chip 110, which may cover the contacts 330- bof an upper memory chip 200- bbut may not cover the contact 370- b.Although the description and illustration relates to connection to a current source 180 for a single voltage level and for a single conductor 340- band a single chip circuit 310- bfor each memory chip 200- b, the conceptual arrangement of contacts 320- b, contacts 330- b, conductors 340- band conductors 345- b(e.g., a straight chip pass arrangement) as applied in FIG. 4B, for one or more other voltage levels, for multi-connections to a single chip circuit 310 of a memory chip 200, for connections to multiple chip circuits 310 of a memory chip 200, or various combinations thereof (not illustrated) may be functionally repeated. In some examples of a memory device 110 or a memory chip 200, one or more described techniques for straight chip pass arrangements may also be used in combination with one or more described techniques for diagonal chip pass arrangements.FIGS. 5A and 5B illustrate examples of a memory chip 200- cand a memory device 110- c, respectively, that support current distribution for stacked memories according to the examples disclosed herein. The memory chip 200- cand the memory device 110- cmay each be an example of aspects of the respective components as described with reference to FIGS. 1 and 2. For illustrative purposes, aspects of memory chip 200- cand memory device 110- cmay be described with reference to an x-direction, a y-direction, and a z-direction of a coordinate system 500.The memory chip 200- cmay be connected to a first surface 301 (e.g., surface 301- c) and a second surface 302 (e.g., surface 302- c), and include a chip circuit 310- c, each of which may be an example of the respective features described with reference to FIGS. 3A to 4B. Memory chip 200- cmay also include a set of contacts 320 (e.g., contacts 320- c- 1 to 320- c- 5), at least some, if not all, of which may conform to surface 301- cand a set of contacts 330 (e.g., contacts 330- c- 1 to 330- c- 3), at least some, if not all, of which may conform to surface 302- b. In the example of memory chip 200- c, each of contacts 330- cmay be coupled (e.g., electrically coupled, directly connected) to one of contacts 320- c(e.g., through or as part of a straight or diagonal chip through conductor).In the example of memory chip 200- c, each of contacts 320- c- 1 to 320- c- 4 and each of contacts 330- c- 1 to 330- c- 4 may be coupled to a selection component 510 (e.g., selection component 510- a). The selection component 510- amay be operable to couple one or more of the contacts 320- cto the chip circuit 310- c(e.g., to operate the memory chip 200- cusing an external current source or voltage source having a first voltage level), to isolate one or more of the contacts 320- cfrom the chip circuit 310- c(e.g., to configure or assign a contact 320 to power another memory chip 200- c), or both. Additionally or alternatively, the selection component 510- amay be operable to couple one or more of the contacts 330- cto the chip circuit 310- c, to isolate one or more of the contacts 330- cfrom the chip circuit 310- c(e.g., to prevent or mitigate noise from operating the chip circuit 310- cachears the contacts 330- cor another memory chip 200- c), or both. Thus, according to these and other examples, a selection component 510 of a memory chip 200 may be operable to select or configure one or more conductive paths to provide current or voltage to the chip circuit 310 of the memory chip 200 and also to select or configure one or more other conductive paths isolated from the chip circuit 310 to provide current or voltage to another memory chip 200.A selection component 510 may be configured with various components or arrangements of components to support the described functionality. For example, selection component 510- aillustrates an example where each of contacts 320- c- 1 to 320- c- 4 and each of contacts 330- c- 1 to 330- c- 4 are each associated with a set of switching components 515 (e.g., switching component 515- a- 1 associated with contacts 320- c- 4 and 330- c- 4, and so forth). In some examples, each of the switching components 515 of a selection component 510 may be a fuse, which may be a one-time programmable switch that is initially in a conductive or closed circuit, but may be programmed or set into a non-conductive, insulating, or open circuit (e.g., by breaking electrical continuity of the fuse). In some examples, each of the switching components 515 of a selection component 510 may be an antifuse, which may be a one-time programmable switch that is initially in a non-conductive, insulative, or open circuit configuration, but may be programmed or set with a conductive or closed circuit configuration (e.g., by establishing electrical continuity of the antifuse). In some examples, each of the switching components 515 of a selection component 510 may be a dynamic or continuously operable or programmable switch, such as a transistor, that may be controlled (e.g., by a logic signal) to be in either a quiescent current or a working current configuration. The state of a switching component 515 may be programmed or otherwise controlled by signaling via one or more contacts 520 coupled to the selection component 510 (e.g., contact 520- acoupled to the selection component 510- a, an input conductor, an input bus), wherein such programming or configuration may be performed in a manufacturing or assembly process (e.g., to set a set of a fuse or anti-fuse), while during operation may be performed (e.g., to set a set of one or more continuously programmable switching components 515, such as during power-on or initialization), or various combinations thereof.Memory chip 200- calso illustrates an example of a shared through-conductor path (e.g., for coupling to an external current source or a voltage source at a second voltage level, such as a ground voltage). For example, contact 320- c- 5 may be coupled to contact 330- c- 5 via a chip pass conductor that is also (e.g., directly) coupled to chip circuit 310- c. Using such an arrangement, contact 320- c- 5 may be operable to provide current or voltage to chip circuit 310- cand contact 330- c- 5, and contact 330- c- 5 may be operable to provide current or voltage to another memory chip 200- c.FIG. 5B illustrates an example of a memory device 110- cincluding a plurality of memory chips 200- c(e.g., memory chips 200- c- 1 to 200- c- 4) as described with reference to FIG. 5A. The memory chips 200- c- 1 to 200- c- 4 may be stacked on (e.g., over) a base 360- c, which may be an example of aspects of a base 360 as described with reference to FIG. 3B or 4B. Base 360- cmay include a current source 180- cthat may receive current via input conductors 175- c- 1 and 175- c- 2 via contacts 370- c- 1 and 370- c- 2, respectively. Current source 180- cillustrates an example of a current source 180 that may provide current corresponding to a first voltage level (e.g., via conductor 375- c- 1) and a second voltage level (e.g., via conductor 375- c- 2), such as a positive voltage and a ground voltage, or a positive voltage and a negative voltage, or two positive voltages, among other configurations. The base 360- cmay also include a device memory controller 155- c(e.g., a logic chip), which may be an example of a device memory controller 155 described with reference to FIG. 1. The device memory controller 155- cmay be coupled to at least each of the chip circuits 310- c- 1 to 310- c- 4 to control aspects of the operation of the memory chips 200- c- 1 to 200- c- 4.In the example of the memory device 110- c illustrating configurable power distribution arrangement, each of the memory chips 200- cmay be identically constructed but differently configured (e.g., based on a position of the memory chip 200- cin the memory device 110- c). For example, to support identical memory chips 200- c, each of the memory chips 200- cmay include a corresponding selection component 510 that is configured differently. In an example, the memory chip 200- c- 1 may be configured with a first switching component 515- alocated in a closed circuit configuration and second through fourth switching components 515- alocated in an open circuit configuration such that the chip circuit 310- c- 1 is coupled to the contact 365- c- 1 of the base 360- cand isolated from the other contacts 365- cof the base 360- c. Further, the memory chip 200- c- 2 may be configured with a second switching component 515- alocated in a closed circuit configuration and first, third, and fourth switching components 515- alocated in an open circuit configuration such that the chip circuit 310- c- 2 is coupled to the contact 365- c- 2 of the base 360- cand isolated from the other contacts 365- cof the base 360- c.In some examples, a power distribution configuration of the memory device 110- cmay be supported by switching components 515 including fuses or antifuses configured to do so before or after assembly of a memory chip 200- cin the memory device 110- cbased on a position of the respective memory chip 200- cin the memory device 110- c. In some examples, each of the selection components 510- amay be coupled to the device memory controller 155- c, and the device memory controller 155- cmay provide one or more logic signals to each of the selection components 510- ato configure the respective switching components 515- a. In various examples, device memory controller 155- cmay include a static configuration for such logic signals (e.g., based on static entries of a mode register associated with device memory controller 155- c, based on fuses or antifuses of device memory controller 155- c, based on a circuit configuration of device memory controller 155- c), or device memory controller 155- cmay otherwise determine such logic signals (e.g., during a boot or initialization operation). In some examples, a device memory controller 155- cor a fabrication controller used in assembling the memory device 110- cmay evaluate different conductive paths of the memory chips 200- cor the base 360- cand configure selection components 510- aor switching components 515- abased on the evaluation, such as establishing preferred conductive paths between the components or avoiding faulty conductive paths or interrupted circuit elements (e.g., open circuit paths), among other considerations.Although the description and illustration relates to a connection to a current source 180 for a single voltage level and for a single chip pass conductor 340- band a single chip circuit 310- cfor each memory chip 200- c, the conceptual arrangement of the contacts 320- c- 1 to 320- c- 4, the contacts 330- c- 1 to 330- c- 4, and the selection components 510- c(e.g., configurable current distribution arrangement) as applied in FIG. 5B, for one or more other voltage levels, for multi-connections to a single chip circuit 310 of a memory chip 200, for connections to a plurality of chip circuits 310 of a memory chip 200, or various combinations thereof, may be functionally repeated (not illustrated). Moreover, in some examples of a memory device 110 or a memory chip 200, one or more described configurable current distribution techniques may be used in combination with one or more described diagonal chip via or straight chip via techniques.FIG. 6 shows a flow diagram illustrating a method supporting current distribution for stacked memories according to the examples disclosed herein. In some examples, one or more operations of the method of FIG. 6 may be implemented by a manufacturing system or one or more controllers connected to a manufacturing system. Additionally or alternatively, one or more operations of the method of FIG. 6 may be performed by a component of a memory device 110 (e.g., a device memory controller 155, a local memory controller 165). In some examples, one or more controllers may execute a set of instructions to control the functional elements of the manufacturing system or the storage device to perform the described functions. Additionally or alternatively, one or more controllers may perform aspects of the described functions using dedicated hardware.At 605, the method may include providing a memory chip for incorporation into a multi-chip memory device. In some examples, the memory chip may include a first plurality of contacts (e.g., on a first surface of the memory chip) and a selection component coupled between each contact of the first plurality of contacts and a circuit for operating a memory array of the memory chip. In some examples, the memory chip may include a second plurality of contacts (e.g., on a second surface of the memory chip) each coupled to a corresponding contact of the first plurality of contacts. The operations of 605 may be performed according to techniques disclosed herein.At 610, the method may include configuring a selection component (e.g., the memory chip) to couple a first contact of a first plurality of contacts to a circuit for operating a memory array and to isolate a second contact of the first plurality of contacts from the circuit for operating the memory array. The operations of 610 may be performed in accordance with techniques disclosed herein.At 615, the method may include coupling a current source circuit to each of the first plurality of contacts. The operations of 615 may be performed in accordance with techniques disclosed herein.In some examples, an apparatus described herein may perform one or more methods, such as the method or methods of FIG. 6. the apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer readable medium storing processor executable instructions) to provide a memory chip for incorporation into a multi-chip storage device. In some examples, the memory chip may include a first plurality of contacts (e.g., on a first surface of the memory chip) and a selection component coupled between each contact of the first plurality of contacts and a circuit for operating a memory array of the memory chip. In some examples, the memory chip may include a second plurality of contacts (e.g., on a second surface of the memory chip) each coupled to a corresponding contact of the first plurality of contacts. The apparatus may further include features, circuits, logic, means, or instructions to configure a selection component (e.g., the memory chip) to couple a first contact of a first plurality of contacts to circuits for operating the memory array and isolate a second contact of the first plurality of contacts from the circuits for operating the memory array, and to couple current source circuits to each of the first plurality of contacts.In some examples of the method of FIG. 6 and the apparatus described herein, coupling the chip circuit of the power source to each of the first plurality of contacts may include operations, features, circuits, logic, means, or instructions for bonding the memory chip to a substrate (e.g., a logic chip) including the chip circuit of the power source, wherein the bonding may include making an electrical connection between each contact of the first plurality of contacts with one or more contacts of the substrate coupled to the chip circuit of the power source.In some examples of the method of FIG. 6 and the apparatus described herein, coupling the circuit of the power source to each of the first plurality of contacts may include operations, features, circuits, logic, means, or instructions for bonding the memory chip to another memory chip including one or more chip pass-through conductors coupled to or otherwise configured to be directly or indirectly connected to a substrate including the circuit of the power source, wherein the bonding may include establishing an electrical connection between each contact of the first plurality of contacts with one or more contacts of the other memory chip coupled to the one or more chip pass-through conductors. In some examples, the memory cells of both the memory chip and the other memory chip may be addressable via the same CA channel or CA bus (e.g., via a logic chip).In some examples of the method of FIG. 6 and the apparatus described herein, configuring the selection component may include operations, features, circuits, logic, means, or instructions operable based at least in part on a position of the memory chip relative to a second memory chip of the multi-chip memory device. For example, a controller of a manufacturing process or a controller of a memory device (e.g., a device memory controller 155) or a controller of a memory chip (e.g., a local memory controller 165) may identify a relative or absolute position of the memory chip (e.g., in a stack or sequence of memory chips) and configure the selection component for coupling or isolation based at least in part on the identified position.In some examples of the method of FIG. 6 and the apparatus described herein, configuring the selection component may include or involve operations, features, circuits, logic, means, or instructions to maintain continuity of a first fuse between the first contact and the circuit for operating the memory array and to interrupt continuity (e.g., in a fabrication operation) of a second fuse between the second contact and the circuit for operating the memory array.In some examples of the method of FIG. 6 and the apparatus described herein, configuring the selection component may include or involve operations, features, circuits, logic, means, or instructions to establish continuity (e.g., in a manufacturing operation) of a first anti-fuse between the first contact and the circuit to operate the memory array and to maintain isolation (e.g., electrical isolation) of a second anti-fuse between the second contact and the circuit to operate the memory array.In some examples of the method of FIG. 6 and the apparatus described herein, configuring the selection component may include or involve operations, features, circuits, logic, means, or instructions for providing a first signal for establishing continuity (e.g., electrical continuity) by a first switching component between the first contact and the circuit for operating the memory array and for providing a second signal for establishing isolation (e.g., electrical isolation) by a second switching component between the second contact and the circuit for operating the memory array. In some examples, the first signal, the second signal, or both may be configured to be provided to the memory chip (e.g., the selection component, the first switching component, the second switching component) by a memory controller. In some examples, the first signal, the second signal, or both may be determined or otherwise operable to be provided based on a mode register setting (e.g., the memory device, the device memory controller), based on a backup or anti-backup setting (e.g., the memory device, the device memory controller), based on a circuit configuration (e.g., the memory device, the device memory controller), based on a setting determined during a start, initialization, or other operation, or other settings, or combinations thereof.It should be appreciated that the methods described herein describe possible implementations and that the operations and steps may be rearranged or otherwise modified and that other implementations are possible. Moreover, parts of two or more of the methods may be combined.An apparatus will be described. The apparatus may include a memory array of a first semiconductor die, the memory array including a plurality of memory cells, and a first interface (e.g., an electrical interface, a conductive interface, a physical interface) connectable to a power source (e.g., external to the first semiconductor die, operable to support access operations to the plurality of memory cells). The device may also include a second interface isolated (e.g., electrically isolated) from the first interface within the first semiconductor die and couplable to the power source. The device may also include a third interface that is isolated (e.g., electrically isolated) from the first interface within the first semiconductor die and that is coupled (e.g., electrically coupled) to the second interface within the first semiconductor die. In some examples, the third interface may be couplable to a second semiconductor die or other component external to the first semiconductor die. In some examples, the first semiconductor die may be couplable to a second semiconductor die in a stack of memory dies (e.g., including the first and second semiconductor dies), the second semiconductor die including a second plurality of memory cells. In some examples, the memory cells of the first and second semiconductor dies may be addressable via the same or a common command / address bus (e.g., from a memory device that includes or is otherwise connected to the first and second semiconductor dies).In some examples of the apparatus, the coupling between the second interface and the third interface may be operable to provide power from the power source to the second semiconductor die (e.g., to support access operations to memory cells of the second semiconductor die) or another component external to the first semiconductor die.In some examples of the apparatus, the first interface may match a first surface of the first semiconductor die and the third interface may match a second surface of the first semiconductor die (e.g., opposite the first surface of the first semiconductor die).In some examples of the device, the coupling between the second interface and the third interface may include a first conductor portion coupled to the second interface and extending perpendicular to the first surface (e.g., as at least a portion of a TSV), a second conductor portion coupled to the third interface and extending perpendicular to the second surface (e.g., as at least a portion of a current distribution layer, as an intra-layer conductor), and a third conductor portion coupled to the first conductor portion and to the second conductor portion and extending in a direction parallel to the first surface, to the second surface, or to both (e.g., as at least a portion of another TSV).In some examples of the device, when viewed along a direction from the first surface to the second surface, a cross-section of the first interface may at least partially overlap or otherwise conform to a cross-section of the third interface.In some examples of the device, a cross-section of the first interface may not overlap or otherwise not match a cross-section of the third interface when viewed along a direction from the first surface to the second surface.In some examples, the device may include a fourth interface couplable to a ground voltage source (e.g., external to the first semiconductor die, to aid access operations to the plurality of memory cells). The device may further include a fifth interface isolated (e.g., electrically isolated) from the fourth interface within the first semiconductor die and couplable to the ground voltage source, and a sixth interface isolated (e.g., electrically isolated) from the fourth interface within the first semiconductor die and coupled (e.g., electrically coupled) to the fifth interface within the first semiconductor die. The sixth interface may be couplable to the second semiconductor chip or another component external to the first semiconductor chip.In some examples, the device may include a fourth interface coupled to a ground voltage source (e.g., external to the first semiconductor die to support access operations to the plurality of memory cells) and a fifth interface coupled to the fourth interface within the first semiconductor die. In some examples, the fifth interface may be couplable to the second semiconductor die or another component external to the first semiconductor die.Another apparatus will be described. The apparatus may include a memory array of a first memory chip, the memory array including a plurality of memory cells. The device may also include a first plurality of contacts (e.g., on or included in the memory chip, on or coincident with a first surface of the first memory chip) each couplable to a voltage source located external to the first memory chip and a second plurality of contacts (e.g., on or included in the memory chip, on or coincident with a second surface of the first memory chip) each coupled (e.g., electrically coupled) to a corresponding one of the first plurality of contacts. In some examples, each of the second plurality of contacts may be couplable to a second memory chip or another component external to the first memory chip. The apparatus may also include a selection component (e.g., on or included in the memory chip) operable to couple a first contact of the first plurality of contacts to the circuit of the first memory chip (e.g., to operate the memory array using the voltage source) and to isolate a second contact of the first plurality of contacts from the circuit.In some examples of the device, each contact of the first plurality of contacts may be isolated (e.g., electrically isolated) from the other contacts of the first plurality of contacts within the first memory chip.In some examples of the apparatus, the respective contact of the second plurality of contacts coupled to the second contact of the first plurality of contacts may be operable to couple the voltage source to the second memory chip (e.g., to operate a second memory array of the second memory chip using the voltage source) or the other component external to the first memory chip.In some examples of the device, the selection component may include a corresponding fuse coupled between the circuit for operating the memory array and each contact of the first plurality of contacts.In some examples of the device, the selection component may include a corresponding anti-fuse coupled between the circuit for operating the memory array and each contact of the first plurality of contacts.In some examples of the device, the selection component may include a corresponding switching component coupled between the circuit for operating the memory array and each contact of the first plurality of contacts. In some examples, the respective switching components may be operable (e.g., to couple or disconnect) based at least in part on a logic signal (e.g., received from a host device received from a device memory controller received from a local memory controller received from a logic chip).Another apparatus will be described. The apparatus may include a voltage source (e.g., from or otherwise connected to a storage device), which may include a conductor or component of the storage device operable to receive a voltage or current from outside the storage device (e.g., from a host device, from an external power supply), and operable to provide a voltage or current to memory chips of the storage device. In some examples, the voltage source may include or refer to a regulated voltage supply common to the memory chips of the memory device, and the voltage source may be external to each of the memory chips of the memory device (e.g., in a logic chip of the memory device). The apparatus may also include a first memory chip (e.g., the memory device, a stack of memory chips). The first memory chip may include a first memory array including a first plurality of memory cells and a first interface coupled to the voltage source and connected to a circuit for operating the first memory array. The first memory chip may also include a second interface isolated (e.g., electrically isolated) from the first interface within the first memory chip and coupled (e.g., electrically coupled) to the voltage source, and a third interface isolated (e.g., electrically isolated) from the first interface and coupled to the second interface within the first memory chip. The apparatus may also include a second memory chip (e.g., the memory device, the stack of memory chips). The second memory chip may include a second memory array including a second plurality of memory cells and a fourth interface coupled to the third interface (e.g., the first memory chip) and connected to a circuit for operating the second memory array.In some examples, the first memory array and the second memory array, or the first plurality of memory cells and the second plurality of memory cells, may be addressable via the same command / address bus or channel of the memory device.In some examples, the device may include a bonding layer between the first memory chip and the second memory chip. The bonding layer may include a conductive material in contact with (e.g., physically coupled, electrically coupled to) the third interface and the fourth interface.In some examples of the device, when viewed along a direction perpendicular to a plane between the first memory die and the second memory die, a cross-section of the first interface may at least partially overlap or otherwise match a cross-section of the third interface.In some examples of the device, a cross-section of the first interface may not overlap or otherwise not match a cross-section of the third interface when viewed along a direction perpendicular to a plane between the first memory die and the second memory die.In some examples, the apparatus may include a second voltage source (e.g., the memory device). In some such examples, the first memory chip may further include a fifth interface coupled (e.g., electrically coupled) to the second voltage source and coupled to the circuit for operating the first memory array. The first memory chip may further include a sixth interface isolated (e.g., electrically isolated) from the fifth interface within the first memory chip and coupled (e.g., electrically coupled) to the second voltage source, and a seventh interface isolated (e.g., electrically isolated) from the fifth interface within the first memory chip and coupled (e.g., electrically coupled) to the sixth interface within the first memory chip. Moreover, in some such examples, the second memory chip may further include an eighth interface coupled to the seventh interface (e.g., the first memory chip) and coupled to the circuit for operating the second memory arrayIn some examples, the apparatus may include a second voltage source (e.g., the memory device). In some such examples, the first memory chip may further include a fifth interface coupled (e.g., electrically coupled) to the second voltage source and coupled to the circuit for operating the first memory array, and a sixth interface coupled to the fifth interface within the first memory chip. Moreover, in some examples, the second memory chip may include a seventh interface coupled to the sixth interface and coupled to the circuit for operating the second memory array.Another apparatus will be described. The apparatus may include a power source (e.g., from a memory device or otherwise connected thereto, from a logic chip), which may include a conductor or component of the memory device that is / is operable to receive a voltage or current from outside the memory device (e.g., from a host device, from an external power supply), and is operable to provide a voltage or current to memory chips of the memory device. In some examples, the current source may include or refer to a regulated voltage supply common to the memory chips of the memory device, and the current source may be external to each of the memory chips of the memory device. The apparatus may also include a first memory chip (e.g., the memory device, a stack of memory chips). The first memory chip may include a first memory array including a first plurality of memory cells and a first plurality of contacts (e.g., on a first surface of the first memory chip) each coupled to the current source. The first memory chip may also include a second plurality of contacts (e.g., on a second surface of the first memory chip) coupled to a corresponding contact of the first plurality of contacts. The first memory chip may also include a first switching component configured or otherwise configured to couple one of the first plurality of contacts to the circuit for operating the first memory array, and a second switching component configured or otherwise configured to isolate one of the second plurality of contacts from the circuit for operating the first memory array. The apparatus may also include a second memory chip (e.g., the memory device, the stack of memory chips). The second memory chip may include a second memory array including a second plurality of memory cells and a third plurality of contacts (e.g., on a first surface of the second memory chip) each coupled to a corresponding one of the second plurality of contacts (e.g., the first memory chip). The second memory chip may also include a third switching component configured or otherwise configurable to couple the one of the third plurality of contacts coupled to the one of the second plurality of contacts to a circuit for operating the second memory array.In some examples, the first memory array and the second memory array, or the first plurality of memory cells and the second plurality of memory cells, may be addressable via the same command / address bus or channel of the memory device.In some examples of the device, the power source may include a voltage regulator that is separate from the first memory chip and the second memory chip and that is configured to provide power to the first memory chip and the second memory chip at a regulated voltage.In some examples of the device, each contact of the first plurality of contacts may be isolated (e.g., electrically isolated) from the other contacts of the first plurality of contacts within the first memory chip, and each contact of the third plurality of contacts may be isolated (e.g., electrically isolated) from the other contacts of the third plurality of contacts within the second memory chip.In some examples of the device, the first switching component may include a one-time programmable switch configured or otherwise configurable in a closed circuit configuration, the second switching component may include a second one-time programmable switch configured or otherwise configurable in an open circuit configuration, and the third switching component may include a third one-time programmable switch configured or otherwise configurable in a closed circuit configuration.The information and signals described herein may be represented using a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to in the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. In some drawings, signals may be represented as a single signal; however, the signal may represent a bus of signals, where the bus may have a plurality of bit widths.The terms "electronic communication", "conductive contact", "connected", and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to communicate electronically with each other (or in conductive contact with each other or connected or coupled) if there is a conductive path between the components that can support the signal flow between the components at any time. At any point in time, the conductive path between components in electronic communication with each other (or in conductive contact with or connected or coupled to them) may be an open or a closed circuit depending on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be temporarily interrupted, e.g., by one or more intermediate components such as switches or transistors.The term "coupling" refers to a state in which a transition is made from an open circuit between components in which signals cannot currently be transmitted via a conductive path between the components to a closed circuit between components in which signals can be transmitted via the conductive path between components. When a component, e.g., a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path that previously did not allow signal flow.The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other (e.g., electrically isolated) when an open circuit exists between them. For example, two components separated by a switch positioned between the components are separated from each other when the switch is open. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components via a conductive path that previously allowed signals to flow.As used herein, the term "layer" or "plane" refers to a layer or sheet of geometric structure (e.g., relative to a substrate). Each layer or plane may have three dimensions (e.g., height, width, and depth) and cover at least a portion of a surface. For example, a layer or plane may be a three-dimensional structure in which two dimensions are larger than a third, e.g., a thin film. Layers or planes may include various elements, components, and / or materials. In some examples, a layer or plane may be composed of two or more sub-layers or sub-planes.The devices discussed herein, including a memory array, may be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate or of sub-regions of the substrate can be controlled by doping with various chemical substances such as phosphorus, boron or arsenic. Doping may be performed during initial formation or growth of the substrate by ion implantation or by any other dopant.A switching component or transistor discussed herein may represent a field-effect transistor (FET) and may include a three terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic elements by conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily doped, e.g. degenerate, semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. When the channel is n-type (i.e., most charge carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most charge carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET and a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. The transistor may be "off" or "disabled" when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

Claims

An apparatus comprising: a memory array (170-a) of a first semiconductor die (160-a), the memory array (170-a) comprising a plurality of memory cells (205); a first interface couplable to a current source (180) external to the first semiconductor die (160-a), the first interface conforming to a first surface of the first semiconductor die (160-a); a second interface electrically isolated from the first interface within the first semiconductor die (160-a) and couplable to the current source (180); and a third interface electrically isolated from the first interface within the first semiconductor die (160-a), coupled to the second interface within the first semiconductor die (160-a), and coupled to a second semiconductor die (160-b) in a stack of memory dies (160-a, 160-b, 160-N) comprising the first and second semiconductor chips, wherein the second semiconductor chip (160-a) comprises a second plurality of memory cells (205) addressable via the same command / address bus as the first semiconductor chip (160-a), the third interface conforming to a second surface of the first semiconductor chip (160-a) opposite the first surface of the first semiconductor chip (160-a), wherein the coupling between the second interface and the third interface comprises: a first conductor portion coupled to the second interface and extending perpendicular to the first surface; a second conductor portion coupled to the third interface and extending perpendicular to the second surface; a third conductor portion coupled to the first conductor portion and to the second conductor portion and extending in a direction parallel to the first surface, the second surface, or both.The apparatus of claim 1, wherein the coupling between the second interface and the third interface is operable to provide power from the power source (180) to the second semiconductor die (160-b) to support access operations to the second plurality of memory cells (205).An apparatus comprising: a memory array (170-a) of a first semiconductor die (160-a), the memory array (170-a) comprising a plurality of memory cells (205); a first interface couplable to a current source (180) external to the first semiconductor die (160-a), the first interface conforming to a first surface of the first semiconductor die (160-a); a second interface electrically isolated from the first interface within the first semiconductor die (160-a) and couplable to the current source (180); and a third interface electrically isolated from the first interface within the first semiconductor die (160-a), coupled to the second interface within the first semiconductor die (160-a), and coupled to a second semiconductor die (160-b) in a stack of memory dies (160-a, 160-b, 160-N) comprising the first and second semiconductor dies, wherein the second semiconductor die (160-b) comprises a second plurality of memory cells (205) addressable via the same command / address bus as the first semiconductor die (160-a), the third interface coincides with a second surface of the first semiconductor die (160-a) opposite the first surface of the first semiconductor die (160-a), wherein when viewed along a direction from the first surface to the second surface, a cross section of the first interface at least partially overlaps with a cross section of the third interface.An apparatus comprising: a memory array (170-a) of a first semiconductor die (160-a), the memory array (170-a) comprising a plurality of memory cells (205); a first interface couplable to a current source (180) external to the first semiconductor die (160-a), the first interface conforming to a first surface of the first semiconductor die (160-a); a second interface electrically isolated from the first interface within the first semiconductor die (160-a) and couplable to the current source (180); and a third interface electrically isolated from the first interface within the first semiconductor die (160-a), coupled to the second interface within the first semiconductor die (160-a), and coupled to a second semiconductor die (160-b) in a stack of memory dies (160-a, 160-b, 160-N) comprising the first and second semiconductor dies, wherein the second semiconductor die (160-b) comprises a second plurality of memory cells (205) addressable via the same command / address bus as the first semiconductor die (160-a), the third interface coincides with a second surface of the first semiconductor die (160-a) opposite the first surface of the first semiconductor die (160-a), wherein when viewed along a direction from the first surface to the second surface, a cross section of the first interface does not overlap with a cross section of the third interface.An apparatus comprising: a memory array (170-a) of a first semiconductor die (160-a), the memory array (170-a) comprising a plurality of memory cells (205); a first interface couplable to a current source (180) external to the first semiconductor die (160-a); a second interface electrically isolated from the first interface within the first semiconductor die (160-a) and couplable to the current source (180); a third interface electrically isolated from the first interface within the first semiconductor die (160-a), coupled to the second interface within the first semiconductor die (160-a), and couplable to a second semiconductor die (160-b) in a stack of memory dies (160-a, 160-b, 160-N) comprising the first and second semiconductor dies, the second semiconductor die (160-b) comprising a second plurality of memory cells (205) addressable via the same command / address bus as the first semiconductor die (160-a); a fourth interface couplable to a ground voltage source external to the first semiconductor die (160-a); a fifth interface electrically isolated from the fourth interface within the first semiconductor die (160-a) and couplable to the ground voltage source; and a sixth interface electrically isolated from the fourth interface within the first semiconductor chip ( 160- a), coupled to the fifth interface within the first semiconductor chip ( 160- a) and couplable to the second semiconductor chip ( 160- b).An apparatus comprising: a memory array (170-a) of a first semiconductor die (160-a), the memory array (170-a) comprising a plurality of memory cells (205); a first interface couplable to a current source (180) external to the first semiconductor die (160-a); a second interface electrically isolated from the first interface within the first semiconductor die (160-a) and couplable to the current source (180); A third interface electrically isolated from the first interface within the first semiconductor die (160-a), coupled to the second interface within the first semiconductor die (160-a), and couplable to a second semiconductor die (160-b) in a stack of memory dies (160-a, 160-b, 160-N) comprising the first and second semiconductor dies, wherein the second semiconductor die (160-b) comprises a second plurality of memory cells (205) addressable via the same command / address bus as the first semiconductor die (160-a); a fourth interface couplable to a ground voltage source located external to the first semiconductor die (160-a); and a fifth interface coupled to the fourth interface within the first semiconductor die (160-a) and couplable to the second semiconductor die (160-b).An apparatus comprising: a voltage source (180) of a memory device (110); a first memory chip (160-a) of the memory device (110), the first memory chip (160-a) comprising: a first memory array (170-a) comprising a first plurality of memory cells (205); a first interface coupled to the voltage source (180) and coupled to a circuit for operating the first memory array (170-a); a second interface electrically isolated from the first interface within the first memory chip (160-a) and coupled to the voltage source (180); and a third interface electrically isolated from the first interface and coupled to the second interface within the first memory chip (160-a); and a second memory chip (160-b) of the memory device, the second memory chip (160-b) comprising: a second memory array (170-b) comprising a second plurality of memory cells (205); and a fourth interface coupled to the third interface and coupled to a circuit for operating the second memory array (170-b), wherein, when viewed along a direction perpendicular to a plane between the first memory chip (160-a) and the second memory chip (160-b), a cross section of the first interface at least partially overlaps with a cross section of the third interface.The device of claim 7, further comprising: a bonding layer between the first memory chip (160-a) and the second memory chip (160-b), wherein the bonding layer comprises a conductive material in contact with the third interface and the fourth interface.An apparatus comprising: a voltage source (180) of a memory device (110); a first memory chip (160-a) of the memory device (110), the first memory chip (160-a) comprising: a first memory array (170-a) comprising a first plurality of memory cells (205); a first interface coupled to the voltage source (180) and coupled to a circuit for operating the first memory array (170-a); a second interface electrically isolated from the first interface within the first memory chip (160-a) and coupled to the voltage source (180); and a third interface electrically isolated from the first interface and coupled to the second interface within the first memory chip (160-a); and a second memory chip (160-b) of the memory device, the second memory chip (160-b) comprising: a second memory array (170-b) comprising a second plurality of memory cells (205); and a fourth interface coupled to the third interface and coupled to a circuit for operating the second memory array (170-b), wherein, when viewed along a direction perpendicular to a plane between the first memory chip (160-a) and the second memory chip (160-b), a cross section of the first interface is not overlapped with a cross section of the third interface.An apparatus comprising: a voltage source (180) of a memory device (110); a second voltage source of the memory device, a first memory chip (160-a) of the memory device (110), the first memory chip (160-a) comprising: a first memory array (170-a) comprising a first plurality of memory cells (205); a first interface coupled to the voltage source (180) and coupled to a circuit for operating the first memory array (170-a); a second interface electrically isolated from the first interface within the first memory chip (160-a) and coupled to the voltage source (180); and a third interface electrically isolated from the first interface and coupled to the second interface within the first memory chip (160-a); a fifth interface coupled to the second voltage source (180-b) and coupled to the circuit for operating the first memory array (170-a); a sixth interface electrically isolated from the fifth interface within the first memory chip (160-a) and coupled to the second voltage source; and a seventh interface electrically isolated from the fifth interface within the first memory chip and coupled to the sixth interface within the first memory chip; and a second memory chip (160-b) of the memory device, the second memory chip (160-b) comprising: a second memory array (170-b) comprising a second plurality of memory cells; and a fourth interface coupled to the third interface and coupled to a circuit for operating the second memory array (170-b); and an eighth interface coupled to the seventh interface and coupled to the circuit for operating the second memory array (170-b).An apparatus comprising: a voltage source (180) of a memory device (110); a second voltage source of the memory device (110); a first memory chip (160-a) of the memory device (110), the first memory chip (160-a) comprising: a first memory array (170-a) comprising a first plurality of memory cells (205); a first interface coupled to the voltage source (180) and coupled to a circuit for operating the first memory array (170-a); a second interface electrically isolated from the first interface within the first memory chip (160-a) and coupled to the voltage source (180); and a third interface electrically isolated from the first interface and coupled to the second interface within the first memory chip (160-a); a fifth interface coupled to the second voltage source and coupled to the circuit for operating the first memory array; and a sixth interface coupled to the fifth interface within the first memory chip (160-a); and a second memory chip (160-b) of the memory device (110), the second memory chip (160-b) comprising: a second memory array (170-b) comprising a second plurality of memory cells (205); and a fourth interface coupled to the third interface and coupled to a circuit for operating the second memory array (170-b); and a seventh interface coupled to the sixth interface and coupled to the circuit for operating the second memory array (170-b).An apparatus comprising: a current source (180) of a memory device (110); a first memory chip (160-a) of the memory device (110), the first memory chip (160-a) comprising: a first memory array (170-a) comprising a first plurality of memory cells (205); a first plurality of contacts on a first surface of the first memory chip (160-a) each coupled to the current source (180); a second plurality of contacts on a second surface of the first memory chip (160-a) coupled to a corresponding one of the first plurality of contacts; a first switching component configured to couple one of the first plurality of contacts to a circuit for operating the first memory array (170-a), the first switching component comprising a one-time programmable switch configured in a closed circuit configuration; and a second switching component configured to isolate one of the second plurality of contacts from the circuit for operating the first memory array (170-a), the second switching component comprising a second one-time programmable switch configured in an open circuit configuration; and a second memory chip (160-b) of the memory device (110), the second memory chip (160-b) comprising: a second memory array (170-b) comprising a second plurality of memory cells (205); a third plurality of contacts on a first surface of the second memory chip (160-b) each coupled to a corresponding one of the second plurality of contacts of the first memory chip (160-a); and a third switching component configured to couple the one of the third plurality of contacts coupled to the one of the second plurality of contacts to a circuit for operating the second memory array (170-b), wherein the third switching component comprises a third one-time programmable switch configured in a closed circuit configuration.The apparatus of claim 12, wherein the power source (180) comprises: a voltage regulator separate from the first memory chip (160-a) and the second memory chip (160-b) and configured to provide power to the first memory chip (160-a) and the second memory chip (160-b) at a regulated voltage.The apparatus of claim 12 or 13, wherein: each contact of the first plurality of contacts is electrically insulated from the other contacts of the first plurality of contacts within the first memory chip (160-a); and each contact of the third plurality of contacts is electrically insulated from the other contacts of the third plurality of contacts within the second memory chip (160-b).A method comprising: providing (605) a memory chip for mounting in a memory device having a plurality of chips, the memory chip comprising: a first plurality of contacts on a first surface of the memory chip; a second plurality of contacts on a second surface of the memory chip, each coupled to a corresponding one of the first plurality of contacts; and a selection component coupled between each contact of the first plurality of contacts and a circuit for operating a memory array of the memory chip; configuring (610) the selection component to couple a first contact of the first plurality of contacts to the circuit for operating the memory array and isolate a second contact of the first plurality of contacts from the circuit for operating the memory array, wherein the configuring of the selection component is based at least in part on a position of the memory chip relative to a second memory chip of the memory device having multiple chips; and coupling (615) a current source circuit to each of the first plurality of contacts on the first surface of the memory chip.The method of claim 15, wherein coupling comprises: connecting the memory chip to a substrate comprising the power source circuit, wherein connecting comprises making an electrical connection between each contact of the first plurality of contacts with one or more contacts of the substrate coupled to the power source circuit.The method of any of the preceding claims 15 or 16, wherein configuring (610) the selection component comprises: maintaining continuity of a first fuse between the first contact and the circuit for operating the memory array; and interrupting continuity of a second fuse between the second contact and the circuit for operating the memory array.The method of any of the preceding claims 15 to 17, wherein configuring (610) the selection component comprises: establishing continuity of a first anti-fuse between the first contact and the circuit for operating the memory array; and maintaining isolation of a second anti-fuse between the second contact and the circuit for operating the memory array.The method of any of the preceding claims 15 to 18, wherein configuring (610) the selection component comprises: providing a first signal for establishing continuity by a first switching component between the first contact and the circuit for operating the memory array; and providing a second signal for establishing isolation by a second switching component between the second contact and the circuit for operating the memory array.

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