METHOD FOR MANUFACTURING A NANOSTRUCTURE FIELD EFFECT TRANSISTOR COMPONENT

Abstract

Method (1000) for manufacturing a semiconductor device, comprising: Forming a fin structure (91) projecting over a substrate (50), wherein the fin structure (91) has a fin (90) and a layer stack (92) above the fin (90), the layer stack (92) having alternating layers of a first semiconductor material (52) and a second semiconductor material (54); Forming a first dummy gate structure and a second dummy gate structure over the fin structure (91); Forming an opening (110) in the fin structure (91) between the first dummy gate structure and the second dummy gate structure; Converting an upper layer of the fin (90) exposed at the underside of the opening (110) into a germinal layer (111) by performing an implantation procedure; selective deposition of a dielectric layer (113) over the nucleation layer (111) on the underside of the opening (110); and selective growth of a source / drain material (112) on the opposite side walls of the second semiconductor material (54) exposed through the opening (110).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. The various material layers are then patterned using lithography to form circuit components and elements.

[0002] US 2018 / 0 301 564 A1 describes a semiconductor device. The semiconductor device comprises a substrate, vertically stacked and spaced-apart channel semiconductor patterns on the substrate, a gate electrode extending over the channel semiconductor patterns, source / drain regions on opposite sides of the gate electrode, the source / drain regions connected to the channel semiconductor patterns, and air gaps between the substrate and the undersides of the source / drain regions such that the undersides of the source / drain regions do not touch the substrate.

[0003] The semiconductor industry is continuously working to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum size of the components so that more components can be integrated into a given area. However, reducing the minimum size of components also creates additional problems that must be solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not illustrated to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for the sake of clarity of explanation. Fig. 1 illustrates an example of a nanostructure field effect transistor (NSFET) in a three-dimensional view, as used in some embodiments. The Fig. 2, 3A, 3B, 4A, 4B, 5A-5C, 6A-6C, 7-10, 11A-11C, 12A, 12B, 13A, 13B, 14A and 14B are cross-sectional views of a nanostructure field-effect transistor at different stages of fabrication. Fig. 15 is a flowchart of a method for manufacturing a semiconductor device. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first feature over or on a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact.

[0006] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "down," "lower," "over," "upon," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may also be interpreted accordingly.

[0007] According to some embodiments, air gaps are formed beneath the source / drain regions of a nanostructured device, e.g., between the source / drain regions and the underlying fin. The air gaps advantageously reduce the fringing capacitance and leakage current of the formed device. To form the air gaps, source / drain openings are formed in the fin structure between adjacent dummy gate structures. Subsequently, an ion implantation process is performed to convert an upper layer of the fin, which is exposed through the source / drain openings, into a seed layer. A dielectric layer is then selectively formed on the seed layer. An epitaxial source / drain material is then selectively grown on a semiconductor material exposed at the sidewalls of the source / drain openings.The dielectric layer at the bottom of the source / drain openings prevents the epitaxial source / drain material from growing from the bottom of the source / drain openings. Accordingly, the source / drain material grows laterally from the sidewalls of the semiconductor material exposed through the source / drain openings and converges to form the source / drain region, creating an air gap between the source / drain regions and the underlying dielectric layer disposed on the fins.

[0008] Fig. 1 illustrates an example of a nanostructure field-effect transistor (NSFET) 30 in a three-dimensional view, according to some embodiments. The NSFET device 30 includes semiconductor fins 90 (also referred to as fins) that protrude above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed over the fins, and source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanostructures 54 (e.g., nanowires or nanosheets) are formed over the fins 90 and between the source / drain regions 112. Isolation regions 96 are formed on opposite sides of the fins 90. A gate dielectric layer 120 is formed around the nanostructures 54. The gate electrodes 122 are present over and around the gate dielectric layer 120.

[0009] Furthermore, Fig. 1 References to cross-sections used in the following figures. Cross-section AA runs along a longitudinal axis of the gate electrode 122 and in a direction that is, for example, perpendicular to the direction of current flow between the source / drain regions 112 of the NSFET device 30. Cross-section BB is perpendicular to cross-section AA and runs along a longitudinal axis of the fin 90 and in a direction, for example, of current flow between the source / drain regions 112 of the NSFET device. Cross-section CC runs parallel to cross-section BB and between two adjacent fins 90. Cross-section DD runs parallel to cross-section AA and extends through the source / drain regions 112 of the NSFET device. The following figures refer to these reference cross-sections for simplicity.

[0010] The Fig. 2, 3A, 3B, 4A, 4B, 5A-5C, 6A-6C, 7-10, 11A-11C, 12A, 12B, 13A, 13B, 14A, and 14B are cross-sectional views of a nanostructure field-effect transistor (NSFET) 100 at various stages of fabrication according to one embodiment.

[0011] In Fig. 2, a substrate 50 is present. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, an SOI substrate (semiconductor on insulator substrate), or the like, which can be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, e.g., a silicon wafer. In general, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer can be, for example, a BOX layer (buried oxide layer), a silicon oxide layer, or the like. The insulator layer is present on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or gradient substrate, can also be used.In some embodiments, the semiconductor material of substrate 50 includes silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0012] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 contains alternating layers of a first semiconductor material 52 and a second semiconductor material 54. In Fig. 2, the layers formed from the first semiconductor material 52 are designated 52A, 52B and 52C and the layers formed from the second semiconductor material 54 are designated 54A, 54B and 54C. Fig. The number of layers formed from the first semiconductor material and the second semiconductor material illustrated in Figure 2 is merely a non-limiting example. Other numbers of layers are also possible and are intended to be within the scope of the present invention.

[0013] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming channel regions of p-type FETs, such as silicon germanium (Si x Ge 1-x, where x can range from 0 to 1), and the second semiconductor material 54 is an epitaxial material suitable for forming channel regions of n-type FETs, such as silicon. The multilayer stacks 64 (which may also be referred to as epitaxial material stacks) are patterned to form the channel regions of an NSFET during subsequent processing. In particular, the multilayer stacks 64 are patterned and etched to form horizontal nanostructures (e.g., nanosheets or nanowires), with the channel regions of the resulting NSFET containing multiple horizontal nanostructures.

[0014] The multilayer stacks 64 may be formed by an epitaxial growth process, which may be performed in a growth chamber. During the epitaxial growth process, in some embodiments, the growth chamber is cyclically exposed to a first set of precursors to selectively grow the first semiconductor material 52 and then exposed to a second set of precursors to selectively grow the second semiconductor material 54. The first set of precursors includes precursors for the first semiconductor material (e.g., silicon-germanium), and the second set of precursors includes precursors for the second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., a germanium), and the second set of precursors includes the silicon precursor but no germanium precursor.The epitaxial growth process may therefore involve continuously allowing a flow of the silicon precursor into the growth chamber and then cyclically: (1) enabling a flow of the germanium precursor into the growth chamber when growing the first semiconductor material 52; and (2) disabling the flow of the germanium precursor into the growth chamber when growing the second semiconductor material 54. The cyclic exposure may be repeated until a certain number of layers are formed.

[0015] The Fig. 3A, 3B, 4A, 4B, 5A-5C, 6A-6C, 7-10, 11A-11C, 12A, 12B, 13A, 13B, 14A, and 14B are cross-sectional views of the NSFET device 100 in subsequent manufacturing stages according to one embodiment. Fig. 3A, 4A, 5A, 6A, 7-10, 11A, 12A, 13A and 14A are cross-sectional views along the cross section BB in Fig. 1. The Fig. 3B, Fig. 4B, Fig. 5C, Fig. 6C, Fig. 11C, Fig. 12B, Fig. 13B and Fig. 14B are cross-sectional views along the cross section AA in Fig. 1. The Fig. 5B, Fig. 6B and Fig. 11B are cross-sectional views along the cross section DD in Fig. 1. Although two fins and two gate structures are illustrated in the figures as a non-limiting example, a different number of fins and a different number of gate structures may be formed.

[0016] In the Fig. 3A and Fig. 3B, fin structures 91 are formed that protrude beyond the substrate 50. Each of the fin structures 91 includes a semiconductor fin 90 (also referred to as a fin) and a layer stack 92 overlying the semiconductor fin 90. The layer stack 92 and the semiconductor fin 90 may be formed by etching trenches into the multilayer stack 64 and the substrate 50, respectively. The layer stack 92 and the semiconductor fin 90 may be formed by the same etching process.

[0017] The fin structures 91 can be patterned using any suitable method. For example, the fin structures 91 can be patterned using one or more photolithography methods, including double-patterning or multi-patterning methods. Generally, double-patterning or multi-patterning methods combine photolithography and the self-aligned method so that structures can be created that have, for example, smaller pitches than would be possible with a single direct photolithography method. In one embodiment, for example, a sacrificial layer is formed on a substrate and patterned using a photolithography method. Spacers are formed along the patterned sacrificial layer in a self-aligned method. The sacrificial layer is then removed, and the remaining spacers can then be used, for example, to pattern the fin structures 91.

[0018] In some embodiments, the remaining spacers are used to pattern a mask 94, which is then used to pattern the fin structures 91. The mask 94 may be a single-layer mask or a multi-layer mask, e.g., a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B may each be formed from a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to a suitable technique. The first mask layer 94A and the second mask layer 94B may comprise different materials that have high etch selectivity. For example, the first mask layer 94A may comprise silicon oxide, and the second mask layer 94B may comprise silicon nitride.The mask 94 may be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. The mask 94 may then be used as an etch mask to etch the substrate 50 and the multilayer stack 64. The etching may be any acceptable etching process, e.g., reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. In some embodiments, the etching is an anisotropic etching process. After the etching process, the patterned multilayer stack 64 forms the layer stack 92, and the patterned substrate 50 forms the fin 90, as shown in FIGS. Fig. 3A and Fig. 3B. Therefore, in the illustrated embodiment, the layer stack 92 also includes alternating layers of the first semiconductor material 52 and the second semiconductor material 54, and the fin 90 is formed from the same material (e.g., silicon) as the substrate 50.

[0019] The following are Fig. 4A and Fig. 4B STI (shallow trench isolation) regions 96 are formed above the substrate 50 and on the opposite sides of the fin structures 91. To form the STI regions 96, for example, an insulating material may be formed above the substrate 50. The insulating material may be an oxide, such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by HDP-CVD (“high density plasma chemical vapor deposition”), FCVD (flowable CVD) (e.g., a CVD-based material deposition in a remote plasma system) and subsequent annealing to convert it to another material, such as an oxide, or the like, or a combination thereof. Other insulating materials formed by any acceptable method may also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD method.After forming the insulating material, an annealing process can be carried out.

[0020] In some embodiments, the insulating material is formed such that excess insulating material covers the fin structures 91. In some embodiments, a liner is first formed along the surfaces of the substrate 50 and the fin structures 91, and a fill material, such as that described above, is formed over the liner. In some embodiments, the liner is omitted.

[0021] Subsequently, an insulating material removal process is applied to remove excess insulating material over the fin structures 91. In some embodiments, a planarization process, such as CMP (chemical mechanical polishing), an etch-back process, a combination thereof, or the like, may be used. The planarization process exposes the layer stacks 92 such that the top surfaces of the layer stacks 92 and the insulating material are flat after completion of the planarization process. Subsequently, the insulating material is recessed to form the STI regions 96. The insulating material is recessed such that the layer stacks 92 protrude between adjacent STI regions 96. Upper portions of the semiconductor fins 90 may also protrude between the adjacent STI regions 96.Furthermore, the upper surfaces of the STI regions 96 may have a flat surface (as illustrated), a convex surface, a concave surface (such as a slope), or a combination thereof. The upper surfaces of the STI regions 96 may be formed flat, convex, and / or concave by suitable etching. The STI regions 96 may be recessed by a suitable etching process, e.g., a process that is selective to the material of the insulating material (e.g., the material of the insulating material etches faster than the material of the fin 90 and the layer stack 92). For example, removing a chemical oxide with a suitable etchant, such as dilute hydrofluoric acid (dilute HF), may be used.

[0022] As in the Fig. 4A and Fig. As illustrated in Figure 4B, a dummy dielectric layer 97 is formed over the layer stack 92 and over the STI regions 96. The dummy dielectric layer 97 may include, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown by any acceptable method. In one embodiment, a silicon layer is conformally formed over the layer stack 92 and over the top surface of the STI regions 96, and a thermal oxidation process is performed to convert the deposited silicon layer into an oxide layer as the dummy dielectric layer 97.

[0023] The following are Fig. 5A-5C Dummy gates 102 are formed over the fin structures 91. To form the dummy gates 102, a dummy gate layer may be formed over the dummy dielectric layer 97. The dummy gate layer may be deposited over the dummy dielectric layer 97 and then planarized, e.g., by a CMP process. The dummy gate layer may be a conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or the like. The dummy gate layer may be deposited by PVD (physical vapor deposition), CVD, sputter deposition, or other methods known and used in the art. The dummy gate layer may be formed from other materials that have high etch selectivity to the STI regions 96.

[0024] Subsequently, masks 104 are formed over the dummy gate layer. Masks 104 may include silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of masks 104 is then transferred to the dummy gate layer using a suitable etching process to form dummy gates 102, and subsequently transferred to the dummy dielectric layer using a suitable etching process to form dummy gate dielectrics 97. Dummy gates 102 cover the respective channel regions of layer stacks 92. The structure of the masks 104 can be used to physically separate each dummy gate 102 from the neighboring dummy gates.The dummy gates 102 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the fin structures 91. The dummy gate 102 and the dummy gate dielectric 97 are collectively referred to as a dummy gate structure in some embodiments.

[0025] Subsequently, a gate spacer layer 108 is formed by blanket depositing an insulating material over the layer stacks 92, the STI regions 96, and the dummy gates 102. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer 108 includes multiple sublayers. For example, a first sublayer (sometimes referred to as a gate seal spacer layer) may be formed by thermal oxidation or deposition, and a second sublayer (sometimes referred to as a main gate spacer layer) may be blanket deposited on the first sublayer.

[0026] The Fig. 5B and Fig. 5C show cross-sectional views of the NSFET device 100 of Fig. 5A along the cross sections EE and FF as in Fig. 5A. The cross sections EE and FF correspond to the cross sections DD and AA in Fig. 1.

[0027] The following are Fig. 6A-6C, the gate spacer layers 108 are etched by an anisotropic etching process to form the gate spacers 108. The anisotropic etching process may remove horizontal portions of the gate spacer layer 108 (e.g., portions above the STI regions 96 and the dummy gates 102), with the remaining vertical portions of the gate spacer layer 108 (e.g., portions along the sidewalls of the dummy gates 102 and the dummy gate dielectric 97) forming the gate spacers 108.

[0028] The Fig. 6B and Fig. 6C show cross-sectional views of the NSFET device 100 of Fig. 6A along the cross sections EE and FF. In Fig. 6B illustrates the portions of the gate spacer layer 108 between the adjacent fins on top of the STI regions 96. These portions of the gate spacer layer 108 may be left in place because the anisotropic etching process described above may not completely remove the gate spacer layer 108 located between the adjacent fins, as the close spacing between the adjacent fins reduces the efficiency of the anisotropic etching process. In other embodiments, the portions of the gate spacer layer 108 located on the top surface of the STI regions 96 between the adjacent fins are completely removed by the anisotropic etching process used to form the gate spacers 108.

[0029] Subsequently, openings 110 (which may also be referred to as recesses) are formed in the layer stacks 92. The openings 110 may extend through the layer stacks 92 and into the fins 90. The openings 110 may be formed by an anisotropic etching process, in which, for example, the dummy gates 102 and the gate spacers 108 are used as an etch mask.

[0030] After forming the openings 110, a selective etching process is performed to remove the end portions of the first semiconductor material 52 exposed by the openings 110 without significantly damaging the second semiconductor material 54. After the selective etching process, recesses (also referred to as sidewall recesses) are formed in the first semiconductor material 52 at the locations where the removed end portions were present.

[0031] Subsequently, an inner spacer layer (e.g., conformal) is formed in the opening 110. The inner spacer layer also fills the sidewall recesses of the first semiconductor material 52 formed by the previous selective etching process. The inner spacer layer may be a suitable dielectric material such as silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like, formed by a suitable deposition process such as PVD, CVD, ALD (atomic layer deposition), or the like. Next, an etching process, e.g., an anisotropic etching process, is performed to remove portions of the inner spacer layers located outside the sidewall recesses of the first semiconductor material 52. The remaining portions of the inner spacer layers (e.g., portions located within the sidewall recesses of the first semiconductor material 52) form the inner spacers 55.As in . Fig. 6A, the openings 110 expose the sidewalls of the second semiconductor material 54 and a top surface 90U of the fin 90. In the example of Fig. 6A, the upper surface 90U of the fin 90 is vertically disposed between an upper surface and a lower surface of a lowermost inner spacer 55A.

[0032] The following is Fig. 7, an implantation process 130 is performed to convert an upper layer of the fin 90, which is exposed through the openings 110, into a seed layer 111. In some embodiments, the implantation process 130 is performed using a gas source containing carbon, nitrogen, oxygen, or a combination thereof. An example of the gas source may be, for example, O2, N2, or CO2. The gas source is ignited to a plasma containing ions of carbon, nitrogen, and / or oxygen, and the ions are implanted into the upper layer of the fin 90 (e.g., silicon) by the implantation process 130, in some embodiments. The implantation process 130 may be performed at a temperature between about 200°C and about 500°C. After the implantation process, an annealing process, such asRTA (rapid thermal anneal) or furnace annealing, at a temperature between approximately 400°C and 800°C. The annealing process, in some embodiments, repairs lattice damage caused by the implantation process. Through the implantation process 130 and annealing process, the upper layer of the fin 90, in the illustrated embodiment, is converted into the seed layer 111. The seed layer 111 may include, for example, silicon oxide (e.g., SiO), silicon carbide (e.g., SiC), silicon nitride (e.g., SiN), or silicon carbonitride (e.g., SiCN). The seed layer 111 facilitates the subsequent selective deposition of a dielectric layer 113 (see . Fig. 8) on the germ layer 111. In the example of Fig. 7, the upper surface 111U of the seed layer 111 is located between the upper surface and the lower surface of the lowermost inner spacer 55A.

[0033] The following is Fig. 8, a dielectric layer 113 is selectively formed on the seed layer 111. In some embodiments, a selective ALD process is performed to selectively deposit the dielectric layer 113 on the seed layer 111. The selective ALD process may be performed using a silicon-containing precursor (e.g., silane) and one or more precursors containing oxygen, nitrogen, and / or carbon. In some embodiments, the seed layer 111 and the dielectric layer 113 comprise the same material, such as SiO, SiC, SiN, or SiCN. Due to the seed layer 111, the deposition rate of the dielectric layer 113 on the seed layer 111 is higher (e.g., five times higher or more) than depositing the dielectric layer 113 on other surfaces, such as the surfaces of the inner spacer 55, the second semiconductor material 54, and the gate spacer 108.

[0034] As in Fig. 8, after completion of the selective ALD process, the dielectric layer 113 is formed on the seed layer 111, and the surfaces of other structures, such as the inner spacer 55, the second semiconductor material 54, and the gate spacer 108, are free from the dielectric layer 113. In other words, the seed layer 111 is covered by the dielectric layer 113, while other structures, such as the inner spacer 55, the second semiconductor material 54, and the gate spacer 108, are exposed from the dielectric layer 113. In the example of Fig. 8, a top surface 113U of the dielectric layer 113 is present between the top surface and the bottom surface of the bottommost inner spacer 55A. In other embodiments, the top surface 113U is higher (e.g., farther from the substrate) than the top surface of the bottommost inner spacer 55A, but is present between the top surface and the bottom surface of another inner spacer 55 (e.g., an inner spacer 55 that is farther from the substrate 50 than the bottommost inner spacer 55A).

[0035] The method described herein enables selective deposition of the dielectric layer 113 on the seed layer 111, which may not be possible with other ALD methods (e.g., ALD methods without the method described herein). In the illustrated embodiment, a uniform thickness of the dielectric layer 113 is achieved across the surfaces of the seed layer 111, regardless of the dimension of the gaps between the dummy gates 102, thereby reducing or avoiding the space loading effect that occurs in other ALD methods not according to the invention. The selective deposition and uniform thickness of the dielectric layer 113 facilitate the selective growth of the source / drain material during subsequent processing, as explained below.

[0036] The following is Fig. 9, a source / drain material 112 is selectively formed in the openings 110 on the exposed sidewalls of the second semiconductor material 54. In the illustrated embodiment, the source / drain material 112 is formed from one or more epitaxial materials and may therefore also be referred to as epitaxial source / drain material 112.

[0037] In some embodiments, the epitaxial source / drain material 112 is epitaxially grown in the openings 110. The epitaxial source / drain material 112 may include any acceptable material suitable for n-type devices or p-type devices. For example, when forming n-type devices, the epitaxial source / drain material 112 may include materials that exert tensile stress in the channel regions, such as silicon, SiC, SiCP, SiP, or the like. Likewise, when forming p-type devices, the epitaxial source / drain material 112 may include materials that exert compressive stress in the channel regions, such as SiGe, SiGeB, Ge, GeSn, or the like.

[0038] As in Fig. 9, the epitaxial source / drain material 112 is selectively formed on the exposed sidewalls of the second semiconductor material 54. In some embodiments, the lattice constant of the epitaxial source / drain material 112 matches the lattice constant of the second semiconductor material 54, such that the epitaxial source / drain material 112 has a high deposition rate (also referred to as growth rate) on the second semiconductor material 54. On the other hand, the dielectric materials, e.g., those of the inner spacer 55, the gate spacer 108, and the dielectric layer 113, are not conducive to the growth of the epitaxial source / drain material 112, such that the deposition rates of the epitaxial source / drain material 112 on these dielectric surfaces are substantially zero.

[0039] Due to the selective growth of the epitaxial source / drain material 112 on the second semiconductor material 54, the epitaxial source / drain material 112 has, in some embodiments, a higher lateral growth rate than the vertical growth rate. The epitaxial source / drain material 112 on the opposite sidewalls of the second semiconductor material 54, exposed through the opening 110, grows and converges to form a source / drain region 112 (also referred to as epitaxial source / drain region 112), as shown in Fig. 10 illustrates.

[0040] As in Fig. 10, the source / drain region 112 extends continuously from a first dummy gate 102 (e.g., the dummy gate 102 on the left) to a second, adjacent dummy gate 102 (e.g., the dummy gate 102 on the right). In particular, an air gap 115 is formed between each source / drain region 112 and the underlying dielectric layer 113. In the illustrated embodiment, the air gap 115 is formed by selectively growing the source / drain material 112 (e.g., not growing the source / drain material 112 on the dielectric layer 113), which is also referred to as bottom-to-sidewall growth selectivity of the source / drain material 112. The air gap 115 advantageously reduces or eliminates the leakage current (e.g., the leakage current from the source / drain region 112 to the fins 90) and reduces the fringing capacitance of the formed device. In the example of Fig. 10, a top surface of the air gap 115 distal from the substrate 50 is closer to the substrate 50 than a bottom surface of a bottommost nanostructure 54 facing the substrate 50. Note that although the top surface of the air gap 115 (which is the bottom surface of the source / drain region 112) is illustrated as a planar, linear surface, the top surface of the air gap 115 may have an irregular shape, such as including multiple intersecting liner segments and / or having a curved surface.

[0041] The epitaxial source / drain regions 112 may be implanted with dopants, followed by an annealing process. Dopants of a suitable type (e.g., p-type or n-type) may be implanted into the epitaxial source / drain regions 112 (also referred to as impurities). The n-type impurities may be any suitable n-type impurities such as phosphorus, arsenic, antimony, or the like, and the p-type impurities may be any suitable p-type impurities such as boron, BF2, indium, or the like. The source / drain regions may have an impurity concentration between about 10 19 cm -3 and about 10 21 cm -3 In some embodiments, the epitaxial source / drain regions 112 may be doped in situ during growth. The annealing process may be performed after the implantation process to activate the dopants.

[0042] In some embodiments, the epitaxial source / drain regions 112 are formed to exert a voltage in the respective channel regions of the formed NSFET device, thereby improving performance. The epitaxial source / drain regions 112 are formed such that each dummy gate 102 is disposed between the respective adjacent pairs of the epitaxial source / drain regions 112. In some embodiments, the gate spacers 108 are used to separate the epitaxial source / drain regions 112 from the dummy gates 102 by an appropriate lateral distance so that the epitaxial source / drain regions 112 do not short-circuit the later-formed replacement gates of the resulting NSFET device.

[0043] As a result of the epitaxial growth process used to form the epitaxial source / drain regions 112, the top surfaces of the epitaxial source / drain regions 112 have facets that protrude laterally outward beyond the sidewalls of the fin structures 91. In some embodiments, adjacent epitaxial source / drain regions 112 remain separated from each other after completion of the epitaxial growth process (see, e.g., Fig. 11B). In other embodiments, these facets cause adjacent epitaxial source / drain regions 112 of the same NSFET to converge.

[0044] The following is Fig. 11A, a CESL (contact etch stop layer) 116 (e.g., conformal) is formed over the source / drain regions 112 and over the dummy gate 102, and a first ILD (interlayer dielectric) 114 is then deposited over the CESL 116. The CESL 116 is formed from a material having a different etch rate than the first ILD 114 and may be formed from silicon nitride using PECVD, although other dielectric materials, such as silicon oxide, silicon oxynitride, or the like, and combinations thereof, and alternative techniques for forming the CESL 116, such as low-pressure CVD (LPCVD), PVD, or the like, may alternatively be used.

[0045] The first ILD 114 may be formed by a dielectric material and deposited by any suitable process, such as CVD, PECVD (plasma-enhanced CVD), or FCVD. The dielectric materials for the first ILD 114 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may also be used. Fig. 11B and Fig. 11C illustrate cross-sectional views of the NSFET device 100 of Fig. 11A along the cross sections EE and FF in Fig. 11A. It should be noted that in Fig. 11B, an air gap 115 exists between each source / drain region 112 and the dielectric layer 113 on the underlying fin 90. In some embodiments, the air gap 115 is sealed by the CESL 116, forming a closed space.

[0046] The following are Fig. 12A and Fig. 12B, the dummy gates 102 and the dummy gate dielectric 97 are removed. To remove the dummy gates 102, a planarization process, e.g., a CMP, is performed to level the top surfaces of the first ILD 114 and the CESL 116 with the top surfaces of the dummy gates 102 and the gate spacers 108. The planarization process may also remove the masks 104 (see Fig. 11A) on the dummy gates 102 and remove portions of the gate spacers 108 along the sidewalls of the masks 104. After the planarization process, the top surfaces of the dummy gates 102, the gate spacers 108, and the first ILD 114 are flat. Accordingly, the top surfaces of the dummy gates 102 are exposed from the first ILD 114.

[0047] Subsequently, the dummy gates 102 are removed in one or more etching steps, forming recesses 103 between the gate spacers 108. The recesses 103 expose portions of the first semiconductor material 52 and portions of the second semiconductor material 54 that were present beneath the dummy gates 102. In some embodiments, the dummy gates 102 are removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process with reactive gas(es) that selectively etches the dummy gates 102 without etching the first ILD 114 or the gate spacers 108. Each recess 103 exposes the channel regions of the NSFET. Each channel region is disposed between adjacent pairs of the epitaxial source / drain regions 112. During the removal of the dummy gates 102, the dummy gate dielectric 97 may be used as an etch stop layer when the dummy gates 102 are etched.The dummy gate dielectric 97 may then be removed after removing the dummy gates 102. In some embodiments, the dummy gate dielectric 97 may be removed by an etching process, e.g., an isotropic etching process. In one embodiment, an isotropic etching process is performed to remove the dummy gate dielectric 97 using an etching gas containing HF and NH3. Fig. 11B illustrates the cross-sectional view of the NSFET device 100 of Fig. 11A along cross section FF.

[0048] The following is in the Fig. 13A and Fig. 13B, the first semiconductor material 52 is removed to expose the second semiconductor material 54. After the first semiconductor material 52 is removed, the second semiconductor material 54 forms a plurality of nanostructures 54 extending horizontally (e.g., parallel to a top major surface of the substrate 50). The nanostructures 54 may be collectively referred to as the channel regions 93 or the channel layers 93 of the formed NSFET device 100. As shown in Fig. 13A, the removal of the first semiconductor material 52 forms the gaps 53 (e.g., empty spaces), e.g., between the nanostructures 54. In some embodiments, the nanostructures 54 are nanosheets or nanowires, depending, e.g., on the dimensions (e.g., size and / or aspect ratio) of the nanostructures 54.

[0049] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective for the first semiconductor material 52 (e.g., having a higher etch rate) such that the first semiconductor material 52 is removed without substantially attacking the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process may be performed using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, and combinations thereof, or the like.

[0050] Fig. 13A illustrates the cross-sectional view of the NSFET device 100 along a longitudinal axis of the fin (e.g., along a current flow direction in the fin), and Fig. 13B illustrates the cross-sectional view of the NSFET device 100 along the cross section FF of Fig. 13A, which is a cross-section along a direction perpendicular to the longitudinal axis of the fin and across a central portion of the nanostructure 54.

[0051] The following are Fig. 14A and Fig. 14B, the gate dielectric layers 120 and gate electrodes 122 for the replacement gates are formed. The gate dielectric layers 120 are conformally deposited in the recesses 103, e.g., on the top surfaces and sidewalls of the fin 90 and on the sidewalls of the gate spacers 108. The gate dielectric layers 120 may also be formed on the top surface of the first ILD 114. In particular, the gate dielectric layers 120 enclose the nanostructures 54. In accordance with some embodiments, the gate dielectric layers 120 include silicon oxide, silicon nitride, or multilayers thereof.In some embodiments, the gate dielectric layers 120 include a high-k dielectric material, and in these embodiments, the gate dielectric layers 120 may have a k value greater than about 7.0 and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb, or combinations thereof. The methods for forming the gate dielectric layers 120 may include MBD (molecular beam deposition), ALD, PECVD, and the like.

[0052] Subsequently, the gate electrodes 122 are deposited over and around the gate dielectric layers 120 and fill the remaining portions of the recesses 103. The gate electrodes 122 may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 122 is illustrated, the gate electrode 122 may include any number of liner layers (e.g., barrier layers), any number of work-function tuning layers, and a fill material. After filling the gate electrodes 122, a planarization process, e.g., a CMP process, may be performed to remove excess portions of the gate dielectric layers 120 and excess portions of the gate electrode 122 material, these excess portions being present above the top surface of the first ILD 114.The remaining portions of the material of the gate electrodes 122 and the gate dielectric layers 120 thus form replacement gates of the resulting NSFET device 100. Each gate electrode 122 and the corresponding gate dielectric layers 120 may collectively be referred to as a gate stack, replacement gate structure, or metal gate structure. Each gate stack extends around the respective nanostructures 54. The cross-sectional view of the NSFET device 100 of FIG. Fig. 14A along the cross section EE is the same or similar to Fig. 11B and is therefore not repeated here.

[0053] Further steps may be performed to complete the NSFET device 100, as will be readily apparent to one skilled in the art, so details will not be repeated here. For example, a second ILD may be deposited over the first ILD 114. Furthermore, gate contacts and source / drain contacts may be formed through the second ILD and / or the first ILD 114 to electrically connect the gate electrode 122 and the source / drain regions 112, respectively.

[0054] Variations of the disclosed embodiments are possible and are intended to be fully within the scope of the present disclosure. For example, depending on the type of device formed (e.g., n-type or p-type device), the second semiconductor material 54 may be removed and the first semiconductor material 52 may remain to form the nanostructures that function as the channel regions of the formed NSFET device. In embodiments where the first semiconductor material 52 remains to form the nanostructures, internal spacers are formed in the sidewall recesses at the end portions of the second semiconductor material 54 before the second semiconductor material 54 is removed, as one of ordinary skill in the art will readily appreciate.

[0055] Fig. 15 illustrates a flowchart of a method 1000 for manufacturing a semiconductor device in accordance with some embodiments. It should be understood that the Fig. The method illustrated in Figure 15 is only one example of many possible embodiments. A person skilled in the art will recognize many variations, alternatives, and modifications. For example, various steps as described in Fig. 15 are added, removed, replaced, rearranged or repeated.

[0056] Referring to Fig.15, in box 1010, a fin structure is formed protruding above a substrate, the fin structure comprising a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material. In box 1020, a first dummy gate structure and a second dummy gate structure are formed over the fin structure. In box 1030, an opening is formed in the fin structure between the first dummy gate structure and the second dummy gate structure. In box 1040, an upper layer of the fin exposed at the bottom of the opening is converted into a seed layer by performing an implantation process. In box 1050, a dielectric layer is selectively deposited over the seed layer at the bottom of the opening.In box 1060, a source / drain material is selectively grown on the opposite sidewalls of the second semiconductor material exposed through the opening.

[0057] Advantages can be achieved through embodiments. Through the ion implantation and selective deposition of the dielectric layer 113, the described method achieves, among other things, selective growth of the source / drain material 112 (e.g., bottom-to-sidewall growth selectivity), which leads to the formation of air gaps 115 between the source / drain regions 112 and the underlying fins 90. The air gaps 115 reduce the fringing capacitance of the formed device and reduce or eliminate the leakage current of the formed device.

[0058] One embodiment comprises a method of manufacturing a semiconductor device comprising: forming a fin structure protruding above a substrate, the fin structure comprising a fin and a layer stack above the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure above the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin, which is exposed at the bottom of the opening, into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source / drain material on the opposite sidewalls of the second semiconductor material,exposed through the opening. In one embodiment, the source / drain material grown on the opposite sidewalls of the second semiconductor material grows together to form a source / drain region, wherein an air gap is present between the source / drain region and the dielectric layer. In one embodiment, the method further comprises, after forming the opening and before converting, the end portions of the first semiconductor material exposed through the openingbe replaced by inner spacers. In one embodiment, after the selective deposition of the dielectric layer, an upper surface of the dielectric layer distal to the substrate is present between a lower surface and an upper surface of a lowermost inner spacer of the inner spacers. In one embodiment, the method further comprises performing an annealing process after the implantation process and before the selective deposition of the dielectric layer. In one embodiment, the fin comprises silicon, and the implantation process is performed using a gas source containing carbon, nitrogen, oxygen, or combinations thereof. In one embodiment, the dielectric layer is made of silicon oxide, silicon carbide,Silicon nitride or silicon carbonitride. In one embodiment, after the selective deposition of the dielectric layer, the seed layer at the bottom of the opening is covered with the dielectric layer, while the opposite sidewalls of the second semiconductor material exposed through the opening areare free of the dielectric layer. In one embodiment, a first lattice constant of the source / drain material matches a second lattice constant of the second semiconductor material. In one embodiment, the method further comprises: forming an interlayer dielectric (ILD) layer over the fin structure around the first dummy gate structure and the second dummy gate structure; and replacing the first dummy gate structure and the second dummy gate structure with a first replacement gate structure and a second replacement gate structure, respectively. One embodiment comprises replacing the first dummy gate structure and the second dummy gate structure comprising: removing the first and second dummy gate structures,to form openings in the ILD layer for exposing the first semiconductor material and the second semiconductor material beneath the first and second dummy gate structures; selectively removing the exposed first semiconductor material by using a first etching process, wherein after the first etching process, the exposed second semiconductor material remains and forms channel regions of the semiconductor device; forming a gate dielectric material around the channel regions; and forming a gate material around the gate dielectric material.

[0059] In one embodiment, a method of manufacturing a semiconductor device comprises: forming a fin structure over a substrate, the fin structure comprising a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming an opening in the fin structure adjacent to the dummy gate structure, wherein sidewalls of the opening expose first end portions of the first semiconductor material and expose second end portions of the second semiconductor material, and wherein a bottom surface of the opening exposes a top surface of the fin; replacing the first end portions of the first semiconductor material with internal spacers; and forming a source / drain region in the opening,comprising: selectively depositing a dielectric layer over the upper surface of the fin; and selectively growing a source / drain material on the second end portions of the second semiconductor material by using an epitaxial growth process, wherein after the epitaxial growth process, the source / drain material is spaced from the dielectric layer. In one embodiment, the method further comprises, prior to selectively depositing the dielectric layer, performing an implantation process to convert an upper layer of the fin into a seed layer, wherein the seed layer comprises the same material as the dielectric layer. In one embodiment, the method further comprises, after performing the implantation process, performing an annealing process. In one embodiment, the implantation process is performed using a gas source containing carbon, nitrogen,Oxygen or combinations thereof, wherein the dielectric layer contains silicon oxide, silicon carbide, silicon nitride, or silicon carbonitride. In one embodiment, the source / drain material grown on the opposite sidewalls of the second semiconductor material converges to form the source / drain region, with an air gap between the source / drain region and the dielectric layer.

[0060] In one embodiment, a semiconductor device comprises: a fin protruding above a substrate; a first gate structure above the fin; a second gate structure above the fin; a source / drain region above the fin between the first gate structure and the second gate structure, wherein an air gap exists between the source / drain region and the fin; and first channel layers below the first gate structure and second channel layers below the second gate structure, wherein the source / drain region extends continuously from the first channel layers to the second channel layers. In one embodiment, the first channel layers and the second channel layers are nanosheets or nanowires. In one embodiment, a top surface of the air gap distal from the substrate is closer to the substrate than a bottom surface of a lowest channel layer of the first channel layers facing the substrate.In one embodiment, the semiconductor device further comprises a dielectric layer between the first gate structure and the second gate structure, the dielectric layer being present on a top surface of the fin, the air gap being between the source / drain region and the dielectric layer.

Claims

[1] A method (1000) for producing a semiconductor device, comprising: Forming a fin structure (91) protruding above a substrate (50), the fin structure (91) comprising a fin (90) and a layer stack (92) above the fin (90), the layer stack (92) comprising alternating layers of a first semiconductor material (52) and a second semiconductor material (54); forming a first dummy gate structure and a second dummy gate structure over the fin structure (91); Forming an opening (110) in the fin structure (91) between the first dummy gate structure and the second dummy gate structure; Converting an upper layer of the fin (90) exposed at the bottom of the opening (110) into a seed layer (111) by performing an implantation process; selectively depositing a dielectric layer (113) over the seed layer (111) at the bottom of the opening (110); and selectively growing a source / drain material (112) on the opposite sidewalls of the second semiconductor material (54) exposed through the opening (110). [2] The method (1000) of claim 1, wherein the source / drain material (112) grown on the opposite sidewalls of the second semiconductor material (54) converges to form a source / drain region (112), wherein an air gap (115) is present between the source / drain region (112) and the dielectric layer (113). [3] The method (1000) of claim 1 or 2, further comprising: after forming the opening (110) and before converting, replacing end portions of the first semiconductor material (52) exposed through the opening (110) with inner spacers (55, 55A). [4] The method (1000) of claim 3, wherein after selectively depositing the dielectric layer (113), an upper surface of the dielectric layer (113) distal from the substrate (50) lies between a lower surface and an upper surface of a lowermost inner spacer (55, 55A) of the inner spacers (55, 55A). [5] Method (1000) according to one of the preceding claims, further comprising: after the implantation process and before the selective deposition of the dielectric layer (113), carrying out an annealing process. [6] The method (1000) of any preceding claim, wherein the fin (90) comprises silicon and the implantation process is performed using a gas source comprising carbon, nitrogen, oxygen, or combinations thereof. [7] Method (1000) according to one of the preceding claims, wherein the dielectric layer (113) is formed from silicon oxide, silicon carbide, silicon nitride or silicon carbonitride. [8] The method (1000) of any preceding claim, wherein, after selectively depositing the dielectric layer (113), the seed layer (111) at the bottom of the opening (110) is covered with the dielectric layer (113), while the opposite sidewalls of the second semiconductor material (54) exposed through the opening (110) are free of the dielectric layer (113). [9] The method (1000) of claim 8, wherein a first lattice constant of the source / drain material (112) matches a second lattice constant of the second semiconductor material (54). [10] The method (1000) according to any one of the preceding claims, further comprising: Forming an intermediate dielectric layer, ILD layer, over the fin structure (91) around the first dummy gate structure and the second dummy gate structure; and Replacing the first dummy gate structure and the second dummy gate structure with a first replacement gate structure and a second replacement gate structure. [11] The method (1000) of claim 10, wherein replacing the first dummy gate structure and the second dummy gate structure comprises: Removing the first dummy gate structure and the second dummy gate structure to form openings (110) in the ILD layer to expose the first semiconductor material (52) and the second semiconductor material (54) beneath the first dummy gate structure and the second dummy gate structure; selectively removing the exposed first semiconductor material (52) using a first etching process, wherein the exposed second semiconductor material (54) remains after the first etching process and forms channel regions (93) of the semiconductor device; forming a dielectric gate material around the channel regions (93); and Forming a gate material around the gate dielectric (97). [12] A method (1000) for producing a semiconductor device, comprising: Forming a fin structure (91) over a substrate (50), the fin structure (91) comprising a fin (90) and a layer stack (92) over the fin (90), the layer stack (92) comprising alternating layers of a first semiconductor material (52) and a second semiconductor material (54); forming a dummy gate structure over the fin structure (91); Forming an opening (110) in the fin structure (91) adjacent to the dummy gate structure, wherein the sidewalls of the opening (110) expose first end portions of the first semiconductor material (52) and expose second end portions of the second semiconductor material (54), and wherein a bottom surface of the opening (110) exposes a top surface of the fin (90); Replacing the first end portions of the first semiconductor material (52) with inner spacers (55, 55A); and Forming a source / drain region (112) in the opening (110), comprising: - performing an implantation process to convert an upper layer of the fin (90) into a seed layer (111), - selectively depositing a dielectric layer (113) onto the seed layer (111); and - selectively growing a source / drain material (112) on the second end portions of the second semiconductor material (54) by using an epitaxial growth process, wherein after the epitaxial growth process the source / drain material (112) is spaced from the dielectric layer (113). [13] The method (1000) of claim 12, further comprising: prior to the selective deposition of the dielectric layer (113), wherein the seed layer contains a same material as the dielectric layer (113). [14] The method (1000) of claim 13, further comprising: after performing the implantation procedure, performing an annealing procedure. [15] The method (1000) of claim 13, wherein the implantation process is performed using a gas source containing carbon, nitrogen, oxygen, or combinations thereof, wherein the dielectric layer (113) contains silicon oxide, silicon carbide, silicon nitride, or silicon carbonitride. [16] The method (1000) of any one of claims 12 to 15, wherein the source / drain material (112) grown on the opposite sidewalls of the second semiconductor material (54) converges to form the source / drain region (112), an air gap (115) being present between the source / drain region (112) and the dielectric layer (113). [17] The method (1000) of any one of claims 12 to 16, wherein after removing the first semiconductor material (52), the second semiconductor material (54) forms a plurality of nanostructures (54) extending horizontally. [18] The method (1000) of claim 17, wherein the nanostructures (54) are nanosheets or nanowires. [19] The method (1000) of any one of claims 12 to 18, wherein the first semiconductor material (52) is removed by a selective etching process using an etchant selective for the first semiconductor material (52) such that the first semiconductor material (52) is removed without substantially attacking the second semiconductor material (54). [20] The method (1000) of any one of claims 12 to 19, wherein an isotropic etching process is performed to remove the first semiconductor material (52).

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