RING-SHAPED BIPOLAR TRANSISTORS

Abstract

Structure comprehensive: a substrate material (12); a collector region (16) parallel to and above the substrate material (12); an intrinsic base region (32) surrounding the collector region (16); an emitter region (42) above the intrinsic base region (32); an extrinsic base region (38) contacting the intrinsic base region (32); and Collector contact regions (24) connected to ends of the collector region (16).

Description

BACKGROUND

[0001] The present disclosure relates to semiconductor structures and, more particularly, to ring-shaped bipolar transistors and fabrication methods.

[0002] Bipolar transistors can be vertical or lateral transistors. In a vertical bipolar transistor, carriers flow in a vertical direction. Since a collector region is formed at a position deep from a wafer surface, the collector resistance increases, thus limiting the transistor performance, especially for high-speed operation. Additionally, the transistor requires a high-concentration buried layer, an epitaxial collector layer, and deep trench isolation. Consequently, the number of process steps increases, and so does the cost. On the other hand, the lateral bipolar transistor is simpler in construction than the vertical bipolar transistor. Also, in a lateral bipolar transistor, a collector electrode can be brought into direct contact with a collector region, which is advantageous for high-speed operation.

[0003] US Pat. No. 5,510,647 A discloses a silicon bipolar transistor in which the collector is arranged above the base and the emitter. Furthermore, US Pat. No. 9,887,278 B2 discloses a lateral heterojunction bipolar transistor in which the emitter and collector are arranged laterally to the base. Furthermore, US Pat. No. 2010 / 0 022 056 A1 discloses a bipolar transistor having a collector, a base located above it, an emitter located above the base, and field plates arranged laterally. BRIEF SUMMARY

[0004] In one aspect of the disclosure, a structure comprises: a substrate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; an extrinsic base region contacting the intrinsic base region; and collector contact regions connected to ends of the collector region.

[0005] In one aspect of the disclosure, a structure comprises: a collector region comprising a first semiconductor material and extending parallel to a surface of an underlying substrate; an intrinsic base region comprising a second semiconductor material and extending around the collector region; an extrinsic base region contacting the intrinsic base region and extending vertically upward from the underlying substrate; and an emitter region contacting the intrinsic base region and extending vertically upward from the underlying substrate.

[0006] In one aspect of the disclosure, a method comprises: forming a collector region parallel to and above a substrate material; forming an intrinsic base region surrounding the collector region; forming an emitter region above the intrinsic base region; forming an extrinsic base region contacting the intrinsic base region; and forming collector contact regions connected to ends of the collector region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is described in the following detailed description with reference to the aforementioned plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. Fig. 1 shows a starting substrate, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 2 shows dummy (sacrificial) material with sidewall spacers over an epitaxial material, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 3 shows a structured stack of materials, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 4 shows collector regions, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 5 shows an elongated collector region, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 6 shows an intrinsic base region around the elongated collector region, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 7 shows trenches exposing the intrinsic base region around the elongated collector region, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 8 shows an extrinsic base region around the intrinsic base region, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 9 illustrates an emitter region, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 10 shows contacts, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 11 shows an alternative bipolar transistor layout and respective manufacturing processes according to aspects of the present disclosure. Fig. 12 shows a three-dimensional view of the bipolar transistor of Fig. 10. DETAILED DESCRIPTION

[0008] The present disclosure relates to semiconductor structures, and more particularly, to ring-shaped bipolar transistors and fabrication methods. More specifically, the present disclosure relates to high-performance ring-shaped bipolar transistors optimized for high Ft / Fmax and beta. Advantageously, the ring-shaped bipolar transistors are applicable in high-voltage RF device applications with low parasitic base / collector / emitter contact and improved current spreading due to their ring-shaped shape.

[0009] In more specific embodiments, the ring-shaped bipolar transistors comprise an ultra-narrow base (Wb) comprising SiGe material. For example, Wb can be between about 1 nm to 15 nm, with a target Wb of about 10 nm to 15 nm. In embodiments, the ring-shaped bipolar transistors comprise a sheet of Si material acting as a collector region (e.g., elongated collector) and an intrinsic base epitaxially grown around the collector region. The intrinsic base comprises a SiGe heterojunction. An emitter region can be epitaxially grown around the intrinsic base, with spacers separating the contact points of the collector, emitter, and base regions. In embodiments, the ring-shaped bipolar transistors can also operate within a fin platform. Furthermore, the ring-shaped bipolar transistors can be integrated within a BiCMOS integration scheme.

[0010] The ring-shaped bipolar transistors of the present disclosure can be fabricated in several ways using several different tools. Generally, however, the methodologies and tools used to form structures with dimensions on the micrometer and nanometer scale are used. The methodologies, i.e., technologies, used to fabricate the ring-shaped bipolar transistors of the present disclosure were adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in material films patterned on top of a wafer using photolithographic processes.Specifically, the fabrication of ring-shaped bipolar transistors uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) application of a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively with respect to the mask. Additionally, pre-cleaning processes can be used to clean etched surfaces of any contaminants, as is known in the art. Furthermore, if necessary, a rapid thermal anneal process can be used to drive in dopants or material layers, as is known in the art.

[0011] Fig. 1 shows a starting substrate according to aspects of the present disclosure. In particular, the structure 10 of Fig. 1, a substrate 12 comprising any suitable semiconductor material, including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The substrate 12 may also be a P+ substrate. The substrate 12 may comprise any suitable crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). In embodiments, the substrate 12 may be a bulk substrate or a semiconductor-on-insulator (SOI) substrate.

[0012] Semiconductor material 14, 16, 18 may be formed on the substrate 12. In embodiments, the semiconductor materials 14, 18 may be the same material, with the semiconductor material 16 being a different material. Furthermore, the semiconductor materials 14, 18 may be different materials than the substrate 12. In this way, selective etching processes may be performed to remove the semiconductor materials 14, 18 during subsequent manufacturing processes. In more specific embodiments, the semiconductor materials 14, 18 may be SiGe material, and the semiconductor material 16 may be Si material. The semiconductor material 16 may be parallel to a top surface of the substrate 12 and may be used as a collector region of the bipolar transistor.

[0013] In embodiments, the semiconductor materials 14, 16, 18 may be epitaxially grown on the substrate 12 using epitaxial processes, as is known in the art, so no further explanation is required for a complete understanding of the present disclosure. Also, the epitaxial growth process of the semiconductor material 16 may include in-situ doping using an n-type dopant, e.g., arsenic, phosphorus, Sb, etc. The dopants may be driven in by a rapid thermal annealing process, as is known in the art. The semiconductor material 16 may have a thickness of about 10 nm to about 25 nm.

[0014] As further stated in Fig. 2, a sacrificial material 20 may be formed over the semiconductor material 18. In embodiments, the sacrificial material 20 may be, for example, a polysilicon material. The sacrificial material 20 may be formed by a conventional deposition process, e.g., chemical vapor deposition (CVD), followed by a patterning process using conventional lithography and etching processes, as further described herein. Sidewall spacers 22 may be formed on sidewalls of the patterned sacrificial material 20. In embodiments, the sidewall spacers 22 may comprise oxide and nitride deposited using a blanket deposition process, e.g., CVD, followed by an anisotropic etching process.

[0015] In Fig. 3, the semiconductor materials 14, 16, 18 may be patterned to form a stack of materials 15 beneath the sacrificial material 20. The patterning may be conventional lithography and etching processes, e.g., a self-aligned double patterning process (SADP). For example, a resist formed over the semiconductor material 18 is exposed to energy (light) to form a structure (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), is used to form the structure, e.g., the stack of materials 15, through the openings of the resist. The resist may be removed by a conventional oxygen ashing process or other known stripping means. In optional embodiments, the etching process may include an overetch to provide a recess or overhang 21 beneath the sidewall spacers 22.

[0016] In Fig. 4, a semiconductor material 24 may be formed over the substrate 12 and in contact with the stack of materials 15, and in particular in contact with the semiconductor material 16 (e.g., the collector region). The semiconductor material 24 may form collector regions (which contact the collector region (e.g., the semiconductor material 16) of the bipolar transistor).

[0017] In more specific embodiments, the semiconductor material 24 may be Si material with a gradient concentration of n-doping. For example, the concentration of an n-type dopant may include a lower concentration (N-) of dopant adjacent to the substrate 12 and the stack of materials 15, compared to a higher concentration (N+) in remaining locations. The semiconductor material 24 may also be n-doped polysilicon material. In both concepts, the semiconductor material 24 may be doped in-situ with the n-type dopant, e.g., arsenic, phosphorus, etc., to form the N+ and N- concentrations. In embodiments, the epitaxial semiconductor material 24 may be grown from the substrate 12 to the sides of the sidewall spacers 22.

[0018] As further stated in Fig. 5, an interlevel dielectric material 26 may be formed over the collector region, e.g., an epitaxial semiconductor material 24. In embodiments, the interlevel dielectric material 26 may be a combination of nitride and oxide material deposited by a CVD process. Following the deposition process, the interlevel dielectric material 26 may be planarized by chemical mechanical polishing (CMP) to expose the sacrificial material 20. The sacrificial material 20 may then be pulled out (e.g., removed) using etchants that are selective with respect to the material of the sacrificial material, e.g., selective with respect to a polysilicon material. This results in a trench 28 between the sidewall spacers 22.

[0019] The semiconductor materials 14, 18 may also be removed by a selective etching process to expose the collector region, leaving, for example, the semiconductor material 16 intact between the collector regions 24. For example, the selective etching process uses an etch chemistry that is selective with respect to SiGe and that does not attack the semiconductor material 16 or the material of the substrate 12. The removal of the semiconductor material 14 may leave a space 30 beneath the semiconductor material 16, for example, between the substrate 12 and the semiconductor material 16. This results in the semiconductor material 16 being a floating sheet with an elongated shape, for example, a nanowire, a nanosheet, cylindrical, annular, etc., comprising a thickness of about 10 nm to about 25 nm, parallel to the surface of the substrate 12.

[0020] In Fig. 6, a semiconductor material 32 may be formed around the exposed semiconductor material 16. In embodiments, the semiconductor material 32 may be an intrinsic base region of the bipolar transistor. Also, in embodiments, the intrinsic base region extends parallel to a surface of the substrate 12, with the intrinsic base region surrounding the collector region along its longitudinal axis.

[0021] The semiconductor material 32 may be epitaxially grown around the exposed semiconductor material 16. Furthermore, the semiconductor material 32 may be a SiGe material formed by an epitaxial growth process with in-situ doping using a p-type dopant, e.g., boron. In embodiments, the SiGe material may have a gradient profile of a Ge material, with a higher concentration of Ge adjacent to the exposed semiconductor material 16. Also, because the semiconductor material 24 has a graded n-type doping concentration, the N-type doping adjacent to the SiGe material prevents leakage and lowers the collector-to-base breakdown.

[0022] Fig. 7 shows an interlevel dielectric material 34 within the trench 28 (opening). In embodiments, the interlevel dielectric material 34 may be, for example, a nitride material or oxide / nitride. The interlevel dielectric material 34 may be deposited within the trench 28 (opening) by a conventional deposition process, e.g., CVD, followed by a planarization process. The interlevel dielectric material 34 may be partially removed, e.g., etched, to form trenches 36 adjacent to the sidewall spacers 22. The interlevel dielectric material 34 may be removed by a lithography and etching process, as known to those skilled in the art. In this way, the semiconductor material 32 and the substrate 12 may be exposed.

[0023] In Fig. 8, semiconductor material 38 may be formed within the trenches 36. As should be apparent to those skilled in the art, the semiconductor material 38 may be the extrinsic base region (extending vertically upward above the substrate 12) of the bipolar transistor, located around the intrinsic base region and collector region. In embodiments, the semiconductor material 38 may be in contact with the substrate 12 and the semiconductor material 32, e.g., intrinsic base region. In particular, the semiconductor material 38 may extend completely around the semiconductor material 32, e.g., intrinsic base region, and the semiconductor material 16, e.g., collector region. The semiconductor material 38 may be epitaxially grown on the semiconductor material 32 and the substrate 12 using an in-situ doping process, e.g., a p-type dopant such as boron. In embodiments, the semiconductor material 38 may be SiGe material, Si material, or polysilicon material.

[0024] In Fig. 9, an additional interlevel dielectric material 40 may be formed over the semiconductor material 38 and the interlevel dielectric materials 34, 26. In embodiments, the interlevel dielectric material 40 may be a nitride or oxide / nitride material deposited by a conventional deposition process, e.g., CVD. A trench may be formed within the interlevel dielectric materials 34, 40 by removing such material to expose the semiconductor material 32 and the substrate 12. An epitaxial semiconductor material 42 may be formed within the trench to contact the exposed semiconductor material 32. In embodiments, the semiconductor material 38 may be a Si material epitaxially grown using an in-situ doping process, e.g., an n-type dopant such as arsenic.It is noted that semiconductor material 42 is isolated from semiconductor material 38 by interlevel dielectric material 34. And, as should be apparent to those skilled in the art, semiconductor material 42 may be the emitter region of the bipolar transistor (extending vertically upward above substrate 12) extending above semiconductor material 38, e.g., extrinsic base region.

[0025] Referring to Fig. 10, contacts 46 can be made to the collector region, e.g. semiconductor material 24, extrinsic base region, e.g. semiconductor material 38 (in Fig. 10) and the emitter region, e.g. semiconductor material 42. In particular, Fig. 10, to form the contacts 46, vias are formed in interlevel dielectric material (e.g., stacks of materials 34, 40, 26) to expose surfaces of the semiconductor materials 24, 38, 42. A silicide process may be performed on the exposed semiconductor materials 24, 38, 42 to form silicide contacts 44. As should be apparent to those skilled in the art, the silicide process begins with a deposition of a thin transition metal layer, e.g., nickel, cobalt, or titanium, over the semiconductor materials 24, 38, 42. After deposition of the material, the structure is heated, allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein), thereby forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 44.

[0026] Conductive material can then be deposited within the vias, over the silicide contacts 44, to form the contacts 46. The conductive material can be tungsten or aluminum, which can also include barrier liner material. Any excess conductive material at the surface of the interlevel dielectric material 34 can be removed using a conventional CMP process.

[0027] Fig. 11 shows an alternative layout of the bipolar transistor according to aspects of the present disclosure. In this layout 10a, an insulator material 48 is completely beneath the semiconductor material 38, e.g., intrinsic base region. In particular, the insulator material 48 is between the semiconductor material 38, e.g., intrinsic base region, and the substrate 12. In this way, the insulator material 48 insulates the extrinsic base region 38 and the emitter region 42 from the substrate 12. Furthermore, the insulator material 48 may provide additional support for the semiconductor material 38, e.g., intrinsic base region. Additionally, in this configuration, there is no junction between the semiconductor material 38, e.g., intrinsic base region, and the substrate 12.

[0028] Fig. 12 is a three-dimensional view of the bipolar transistor of Fig.8, as an example. As shown in this illustration, the contacts 44a for the emitter region 42 and the collector region 24 are in alignment; whereas the contacts 44b for the extrinsic base region 38 are offset from the contacts 44a of the emitter region 42 and the collector region 44.

[0029] The transistors can be used in a system-on-chip (SoC) technology. The SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, SoCs consume much less power and take up much less space than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant force in the mobile computing (such as smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0030] The process(es) described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., a single wafer containing multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier, with conductors attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier containing one or both surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that include a display, a keyboard or other input device, and a central processor.

Claims

[1] Structure comprising: a substrate material (12); a collector region (16) parallel to and above the substrate material (12); an intrinsic base region (32) surrounding the collector region (16); an emitter region (42) above the intrinsic base region (32); an extrinsic base region (38) contacting the intrinsic base region (32); and Collector contact regions (24) connected to ends of the collector region (16). [2] The structure of claim 1, wherein the collector region (16) comprises an elongated shape, a nanowire, a nanosheet, an annular or a cylindrical shape. [3] The structure of claim 1 or 2, wherein the collector region (16) and the intrinsic base region (32) extend parallel to a surface of the substrate material (12) and the intrinsic base region (32) surrounds the collector region (16) along an elongated axis. [4] The structure of claim 3, wherein the emitter region (42) surrounds the intrinsic base region (32), the extrinsic base region (38) surrounds the intrinsic base region (32), and both the emitter region (42) and the extrinsic base region (38) contact the substrate material (12). [5] The structure of claim 4, further comprising insulator material (22, 26) separating the extrinsic base region (38) from the collector contact region (24) on sides of the collector region (16) and further separating the extrinsic base region (38) from the emitter region (42). [6] The structure of claim 5, wherein the emitter region (42) and the extrinsic base region (38) extend vertically upward from the substrate material (12). [7] The structure of any one of claims 1 to 3, further comprising insulator material (48) separating the substrate material (12) from the collector region (16), the intrinsic base region (32), the extrinsic base region (38) and the emitter region (42). [8] The structure of any one of claims 1 to 7, wherein the intrinsic base region (32) comprises SiGe material and the collector region (16) comprises Si material. [9] Structure comprising: a collector region (16) comprising a first semiconductor material and extending parallel to a surface of an underlying substrate (12); an intrinsic base region (32) comprising a second semiconductor material and extending around the collector region (16); an extrinsic base region (38) contacting the intrinsic base region (32) and extending vertically upward from the underlying substrate (12); and an emitter region (42) contacting the intrinsic base region (32) and extending vertically upward from the underlying substrate (12). [10] The structure of claim 9, wherein the extrinsic base region (38) and the emitter region (42) are separated by insulator material (26). [11] The structure of claim 9 or 10, further comprising a collector contact region (24) contacting ends of the collector region (16) and separated from the extrinsic base region (38) by sidewall spacers (22). [12] The structure of any one of claims 9 to 11, wherein the first semiconductor material comprises Si material and the second semiconductor material comprises SiGe material. [13] The structure of claim 12, wherein the SiGe material comprises a graded concentration of Ge material. [14] The structure of claim 13, wherein the collector region (16) comprises a dopant concentration gradient. [15] The structure of any one of claims 9 to 14, wherein the intrinsic base region (32) surrounds the collector region (16) along an elongated axis of the collector region (16). [16] The structure of any one of claims 9 to 15, wherein the extrinsic base region (38) and the emitter region (42) surround the intrinsic base region (32). [17] The structure of any one of claims 9 to 16, wherein the extrinsic base region (38) and the emitter region (42) both contact the underlying substrate material (12). [18] The structure of any one of claims 9 to 15, wherein the extrinsic base region (38) and the emitter region (42) are separated from the underlying substrate material (12) by an insulator material (48). [19] Procedure comprising: Forming a collector region (16) parallel to and above a substrate material (12); Forming an intrinsic base region (32) surrounding the collector region (16); Forming an emitter region (42) over the intrinsic base region (32); Forming an extrinsic base region (38) which contacts the intrinsic base region (32); and Forming collector contact regions (24) connected to ends of the collector region (16).

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