Monolithic integration of various device types with split electrical insulation

Abstract

Structure, including: a substrate (10) having a device layer (12), a handling substrate (16) and a buried insulator layer (14) between the handling substrate (16) and the device layer (12); a first semiconductor layer (20) on the device layer (12) in a first device region (22), the first semiconductor layer (20) being formed of a III-V compound semiconductor material; a second semiconductor layer (28) on the device layer (12) in a second device region (30), the second semiconductor layer (28) being formed of silicon; a first device structure (38) having a gate structure (34) on the first semiconductor layer (20); and a second device structure (40) having a doped region (42) in the second semiconductor layer (28), wherein the doped region (42) and the second semiconductor layer (28) form a pn junction.

Description

BackgroundThe present invention relates to the fabrication of semiconductor devices and integrated circuits, and more particularly to structures having III-V compound semiconductor based devices and silicon based devices integrated on a semiconductor substrate, and methods of forming such structures.High voltage power electronic devices such as high electron mobility transistors may be fabricated using III-V compound semiconductors to take advantage of their material properties, such as charge carrier mobility greater than that of silicon and a band gap greater than that of silicon. III-V compound semiconductors contain Group III elements (aluminum, gallium, indium) and Group V elements (nitrogen, phosphorus, arsenic, antimony) in combination with the Group III elements. A common III-V compound semiconductor used as a base material for device construction is gallium nitride. A high electron mobility transistor may include a heterojunction between crystalline III-V compound semiconductor materials having different band gaps, e.g., a heterojunction between binary gallium nitride and trinar aluminum gallium nitride. In operation, a two-dimensional electron gas forms near an interface at the heterojunction defining the channel of the high electron mobility transistor.Integration of high electron mobility transistors with silicon-based thyristors such as field effect transistors or heterojunction bipolar transistors on the same chip has proved difficult. Integration may be achieved by wafer bonding or by using hybrid substrates with portions of different crystalline orientation, which naturally makes the processes for integrating high electron mobility transistors very complex with these other transistor types.Improved structures including III-V compound semiconductor devices and silicon-based devices integrated on a semiconductor substrate and methods of making such structures are required.US 2012 / 0 305 992 A1 relates to a hybrid integrated circuit comprising both CMOS and III-V components which are monolithically integrated in a single chip. The circuit comprises a silicon substrate having a (100) orientation; at least one first semiconductor region formed in the silicon substrate having a (100) orientation; at least one CMOS integrated circuit formed in at least one of the first semiconductor regions; at least one second semiconductor region comprising at least one compound semiconductor material; at least one semiconductor device formed in at least one of the second semiconductor regions; wherein at least one of the second semiconductor regions is formed after the high temperature process steps of the CMOS integrated circuit have been performed.SummaryIn an embodiment of the invention, a structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer is formed of a III-V compound semiconductor material and the second semiconductor layer is formed of silicon. A first device structure includes a gate structure on the first semiconductor layer and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer form a pn junction.In an embodiment of the invention, a structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a semiconductor layer on the device layer in a first device region, a first device structure having a gate structure on the semiconductor layer, and a second device structure having a doped region in a second device region of the device layer. The device layer is formed of single crystal silicon having <111> crystal orientation, and the semiconductor layer is formed of a III-V compound semiconductor material. The doped region and the device layer define a pn junction.In an embodiment of the invention, a method includes providing a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer, forming a first semiconductor layer on a first device region of the device layer, and forming a second semiconductor layer on a second device region of the device layer. The first semiconductor layer is formed of a III-V compound semiconductor material and the second semiconductor layer is formed of silicon. The method further includes forming a first device structure having a gate structure on the first semiconductor layer and forming a second device structure having a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a pn junction.Brief Description of the DrawingsThe accompanying drawings, which form a part of this specification, illustrate various embodiments of the invention and together with the general description of the invention above and the detailed description of the embodiments of the invention below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features throughout the several views. FIG. 1 is a cross-sectional view of a structure at an initial fabrication stage according to embodiments of the invention. FIG. 2 is a cross-sectional view of the structure at a subsequent stage of fabrication to FIG. 1. FIG. 3 is a cross-sectional view of a structure according to alternative embodiments of the invention. FIGS. 4 and 5 are cross-sectional views of structures according to alternative embodiments of the invention. FIG. 6 is a cross-sectional view of a structure according to alternative embodiments of the invention. FIG. 7 is a cross-sectional view of a structure according to alternative embodiments of the invention. FIG. 8 is a cross-sectional view of the structure at a subsequent stage of fabrication to FIG. 7. Figure 9 is a cross-sectional view of a structure according to alternative embodiments of the invention. FIG. 10 is a cross-sectional view of the structure at a subsequent stage of fabrication to FIG. 9.Detailed DescriptionReferring to FIG. 1, and in accordance with embodiments of the invention, a substrate 10 is provided that includes a substrate stack that includes a device layer 12, a buried insulator layer 14, and a handle substrate 16. The device layer 12 is separated from the handle substrate 16 by the buried insulator layer 14 therebetween. The device layer 12 has a top surface 18, which may be planar. Buried insulator layer 14 may be formed of a buried oxide (BOX) layer comprising a layer of a solid dielectric material such as silicon dioxide.The device layer 12 and the handle substrate 16 may include a semiconductor material such as single crystal silicon. In an embodiment, the single crystal semiconductor material of device layer 12 may have a diamond crystal lattice structure with <111> crystal orientation according to Miller indices. In one embodiment, the substrate 10 may comprise single crystal silicon having a diamond crystal lattice structure with <111> crystal orientation. In a device layer 12 having a <111> crystal orientation, the (111) crystal plane is parallel to the top surface 18 of the device layer 12. The (100) crystallographic axes are not in the plane of the top surface 18.A layer stack 20 is formed on the device layer 12 in a device region 22, and a semiconductor layer 28 is formed on the device layer 12 in a device region 30. A trench isolation region 32 is formed that cooperates with buried insulator layer 14 to electrically isolate device region 22 from device region 30.The layer stack 20 comprises semiconductor layers such as a buffer layer 24 and a barrier layer 26, each comprising one or more compound semiconductor layers. The buffer layer 24 and the barrier layer 26 may be serially deposited with an epitaxial process such as metal organic chemical vapor deposition, vapor phase epitaxy, or molecular beam epitaxy to form the layer stack. Prior to forming the layer stack 20, a thin nucleation layer, e.g., of aluminum nitride, may be formed on the device layer 12. The device layer 12 serves as a seed for epitaxial growth. In an embodiment, the layer stack 20 may be epitaxially grown in both device regions 22, 30 and removed from the device region 30 by etching, wherein the layer stack 20 in the device region 22 is covered and protected by a dielectric layer.The buffer layer 24 and the barrier layer 26 may each have a single crystal structure or alternatively a substantially single crystal structure with different degrees of crystalline defects. The buffer layer 24 may comprise a binary III-V compound semiconductor material such as gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination of these materials tailored in material composition, doping, and / or layer thickness to accommodate lattice mismatches, thermal property differences, and mechanical property differences between the material of the substrate 10 and the material of a channel layer atop the buffer layer. The barrier layer 26 disposed over the buffer layer 24 may comprise a ternary III-V compound semiconductor such as aluminum gallium nitride having 15 to 35 atomic percent aluminum, which forms a heterogeneous interface with the buffer layer 24 of different composition. The buffer layer 24 may include an undoped layer of a III-V compound semiconductor (e.g., undoped gallium nitride) immediately adjacent to the barrier layer 26.In an embodiment, the semiconductor layer 28 may be formed by a selective epitaxial growth (SEG) process in which the semiconductor material for epitaxial growth is seeded from the exposed surface of the device layer 12. The layer stack 20 in the device region 22 may be covered and protected with a dielectric layer, e.g. a layer of silicon nitride, preventing epitaxial growth. In one embodiment, the portion of device layer 12 in device region 30 may be doped to have an n-type conductivity prior to forming semiconductor layer 28.The semiconductor layer 28 may be formed of a single crystalline semiconductor material, e.g., single crystalline silicon, and may be in situ doped with an electrically active dopant, e.g., an n-type dopant (e.g., phosphorus or arsenic) during epitaxial growth. In an alternative embodiment, the semiconductor layer 28 may be non-selectively grown followed by planarization via chemical mechanical polishing, which includes removal from the device region 22.The trench isolation region 32, which may be formed at the junction between the layer stack 20 and the semiconductor layer 28, may extend through the device layer 12 and into the buried insulator layer 14. The trench isolation region 32 may comprise a dielectric material that has been introduced, polished and devitrified into an etched trench by chemical vapor deposition. The dielectric material formed in the trench isolation region 32 may include silicon dioxide.The layer stack 20 in the device region 22 has a top surface 21 and the semiconductor layer 28 in the device region 30 has a top surface 27. In an embodiment, the top surface 21 of the layer stack 20 may be coplanar with the top surface 27 of the semiconductor layer 28. In an embodiment, the top surface 21 of the layer stack 20 may be substantially coplanar with the top surface 27 of the semiconductor layer 28. In an embodiment, the top surface 21 of the layer stack 20 and the top surface 27 of the semiconductor layer 28 may differ in height by about 100 nanometers (nm) to about 500 nm, which may be considered substantially coplanar.Referring to FIG. 2, wherein like reference numerals refer to like features in FIG. 1, at a subsequent fabrication stage, a device structure 40 may be formed in the device region 30. In one embodiment, device structure 40 may be a Schottky diode that includes a doped region 42, a silicide layer 44 that forms a Schottky contact with doped region 42 that defines an anode, a doped region 46 that defines a cathode, and a doped region 48 that forms a guard ring that surrounds doped region 42. The silicide layer 44 may be formed by a silicide process, the doped regions 42, 46 may be formed in the semiconductor layer 28 by a masked implant, and the doped region 48 may be formed in the semiconductor layer 28 by a separate masked implant. The doped region 46 may have the same conductivity type as the semiconductor layer 28 and may include a higher doping concentration than the semiconductor layer 28. Doped region 42 is doped to have a conductivity type opposite semiconductor layer 28 to form a pn junction 43, and doped region 48 is also doped to have a conductivity type opposite semiconductor layer 28 to form a pn junction 47. For example, the doped regions 42, 48 may be doped to have a p-type conductivity when the semiconductor layer 28 has an n-type conductivity.A device structure 38 is formed in the device region 22. The semiconductor layer 28 may be covered and protected by a dielectric layer during the formation of the device structure 38. In an embodiment, the device structure 38 may be a high-electron-mobility transistor (HEMT) in enhancement mode. In an embodiment, the device structure 38 may include a gate structure 34 on the layer stack 20. The gate structure 34 may include a gate 36 in contact with the barrier layer 26 and a gate metal layer 37 disposed on and over the gate 36. The gate 36 may be formed of a doped III-V compound semiconductor, such as p-type gallium nitride or p-type aluminum gallium nitride doped with magnesium, and the gate metal layer 37 may be formed of one or more metals, such as aluminum copper, titanium nitride, titanium, etc. In one embodiment, the gate 36 may be formed by patterning a layer of the doped III-V compound semiconductor epitaxially grown either before or after the formation of the semiconductor layer 28 on the layer stack 20.In the representative embodiment, the gate 36 is disposed on the barrier layer 26 at the top surface 21 of the layer stack 20. In an alternative embodiment, the barrier layer 26 below the gate 36 may be reduced in thickness, optionally with an insulator layer (e.g., a silicon nitride layer) deposited between the gate 36 and the thinned barrier layer 26. In one embodiment, device structure 38 may be operated in enhancement mode (E-mode) by adjusting the threshold voltage such that device structure 38 is turned off when gate 36 is not biased. In one embodiment, the device structure 38 may be operated in depletion mode (D-mode) by adjusting the threshold voltage such that the device structure 38 is turned off by applying a negative voltage to the gate 36. In an alternative embodiment, a mixture of E-mode device structures 38 and D-mode device structures 38 may be integrated into device region 22. In an alternative embodiment, passive device structures, such as Schottky diodes, may be integrated into device region 22.The middle-of-line processing and the back-end-of-line processing follow, which includes the formation of contacts, vias, and wirings for a connection structure disposed over the substrate 10 and connected to the device structures 38, 40.The buried insulator layer 14 electrically isolates both the device structure 38 and the device structure 40 from the handle substrate 16. The device structure 38 and the device structure 40 are formed on the same device layer 12, wherein the layer stack 20 is formed on the device layer 12 in the device region 22 and the semiconductor layer 28 is also formed on the device layer 12 in the device region 30. The use of the device layer 12 with only a <111> crystal orientation enables integration of the device structures 38, 40 without a complex manufacturing process, such as wafer bonding, or the use of a technical or hybrid substrate (e.g., an SOI substrate with one or more crystal orientations for the device layer).Monolithic co-integration of the device structures 38, 40 on the same device layer 12 may enable both low cost construction and high performance devices with improved operating parameters. A Schottky diode as a cointegrated device structure 40 may have a small forward voltage drop and a small stored charge, as compared with a Schottky diode formed of a III-V compound semiconductor material such as gallium nitride. The parametric improvements resulting from the smaller band gap of silicon compared to gallium nitride may result in lower power dissipation and higher operational reliability.In an alternative embodiment, the device structure 40 formed using the semiconductor layer 28 may be a barrier layer diode that has little leakage as a result of its formation using the semiconductor layer 28. In an alternative embodiment, the device structure 40 formed using the semiconductor layer 28 may be a transition bipolar transistor or a heterojunction bipolar transistor having a vertical or lateral collector, emitter and base arrangement and having a base doped to have either a p-type conductivity or an n-type conductivity. In an alternative embodiment, the device structure 40 formed using the semiconductor layer 28 may be a silicon controlled rectifier or thyristor. In an alternative embodiment, the device structure 40 may be an insulated gate bipolar transistor. In an alternative embodiment, the device structure 40 may be a diffusion resistor. In an alternative embodiment, the device structure 40 may be a junction field effect transistor. In an alternative embodiment, device structures 40 of multiple different types may be formed using the semiconductor layer 28.Referring to FIG. 3, wherein like reference numerals refer to like features in FIG. 2, and in accordance with alternative embodiments, device structure 40 may be a lateral bipolar transistor in which doped region 42 defines an emitter, doped region 46 participates in defining a base, and doped region 48 provides a collector surrounding the emitter. The doped region 42, which may include overlapping portions having different dopant concentrations, is doped to have a conductivity type opposite to the semiconductor layer 28 to form a pn junction. For example, the doped region 42 may be doped to have a p-type conductivity when the semiconductor layer 28 has an n-type conductivity.Referring to FIGS. 4, 5, wherein like reference numerals refer to like features in FIG. 2, and in accordance with alternative embodiments, device structure 40 may be formed using device layer 12 in device region 30 in place of semiconductor layer 28. In this case, the semiconductor layer 28 is not formed in the device region 30, leaving the device layer 12 accessible for the formation of the device structure 40. The top surface 21 of the layer stack 20 and the top surface 18 of the device layer 12 may differ in height by more than 500 nm.As shown in FIG. 4, the device structure 40 formed using the device layer 12 in the device region 30 may be a Schottky diode. As shown in FIG. 5, the device structure 40 formed using the device layer 12 in the device region 30 may be a bipolar transistor.Referring to FIG. 6, wherein like reference numerals refer to like features in FIG. 4, and in accordance with alternative embodiments, a dielectric layer 50 may be formed on device layer 12 in device region 30. The dielectric layer 50 is formed of a dielectric material, such as silicon dioxide, and has a top surface 52. The dielectric material of the dielectric layer 50 may be deposited by, for example, chemical vapor deposition and subsequently planarized. Access to the doped regions 42, 46, 48 may be via trenches 51 that are patterned in the dielectric layer 50 and that completely penetrate the dielectric layer 50 from the top surface 52 to the device layer 12. In an alternative embodiment, the device structure 40 may be a bipolar transistor instead of a Schottky diode.In an embodiment, the top surface 21 of the layer stack 20 and the top surface 52 of the dielectric layer 50 may be coplanar in the device region 30. In an embodiment, the top surface 21 of the layer stack 20 may be substantially coplanar with the top surface 52 of the dielectric layer 50 in the device region 30. In an embodiment, the top surface 21 of the layer stack 20 and the top surface 52 of the dielectric layer 50 in the device region 30 may differ in height by about 100 nm to about 500 nm, which may be considered substantially coplanar.Referring to FIG. 7, wherein like reference numerals refer to like features in FIG. 1, and in accordance with alternative embodiments, the device layer 12 may be formed prior to forming the layer stack with respect to its original thickness in the reduced thickness device region 22. In the device region 30, the device layer 12 maintains its original thickness. In this case, the semiconductor layer 28 is not formed in the device region 30, and the original thickness of the device layer 12 is greater than the thickness of the layer stack 20.In an embodiment, the top surface 21 of the layer stack 20 and the top surface 18 of the device layer 12 may be coplanar in the device region 30. In an embodiment, the top surface 21 of the layer stack 20 may be substantially coplanar with the top surface 18 of the device layer 12 in the device region 30. In an embodiment, the top surface 21 of the layer stack 20 and the top surface 18 of the device layer 12 in the device region 30 may differ in height by about 100 nm to about 500 nm, which may be considered substantially coplanar.Referring to FIG. 8, wherein like reference numerals refer to like features in FIG. 7, at a subsequent fabrication stage, processing continues to form the device structures 38, 40. In the device region 30, the device structure 40 is formed using the semiconductor material of the device layer 12, which may be doped (e.g., with an n-type doping) to facilitate device fabrication.Referring to FIG. 9, wherein like reference numerals refer to like features in FIG. 1, and in accordance with alternative embodiments, the substrate 10 may be a technical substrate that includes a handling substrate 56 formed of a polycrystalline ceramic material closely matched to the thermal expansion characteristics of the materials of the layer stack 20. In one embodiment, the handling substrate 56 may be formed of polycrystalline aluminum nitride that closely matches the thermal expansion properties of gallium nitride. In one embodiment, the handle substrate 56 may be formed of polycrystalline silicon carbide, which also fits very well to the thermal expansion properties of gallium nitride. The handling substrate 56 is covered with a layer stack 54 comprising technical layers, for example layers containing silicon dioxide, silicon nitride, polysilicon etc. The device layer 12 is arranged on the layer stack 54.Referring to FIG. 10, wherein like reference numerals refer to like features in FIG. 9, and at a subsequent fabrication stage, processing continues to form the layer stack 20, optionally to form the semiconductor layer 28, and to form the device structure 38, 40.The above-described methods are used in the production of integrated circuit chips. The resulting integrated circuit chips may be sold by the manufacturer in the form of untreated wafers (e.g., as a single wafer with multiple unpackaged chips), as a bare chip, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with terminals attached to a motherboard or other parent carrier) or in a multichip package (e.g., a ceramic carrier with surface interconnections and / or buried interconnections). In either case, the chip may be integrated with other chips, discrete circuit elements, and / or other signal processing devices, either as part of an intermediate product or an end product.References throughout this document to terms modified by approximation formulae such as "about", "about", and "substantially" are not to be limited to the exact value. The approximation formula may correspond to the accuracy of an instrument used to measure the value and, unless otherwise dependent on the accuracy of the instrument, specify + / - 10% of the specified value / values.References herein to terms such as "vertical", "horizontal", etc. are used by way of example only and not limitation to provide a frame of reference. As used herein, the term "horizontal" is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal direction just defined. The term "lateral" refers to a direction within the horizontal plane.A feature "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intervening features may instead be present. One feature may be "directly connected" or "directly coupled" to another feature when there are no intervening features present. A feature may be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intervening features may instead be present. A feature may be "directly on" or in "direct contact" with another feature if there are no intervening features. A feature may be "indirectly on" or in "indirect contact" with another feature if at least one intervening feature is present.

Claims

A structure comprising: a substrate (10) having a device layer (12), a handle substrate (16), and a buried insulator layer (14) between the handle substrate (16) and the device layer (12); a first semiconductor layer (20) on the device layer (12) in a first device region (22), the first semiconductor layer (20) being formed from a III-V compound semiconductor material; a second semiconductor layer (28) on the device layer (12) in a second device region (30), the second semiconductor layer (28) being formed from silicon; a first device structure (38) having a gate structure (34) on the first semiconductor layer (20); and a second device structure (40) having a doped region (42) in the second semiconductor layer (28), wherein the doped region (42) and the second semiconductor layer (28) form a pn junction.The structure of claim 1, wherein the first device structure (38) is a high electron mobility transistor and the second device structure (40) is a Schottky diode.The structure of claim 1, wherein the first device structure (38) is a high electron mobility transistor and the second device structure (40) is a bipolar transistor.The structure of claim 1, wherein the device layer (12) is formed of single crystal silicon having a <111> crystal orientation and the silicon of the second semiconductor layer (28) is single crystal having a <111> crystal orientation.The structure of claim 1, wherein the III-V compound semiconductor material comprises gallium nitride.The structure of claim 1, wherein the first semiconductor layer (20) has a first top surface (21), the second semiconductor layer (28) has a second top surface (27), and the first top surface (21) and the second top surface (27) are substantially coplanar.The structure of claim 1, wherein the first semiconductor layer (20) has a first top surface (21), the second semiconductor layer (28) has a second top surface (27), and the first top surface (21) and the second top surface (27) differ in height by about 100 nanometers to about 500 nanometers.The structure of claim 1, wherein the handling substrate (16) is formed of a polycrystalline ceramic material.A structure comprising: a substrate (10) having a device layer (12), a handle substrate (16), and a buried insulator layer (14) between the handle substrate (16) and the device layer (12), the device layer (12) being formed of single crystal silicon having a <111> crystal orientation; a semiconductor layer (20) on the device layer (12) in a first device region (22), the semiconductor layer (20) being formed of a III-V compound semiconductor material; a first device structure (38) having a gate structure (34) on the semiconductor layer (20); and a second device structure (40) having a doped region (42) in the device layer (12) in a second device region (30), the doped region (42) and the device layer (12) defining a pn junctionA method comprising: providing a substrate (10) comprising a device layer (12), a handle substrate (16), and a buried insulator layer (14) between the handle substrate (16) and the device layer (12); forming a first semiconductor layer (20) on the device layer (12) in a first device region (22), the first semiconductor layer (20) being formed of a III-V compound semiconductor material; forming a second semiconductor layer (28) on the device layer (12) in a second device region (30), the second semiconductor layer (28) being formed of silicon; forming a first device structure (38) having a gate structure (34) on the first semiconductor layer (20); forming a second device structure (40) having a doped region (42) in the second semiconductor layer (28), the doped region (42) and the second semiconductor layer (28) defining a pn junction.The method of claim 10, wherein forming the first semiconductor layer (20) on the first device region (22) of the device layer (12) comprises: epitaxially growing the first semiconductor layer (20) in the first device region (22) and the second device region (30); and removing the first semiconductor layer (20) from the second device region (30).The method of claim 11, wherein the first semiconductor layer (20) is removed from the second device region (30) prior to forming the second semiconductor layer (28).The method of claim 10, wherein the first semiconductor layer (20) has a first top surface (21), the second semiconductor layer (28) has a second top surface (27), and the first top surface (21) and the second top surface (27) differ in height by about 100 nanometers to about 500 nanometers.The method of claim 10, wherein the device layer (12) is formed of single crystal silicon having a <111> crystal orientation and the silicon of the second semiconductor layer (28) is single crystal having a <111> crystal orientation.

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