Method for manufacturing a semiconductor device

Abstract

Method for manufacturing a semiconductor device, showing the steps: - Formation of first inorganic films (9) on lower surfaces of a plurality of silicon carbide wafers (50); - Performing an etching of the plurality of silicon carbide wafers (50) after the formation of the first inorganic films (9); - Performing the etching such that a thickness of 750 nm or more of the first inorganic films of the plurality of silicon carbide wafers (50) remains after etching; - Forming oxide films (5) on the upper surfaces of the plurality of silicon carbide wafers (50) by performing a thermal oxidation treatment using a semiconductor fabrication device (80, 80c, 80d, 80e); and - Performing the thermal oxidation treatment in a state in which at least one wafer (51, 51a, 52) comprising at least one dummy wafer (51, 51a) and one monitoring wafer (52) is different from the plurality of silicon carbide wafers (50), and the plurality of silicon carbide wafers (50) are aligned in one direction and the upper surfaces of the plurality of silicon carbide wafers (50) are oriented in one direction, where: - in the state of thermal oxidation treatment, a first silicon carbide wafer (50) of the plurality of silicon carbide wafers (50) is placed directly below any one of the at least one wafer (51, 51a, 52), and a second silicon carbide wafer (50) of the plurality of silicon carbide wafers (50) is placed directly below a third silicon carbide wafer (50) of the plurality of silicon carbide wafers (50), - the thermal oxidation treatment is carried out using oxygen gas or ozone gas and - during thermal oxidation treatment, more oxygen gas is supplied to an area between any of the at least one wafer (51, 51a, 52) and the first silicon carbide wafer (50) than to an area between the second silicon carbide wafer (50) and the third silicon carbide wafer (50).

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor manufacturing facility. Description of the background technology

[0002] In the published Japanese patent application JP 2014-165 348 A and the Japanese patent JP 6 141 130 B2, a procedure is disclosed to suppress variations in the thickness of oxide films under a plurality of silicon carbide (hereinafter also referred to as SiC) wafers when the oxide films are formed on the plurality of SiC wafers.

[0003] Publication JP 6 141 130 B2 discloses, in particular, a method for manufacturing a silicon carbide semiconductor device capable of suppressing variations in the film thickness of an oxide film between silicon carbide substrates for products. A SiC dummy wafer or a silicon wafer on which a TEOS (tetraethyl orthosilicate) oxide film or a thermal oxide film is formed by oxidation treatment of a C-plane is positioned between a SiC monitor wafer and a SiC product wafer. Oxidation treatment is performed with an oxidizing gas. Instead of the SiC dummy wafer or the silicon wafer, the SiC monitor wafer, whose C-plane undergoes oxidation treatment, can be used. The distance between the SiC monitor wafer and the SiC product wafer can be set to a predetermined value or greater.A Si layer of the SiC monitoring wafer and a Si layer of the SiC product wafer can be opposite each other.

[0004] The state-of-the-art procedure is not necessarily sufficient as a procedure for suppressing fluctuations in the thickness of thermal oxide films under a large number of SiC wafers.

[0005] Publication JP 2014-165 348 A relates to a method for manufacturing a semiconductor device and describes steps (b) of forming inorganic layers on a back face of a dummy substrate and back faces of a plurality of semiconductor substrates with such a thickness that the inorganic layers are resistant to temperature during a thermal oxidation treatment or a heat treatment and the amount of oxidizing or reducing gases reaching the back faces of the dummy substrate and the plurality of semiconductor substrates is sufficiently reduced.(c) arranging the dummy substrate and the plurality of semiconductor substrates in a stack with surfaces facing in the same direction and a space between the substrates and (d) performing a thermal oxidation treatment or a post-heat treatment of the front surfaces of the semiconductor substrates in an oxidizing gas atmosphere or a reducing gas atmosphere according to steps b and c.,

[0006] Publication JP 2013-197 116 A describes a substrate processing device that simplifies gas flow control and prevents nozzle damage and increased maintenance. The substrate processing device comprises: a reaction tube for processing multiple substrates; a heating device for heating the multiple substrates in the reaction tube; a holding device for arranging and holding the multiple substrates in the reaction tube; a first nozzle arranged horizontally around the substrate arrangement area and supplying hydrogen-containing gas from multiple points; a second nozzle arranged horizontally around the substrate arrangement area and supplying oxygen-containing gas from multiple points; and a pressure regulator for controlling the pressure in the reaction tube to a value below atmospheric pressure.The first nozzle has at least as many first gas nozzle holes as there are substrates, and at least as many as there are substrates. The second nozzle has at least as many second gas nozzle holes as there are substrates, and at least as many as there are substrates.

[0007] US patent 2004 / 0043617A1 discloses a wafer carrier with a partition that separates vertically adjacent wafer slots in the wafer carrier and at least partially shields each wafer from the backside emission of the wafer above it, in order to form a substantially uniform oxide layer on the wafers during thermal oxidation. Each partition can be made of quartz. In a further embodiment, each wafer is at least partially shielded from the backside emission of the wafer above it by separating or subdividing the wafers with an uncoated wafer.

[0008] Document D1, US 2009 / 0305512A1, discloses a substrate processing device comprising a holder for the tiered storage of substrates, a processing vessel containing the holder in which the substrates are subjected to a predetermined heating process in a process gas atmosphere at a predetermined temperature and pressure, a gas inlet section that introduces a process gas into the processing vessel, a gas outlet section that removes a gas from the processing vessel to create a predetermined vacuum pressure within it, and a heating section for heating the processing vessel. The holder is provided with baffle plates, each forming a processing chamber for each substrate when the holder is located in the processing vessel.The gas inlet section is provided with gas inlet holes on one side of the respective processing chambers, and the gas outlet section is provided with gas outlet holes on the other side of the respective processing chambers, opposite the gas inlet holes.

[0009] Publication JP 2011-187 884 A discloses a substrate treatment device that improves the uniformity of film thickness on a wafer surface when an oxide film is formed at low temperature.The substrate treatment device comprises a reaction tube in which several substrates are stored and processed, a heating device for heating the interior of the reaction tube, a substrate holder for stacking, aligning, and holding the multiple substrates in the reaction tube at predetermined intervals, a gas supply nozzle in an area corresponding to a substrate alignment area in which the multiple substrates in the reaction tube are aligned, and which mixes and supplies oxygen- and hydrogen-containing gas from several points in the substrate alignment direction into the reaction tube, an outlet opening for evacuating the interior of the reaction tube, and a pressure control unit that regulates the pressure in the reaction tube to reach a predetermined value that is lower than atmospheric pressure. SUMMARY

[0010] A method for manufacturing a semiconductor device capable of suppressing variations in the thickness of oxide films under a large number of SiC wafers is provided.

[0011] The problem underlying the invention is solved according to the invention in a method for manufacturing a semiconductor device by the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0012] According to the method for fabricating a semiconductor device of the present invention, first inorganic films are formed on the lower surfaces of a plurality of silicon carbide wafers, and the plurality of silicon carbide wafers are etched after the formation of the first inorganic films. The etching is carried out such that a thickness of 750 nm or more of the first inorganic films of the plurality of silicon carbide wafers remains after etching.Oxide films are formed on the upper surfaces of the plurality of silicon carbide wafers by performing a thermal oxidation treatment using a semiconductor fabrication facility, and the thermal oxidation treatment is performed in a state in which at least one wafer, comprising at least one dummy wafer and one monitoring wafer, is distinct from the plurality of silicon carbide wafers, and the plurality of silicon carbide wafers are aligned in one direction and the upper surfaces of the plurality of silicon carbide wafers are oriented in one direction.In the thermal oxidation state, a first silicon carbide wafer of the plurality of silicon carbide wafers is placed directly below any one of the at least one wafer, and a second silicon carbide wafer of the plurality of silicon carbide wafers is placed directly below a third silicon carbide wafer of the plurality. According to the invention, the thermal oxidation treatment is carried out using oxygen gas or ozone gas. During the thermal oxidation treatment, more oxygen gas is supplied to a region between any one of the at least one wafers and the first silicon carbide wafer than to a region between the second silicon carbide wafer and the third silicon carbide wafer.

[0013] According to the present invention, a method for manufacturing a semiconductor device for suppressing variations in the thickness of oxide films under a plurality of SiC wafers is provided.

[0014] These and other tasks, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when it is carried out in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a diagram illustrating a vertical batch-type diffusion furnace according to the first embodiment, which can be used in the process according to the invention. Fig. Figure 2 is a cross-sectional view illustrating a state near a SiC wafer during a thermal oxidation treatment. Fig. Figure 3 is a diagram that schematically illustrates the crystal structure of a SiC wafer. Fig. Figure 4 is a diagram illustrating the interior of a cell of a semiconductor device according to the first embodiment, which can be used in the method according to the invention. Fig. Figure 5 is a diagram illustrating an outer circumferential part of the cell of the semiconductor device using the first embodiment. Fig. Figure 6 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. Figure 7 is a cross-sectional view illustrating a state during a fabrication of the semiconductor device according to the invention using the first embodiment. Fig. Figure 8 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. 9 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. 10 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. Figure 11 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. 12 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. 13 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. Figure 14 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. 15 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. 16 is a cross-sectional view illustrating a state during a manufacturing of the semiconductor device according to the invention using the first embodiment. Fig. Figure 17 is a flowchart of a method according to the invention for manufacturing the semiconductor device using the first embodiment. Fig. Figure 18 is a graphical representation illustrating the relationship between the thickness of an interlayer insulating film formed on a C surface of the SiC wafer and the variations in the thickness of gate oxide films under the SiC wafers. Fig. Figure 19 is a diagram illustrating the placement of wafers in the second embodiment, which can be used in the method according to the invention. Fig. Figure 20 is a diagram illustrating a vertical batch-type diffusion furnace according to the third embodiment, which can be used in the process according to the invention. Fig. Figure 21 is a diagram illustrating a vertical batch-type diffusion furnace according to the fourth embodiment, which can be used in the process according to the invention. Fig. Figure 22 is a diagram illustrating a vertical batch-type diffusion furnace according to the fifth embodiment, which can be used in the process according to the invention. Fig. Figure 23 is a diagram illustrating a vertical batch-type diffusion furnace according to the fifth embodiment, which can be used in the process according to the invention. DESCRIPTION OF PREFERRED EXECUTION FORMS<Vorläufertechnik>

[0015] Fig. Figure 1 is a diagram illustrating a configuration of a batch-type vertical diffusion furnace 80, which is an example of a batch-type vertical diffusion furnace used in any embodiment applicable to the process according to the invention. In any embodiment subsequently described that can be used in the process according to the invention, for example, the one shown in Figure 1 is used. Fig. Figure 1 illustrates a batch-type vertical diffusion furnace 80 used to form an oxide film on a SiC wafer 50, which is intended to be a silicon carbide semiconductor device.

[0016] The batch-type vertical diffusion furnace 80 comprises a tube 81, a boat 82, and a gas inlet line 83. The boat 82 has a plurality of support sections 82a for carrying the wafers. The tube 81 is a vessel in which the thermal oxidation treatment is carried out. In the batch-type vertical diffusion furnace 80, a plurality of wafers are carried by a plurality of support sections 82a along one direction, with the main surfaces of the plurality of wafers oriented in one direction.

[0017] The large number of SiC wafers 50 will be, as in Fig. Figure 1 illustrates that during thermal oxidation treatment, the wafers are supported by the carrier section 82a and are positioned in the tube 81 in a spaced-apart state. Hereinafter, a group of the multitude of SiC wafers 50, which are processed simultaneously in the vertical diffusion furnace 80 of the batch type, is referred to as a batch. The gas introduction line 83 is a line for introducing an oxidizing gas into the tube 81. The gas introduction line 83 is provided with an opening 830, and the oxidizing gas is introduced into the tube 81 through the opening 830. The oxidizing gas is a gas used for thermal oxidation treatment and is, for example, oxygen (O2) gas or ozone (O3) gas.

[0018] In the SiC wafer 50, for example, one main surface is a carbon (C) surface and the other main surface is a silicon (Si) surface.

[0019] Fig. Figure 1 illustrates an example of the placement of the SiC wafer 50 when the thermal oxidation treatment is performed.

[0020] Each SiC wafer 50 is held on the boat 82 such that its carbon (C) surface faces downwards and its silicon (Si) surface faces upwards. The SiC wafers 50 are stacked with a gap in a direction that intersects the main surface of the SiC wafer 50, for example, in a direction perpendicular to the main surface of the SiC wafer 50.

[0021] Prior to the thermal oxidation treatment, an inorganic film 90 (see Fig. 2 and Fig. 3) formed on a C-surface 12 which is the lower surface of each SiC wafer 50.

[0022] Above the SiC wafer 50, which is held in the top tray of SiC wafer 50, a SiC dummy wafer 51 is placed at a distance from the SiC wafer 50 on the top tray. Above the SiC dummy wafer 51, a Si monitoring wafer 52 is placed at a distance from the SiC dummy wafer 51.

[0023] Similar to the lower surface of the SiC wafer 50 in Fig. 2 An inorganic film 90 is formed on the lower surface of the SiC dummy wafer 51. The reason for the placement of the SiC dummy wafer 51 will be described later.

[0024] The thickness of the oxide film of the Si monitoring wafer 52 is measured after the thermal oxidation treatment is completed; this confirms whether or not there is a problem with the oxide film formed on each SiC wafer 50.

[0025] When O2 gas is used as the oxidizing gas, the thermal oxidation reaction in the SiC wafer 50 is expected to occur as illustrated in the following equation (1). In each of the following equations, “(↑)” indicates that gas is produced. SiC+2O2=SiO2+CO2(↑) (1)

[0026] As illustrated in equation (1), a silicon dioxide (SiO2) film is formed in the SiC wafer 50 during the thermal oxidation reaction, and carbon dioxide (CO2) gas is generated. The CO2 gas generated is expected to decompose reversibly under the high-temperature environment inside the tube 81, causing the reaction represented by equation (2) below, such that carbon monoxide (CO) gas is released and O2 gas is generated again. 2CO2=2CO(↑)+O2(↑) (2)

[0027] Fig. Figure 2 is a cross-sectional view illustrating a state near the SiC wafer 50 during a thermal oxidation treatment. Fig. Figure 3 is a diagram that schematically illustrates a crystal structure of the SiC wafer 50.

[0028] As in Fig. As illustrated in Figure 3, the crystal structure of the SiC wafer 50 consists of silicon (Si) atoms 45 and carbon (C) atoms 46. One main surface of the SiC wafer 50 is the C surface 12 with the exposed C atoms 46, and the other main surface is the Si surface 13 with the exposed Si atoms 45.

[0029] As in Fig. As illustrated in Figure 2, CO2 gas is produced due to the reaction of equation (1) when O2 gas is supplied to the SiC wafer 50 to form an oxide film 5a. As shown in Figure 2, CO2 gas is produced due to the reaction of equation (1). Fig. As illustrated in Figure 3, the side of the C surface 12 of the SiC wafer 50 has more C atoms 46 than the side of the Si surface 13. Therefore, it is assumed that the C surface 12 produces more CO2 gas than the Si surface 13.

[0030] As described above, the inorganic film 90 is formed on the carbon surface 12 of the SiC wafer 50. The inorganic film 90, arranged on the carbon surface 12 of the SiC wafer 50, has the effect of suppressing the reaction of equation (1) on the carbon surface 12 of the SiC wafer 50. If the inorganic film 90 is thin, the effect of suppressing the reaction of equation (1) mentioned above is small, and therefore the extent of suppressing the reaction of equation (2) is small, and the effect of the oxygen concentration increasing below the carbon surface 12 of the SiC wafer 50 due to equation (2) becomes large. If the carbon surface 12 of the SiC wafer 50 is opposite or facing the Si surface 13 of the adjacent SiC wafer 50, as in Fig. As illustrated in Figure 2, it is therefore assumed that the oxide film 5a formed by the thermal oxidation treatment in the Si wafer 50 placed directly below the SiC wafer 50 becomes thicker. Furthermore, the influence of oxygen generated as a result of equation (2) differs depending on the position on the wafer surface, and the extent of the oxidation reaction is uneven across the surface; therefore, it is assumed that the thickness of the oxide film 5a formed by the thermal oxidation treatment in the SiC wafer 50 placed directly below the SiC wafer 50 varies depending on its position in the plane.

[0031] In the Fig. In the placement illustrated in Figure 1, consider a case in which the inorganic film 90 formed on the C-surface 12 of the SiC wafer 50 is thin and the SiC dummy wafer 51 is not placed between the Si monitoring wafer 52 and the SiC wafer 50. That is, in Fig. 1. Consider a case in which the SiC wafer 50 is also placed at the position of the SiC dummy wafer 51. The reaction of equation (1) does not occur in the Si monitoring wafer 52; therefore, the reaction of equation (2) and the generation of O2 gas do not take place due to the presence of the Si monitoring wafer 52. In this case, the oxide film 5a formed by the thermal oxidation treatment in the SiC wafer 50 directly below the Si monitoring wafer 52 is thinner than that in the case of the SiC wafer 50 directly below the SiC wafer 50. Accordingly, the thickness of the oxide film 5a formed on the upper surface of the SiC wafer 50 is uneven among the SiC wafers 50 in the batch.

[0032] By placing the SiC dummy wafer 51 with the inorganic film 90 formed on the C-surface 12 between the Si monitoring wafer 52 and the SiC wafer 50 as in Fig. As illustrated in Figure 1, the placement prevents the thickness of the oxide film 5a formed by the thermal oxidation treatment from becoming uneven under the SiC wafers 50 in the batch.

[0033] An inorganic film 90 is formed on the carbon surface 12 of the SiC dummy wafer 51. The inorganic film 90 on the carbon surface 12 of the SiC dummy wafer 51 has, for example, the same thickness as the inorganic film 90 on the carbon surface 12 of the SiC wafer 50. In this case, the same amount of CO2 gas is generated by the carbon surface 12 of the SiC wafer 50 as by the carbon surface 12 of the SiC dummy wafer 51, thus preventing the thickness of the oxide film 5a formed by the thermal oxidation treatment from becoming uneven among the SiC wafers 50 in the batch.

[0034] However, through repeated use of the SiC dummy wafer 51, a thick thermal oxide film forms on the C-surface 12 of the SiC dummy wafer 51, and the inorganic film 90 becomes thicker. Therefore, the amount of O2 gas generated by the C-surface 12 of the SiC dummy wafer 51 is less than that generated by the C-surface 12 of the SiC wafer 50. The oxide film 5a formed on the upper surface of the SiC wafer 50 directly below the SiC dummy wafer 51 by the thermal oxidation treatment is thinner than the oxide film 5a formed on the upper surface of the SiC wafer 50 directly below the SiC dummy wafer 50 by the thermal oxidation treatment. As a result, the thickness of the oxide film 5a formed by the thermal oxidation treatment is uneven under the SiC wafers 50 in the batch.

[0035] As will be described later, in the methods according to the invention for producing the semiconductor devices according to the first to fifth embodiments, the thick inorganic film 90 is formed on the C-surface 12 of the SiC wafer 50 during the thermal oxidation treatment; therefore, the thickness of the oxide film 5a formed by the thermal oxidation treatment is prevented from being uneven among the SiC wafers 50 in the batch.

[0036] Although the explanation in the above description is based on the assumption that the reactions of equations (1) and (2) take place, the effects of the inventive methods for fabricating the semiconductor devices of the first to fifth embodiments are not limited to suppressing the effects of the reactions of equations (1) and (2). The atmosphere above a SiC wafer 50 can vary depending on whether the upper wafer is the SiC monitoring wafer 52, the SiC dummy wafer 51, or the SiC wafer 50. In the methods for fabricating semiconductor devices according to the first to fifth embodiments, the suppression of the inconsistency in the thickness of the oxide film 5a formed by the thermal oxidation treatment under the SiC wafers 50 in the batch is ensured as a function of such atmospheric changes. <A. Erste erfindungsgemäß einsetzbare Ausführungsform><A-1. Konfiguration>

[0037] The inventive method for manufacturing the silicon carbide semiconductor device according to the first embodiment is used, for example, to manufacture a MOSFET, a pn diode, a Schottky barrier diode (SBD), a bipolar junction transistor (BJT), a junction FET (JFET), an insulated gate bipolar transistor (IGBT) or the like.

[0038] The following is a description in which a case is assumed in which the semiconductor device produced by the inventive method for manufacturing the silicon carbide semiconductor device according to the first embodiment is a Fig. 4 and Fig. 5 illustrated MOSFET 100 is shown. Fig. Figure 4 illustrates the interior of the MOSFET 100 cell. Fig. Figure 5 illustrates the outer circumferential region of the MOSFET 100 cell. In the following description, the conductivity types of the semiconductor layers can be interchanged.

[0039] As in Fig. 4 and Fig. As illustrated in Figure 5, the MOSFET 100 comprises a SiC substrate 1, a SiC drift layer 2, a base region 3, a source region 4, a gate oxide film 5, a gate wiring 6, a source electrode 7, a drain electrode 8, an interlayer insulating film 9 and a gate electrode 10.

[0040] The upper surface of SiC substrate 1 is a Si surface. SiC substrate 1 is a single-crystal n-type substrate with a 4H crystal structure.

[0041] The SiC drift layer 2 is formed on the upper surface of the SiC substrate 1.

[0042] Base region 3 is selectively formed in the surface layer subregion of the upper surface of the SiC drift layer 2. Base region 3 is a p-type semiconductor layer and contains, for example, aluminum (Al) as p-type defects.

[0043] Source region 4 is selectively formed in the surface layer subregion on the upper surface of base region 3 within the cell. Source region 4 is an n-type semiconductor layer. Source region 4 contains, for example, nitrogen (N) as n-type impurities.

[0044] The gate oxide film 5 is formed over a region 2a located between two adjacent source regions 4 of the source region 4, the base region 3, and the SiC drift layer 2. The gate wiring 6 is formed on the gate oxide film 5. The drain electrode 8 is formed on the C surface, which is the lower surface of the SiC substrate 1. The gate wiring 6 and the source electrode 7 are separated by the interlayer insulating film 9. The gate wiring 6 extends from the interior of the cell to the outer circumference of the cell and is connected to the gate electrode 10 at the outer circumference of the cell.

[0045] Although the MOSFET 100 in Fig. Figure 4 illustrates a planar gate structure, and the MOSFET 100 can be of the trench-gate type. <A-2. Erfindungsgemäßes Herstellungsverfahren>

[0046] Fig. Figure 17 is a flowchart of a method according to the invention for manufacturing the semiconductor device according to the first embodiment.

[0047] Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 are cross-sectional views illustrating a state in which the MOSFET 100 is located during the manufacturing process. The MOSFET manufacturing process is described below with reference to... Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. 11 described. Fig. Figure 6 is a diagram that corresponds to both the interior of the cell and the outer perimeter sub-area of ​​the cell. Fig. 7 to 9, 11, 13 and 15 are diagrams that correspond to the interior of the cell. Fig. 10, Fig. 12, Fig. 14 and Fig. 16 are diagrams that correspond to the outer perimeter sub-area of ​​the cell.

[0048] First, in step S1, the silicon carbide substrate 1 is prepared.

[0049] Next, in step S2, the SiC drift layer 2 is epitaxially grown on the upper surface of the silicon carbide substrate 1 using the CVD process (see Fig. 6) The concentration of n-type defects in the SiC drift layer 2 is 1×10 15 cm- 3 up to 1×10 17 cm- 3 and their thickness ranges from 5 to 50 µm.

[0050] Next, in step S3, a mask 41 is formed on the upper surface of the SiC drift layer 2, and ions of AI, which are p-type defects, are implanted into the SiC drift layer 2 using the mask 41 (see Fig. 7) At this point, the depth of Al ion implantation is approximately 0.5 to 3 µm, which does not exceed the thickness of the SiC drift layer 2. The defect concentration of the ion-implanted Al is in the range of 1 × 10 17 cm-3 up to 1×10 10 cm- 3 , which is higher than the concentration of n-type defects in the SiC drift layer 2. The area of ​​the SiC drift layer 2 where Al ions are implanted and which becomes p-type is the base region 3. After performing the Al ion implantation, the mask 41 is removed.

[0051] Furthermore, in step S3, after removing mask 41, a mask 42 is formed on the upper surface of the SiC drift layer 2, and the mask 42 is used to implant N ions, which are n-type defects, into the surface layer subregion of the SiC drift layer 2 (see Fig. 8) In step S3, the area of ​​the SiC drift layer 2, into which the All-ion was previously injected in step S3, is also referred to collectively as the SiC drift layer 2. The depth of the N ion implantation is set to be shallower, or less than the thickness of the base region 3. The impurity concentration of N to be implanted as an ion exceeds the concentration of p-type impurities in the base region 3 by approximately 1 × 10⁻⁶. 18 cm- 3 up to 1×10 21 cm- 3 In the area in the SiC drift layer 2, into which N is injected, the region representing the n-type is the source region 4. After performing an N-ion implantation, the mask 42 is removed.

[0052] Next, in step S4, the N and Al ions implanted in step S3 are activated by curing them at 1300 to 1900°C for 30 seconds to 1 hour in an atmosphere of a noble gas such as argon (Ar) gas using a heat treatment device.

[0053] Next, in step S5, a step forming an intermediate layer insulating film is carried out to form the intermediate layer insulating film 9 using the CVD process (see Fig. 9 and Fig. 10) When the gate wiring 6, which is formed in the subsequent process, is pulled to the outer circumferential region of the cell and connected to the gate electrode 10, the gate wiring 6 is insulated from the SiC drift layer 2, the base region 3, and the source region 4 by the interlayer insulating film 9. The thickness of the interlayer insulating film 9 is preferably 1 to 3 µm, which does not affect the gate capacitance and reduces the likelihood of the interlayer insulating film 9 being destroyed due to a switching operation, overvoltage, or the like. The material of the interlayer insulating film 9, which is an inorganic film, is borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), or the like. The in Fig. The illustrated configuration, comprising the SiC substrate 1, the SiC drift layer 2, the base area 3 and the source area 4, corresponds to the SiC wafer 50 in Fig. 1. The interlayer insulating film 9 corresponds to the inorganic film 90 in Fig. 2.

[0054] The interlayer insulating films 9 are formed on the Si surface 13 (i.e., the main surface on the side of the source region 4), which is the upper surface of the SiC wafer 50, and on the C surface 12 (i.e., the main surface on the side of the lower surface of the SiC substrate 1), which is the lower surface of the SiC wafer 50. The interlayer insulating film 9 on the C surface 12 is an example of a first inorganic film, and the interlayer insulating film 9 on the Si surface 13 is an example of a second inorganic film.

[0055] Next, an etching step is performed in step S6. In the etching step of step S6, the interlayer insulating film 9 on the side of the Si surface 13 inside the cell is removed by structuring, dry etching, and wet etching, and the interlayer insulating film 9 is also removed at a desired position on the side of the Si surface 13 on the outer circumferential part of the cell (see Fig. 9 and Fig. 10).

[0056] In step S6, the interlayer insulating film 9 is etched on the side of the Si surface 13. At this point, depending on the etching method, the interlayer insulating film 9 on the side of the C surface 12 of the SiC wafer 50 is also etched, which makes the interlayer insulating film 9 thinner on the side of the C surface 12 of the SiC wafer 50. In the following step, the thickness of the interlayer insulating film 9 on the side of the C surface of the SiC wafer 50 is preferably 0.75 µm, that is, 750 nm, or more. Therefore, in the first embodiment, the etching step of step S6 is carried out such that the remaining thickness of the interlayer insulating film 9 on the side of the C surface 12 of the SiC wafer after etching step S6 is 0.75 µm or more.The reason why it is preferable for the remaining thickness of the interlayer insulating film 9 on the side of the C-surface 12 of the SiC wafer 50 after etching in step S6 to be at least 0.75 µm or more will be described later. The remaining thickness of the interlayer insulating film 9 on the side of the C-surface 12 of the SiC wafer 50 after etching in step S6 can also be 1.2 µm or more, and can be 1.6 µm or more.

[0057] In step S6, for example, the remaining thickness of the interlayer insulating film 9 on the C-surface side of the SiC wafer 50 in the central subregion of the SiC wafer 50 in plan view is 0.75 µm or more. Furthermore, in step S6, for example, 0.75 µm or more of the interlayer insulating film 9 remains on the entire C-surface side of the SiC wafer. In step S6, an average of, for example, 0.75 µm or more of the interlayer insulating film 9 also remains on the C-surface side of the SiC wafer 50. The average thickness of the interlayer insulating film 9 is defined here as the average of each thickness measured at a large number of points evenly spaced in the plane of the SiC wafer 50, for example, 100 points or more.

[0058] For example, processes include those in which, after etching in step S6, 0.75 µm or more of the interlayer insulating film 9 remains on the side of the C-surface 12 of the SiC wafer 50, a process in which the interlayer insulating film 9 on the side of the C-surface 12 of the SiC wafer 60 is made thicker beforehand, a process in which a protective film is formed on the interlayer insulating film 9 on the side of the C-surface 12 of the SiC wafer 50 when the process of step S6 is carried out, so that the interlayer insulating film 9 on the side of the C-surface 12 of the SiC wafer 50 cannot simply be etched in step S6, and the like. For example, if wet etching is carried out in step S6 without forming the protective film, not only the intermediate insulating film 9 on the side of the Si surface 13, but also the intermediate insulating film 9 on the side of the C surface 12 will be etched.By forming the protective film on the interlayer insulating film 9 on the side of the C-surface 12 of the SiC wafer 50 and then performing wet plating by immersion, costs can be reduced and, for example, 0.75 µm or more of the interlayer insulating film 9 can remain on the side of the C-surface 12 of the SiC wafer 50.

[0059] Next, in step S7, as in Fig. 11 and Fig. Figure 12 illustrates that the gate oxide film 5, which is a thermal oxide film, is formed by thermal oxidation treatment in an area where no intermediate insulating film 9 is formed, on the side of the upper surface of the SiC wafer 50. An oxidizing gas, for example O2 gas or O3 gas, is used in the thermal oxidation treatment, as described above. The gate oxide film 5 corresponds to the oxide film 5a in Figure 12. Fig. 2. In Fig. Figure 2 shows the inorganic film 90 on the lower surface of the SiC wafer 50, and the oxide film 5a is shown on the upper surface of the SiC wafer 50. In step S7 of the first embodiment, the intermediate insulating film 9 can also be formed on a portion of the upper surfaces of the SiC wafer 50.

[0060] The details of step S7 are described below. In step S7, the gate oxide film 5 is formed by placing the SiC wafer 50 in the Fig. 1 illustrated vertical diffusion furnace 80 of the batch type is subjected to a thermal oxidation treatment.

[0061] In step S7, the SiC wafer 50, in which 0.75 µm or more of the interlayer insulating film 9 remains on the C-surface 12, is first prepared as in Fig. Figure 1 illustrates the placement of the SiC wafer 50 and the SiC dummy wafer 51 in the vertical diffusion oven 80 of the batch type. The wafers are arranged with their C-surfaces 12 facing downwards. The illustration of the interlayer insulating film 9 is shown in Figure 1. Fig. 1 omitted.

[0062] Next, the Si surface 13 of the SiC wafer 50 is thermally oxidized at 1200°C or higher and 1300°C or lower to form a thermal oxide film on the Si surface 13 of the SiC wafer 50. At this point, the gate oxide film 5, which is a thermal oxide film, forms in the region of the Si surface 13 of the SiC wafer 50 where the interlayer insulating film 9 is not formed (i.e., the region where the interlayer insulating film 9 is removed in step S6). The thicker the interlayer insulating film 9 remaining on the side of the C surface 12 of the SiC wafer 50, the more difficult it is for the O2 gas to reach the C surface 12 due to the obstruction caused by the interlayer insulating film 9.Therefore, the amount of O2 gas produced by the C surface 12 as a result of the reactions of the above equations (1) and (2) is reduced, and it is less likely that the oxidation reaction by the O2 gas in the SiC wafer 50 takes place directly below the SiC wafer 50.

[0063] The thickness of the gate oxide film 5 formed in step S7 is determined with reference to Fig. 18 described in detail. Fig. Figure 18 is a graphical representation illustrating the relationship between the thicknesses of the interlayer insulating film 9 formed on the C-surface 12 of the SiC wafer 50 and the variations in the thickness of the gate oxide films 5 under the SiC wafers 50. The horizontal axis of Fig. 18 represents the average thickness of the interlayer insulating film 9 formed on the C-surface 12 of a specific SiC wafer 50. The horizontal axis of Fig. Figure 18 represents the thickness of the interlayer insulating film 9 formed on the C-surface 12 of a typical SiC wafer 50, and the interlayer insulating film 9 of substantially the same thickness is formed on the C-surface 12 of each SiC wafer 50 in the batch. The vertical axis in Fig. 18 represents a difference between the maximum and minimum thicknesses of the gate oxide films 5 formed on the Si surfaces 12 of the SiC wafers 50 in the batch when the thermal oxidation treatment is carried out in step S7. Fig. 18 represents the aforementioned “Measured Value” as a result of a measurement performed after the actual thermal oxidation treatment, and “Calculated Value” as a result obtained through numerical simulation. Of each SiC wafer 50 in the batch, the SiC wafer 50 directly below the SiC dummy wafer 51 exhibited the thinnest gate oxide film 5 formed on the Si surface 13.

[0064] The in Fig. The 18 illustrated results are those obtained when thermal oxidation treatment was performed using the [product name] in Fig. The thermal oxidation process was carried out in a batch-type vertical diffusion furnace 80, as illustrated in Figure 1. During the thermal oxidation treatment, the gate oxide film 5, approximately 45 to 50 nm thick, is formed on the top surface of the 4-inch diameter SiC wafer 50. Prior to the thermal oxidation treatment, an intermediate insulating film 9 of sufficient thickness to ensure that no O2 gas is generated according to equations (1) and (2) is formed on the carbon surface 12 of the SiC dummy wafer 51. The intermediate insulating film 9, which is an inorganic film, is thicker on the carbon surface 12 of the SiC dummy wafer 51 than the intermediate insulating film 9 formed on the carbon surface 12 of each SiC wafer 50 in the batch.

[0065] As in Fig. As illustrated in Figure 18, the variations in the thickness of the gate oxide films 5 formed in step S7 under the SiC wafers 50 in the batch become smaller the thicker the interlayer insulating films 9 formed on the C-surface 12 of the SiC wafers 50 are. This is because the thicker the interlayer insulating film 9 formed on the C-surface 12 of the SiC wafer 50, the more O2 gas generated by the C-surface 12 of the SiC wafer 50 as a result of the reactions represented by equations (1) and (2) can be suppressed.

[0066] The interlayer insulating film 9, with a thickness sufficient to assume that no O2 gas generated according to equations (1) and (2) is present, is formed on the SiC dummy wafer 51; therefore, when step S7 is carried out, the same result as in Fig. 18 are obtained even if the SiC dummy wafer 51 is not placed and the Si monitoring wafer 52 is placed directly above the SiC wafer 50. That is, by setting the thickness of the interlayer insulating film 9 on the C-surface 12 of the SiC wafer 50 to 0.75 µm or more, even if the SiC dummy wafer 51 is eliminated, the variations in the thickness of the gate oxide films 5 under the SiC wafers 50 in the batch are suppressed. Therefore, if the thickness of the interlayer insulating film 9 on the C-surface 12 of the SiC wafer 50 is 0.75 µm or more, the SiC wafer 50 can be placed at the position where in Fig. 1 of the SiC dummy wafer 51 is placed.

[0067] As described above, if the thickness of the interlayer insulating film 9 remaining on the lower surface of the SiC wafer 50 in step S6 is 0.75 µm or more, the thickness difference of the gate oxide films 5 formed in step S7 among the SiC wafers 50 in the batch is suppressed to 0.8 nm or less. This was determined as a result of careful research.

[0068] If the interlayer insulating film 9 on the C-surface 12 of the SiC wafer 50 is thin, its thickness is not uniform in the plane, resulting in a highly distorted amount of O2 produced depending on its position in the plane. This impairs the uniformity in the plane of the gate oxide film 5 of the SiC wafer 50 directly beneath it. If 0.75 µm or more of the interlayer insulating film 9 remains, O2 gas production can be suppressed. Therefore, the uniformity in the plane of the gate oxide film 5 formed on the Si-surface 13 of the SiC wafer 50 directly beneath it is improved.

[0069] If the thickness of the interlayer insulating film 9 on the C-surface 12 of the SiC wafer 50 is set to 1.2 µm or more, the difference in the thickness of the gate oxide films 5 among the SiC wafers 50 in the batch can be suppressed to 0.3 nm or less. If the thickness of the interlayer insulating film 9 on the C-surface 12 of the SiC wafer 50 is set to 1.6 µm or more, the difference in the thickness of the gate oxide films 5 among the SiC wafers 50 in the batch can be suppressed to 0.1 nm or less. Therefore, it is preferable to retain 1.2 µm of the interlayer insulating film 9 in step S6, and it is even more preferable to retain 1.6 µm of the interlayer insulating film 9 in step S6.

[0070] In step S7, after the thermal oxide film has formed, a post-annealing or post-curing process is carried out to reduce the interfacial state at the interface between SiO2 and SiC, using the same wafer placement as in [previous step]. Fig. 1. Post-curing is carried out under a wet atmosphere, a nitrogen oxide (NO or N2O) atmosphere, an oxidation gas atmosphere such as a POCl3 atmosphere, or a reducing gas atmosphere such as an H2 gas or NH3 gas.

[0071] In step S8, the gate wiring 6 is formed on the gate oxide film 5. The gate wiring 6 is formed by creating a conductive polycrystalline silicon film using a CVD process under reduced pressure, followed by structuring the polycrystalline silicon film. Subsequently, an intermediate insulating film 9 with a thickness of approximately 1.0 to 3.0 µm is additionally formed using a CVD device to cover the gate wiring 6.

[0072] In step S9, the interlayer insulating film 9 and the polycrystalline silicon film on the lower surface of the SiC wafer 50 are removed by wet etching or dry etching. This removes the Fig. 13 and Fig. 14 illustrated states are obtained.

[0073] Next, in step S10, the source electrode 7 and the gate electrode 10 are formed.

[0074] In step S10, the intermediate insulating film 9 in the area where the source electrode 7 is formed is first removed by structuring and dry etching. After forming a silicide layer in the area where the source electrode 7 is to be formed, the intermediate insulating film 9 in the area for establishing contact with the gate wiring 6 is further removed by structuring and dry etching (see Fig. 15 and Fig. 16) Next, the source electrode 7, electrically connected to the source region 4, and the gate electrode 10, electrically connected to the gate wiring 6, are formed. The source electrode 7 and the gate electrode 10 are formed by sputtering a film, such as an Al alloy, onto the entire top surface of the SiC wafer 50, and then by structuring and wet forming to define the shape of the film.

[0075] Next, in step S11, the drain electrode 8 is formed on the side of the lower surface of the SiC wafer 50. The material of the drain electrode 8 is, for example, an Al alloy.

[0076] The above steps will result in the Fig. 4 and Fig. 5 illustrated vertical MOSFET 100 completed.

[0077] The manufacturing process according to the invention for the silicon carbide semiconductor device of the first embodiment, as described above, can be summarized as follows. A plurality of SiC wafers 50 are prepared, interlayer insulating films 9, which are first inorganic films, are formed on the lower surfaces of the plurality of SiC wafers 50, and the plurality of SiC wafers 50 are etched after the formation of the first inorganic films. The etching is carried out such that the remaining thickness of the first inorganic films of the plurality of SiC wafers 50 after etching is 0.75 µm or more. Next, in step S7, the gate oxide films 5 are formed on the upper surfaces of the plurality of SiC wafers 50 by performing a thermal oxidation treatment using the batch-type vertical diffusion furnace 80.The thermal oxidation treatment is carried out in a state in which at least one wafer, which includes at least one of the Si monitoring wafer 52 or the SiC dummy wafer 51 and which is distinct from the plurality of SiC wafers 50, and the plurality of SiC wafers 50 are aligned in one direction and the top surfaces of the plurality of SiC wafers 50 are oriented in one direction. In the thermal oxidation treatment state, a first SiC wafer 50 of the plurality of SiC wafers 50 is placed directly below any one of the at least one wafer that includes at least one of the Si monitoring wafer 52 and the SiC dummy wafer 51, and a second SiC wafer 50 of the plurality of SiC wafers 50 is placed directly below a third SiC wafer 50 of the plurality of SiC wafers 50.

[0078] In step S7, the fact that the thickness of the interlayer insulating film 9 on the side of the C-surface 12 of the SiC wafers 50 is 0.75 µm or more suppresses the gas generated by the C-surfaces 12 of the SiC wafers 50, thus standardizing the thicknesses of the gate oxide films 5 under the SiC wafers 50 in the batch. Furthermore, the gas generated by the C-surfaces 12 of the SiC wafers 50 is suppressed; therefore, the SiC dummy wafer 51 can be eliminated.

[0079] The same configuration as in step S7 of the manufacturing process of the first embodiment can be adopted for another step to perform a heat treatment using a batch-type device, such as a heat treatment step of a metal electrode. Furthermore, the same configuration as in step S7 can be adopted for the step to form an oxide film other than the gate oxide film 5. <B. Zweite erfindungsgemäß einsetzbare Ausführungsform>

[0080] Fig. Figure 19 is a diagram illustrating how batch-type wafers are processed in the vertical diffusion furnace 80 in step S7 (see Fig. 17) of the inventive method for fabricating a semiconductor device according to the second embodiment. In step S7 of the second embodiment, the SiC wafers 50 and the SiC dummy wafers 51a are alternately placed on the boat 82. With the exception of this configuration, the inventive method for fabricating the semiconductor device according to the second embodiment is the same as the inventive method for fabricating the semiconductor device according to the first embodiment.

[0081] By processing the wafers as in Fig. As illustrated in Figure 19, the diffusion of O2 gas generated by the C-surfaces 12 of the SiC wafers 50 is blocked by the SiC dummy wafers 51a installed directly below the C-surfaces 12. The amount of O2 gas reaching the other SiC wafers 50 by diffusion is reduced. Therefore, oxidation by O2 gas generated by the C-surfaces 12 of the other SiC wafers 50 is less likely to occur in the SiC wafers 50 directly below the SiC dummy wafers 51a, and variations in the thickness of the gate oxide films 5 under the SiC wafers 50 in the batch are suppressed.

[0082] Furthermore, the generation of O2 gas is suppressed; therefore, in step S7, the uniformity in the plane of the thickness of the gate oxide film 5 formed on the Si surface 13 of each SiC wafer 50 in the batch is improved. Instead of the Si dummy wafers 51a, other dummy wafers can be used that are less likely to generate O2 gas on their lower surfaces and less likely to cause a non-uniform oxidation reaction on the SiC wafers 50 directly below them. These other dummy wafers are, for example, SiC dummy wafers 51 that have an inorganic film formed on their lower surfaces with a thickness of 0.75 µm or more.

[0083] If 0.75 µm or more of the interlayer insulating film 9 remains on the lower surface of the SiC wafer 50, the amount of O2 gas generated from the lower surface of the SiC wafer 50 decreases in step S7; therefore, the amount of O2 gas that bypasses the Si dummy wafer 51a and diffuses to other SiC wafers 50 is also reduced, and variations in the thickness of the gate oxide films 5 under the SiC wafers 50 in the batch can be suppressed with higher accuracy. <C. Dritte erfindungsgemäß einsetzbare Ausführungsform>

[0084] Fig. Figure 20 is a diagram illustrating a configuration of a batch-type vertical diffusion furnace 80c used in the third embodiment. The inventive method for producing a semiconductor device of the third embodiment differs from the inventive method for producing the semiconductor device of the first embodiment in that, instead of the batch-type vertical diffusion furnace 80, in step S7 (see Figure 20) Fig. 17) the vertical diffusion furnace 80c of the batch type is used. Although Fig. Figure 20 illustrates a case in which the SiC dummy wafer 51 is not used. In the third embodiment, the SiC dummy wafer 51 can also be placed between the Si monitoring wafer 52 and the SiC wafer 50, as in the first embodiment. Except for this configuration, the method for fabricating the semiconductor device according to the third embodiment is the same as the method for fabricating the semiconductor device according to the first embodiment.

[0085] In comparison with the batch-type vertical diffusion oven 80 used in the first and second embodiments, the batch-type vertical diffusion oven 80c of the third embodiment contains support sections 82b instead of support sections 82a. The batch-type vertical diffusion oven 80c is otherwise similar to the batch-type vertical diffusion oven 80.

[0086] In the vertical diffusion furnace 80 of the batch type of the first embodiment, the support part areas 82a of the boat 82 are claw-shaped, only the end part areas of the wafer are in contact with the support part areas 82a, and the wafer is supported by the support part areas 82a, wherein its central part area does not overlap with the support part areas 82a in plan view.

[0087] On the other hand, in the vertical diffusion furnace 80c of the batch type of the third embodiment, the support sections 82b are plate-shaped. The SiC wafer 50 is placed on the plate-shaped support section 82b with the C-surface 12 facing downwards. For example, the SiC wafer 50 is placed on the plate-shaped support section 82b such that, in plan view, it completely overlaps the plate-shaped support section 82b. The SiC wafer 50 is placed on the plate-shaped support section 82b, for example, in a state where it is in contact with the support section 82b in a portion including the center of the SiC wafer 50 or the entire SiC wafer 50 in plan view.

[0088] In the batch-type vertical diffusion furnace 80c, a specific SiC wafer 50 is separated from a SiC wafer 50 directly below it by the plate-shaped support sections 82b. Therefore, the diffusion of O2 gas, generated from the carbon surface 12 of the specific SiC wafer 50 as a result of the reactions of equations (1) and (2), to the SiC wafer 50 directly below it is suppressed, and excessive oxidation by the O2 gas in the SiC wafer 50 directly below it is suppressed. For example, in the batch-type vertical diffusion furnace 80c, the adjacent SiC wafers 50 are separated by the plate-shaped support section 82b.

[0089] As described above, the use of the batch-type vertical diffusion furnace 80c suppresses variations in the thickness of the gate oxide films 5 among the SiC wafers 50 in the batch. Furthermore, the influence of O2 gas generated as a result of the reactions of equations (1) and (2) is suppressed; therefore, the in-plane uniformity of the thickness of the gate oxide film 5 formed on the Si surface 13 of each SiC wafer 50 in the batch is improved.

[0090] If on the lower surface of the SiC wafer 50 in step S6 (see Fig. 17) As 0.75 µm or more of the interlayer insulating film 5 remains, the amount of O2 gas escaping from the lower surface of the SiC wafer 50 in step S7 decreases (see Fig. 17) is generated. Therefore, the O2 gas that bypasses and diffuses around the plate-shaped support part areas 82b is reduced, and the variations in the thickness of the gate oxide films 5 under the SiC wafers 50 in the batch are suppressed with higher accuracy. <D. Vierte erfindungsgemäß einsetzbare Ausführungsform>

[0091] Fig. Figure 21 is a diagram illustrating a configuration of a batch-type vertical diffusion furnace 80d used in the fourth embodiment. The inventive method for producing a semiconductor device of the fourth embodiment differs from the inventive method for producing the semiconductor device of the first embodiment in that in step S7 (see Figure 21) Fig. 17) instead of the batch-type vertical diffusion oven 80, the batch-type vertical diffusion oven 80d is used. Although Fig. Figure 21 illustrates a case in which the SiC dummy wafer 51 is not used. In the fourth embodiment, the SiC dummy wafer 51 can also be placed between the Si monitoring wafer 52 and the SiC wafer 50, as in the first embodiment. Except for this configuration, the method for fabricating the semiconductor device according to the fourth embodiment is the same as the method for fabricating the semiconductor device according to the first embodiment.

[0092] In comparison with the batch-type vertical diffusion oven 80 used in the first and second embodiments, the batch-type vertical diffusion oven 80d of the fourth embodiment further comprises partitions 84. The batch-type vertical diffusion oven 80d is otherwise similar to the batch-type vertical diffusion oven 80.

[0093] In the batch-type vertical diffusion furnace 80d, a wafer supported by a specific support section 82a and a wafer supported by a support section 82a in the adjacent stage are separated by a partition 84. In the batch-type vertical diffusion furnace 80c, for example, the adjacent SiC wafers 50 are separated by the plate-shaped support section 82b.

[0094] The partition 84 suppresses the diffusion of O2 gas generated from the lower surface of the SiC wafer 50 into the SiC wafer 50 directly below it in step S7, and an oxidation reaction by O2 gas in the SiC wafer 50 directly below it is suppressed. As a result, variations in the thickness of the gate oxide film 5 under the SiC wafers 50 are suppressed. Furthermore, the diffusion of O2 gas is suppressed; therefore, the uniformity in the plane of the thickness of the gate oxide film 5 on the Si surface 13 in each SiC wafer 50 in the batch is improved.

[0095] If on the lower surface of the SiC wafer 50 in step S6 (see Fig. 17) As 0.75 µm or more of the interlayer insulating film 9 remains, the amount of O2 gas escaping from the lower surface of the SiC wafer 50 in step S7 decreases (see Fig. 17) is generated. Therefore, the O2 gas that bypasses and diffuses around the partitions 82b is reduced, and the variations in the thickness of the gate oxide films 5 under the SiC wafers 50 in the batch are suppressed with higher accuracy.

[0096] To prevent the gas generated by the SiC wafer 50 from bypassing and diffusing around the partition 84, it is desirable that the size of the partition 84 be equal to or larger than the size of the wafer. For example, in step S7 (see Fig. 17) the SiC wafer 50 is supported by the support section 82a in such a placement or arrangement that, in plan view, the entire SiC wafer 50 overlaps the partition 84.

[0097] The partitions 84 can be integrated with the boat 82 or can be removed from the boat 82.

[0098] If the partitions 84 are removable from the boat 82, the boat 82 can be easily handled and the vertical diffusion oven 80d of the batch type can be easily set up and maintained. <E. Fünfte erfindungsgemäß einsetzbare Ausführungsform>

[0099] Fig. 22 is a diagram showing a configuration of the batch-type vertical diffusion furnace 80e used in the fifth embodiment and the placement of wafers in step S7 (see Fig. 17) illustrated. The inventive method for manufacturing a semiconductor device of the fifth embodiment differs from the inventive method for manufacturing the semiconductor device of the first embodiment in that, in step S7, the vertical diffusion furnace 80e of the batch type is used instead of the vertical diffusion furnace 80 of the batch type. Fig. Figure 22 illustrates a case in which the SiC dummy wafer 51 is not used. Except for this configuration, the inventive method for fabricating the semiconductor device according to the fifth embodiment is the same as the inventive method for fabricating the semiconductor device according to the first embodiment.

[0100] In comparison with the batch-type vertical diffusion furnace 80 used in the first and second embodiments, the batch-type vertical diffusion furnace 80e differs in that, in addition to the gas introduction line 83, the gas introduction line 83a is provided. By using the gas introduction line 83a, the batch-type vertical diffusion furnace 80e can supply more O2 gas or O3 gas to an area between a set of support part areas 82a that are adjacent in the direction in which a plurality of wafers are stacked than it can supply O2 gas or O3 gas to an area between another set of support part areas 82a that are adjacent in the direction in which the plurality of wafers are stacked.

[0101] In the inventive method for manufacturing the semiconductor device according to the fifth embodiment, in step S7 (see Fig. 17) In addition to oxygen supplied through gas inlet line 83, O2 gas or O3 gas is selectively supplied through gas inlet line 83a between the Si monitoring wafer 52 and the SiC wafer 50. This supplies more O2 or O3 gas to the area between the Si monitoring wafer 52 and the SiC wafer 50 than to the area between the SiC wafers 50. If in step S7 (see Fig. 17) If a dummy wafer is used, O2 gas or O3 gas is supplied to the area between the dummy wafer and the SiC wafer 50 via the gas introduction line 83a. This results in more O2 or O3 gas being supplied to the area between the dummy wafer and the SiC wafer 50 than to the area between the SiC wafers 50 themselves.

[0102] As mentioned above, in the Fig. 18 illustrated results of the first embodiment of the gate oxide film 5, which is placed on the SiC wafer 50 directly below the monitoring wafer or the dummy wafer in step S7 (see Fig. 17) is formed, thinner than the gate oxide film 5, which is formed on the SiC wafer 50 placed directly below the SiC wafer 50 in step S7 (see Fig. 17) is formed.

[0103] In the inventive method for manufacturing the semiconductor device of the fifth embodiment, O2 gas or O3 gas is preferably supplied from the gas introduction line 83a to the upper surface of the SiC wafer 50 placed directly below the monitoring wafer or the dummy wafer, and this causes the oxidation reaction by the O2 or O3 gas simply on the upper surface of the SiC wafer 50 placed below the monitoring wafer or the dummy wafer. Therefore, the fluctuations in the thickness of the gate oxide film 5 under the SiC wafers 50 in the batch are suppressed.

[0104] The vertical diffusion oven 80e of the batch type may also not include the gas inlet line 83a. In this case, as described in Fig. As illustrated in Figure 23, the gas introduction line 83 is provided with an opening 831 on its lateral surface in addition to an opening 830 in the tube 81. By supplying O2 gas or O3 gas from the opening 831 preferably to the area between the monitoring wafer and the SiC wafer 50 placed directly below the monitoring wafer, or to the area between the dummy wafer and the SiC wafer 50 placed directly below the dummy wafer, variations in the thickness of the gate oxide film 5 under the SiC wafers 50 in the batch are suppressed.

[0105] Although the first embodiment described that if 0.75 µm or more of the interlayer insulating film 9 is present on the lower surface of the SiC wafer 50 in step S6 (see Fig. 17) If the difference in the thickness of the gate oxide films 5 under the SiC wafers 50 in the batch can be suppressed to 0.8 nm or less in step S7, the variations in the thickness of the gate oxide films 5 under the SiC wafers 50 in the batch are suppressed together with higher accuracy using the fifth embodiment. In this case, in step S7 (see Fig. 17) the amount of oxidizing gas supplied by the gas introduction line 83a is adjusted according to the thickness of the interlayer insulating film 9 formed on the lower surface of the SiC wafer 50. When the SiC dummy wafer 51 is placed between the SiC wafer 50 and the Si monitoring wafer 52, the amount of oxidizing gas supplied by the gas introduction line 83a is adjusted according to the thickness of the interlayer insulating film 9 formed on the lower surface of the SiC wafer 50 and the thickness of the interlayer insulating film 9 formed on the lower surface of the SiC dummy wafer 51 in step 7 (see Fig. 17) discontinued.

[0106] In the present invention, the embodiments can be combined, suitably modified or omitted without deviating from the scope of the invention.

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