Integrated circuit with single-wire JTAG test interface with test-enable signaling via a fourth voltage range

Abstract

Integrated Circuit (IC) wherein the integrated circuit (IC) includes a one-wire test interface for testing this integrated circuit (IC), wherein the single-wire test interface has exactly one test data bus connection (TEST) for one data line (TOW) and wherein the integrated circuit (IC) has a positive supply voltage connection (VDD) and wherein the integrated circuit (IC) has a negative supply voltage terminal (GND) as a reference potential terminal for a reference potential line (GND) at a reference potential (V DIS ) exhibits and where, in the following, the term data line level refers to the data bus voltage between the potential of the data line (TOW) minus the reference potential (V). DIS ) the reference potential line (GND), wherein the integrated circuit (IC) is configured to be connected to a power source via a positive supply voltage terminal (VDD) and a reference potential line (GND), and wherein the integrated circuit (IC) is configured to be supplied with electrical energy via the positive supply voltage terminal (VDD) and the reference potential line (GND), and wherein the integrated circuit (IC) is configured to detect data line levels that are in a first voltage range (V B1 ) or in a second voltage range (V B2 ) or in a third voltage range (V B3 ) or in a fourth voltage range (V B4 ) relative to the reference potential (V DIS ) of the reference potential line (GND) and where a total voltage range constitutes the first voltage range (V B1 ) and the second voltage range (V B2) and the third voltage range (V B3 ) includes and where the fourth voltage range (V B4 ) differs from the total voltage range and where the first voltage range (V B1 ) and the second voltage range (V B2 ) and the third voltage range (V B3 ) do not overlap and wherein the integrated circuit (IC) is configured such that a data line level in the total voltage range activates a test state of the microelectronic circuit, and wherein the integrated circuit (IC) is configured to provide a data line level in the fourth voltage range (V B4 ) deactivated the test state of the microelectronic circuit, and wherein the integrated circuit (IC) is configured to provide a data line level in the first voltage range (V B1) signals a first logical value to the microelectronic circuit (IC), and the integrated circuit (IC) is configured to provide a data line level in the second voltage range (V B2 ) signals a second logical value to the microelectronic circuit (IC), and wherein the integrated circuit (IC) is configured to provide a data line level in the third voltage range (V B3 ) signals a third logical value to the microelectronic circuit (IC), and wherein the integrated circuit (IC) is configured such that a temporal sequence of first logic values ​​and / or second logic values ​​and / or third logic values ​​represents a test signal sequence for the integrated circuit (IC), and wherein the integrated circuit (IC) is configured so that this test signal sequence controls a test of the microelectronic circuit (IC) when the microelectronic circuit (IC) is in a test state.

Description

Field of invention

[0001] The invention relates to an integrated circuit comprising a single-wire test interface with test enable signaling for testing this integrated circuit (IC) and using a data protocol with four voltage ranges.

[0002] This invention relates generally to the testing, programming and emulation of integrated circuits, and more particularly, to the testing, programming and emulation of integrated circuits using the JTAG protocol, wherein all data and also the test enable signal are transmitted over a single-wire data bus. General introduction

[0003] The JTAG protocol has developed into one of the leading tools for programming, testing, debugging, and emulating integrated circuits. Using a process known as boundary-scan, a host processor can control the state of an integrated circuit. Specifically, the host processor, acting as the master, is able to program and, if necessary, initialize the integrated circuit as a slave via a special interface, the JTAG interface according to the IEEE 1149 standard. Furthermore, the host processor is able to read the state of the integrated circuit after a predetermined number of test system clock periods of the JTAG interface according to the IEEE 1149 standard, or upon detection of a predetermined event, or to modify it during operation of the integrated circuit (i.e., the slave).This also includes stopping the integrated circuit or forcing it to change states or changing memory contents.

[0004] The invention thus relates to a method and a device for testing and / or controlling and / or programming integrated circuits and microsystems, including microelectromechanical systems (MEMS) and integrated microelectrooptical systems (MEOS), where these assume the role of the slave. Such systems are typically controlled via a JTAG test bus according to the IEEE 1149 standard. This bus has a test data port with typically five test connections: 1. at least one serial test data input TDI, 2. at least one serial test output TDO, 3. at least one test mode input TMS, 4. at least one test clock input TCK, 5. an optional test reset input TRST, 6. a test enable input (test enable input) TEN.

[0005] In the semiconductor manufacturer's end-of-band test, a test system signals to the integrated circuit or microsystem or microelectromechanical system (MEMS) or integrated microelectrooptical system (MEOS) under test via the separate test enable input TEN that the respective integrated circuit or microsystem or microelectromechanical system (MEMS) or integrated microelectrooptical system (MEOS) under test should assume a test state or a normal operating state.

[0006] The problem addressed by this document is that this test enable input TEN requires an additional chassis connector, which incurs additional costs.

[0007] Since the multi-connection method has been known for several decades, reference is made here to the relevant technical literature (IEEE 1149.1 4-wire JTAG protocol). This document also refers to the IEEE 1149.7 standard.

[0008] This IEEE 1149 specification describes circuits that can be added to an integrated circuit to provide access to the on-chip test access ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry proposed in the standard uses the IEEE 1149.1-2001 standard as a foundation, providing backward compatibility while adding new functionality to support testing and application debugging. Six classes of 1149.7 test access ports (TAP.7s), T0–T5, are defined in the standard, with each class providing incremental capabilities that build on those of the lower classes. Class T0 provides the startup behavior specified in 1149.1 when multiple TAPs are present on the chip. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance.It also offers an optional hot-connect feature that prevents system corruption when connecting to a powered-on system. Class T3 supports operation in a four-wire serial or star-scan topology. Class T4 enables communication with a two-pin or four-pin interface. Two-pin operation serializes 1149.1 transactions and enables higher test clock rates. Class T5 provides the ability to perform data transfers concurrently with scanning, supports the use of functions other than scanning, and enables control of TAP.7 pins for custom debug technologies in a manner that ensures current and future interoperability.

[0009] None of the interfaces described in the IEEE 1149 standard requires a single data transmission port.

[0010] Here is just a brief description: The JTAG protocol according to the IEEE 1149 standard comprises five signal groups in the basic standard that are exchanged between the emulation unit, which contains the host processor, and the integrated circuit as the slave. The TCK signal represents the test system clock and synchronizes the internal state machine of the JTAG test interface according to the IEEE 1149 standard of the integrated circuit. The TMS signal controls the state of the test controller of the JTAG interface of the integrated circuit, which represents the slave. Depending on the state of the test controller, the JTAG test interface of the integrated circuit performs different operations. The TDI input represents a serial input for test data. The TDO output represents a serial output for test data. The two inputs TMS and TDI are typically, but not necessarily, sampled on the rising TCK edge.The TDO output typically also changes its data with the falling edge of the TCK signal. The individual TCK, TMS, and TDI signals form the test data input signals. The TDO signal represents the test data output signal. With the rising TCK edge and with a suitable setting of a test controller's internal test register, the test data is shifted serially via the serial test data input TDI into various shift register chains, so-called scan paths, in the integrated circuit as a slave. At the same time, the original content of the respective scan chain is output at the serial test data output TDO. State vectors of finite state machines within the integrated circuit can be part of the scan chain. Thus, changing the contents and states, or controlling these contents and states, of the memory cells of the scan chains via this interface is easily possible in the state of the art.Here we refer again to the specialist literature. Further state of the art

[0011] In recent years, the semiconductor industry has repeatedly attempted to reduce the number of connections used in order to limit the size of the required packages and thus reduce manufacturing costs. Various relevant documents have been disclosed for this purpose. One example is US patent application US 2007 / 0 033 465 A1. The technology disclosed therein does not allow for consistent conversion of the data of the IEEE 1149.1 4-Wire JTAG protocol into the data of the method described therein, and vice versa. The device arrangement and method described therein require synchronized time slots between the test bus master, i.e., the host processor, and the test bus slave, i.e., the integrated circuit to be tested, programmed, or debugged (programming errors removed).In case of a lack of temporal synchronization of the access of the test bus master and the test bus slave to the test data bus, the TDO output driver of the slave and the master output driver (typically a push-pull stage) can create a short circuit if they simultaneously transmit access to the test data line.

[0012] DE 10 2015 004 436 B3 describes a device and a method for combining the above-mentioned test terminals 1 to 5 in time-division multiplexing and by using a protocol with three voltage levels as data line levels in such a way that the device can perform the end-of-band test and / or debugging of the circuit to be tested via a single test terminal.

[0013] The technical teaching of DE 10 2015 004 436 B3 does not solve the problem of how the test enable terminal TEN can also be integrated into the test data interface. Particularly critical in this case is that accidental activation of the test state of the integrated circuit under test, the microsystem under test, the microelectromechanical system (MEMS), or the integrated microelectrooptical system (MEOS) under test must be strictly avoided within the framework of functional safety as defined in ISO 26262.

[0014] DE 10 2015 004 433 B3 discloses a test data bus between a first sub-device, the master, and a second sub-device, the slave. The data bus of DE 10 2015 004 433 B3 has a reference potential line with a reference potential and a data line. The data bus interface of the master of DE 10 2015 004 433 B3 has a first switchable voltage source with a first internal resistance, which can connect the data line to a first potential. The data bus interface of the master of DE 10 2015 004 433 B3 has a second switchable voltage source with a second internal resistance, which can connect the data line to a second potential. The data bus interface of the slave of DE 10 2015 004 433 B3 has a third switchable voltage source with a third internal resistance, which can connect the data line of DE 10 2015 004 433 B3 to a third potential, which is preferably equal to the second potential.The data line of DE 10 2015 004 433 B3 is held at an average potential by a fourth voltage source, in particular a pull circuit, between a fourth potential, which is preferably equal to the second and third potentials, and the first potential, with a fourth internal resistance. According to the technical teaching of DE 10 2015 004 433 B3, the value of the average potential lies between the value of the first potential and the value of the second potential and / or between the value of the first potential and the value of the third potential. In the case of the technical teaching of DE 10 2015 004 433 B3, the first internal resistance is smaller than the other internal resistances. In the case of the technical teaching of DE 10 2015 004 433 B3, the fourth internal resistance is greater than the other internal resistances.

[0015] DE 10 2015 004 434 B3 discloses a data bus and corresponding sub-devices, which particularly relate to the data bus between a first sub-device, the master, and a second sub-device, the slave. The data bus of DE 10 2015 004 434 B3 has a reference potential line with a reference potential and a data line for transmitting data and a test system clock between the master and slave. Data is transmitted bidirectionally between the master and the slave of DE 10 2015 004 434 B3 via the data line of DE 10 2015 004 434 B3. A test system clock with a test system clock period, which is divided into a first half-clock period and a second half-clock period, is additionally transmitted via the data line of DE 10 2015 004 434 B3.The slave of DE 10 2015 004 434 B3 has a first device, in particular a first comparator, which compares the signal level in the form of a signal voltage between the reference potential of the reference potential line and the potential of the data line with a first threshold signal. The slave of DE 10 2015 004 434 B3 also has a second device, in particular a second comparator, which compares the signal level in the form of a signal voltage between the reference potential of the reference potential line and the potential of the data line with a second threshold signal. According to the technical teaching of DE 10 2015 004 434 B3, the first threshold is different from the second threshold. According to DE 10 2015 004 434 B3, the first and second threshold values ​​thus define three signal voltage ranges between the operating voltage and the reference potential of the reference potential line of DE 10 2015 004 434 B3.The middle voltage range of DE 10 2015 004 434 B3 is limited as a second voltage range upwards or downwards by a first voltage range, and wherein at the same time the second voltage range of DE 10 2015 004 434 B3 is limited downwards or upwards, but in each case differently than the first voltage range, by a third voltage range. The data on the data line of DE 10 2015 004 434 B3 is transmitted in time-spaced or successive time slot packets of at least three successive time slots, each lasting one test system clock period. According to the technical teaching of DE 10 2015 004 434 B3, a first time slot and a second time slot typically contain a control data item and / or a first data item, which are each transmitted from the master to the slave.According to the technical teaching of DE 10 2015 004 434 B3, a third time slot contains a second datum that is transmitted from the slave to the master, the master receiving this second datum, and the second datum, according to the technical teaching of DE 10 2015 004 434 B3, is transmitted only in the second voltage range (VB2) and third voltage range (VB3). According to the description of DE 10 2015 004 434 B3, the data is transmitted in one half-clock period of the at least two half-clock periods (T1H, T2H) of a test system clock period (T). According to the technical teaching of DE 10 2015 004 434 B3, the test system clock is transmitted by a clock signal in the first voltage range (TB1) during the other half-clock period of the at least two half-clock periods (T1H, T2H) of the test system clock period (T).

[0016] From DE 10 2015 004 435 B3, a method for operating a data bus between a first sub-device, the master, and a second sub-device, the slave, is known, wherein the data bus has a reference potential line with a reference potential and a data line. The method of DE 10 2015 004 435 B3 comprises the steps a. bidirectional transmission of data via the data line between master and slave according to the technical teaching of DE 10 2015 004 435 B3, b. simultaneous transmission of a clock signal via the data line from the master to the slave according to the technical teaching of DE 10 2015 004 435 B3 with a test system clock period which is divided into at least a first half-clock period and a second half-clock period, c. cComparing the signal level on the data line in the form of a signal voltage between the reference potential of the reference potential line and the potential of the data line according to the technical teaching of DE 10 2015 004 435 B3 with a first threshold value, in particular that of a first threshold value signal, by a first device of the slave, in particular a first comparator, d. d Comparing the signal level on the data line in the form of a signal voltage between the reference potential on the reference potential line and the potential of the data line according to the technical teaching of DE 10 2015 004 435 B3 with a second threshold value different from the first threshold value, in particular that of a second threshold value signal, by a second device of the slave, in particular a second comparator, wherein the first and second threshold values ​​between an operating voltage and the reference potential of the reference potential line define three signal voltage ranges, wherein a middle voltage range as a second voltage range is limited upwards or downwards by a first voltage range and wherein the second voltage range is limited upwards or downwards by a third voltage range, but in the opposite direction to the first voltage range, e. Transmitting the data on the data line in time slot packets of at least three consecutive time slots, each lasting one test system clock period, in accordance with the technical teaching of DE 10 2015 004 435 B3, whereby the order of the time slots within the sequence of these at least three time slots can be selected system-specifically, f. Transmitting at least one control date and / or a first date in a first time slot and in a second time slot from the master to the slave according to the technical teaching of DE 10 2015 004 435 B3, wherein the control date and the first date can be compatible in particular with the data of the IEEE1149.1 4-wire test data bus and wherein the slave receives the control date and the first date g. Transmitting a second datum in a half-clock period of the at least two half-clock periods of the test system clock period in the second voltage range and in the third voltage range on the data line from the slave to the master in a third time slot of the at least three consecutive time slots according to the technical teaching of DE 10 2015 004 435 B3, the master receiving this second datum, h. Transmitting a control date and / or a first date in a half-clock period of the at least two half-clock periods of the test system clock period of the relevant time slot, in the second voltage range and third voltage range on the data line from the master to the slave in the first and / or second time slot of the at least three consecutive time slots according to the technical teaching of DE 10 2015 004 435 B3, wherein the slave receives the control date and the first date, wherein the transmission of the data occurs by changing the potential on the data line between I. the first voltage range on one side and the third voltage range on the other side and / or II. the second voltage range on one side and the third voltage range on the other side and / or III. the third voltage range on one side and the first voltage range on the other side, i. Transmitting a test system clock in the other half-clock period of the at least two half-clock periods of the test system clock period of the respective time slot, typically in each of the at least three time slots according to the technical teaching of DE 10 2015 004 435 B3, wherein no data is sent in this half-clock period and wherein the transmission of the test system clock in the respective time slot is effected by a change of the potential on the data line between the first voltage range on the one side and the second voltage range and / or third voltage range on the other side and a change in the opposite direction, j. according to the technical teaching of DE 10 2015 004 435 B3, three logical states are used for bidirectional transmission of data on the data line by master and slave, k. and wherein, according to the technical teaching of DE 10 2015 004 435 B3, each logical state is assigned to one, typically exactly one, voltage range of the potential of the data line; l. temporarily closing a dominant switch, which may also be a transistor or other semiconductor switch, to temporarily generate a first of the three logical states on the data line according to the technical teaching of DE 10 2015 004 435 B3, whereby the potential of the data line is forced into the first voltage range; m. temporarily switching on a first switchable current source in the master and / or by temporarily switching on a second switchable current source to generate a second of the three logical states on the data bus according to the technical teaching of DE 10 2015 004 435 B3; characterized by the step of generating a third of the three logical states on the data line by a pull circuit if none of the other logical states are present on the data bus, in that the pull circuit (R0H, R0L) raises the potential of the data line to a medium potential in the second voltage range. Task

[0017] The proposal is therefore based on the object of creating a solution that does not have the above-mentioned disadvantages of the prior art and that does not have a separate test enable connection TEN. Preferably, the technical solution should have further advantages. It is therefore the object of the invention to propose an arrangement with a single-wire test data bus with test activation via the single-wire test data bus and to provide a suitable protocol and method for bidirectional transmission on this test data bus.

[0018] The device and method according to the two independent claims solve the problem. This object is thus achieved by the technical teaching of the independent claims. Further embodiments may be the subject of subclaims. Solution to the task

[0019] The method proposed here for activating a single-wire test interface of a micro-integrated circuit IC and for testing this micro-integrated circuit IC solves the problem according to the proposal in that the proposed method and the associated device use a data transmission protocol with four voltage levels as data line levels instead of a data transmission protocol with three voltage levels.

[0020] The present proposal achieves the above and other objects according to the present proposal by providing an interface device SVIC of the microintegrated circuit IC with a JTAG unit that can exchange a time sequence of time-multiplexed signals by means of an interface device with the interface device SVIC of the integrated circuit IC. The method and device according to the present proposal format the signals in such a way that all information required by the JTAG TAP unit to perform a test is transmitted serially via this interface device. In contrast to the technical teaching of DE 10 2015 004 436 B3, this also includes the transmission of the test enable signal TEN of the test enable terminal of the JATG test interface from the prior art. This has the advantage that the test enable terminal can be omitted.

[0021] For this purpose, the interface device of the bus master transmits the test signals and the test enable signal TEN via the data line TOW to the integrated circuit IC by means of a test signal which has a test signal voltage value relative to a reference potential V DIS which essentially has four data line levels in four different voltage ranges (V B1 , V B2 , V B3 , V B4 ) may have. Preferred arrangement of the voltage ranges

[0022] To keep the notation synchronized with document DE 10 2015 004 436 B3, the first voltage range corresponds to V B1 , the first voltage range V B1 , DE 10 2015 004 436 B3 and the second voltage range V B2 the second voltage range V B2 DE 10 2015 004 436 B3 and the third voltage range V B3 the third voltage range V B3 DE 10 2015 004 436 B3.

[0023] In the example presented here, the Fig. 1, deviating from the technical teaching of DE 10 2015 004 436 B3, the amounts of the voltage values ​​of the data line TOW for third logical values ​​are now in the third voltage range V B3 below the magnitude of the voltage value of the data line TOW for second logical values ​​in the second voltage range V B2 and below the magnitude of the voltage value of the data line TOW for first logical values ​​in the first voltage range V B1 .

[0024] In the example presented here, the Fig. 1, deviating from the technical teaching of DE 10 2015 004 436 B3, the amounts of the voltage values ​​of the data line TOW for second logical values ​​are now in the second voltage range V B2 above the magnitude of the voltage value of the data line TOW for third logical values ​​in the third voltage range V B3and below the magnitude of the voltage value of the data line TOW for first logical values ​​in the first voltage range V B1 .

[0025] In the example presented here, the Fig. 1, deviating from the technical teaching of DE 10 2015 004 436 B3, the amounts of the voltage values ​​of the data line TOW for first logical values ​​are now in the first voltage range V B1 , above the magnitude of the voltage value of the data line TOW for third logical values ​​in the third voltage range V B3 and above the magnitude of the voltage value of the data line TOW for second logical values ​​in the second voltage range V B2 .

[0026] According to the proposal of the technical teaching presented here in this document of the Fig. 1, the magnitudes of the voltage values ​​of the data line TOW for fourth logical values ​​are in the fourth voltage range V B4 as follows: The magnitudes of the voltage values ​​of the data line TOW for fourth logical values ​​in the fourth voltage range V B4 Firstly, they are below the amount of the voltage value of the data line TOW for third logical values ​​in the third voltage range V B3 . The magnitudes of the voltage values ​​of the data line TOW for fourth logical values ​​in the fourth voltage range V B4 Secondly, they are below the amount of the voltage value of the data line TOW for second logical values ​​in the second voltage range V B2 . The magnitudes of the voltage values ​​of the data line TOW for fourth logical values ​​in the fourth voltage range V B4 Thirdly, they are below the value of the voltage of the data line TOW for the first logical values ​​in the first voltage range V B1 This distinguishes the technical teaching presented here from the state of the art.

[0027] However, this is only one possibility for the voltage arrangement of the voltage ranges VB1 , V B2 , V B3 and V B4 .

[0028] Preferably, the first voltage range V B1 , and the second voltage range V B2 and the third voltage range V B3 and the fourth voltage range V B4 not among each other.

[0029] In the following, the document presented here describes the other arrangements of the four voltage ranges V B1, V B2 , V B3 and V B4 based on the Fig. 1 to 4.

[0030] Obviously, the micro-integrated circuit IC can provide the interface device SVIC presented here as a test interface with positive or negative voltage levels (data line levels) of the voltage of the data line TOW with respect to the reference potential V DlS In addition to the different arrangements of the four voltage ranges according to the Fig. 1 to 4, the expert arrives by multiplying the voltages between the data line TOW and the reference potential V DIS with -1 to four further possible functionally equivalent arrangements of the voltage ranges relative to the reference potential V DIS . The document presented here therefore also claims to describe these voltage range arrangements.

[0031] In order to keep the text concise and clear, the document presented here describes only positive values ​​of the voltage of the data line TOW compared to the reference potential V DlS the reference voltage line GND. However, the technical teaching of the document presented here also explicitly includes negative values ​​of the voltage of the data line TOW with respect to the reference potential V DISthe reference voltage line GND. Preferably, a microintegrated circuit IC with a proposed interface device SVIC as a test interface uses either only positive values ​​of the voltage of the data line TOW relative to the reference voltage line GND or, alternatively, only negative values ​​of the voltage of the data line TOW relative to the reference voltage line GND. For this reason, the exemplary arrangement of the voltage ranges V B1, V B2 , V B3 , V B4 described in the preceding text by means of the magnitudes of the voltage values ​​of the voltage of the data line TOW relative to the reference voltage line GND.

[0032] In the examples of Fig. 1 and Fig. 2, the test enable signal TEN is proposed and particularly preferably active when the magnitude of the voltage value of the electrical voltage of the data line TOW relative to a reference potential GND is above a TOW threshold value V0 in the first voltage range V B1 , or in the second voltage range V B2 or in the third voltage range V B3 As suggested and particularly preferred, the test enable signal TEN is in the examples of Fig. 1 and Fig. 2 is not active if the magnitude of the voltage value of the electrical voltage of the data line TOW relative to the reference potential GND is below the TOW threshold value V0 in a fourth voltage range V B4 In the examples of Fig. 3 and Fig. 4, the test enable signal TEN is proposed and particularly preferably active when the magnitude of the voltage value of the electrical voltage of the data line TOW is lower than a supply voltage V IObelow a TOW threshold V0 in the first voltage range V B1 , or in the second voltage range V B2 or in the third voltage range V B3 As suggested and particularly preferred, the test enable signal TEN is in the examples of Fig. 3 and Fig. 4 not active if the magnitude of the voltage value of the electrical voltage of the data line TOW compared to the supply voltage V IO above the TOW threshold V0 in a fourth voltage range V B4If the test-enable signal TEN is active, the test input of the interface device SVIC of the microintegrated circuit IC preferably operates essentially like a test input according to the technical teaching of DE 10 2015 004 436 B3. If the test-enable signal TEN is not active, the interface device SVIC of the microintegrated circuit IC does not receive any data from the production test system that the microintegrated circuit IC controls via the data line TOW. If the test-enable signal TEN is not active, a locking circuit BC within the microintegrated circuit IC preferably prevents the test input TEST of the interface device SVIC of the microintegrated circuit IC from influencing the normal operation of the microintegrated circuit IC.

[0033] In case of an arrangement of the voltage ranges V B1 , V B2 , V B3 , V B4 according to the Fig. 1 or Fig. 2 can be a direct electrical connection between a line on the reference potential V DIS and the data line TOW of the microintegrated circuit IC, the test interface of the interface device SVIC of the microintegrated circuit IC is preferably switched off. This requires that it be integrated with the microintegrated circuit IC in an application circuit in this way. In the case of an arrangement of the voltage ranges V B1 , V B2 , V B3 , V B4 according to the Fig. 1 or Fig. 2, a very short short-circuit line VL can then realize such a direct connection. In the case of an arrangement of the voltage ranges V B1 , V B2 , V B3 , V B4 according to the Fig. 1 or Fig. 2, the short-circuit line is preferably a line VL between the reference potential line GND or a functionally equivalent line on the one hand and the data line TOW of the micro-integrated circuit IC on the other. In the case of an arrangement of the voltage ranges V B1 , V B2 , V B3 , V B4 according to the Fig. 1 or Fig. 2, such a short-circuit line VL can then prevent unwanted test states of the microintegrated circuit IC on a circuit carrier of the application circuit. This is also possible in the event of strong electromagnetic interference during subsequent operation in the vehicle.

[0034] In case of an arrangement of the voltage ranges V B1 , V B2 , V B3 , V B4 according to the Fig. 3 or Fig. 4 can be a direct electrical connection between a line on the supply voltage V IOand the data line TOW of the microintegrated circuit IC, the test interface of the interface device SVIC of the microintegrated circuit IC is preferably switched off. This requires that it be integrated with the microintegrated circuit IC in an application circuit in this way. In the case of an arrangement of the voltage ranges V B1 , V B2 , V B3 , V B4 according to the Fig. 3 or Fig. 4, a very short short-circuit line VL can then realize such a direct connection. In the case of an arrangement of the voltage ranges V B1 , V B2 , V B3 , V B4 according to the Fig. 3 or Fig. 4, the short-circuit line is preferably a line VL between the supply voltage line VDD or a functionally equivalent line on the one hand and the data line TOW of the microintegrated circuit IC on the other hand. In the case of an arrangement of the voltage ranges V B1 , V B2 , V B3 , V B4 according to the Fig. 3 or Fig. 4, such a short-circuit line VL can then prevent unwanted test states of the microintegrated circuit IC on a circuit carrier of the application circuit. This is also possible in the event of strong electromagnetic interference during subsequent operation in the vehicle.

[0035] It is therefore typically safety-relevant that the fourth voltage range V B4for the data line level of the data line TOW, which deactivates the test interface of the interface device SVIC of the microintegrated circuit IC by an active test enable signal TEN, preferably at the upper or lower end of the three voltage ranges V B1, V B2 , V B3 In the following, the document presented here refers to the three voltage ranges V B1 , V B2 , V B3 together as the total voltage range. Preferably, the fourth voltage range V B4 above or below the total voltage range to the total voltage range.

[0036] The order of the three voltage ranges V B1 , V B2 , V B3 within the total voltage range may vary.

[0037] For example, voltages in the first voltage range V B1 , under the voltages in the second voltage range V B2and third voltage range V B3 This situation is shown by the Fig. 2 and Fig. 3.

[0038] For example, voltages in the first voltage range V B1 , over the voltages in the second voltage range V B2 and third voltage range V B3 This situation is shown by the Fig. 1 and Fig. 4.

[0039] For example, voltages in the third voltage range V B3 under the voltages in the second voltage range V B2 and first voltage range V B1 This situation is shown by the Fig. 1 and Fig. 4.

[0040] For example, voltages in the third voltage range V B3 above the voltages in the second voltage range V B2 and first voltage range V B1 This situation is shown by the Fig. 2 and Fig. 3.

[0041] According to the technical teaching of the document presented here, the second voltage range V B2 always between the first voltage range V B1 and the third voltage range V B3 . Summary of the arrangement of the voltage ranges

[0042] The voltage levels in the fourth voltage range V B4 The voltages of the data line TOW as data line levels deactivate the test interface of the interface device SVIC of the microintegrated circuit IC. As explained above, it is therefore typically safety-relevant that the fourth voltage range V B4 at the upper or lower end of the voltage ranges (V B1 , V B2 , V B3 , V B4 ) in the order of the voltage ranges (V B1 , V B2 , V B3 , V B4 ). Therefore, the following sequences are conceivable: (V B1 , V B2 , V B3 , VB4 ) ( Fig. 1); (V B4 , V B1 , V B2 , V B3 ) ( Fig. 4); (V B3 , V B2 , V B1 , V B4 ) ( Fig. 2); (V B4 , V B3 , V B2 , V B1 ) ( Fig. 3) Operation of the test interface

[0043] The document presented here explains the operation of the test interface, i.e. the interface device SVIC of the micro-integrated circuit IC, using the example Fig. 5. The Fig. 5 the voltage levels correspond to the data line levels of the Fig. 2. It is easy for the expert to determine the values ​​of the threshold signals and the construction of the Fig. 5 so that the voltage levels, i.e. the data line levels, of one of the other Fig. 1, Fig. 3, or 4 correspond.

[0044] According to the technical teaching of the document presented here, the test enable signal TEN is not active if the voltage value of the data line TOW is below the reference potential V DlS the reference potential line GND is preferably in the fourth voltage range V B4 is located.

[0045] The test enable signal TEN is active when the voltage value of the data line TOW is lower than the reference potential V DlS the reference potential line GND is preferably in the fourth voltage range V B4The test enable signal TEN can be a real signal in the form of a real line of the microintegrated circuit IC. However, the test enable signal TEN can also be the class of states of the microintegrated circuit IC in which the microintegrated circuit IC is in one of its intended test states. A programming state of the microintegrated circuit IC that is set and / or operated via the test interface TEST of the interface device SVIC of the microintegrated circuit IC is considered a test state within the meaning of this document. Voltage values ​​of the voltage between the data line TOW and the reference potential V DIS of the reference potential line GND are data line levels within the meaning of this document. Data line levels in a voltage range that is not the fourth voltage range V B4are typically within a total voltage range. All states of the microintegrated circuit IC that require operation of the test interface of the microintegrated circuit IC with data line levels within the total voltage range are test states within the meaning of this document.

[0046] As described, the micro-integrated circuit IC comprises the aforementioned locking circuit BC. If the test enable signal TEN is not active, the aforementioned locking circuit BC within the micro-integrated circuit IC prevents the test input TEST of the micro-integrated circuit IC from behaving like a test input according to the technical teaching of DE 10 2015 004 436 B3. The aforementioned locking circuit BC then also prevents an alternative arrangement of the voltage ranges (V B1 , V B2 , V B3 , V B4) that the test input TEST of the micro-integrated circuit IC behaves like a test input according to the technical teaching of DE 10 2015 004 436 B3. If the test enable signal TEN is not active, then an alternative arrangement of the voltage ranges (V B1 , V B2 , V B3 , V B4 ) the locking circuit BC within the microintegrated circuit IC, that the test input of the interface device SVIC of the microintegrated circuit IC affects the normal operation of the microintegrated circuit IC.

[0047] First of all, the document presented here assumes in the following description that the test enable signal TEN is active.

[0048] The method and device according to the present proposal transmit, in a test state with the test enable signal TEN active, all data values ​​of the JTAG boundary scan protocol in designated time slots (TIN0, TIN1, TDO). In addition to the time multiplexing of the JTAG control signals, as mentioned above, the proposed interface device uses four different voltage ranges (V B1 , V B2 , V B3 , V4) to 1. at least the data of the serial test data input TDI and 2. at least the data of one serial test output TDO and 3. at least the control data of the test mode input TMS for controlling the JTAG test controller of the integrated circuit IC and 4. at least the test clock to supply the JTAG test controller of the micro-integrated circuit IC with its test system clock TCK and 5. at least one test enable signal TEN and 6. an optional test reset signal TRST Preferably, the JTAG test controller of the micro-integrated circuit IC comprises said locking device BC, which prevents a test state of the micro-integrated circuit IC when the voltage value of the voltage between data line TOW and reference potential V DIS in the fourth voltage range V B4 In this case, the voltage value of the voltage between data line TOW and reference potential V DIS in the fourth voltage range V B4 The JTAG test controller uses its locking device BC to prevent the micro-integrated circuit IC from entering a test state.

[0049] The proposal presented in this document therefore primarily concerns a data bus with a data line TOW between a first sub-device, the bus master, and a second sub-device, the bus slave. The bus slave is identical to the aforementioned microintegrated circuit IC, whose states the bus master is intended to control or change via the data line TOW using the data protocol presented here. The states of the microintegrated circuit IC include test states and normal operation states. Normal operation states are not test states within the meaning of this document. Test states are not normal operation states within the meaning of this document. This data bus preferably has only one reference potential line GND at a reference potential and preferably a single data line TOW.The reference potential line GND can, for example, be the metallic and electrically conductive vehicle body. In contrast to the prior art (DE 10 2015 004 436 B3), the proposed method also transmits the test enable signal TEN via this single data line TOW. As a result, the device proposed in this document requires only a single additional electrical connection of the microelectronic circuit IC and thus eliminates the test enable connection TEN, unlike in the prior art (DE 10 2015 004 436 B3). In order to be able to both send data into the microintegrated circuit IC, the slave, and read data from the microintegrated circuit IC, the interface device SVIC of the microintegrated circuit IC can send and receive data preferably bidirectionally via the data line TOW.The proposed method, which the interface device SVIC of the microintegrated circuit IC executes, must not only transmit and receive data, but also receive a synchronization signal. For this purpose, the bus master transmits the test system clock TCK, preferably via the data line TOW, using the proposed method, in particular from the bus master to the interface device SVIC of the bus slave, i.e., to the microintegrated circuit IC. Data extraction (SDA)

[0050] To enable this communication, the bus slave, i.e., the microintegrated circuit IC, preferably has a first device. The first device compares the voltage value between the data line TOW and the reference potential V DlSa reference potential line GND with a first threshold value. To simplify the description, the document presented here refers to the term "voltage value of the voltage between the data line TOW with respect to the reference potential V DlS a reference potential line GND" as a "data line level". Preferably, the interface device SVIC of the microintegrated circuit IC comprises this first device. Preferably, the first device comprises a first comparator C2H or a functionally equivalent device that compares the data line level or a value derived from the data line level with the value of a first threshold signal V 2H , compare. The first threshold signal V 2H can also be a register value or any other programmable, adjustable or constructively set value. In the example of the Fig. 5 a voltage divider generates the first threshold signal V 2Hfrom the voltage difference between the potential of the supply voltage line and the supply voltage V IO and the reference potential V DlS the reference potential line GND. Extraction of the SCLK clock

[0051] Furthermore, the bus slave, i.e., the interface device SVIC of the integrated circuit IC, preferably has a second device. The second device compares data line levels with a second threshold value. The interface device SVIC of the microintegrated circuit IC preferably comprises this second device. The second device preferably comprises a second comparator C2L or a functionally equivalent device that compares the data line level or a value derived from the data line level with the value of a second threshold signal V 2L , compare. The second threshold signal V 2Lcan also be a register value or another programmable, adjustable or constructively set value.

[0052] If the first threshold V 2H from the second threshold V 2L different and the threshold values ​​are within the supply voltage range between the reference potential V DIS and the supply voltage V IO these two threshold values ​​V 2H , V 2L the three voltage ranges V B1 , V B2 , V B3 of the total voltage range is preferably defined and specified. The fourth voltage range V B4 excluded from this.

[0053] The first threshold V 2H preferably limits the third voltage range V B3 against the second voltage range V B2 away.

[0054] The second threshold V 2L preferably limits the second voltage range VB2 against the first voltage range V B1 , away.

[0055] The TOW threshold V0 limits the Fig. 1 and the Fig. 3 the third voltage range V B3 against the fourth voltage range V B4 away.

[0056] The TOW threshold V0 limits the Fig. 2 and the Fig. 4 the first voltage range V B1 , towards the fourth voltage range V B4 away.

[0057] The first comparator C2H and the second comparator C2L on the slave side - the side of the micro-integrated circuit IC - detect in which voltage range of the three voltage ranges V B1 , V B2 , V B3 of the total voltage range the data line level of the data line TOW is currently at when the test enable signal TEN is active.

[0058] In the Fig. 1 and in the Fig. 2 define the first threshold V 2L and the second threshold V 2H the three signal voltage ranges V B1 , V B2 , V B3 the three voltage ranges of the test operation and the test conditions. In the Fig. 1 and in the Fig. 2 are the three signal voltage ranges V B1 , V B2 , V B3 the three voltage ranges of the test operation and the test states between the operating voltage V IO the interface device SVIC on the one hand and the TOW threshold V0 on the other.

[0059] In the Fig. 3 and the Fig. 4 define the first threshold V 2L and the second threshold V 2H the three signal voltage ranges V B1 , V B2 , V B3 the three voltage ranges of the test operation and the test conditions. In the Fig. 3 and the Fig. 4 are the three signal voltage ranges V B1 , V B2 , V B3 of the three voltage ranges of the test operation and the test states between the reference potential V DlS the reference potential line GND on the one hand and the TOW threshold value V0 on the other.

[0060] For clarity, we call the middle voltage range of the three signal voltage ranges V B1 , V B2 , V B3 as a second voltage range V B2 This will be in the Fig. 1 and the Fig. 4 of the first voltage range V B1 , is limited to the upper limit. This is shown in the Fig. 2 and the Fig. 3 of the first voltage range V B1 , limited downwards. We deliberately leave open whether the first voltage range V B1to create a voltage range with more positive or more negative voltages than the voltages of the middle, second voltage range V B2 This is because the system, as described above, also works with reversed voltage polarities. At the same time, the second voltage range V B2 to the other side of the voltage, i.e. downwards or upwards, but in each case the other way round than in the first voltage range V B1 , by a third voltage range V B3 In contrast to the state of the art, the method presented here works with a fourth voltage range V B4 .

[0061] In contrast to the technical teaching of DE 10 2015 004 436 B3, in the example of Fig. 1 and the Fig. 2 the TOW threshold V0 is now not at the reference potential V DISthe reference potential line GND. In contrast, the technical teaching of the document presented here raises the TOW threshold V0 by the threshold V0 of the locking device BC of the interface device SVIC of the microintegrated circuit IC. Thus, the voltage range scheme of the method proposed here allocates the said fourth voltage range V B4 on.

[0062] The fourth voltage range V B4 therefore limited, for example, in the Fig. 1 the third voltage range V B3 in the technical teaching of the document presented here, preferably downwards.

[0063] The fourth voltage range V B4 therefore limited, for example, in the Fig. 2 the first voltage range V B1 , in the technical teaching of the document presented here preferably downwards.

[0064] The fourth voltage range V B4 therefore limited, for example, in the Fig. 3 the third voltage range V B3 in the technical teaching of the document presented here, preferably upwards.

[0065] The fourth voltage range V B4 therefore limited, for example, in the Fig. 4 the first voltage range V B1 , in the technical teaching of the document presented here preferably upwards.

[0066] It is expressly stated, as in the Fig. 3 and Fig. 4 conceivable, the fourth voltage range V B4 above the other voltage ranges V B1, V B2 and V B3 of the total voltage range. Such an arrangement is expressly covered by the disclosure of the document presented here.

[0067] Of course, the use of other voltage ranges for other purposes is also conceivable.

[0068] According to the technical teaching of Fig. 1 of the document presented here, the second threshold V 2L down and the supply voltage V IO up the first voltage range V B1 .

[0069] According to the technical teaching of Fig. 2 of the document presented here, the second threshold V 2L upwards and the TOW threshold V0 downwards the first voltage range V B1 .

[0070] According to the technical teaching of Fig. 3 of the document presented here, the second threshold V 2L upwards and the reference potential V DlS down the first voltage range V B1 .

[0071] According to the technical teaching of Fig. 4 of the document presented here, the second threshold V 2L downwards and the TOW threshold V0 upwards the first voltage range V B1 .

[0072] According to the technical teaching of Fig. 1 and Fig. 2 of the document presented here, the TOW threshold V0 limits the fourth voltage range V B4 .

[0073] According to the technical teaching of Fig. 3 and Fig. 4 of the document presented here, the TOW threshold V0 limits the fourth voltage range V B4 .

[0074] If the micro-integrated circuit IC to be tested is to be in the normal operating state and thus in a normal state and not in a test state, the proposed method keeps the potential of the data line TOW relative to the reference potential V DIS at a potential in the fourth voltage range V B4. This allows the interface device SVIC of the bus slave—that is, the microintegrated circuit IC—to recognize that the bus slave should not enter a test state. Instead, the interface device SVIC of the bus slave recognizes that the bus slave, that is, the microintegrated circuit IC, should operate in an operating state other than the test state. Therefore, the interface device SVIC of the microintegrated circuit IC preferably signals other device parts of the integrated circuit IC that they may enter states other than the test state and / or the test state.

[0075] The method proposed in this document first changes the operating state of the microintegrated circuit IC to be tested to the selected test state at the start of a test. To this end, the bus master preferably first changes the operating state of the microintegrated circuit IC to be tested as a bus slave to the intended test state by signaling via the TOW data line. Furthermore, the bus master uses the method proposed here to signal a change in the test enable state TEN to the interface device SVIC of the microintegrated circuit IC via the TOW data line. To this end, for example, the bus master signals a change in the test enable state TEN of the microintegrated circuit IC via the TOW data line of the interface device SVIC of the microintegrated circuit IC operating as a bus slave.For this purpose, the bus master uses the method presented here to change the potential of the data line TOW in relation to the reference potential of the reference potential line GND, i.e. the data line level, in one process step in such a way that the data line level is no longer in the fourth voltage range V. B4 This typically causes the test enable state TEN to change to the active state. The active state of the test enable state TEN allows the interface device SVIC of the micro-integrated circuit IC and other device parts of the micro-integrated circuit IC to enter test states. In the example mentioned, the bus master therefore changes the data line level in such a way that the data line level is no longer in the fourth voltage range V B4For the signaling of the test data, the bus master uses the procedure presented here to ensure that the data line level instead has a potential in a voltage range of the other of the three aforementioned signal voltage ranges V B1 , V B2 , V B3 , i.e., in the entire voltage range. This allows the interface device SVIC of the microintegrated circuit IC to recognize that a test is to be performed.

[0076] To bidirectionally transmit data from the bus master, i.e., the host processor, to the slave, i.e., the integrated circuit IC, the bus master and the slave transmit data via the TOW data line using the proposed method in at least three consecutive time slots (TIN0, TIN1, TDO). In the example, the bus master transmits data back and forth to the bus slave, i.e., the integrated circuit IC, in at least three consecutive time slots (TIN0, TIN1, TDO), for example, via the TOW data line.

[0077] According to the method presented here, the temporal position of the respective time slot TIN0, TIN1, TDO determines who has transmission authorization in the respective time slot. Typically, the proposed method assigns two time slots TIN0, TIN1 to the bus master and one time slot TDO to the bus slave in the packet of three consecutive time slots TIN0, TIN1, TDO for transmission by the bus master and the bus slave, respectively. The relative time slot position according to the method presented here within the packet of at least three time slots TIN0, TIN1, TDO is preferably, but not necessarily, always the same. Particularly preferably, the first time slot TIN0 and the second time slot TIN1 contain a control date and / or a first date that the bus master transmits from the bus master to the bus slave, i.e., to the microintegrated circuit IC, using the proposed method.In particular, the control date and the first date can be compatible with the data of the IEEE 1149.1 4-wire test data bus. The bus slave, which is typically the integrated circuit IC under test, typically receives the control date and the first date via the aforementioned interface device SVIC, according to the technical teaching presented here.

[0078] The micro-integrated circuit IC transmits as a bus slave using the proposed method in the third time slot TDO the data to be sent from the micro-integrated circuit IC to the bus master, preferably only in the second voltage range V B2 and in the third voltage range V B3 . The micro-integrated circuit IC transmits as a bus slave using the proposed method in the third time slot TDO the data to be sent from the micro-integrated circuit IC to the bus master, preferably not in the first voltage range V B1, or fourth voltage range V B4 .

[0079] Thus, according to the invention, the third time slot TDO contains a second datum, which the bus slave, i.e., the microintegrated circuit IC, transmits from the bus slave, i.e., the microintegrated circuit IC, to the bus master using the proposed method. The bus master receives this second datum of the third time slot TDO, which originates from the bus slave, i.e., the microintegrated circuit IC. The bus slave, i.e., the microintegrated circuit IC, preferably transmits the second datum only in the second voltage range V using the method proposed here. B2 and in the third voltage range V B3 and not in the fourth voltage range V B4 and not in the first voltage range V B1. At the same time, however, the bus master transmits the clock TCK in each of the three time slots TIN0, TIN1, TDO using the proposed method. The clock TCK has a test system clock period T. Each test system clock period T preferably has a first half-clock period T 1H and a second half-stroke period T 2H Preferably, the first half-cycle period T 1H and the second half-stroke period T 2H together the test system clock period T. Preferably, the first half-clock period T 1H and the second half-stroke period T 2H The clock signal TCK fluctuates between the first voltage range V B1 , in the first half-stroke period T 1H , T 2H a test system clock period T on the one hand and the second voltage range V B2 or third voltage range V B3 in the second half-stroke period T 2Ha test system clock period T on the other side. The clock signal TCK signals the clock signal TCK. The interface device SVIC of the microintegrated circuit IC can therefore detect the clock signal TCK by the interface device SVIC of the microintegrated circuit IC detecting a change in the data line level from the second voltage range V B2 or third voltage range V B3 on the one hand in the first voltage range V B1, or a reverse change is detected. Since this data line level is greater than the TOW threshold V0, the interface device SVIC of the bus slave, i.e. the microintegrated circuit IC, simultaneously detects that the bus slave, i.e. the microintegrated circuit IC, should still be in the test state and that the test enable signal TEN is 1. Therefore, the interface device SVIC of the bus slave, i.e. the microintegrated circuit IC, also treats the clock signal TCK extracted from the signal on the data line TOW as the clock signal SCKL of the interface device SVIC of the microelectronic circuit IC. The microintegrated circuit IC preferably uses this clock SCLK of the interface device as the clock TCK_I of a test data interface. The microintegrated circuit IC preferably comprises this test data interface. The test data interface is preferably a JTAG test data interface.Preferably, the interface device SVIC of the microintegrated circuit IC serves to convert a time-division multiplexed data protocol into a space-division multiplexed data protocol. The interface device SVIC preferably adapts a JTAG data bus interface of the microintegrated circuit IC to a data bus TOW with a time-division multiplexed data transmission protocol. The associated second comparator C. 2L or the corresponding second device of the interface device SVIC of the microintegrated circuit IC can detect the crossing of the corresponding second threshold value V 2Lby data line level detection. This enables the bus slave's interface device SVIC to reliably extract the test system clock TCK on the slave side, i.e., the integrated circuit IC side, from the temporal potential profile of the data line level, independently of the transmitted TDI and TDO data. Compared to the design of the other signals, the clock imprinting structure is preferably selected so that the clock transmitter on the bus master side can preferentially overwrite all other data line level sources for data line levels. Data line level sources refer to sources that can be active in parallel on the TOW data line and can imprint data line levels into the TOW data line.

[0080] In a special version of the proposal, this clock transmitter on the bus master side is characterized by the fact that, in the active test state of the bus slave, the bus master and the bus slave use four logical states for bidirectional data transmission on the data line TOW. These four logical states exhibit a hierarchy. A normal state of the bus slave, in which the data line potential is in the fourth voltage range V B4 preferably has the highest priority to ensure that a test state of the microelectronic circuit IC cannot be accidentally activated. The bus master preferably imprints this normal state with a very low resistance. This allows the bus master to enforce the normal state of the bus slave, i.e., the microintegrated circuit IC, in the data bus system. If • the housing GH of the integrated circuit IC with this integrated circuit IC is permanently installed on a circuit carrier PCB of the later application circuit and • the use of the interface device SVIC of the micro-integrated circuit IC is not desired and • the micro-integrated circuit IC a voltage range schemes of the Fig. 1 and Fig. 2 expected for the control or • alternatively, the micro-integrated circuit IC a voltage range schemes of the Fig. 3 and Fig. 4 for the control, a short-circuit line and the data line TOW as short as possible can ensure that the data line potential at the input of the interface device SVIC of the micro-integrated circuit IC is in the fourth voltage range V B4 In the case of a voltage range scheme of the Fig. 1 and Fig. 2, the short-circuit line VL preferably connects the reference potential line GND and the data line TOW. In the case of a voltage range scheme of the Fig. 3 and Fig. 4 connects the short-circuit line VL preferably to the supply voltage V IO and the data line TOW. This short-circuit line forces the microintegrated circuit IC to be in a normal state during normal operation and not in a test state. Instead of the short-circuit line, a resistor R short be provided.

[0081] This resistance R short The data line potential at the input of the interface device SVIC of the micro-integrated circuit can then be set to the fourth voltage range V B4The advantage is that the data interface of a bus master connected via a connector, for example, can then overwrite this potential. The bus master can then put the interface device SVIC of the microintegrated circuit IC of the circuit carrier PCB into a test state. The bus master can then, as described here, address the microintegrated circuit IC using test signals.

[0082] A clock state in which the bus slave and thus the micro-integrated circuit IC is in the test state and in which the data line potential is in the first voltage range V B1 , preferably has the second highest priority. During the test, other transmitting devices can have a clock state in which the bus slave and thus the microintegrated circuit IC is in the test state and in which the data line potential is in the first voltage range V B1, with a potential in the fourth voltage range V B4 overwritten. In this case, these other transmitting devices are connected to the data bus line TOW. As suggested, only the bus master can, for example, set a data line level on the data line TOW that is in the first voltage range V B1 , or in the second voltage range V B2 or in the third voltage range V B3 with a potential (data line level) in the fourth voltage range V B4 overwrite.

[0083] A production test system for testing the microintegrated circuit IC preferably comprises the bus master or emulates its behavior. Using the bus master of the production test system, the production test system can test at least parts of the microintegrated circuit IC via the data line TOW and the reference potential line GND. Within the meaning of the document presented here, the production test system can also be a programming system. For example, using the bus master of the programming system, the programming system can program the data contents of memory cells of one or more programmable memories of the microintegrated circuit IC via the data line TOW. For example, using the bus master of the programming system, the programming system can read out at least parts of the data contents of memory cells of one or more memories of the microintegrated circuit IC via the data line TOW.

[0084] This ensures that during production testing, the bus master and the bus slave essentially always operate synchronously with respect to the TCK clock, at least with regard to the base clock of the interface device of the bus slave and the corresponding interface device of the bus master. The bus master uses the TCK clock to transmit data to the bus slave. The bus master thus uses the TCK clock to transmit data to the microintegrated circuit IC. The bus master receives data from the bus slave via the TOW data line with the TCK clock. The bus master thus receives data from the microintegrated circuit IC via the TOW data line with the TCK clock. As described above, the bus master transmits this TCK clock to the bus slave and thus to the microintegrated circuit IC by means of edge transitions between the first voltage range V B1 , on the one hand and the second voltage range V B2 and the third voltage range V B3on the other hand and vice versa.

[0085] In this first logical state, the data line TOW is switched to the first voltage range V B1 To use this first logical state for the realization of an exemplary voltage range scheme according to the Fig. 2, the interface device SVIC of the bus master preferably has a dominant switch S 1H The interface device SVIC of the bus master is preferably an interface of the host processor of the production test system. For the purpose of implementing a voltage range scheme, for example, according to the Fig. 2 forces the dominant switch S 1H the data bus TOW, for example, to the TOW threshold V0. The dominant switch S 1H preferably forces the data bus TOW to the TOW threshold V0 in the corresponding half-clock periods of the at least two half-clock periods T 1H , T 2Hthe respective test system clock period T p . In the examples of Fig. 1 to 4, a data exchange period T comprises three test system clock periods T p , which represent the three time slots TIN0, TIN1, TDO.

[0086] In this first logical state, the data line TOW is switched to the first voltage range V B1 To use this first logical state for the realization of an exemplary voltage range scheme according to the Fig. 1, the interface device SVIC of the bus master preferably has a dominant switch S 1H The interface device SVIC of the bus master is preferably an interface of the host processor of the production test system. For the purpose of implementing a voltage range scheme, for example, according to the Fig. 1 forces the dominant switch S 1Hthe data line level of the data bus TOW, for example, to the data line level of the supply voltage V IO . The dominant switch S 1H forces the data line level of the data bus TOW to the data line level of the supply voltage V IO preferably in the corresponding half-clock periods of the at least two half-clock periods T 1H , T 2H the respective test system clock period T p .

[0087] In this first logical state, the data line TOW is switched to the first voltage range V B1 To use this first logical state for the realization of an exemplary voltage range scheme, for example, according to the Fig. 3, the interface device SVIC of the bus master, i.e. the host processor of the production test system, preferably has a dominant switch S 1HThe interface device SVIC of the bus master is preferably an interface of the host processor of the production test system. For the purpose of implementing an exemplary voltage range scheme according to the Fig. 3 the dominant switch S forces 1H the data line level of the data bus TOW, for example, to the data line level of the reference potential supply voltage V DIS . The dominant switch S 1H preferably forces the data line level of the data bus TOW, for example, to the data line level of the reference potential supply voltage V DIS in the corresponding half-clock periods of at least two half-clock periods T 1H , T 2H the respective test system clock period T p .

[0088] In this first logical state, the data line TOW is switched to the first voltage range V B1To use this first logical state for the realization of a voltage range scheme, for example, according to the Fig. 4, the interface device SVIC of the bus master, i.e. the host processor of the production test system, preferably has a dominant switch S 1H The interface device SVIC of the bus master is typically the interface of the host processor of the production test system. For the purpose of implementing an exemplary voltage range scheme according to the Fig. 4 the dominant switch S forces 1H the data line level of the data bus TOW, for example, to the data line level of the TOW threshold V0. The dominant switch S 1H forces the data line level of the data bus TOW preferentially to the data line level of the TOW threshold V0 in the corresponding half-clock periods of the at least two half-clock periods T 1H , T 2Hthe respective test system clock period T p .

[0089] If the internal resistance of other transmitters is higher than that of the dominant switch S 1H , these other transmitters can no longer overwrite this periodic potential modulation.

[0090] In order to transmit data with a first logical value, the transmitters of the bus master and / or the bus slave keep the potential of the data line TOW in the second voltage range V B2 . In order to transmit data with a first logical value, the transmitters of the bus master and / or the bus slave can also measure the potential of the data line TOW from a voltage range V B2 different voltage range in this second voltage range V B2 The potential of the data line TOW is preferably set to the reference potential V DIS The bus slave here is again the microintegrated circuit IC.

[0091] In order to transmit data with a second logical value, the transmitters of the bus master and / or the bus slave keep the potential of the data line TOW in the third voltage range V B3 . In order to transmit data with a second logical value, the transmitters of the bus master and / or the bus slave can also measure the potential of the data line TOW from a voltage range V B3 different voltage range in this third voltage range V B3 The second logical value is not the first logical value and is different from it. The potential of the data line TOW is preferably connected to the reference potential V DIS The bus slave here is again the microintegrated circuit IC.

[0092] For this purpose, the respective transmitting unit, i.e. the bus master or the microintegrated circuit IC as bus slave, feeds a current into the data line TOW. This leads to a changed voltage drop across the resistors R1, R2, R3. The microintegrated circuit IC uses the switch S to supply this current. 2L . The switch S 2L draws a current from the data line TOW via resistor R4. The switch S 2L thus represents a voltage in the range of the third voltage range V B3 on when the bus master with its switch S 1H does not imprint the higher priority TCK signal on the TOW data line.

[0093] The fourth resistor R4 is in the example the Fig. 5 and the Fig. 1 preferably chosen so that • with a closed fourth switch S 4L and • with an open switch S 3L (TEN=1) and • with a closed switch S 3H (TEN=1) and with an open switch S 1H (TCK=0) and • with a closed switch S 1L (TCK=0)the data line level is in the third voltage range V B3 is located.

[0094] In the example of Fig. 5 and the Fig. 1 is located • with an open switch S 4L and • with an open switch S 3L (TEN=1) and • with a closed switch S 3H (TEN=1) and • with an open switch S 1H (TCK=0) and • with a closed switch S 1L (TCK=0)the data line level is in the second voltage range V B2 or in the first voltage range V B1 .

[0095] The following table shows the relative data line level V Ras the ratio of the data line level on the data line TOW against the reference potential GND divided by the supply voltage V IO The first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 should all have essentially the same values.

[0096] If the test enable signal TEN=0, the AND gates, which are marked with an “&” in the Fig. 3, the closing of the high-side switch S 2H and S 1H .

[0097] This means that the switches S 3L , S 2L , S 1L closed. The transmission switch S 4L of the bus slave, i.e. the micro-integrated circuit IC, is open. This means that the data line level is at the reference potential V DIS the reference potential line GND. (See also Fig. 5)

[0098] In the TIN0 time slot and in the TIN1 time slot, the bus master (the production test system) sends data to the bus slave, i.e. the microintegrated circuit IC, together with the transmit clock TCK.

[0099] The following table can be used to send data from the production test system to the microintegrated circuit IC. Where R pullup for the effective electrical resistance of the interconnection of resistors R1, R2, R3 from the data line TOW to the supply voltage line V IO . Furthermore, R pulldown for the effective electrical resistance of the interconnection of resistors R1, R2, R3 from the data line TOW to the reference potential line GND to reference potential V DlS . The data line level is defined as the relative data line level V R relative to the supply voltage V IO specified. TEN TDI TCK SDA_OUTB R pullup / R R pulldown / R V R 1 0 0 0 1 (1||1)=0,5 1 / 3 1 0 1 0 0 1 1 1 1 0 0 (1 || 1) = 0,5 1 2 / 3 1 1 1 0 0 kein 1

[0100] Fig. 1 shows a simplified schematic of the corresponding data line levels.

[0101] It is obvious that a cutting level at V 2L = 5 / 6 is suitable for extracting the clock signal TCK.

[0102] Equally obvious is a second cutting level V 2H =3 / 6=1 / 2 suitable for extracting the data signal TDI.

[0103] Preferably, referring to the example of Fig. 1 the interface device SVIC of the microintegrated circuit IC always switches off the output of the second comparator C2L at a falling edge of the clock signal TCK in the middle of a time slot TIN1, TIN2.

[0104] Preferably, the interface device SVIC of the microintegrated circuit IC synchronizes itself to the clock signal TCK sent by the bus master. The interface device SVIC of the microintegrated circuit IC then begins to transmit itself in the third time slot TDO. In the third time slot TDO, the bus master only transmits the clock signal. However, the bus master does not transmit any data in the third time slot TDO. This allows the microintegrated circuit IC to synchronize itself with the clock signal TCK sent by the bus master. 4L If necessary, determine the data line level depending on the date. During this transmission phase, the bus master sends in the examples of Fig. 1 and Fig. 5 TDI=1. This 1 of the bus master can then be overwritten with a 0 by the bus slave, i.e. the micro-integrated circuit IC, by the interface device SVIC of the micro-integrated circuit IC as bus slave, setting the fourth switch S 4L closes.

[0105] The following table then results for sending (see Fig. 1): TEN TDI TCK SDA_OUTB R pullup / R R pulldown / R V R 1 1 0 0 (1 || 1) = 0,5 1 2 / 3 1 1 0 1 (1 || 1) = 0,5 (1 || 1 / 3) = 0,25 1 / 3

[0106] The value of the fourth resistor R4 is preferably selected so that the analog data line levels are set for the data. Other states and switch configurations are preferably prohibited.

[0107] The first voltage range V B1 ,is sufficient in the Fig. 1 according to the Fig. 5 from the relative data line level V R =1 up to the relative data line level V R =5 / 6. The relative data line level V R =5 / 6 corresponds to the threshold value V 2L . to extract the clock TCK in the example of Fig. 1 and Fig. 5.

[0108] The second voltage range V B2 is sufficient in the Fig. 1 according to the Fig. 5 from the relative data line level V R =5 / 6 to the relative data line level V R=3 / 6=1 / 2. The relative data line level V R =1 / 2 corresponds to the threshold values ​​V 1H and V 2H to extract the data in the example of Fig. 1 and Fig. 5.

[0109] The third voltage range V B3 is sufficient in the Fig. 1 according to the Fig. 5 from the relative data line level V R =V0=1 / 3 up to the relative data line level V R =1 / 2.

[0110] The output enable switch OE establishes the actual connection between the bus master and the interface device SVIC of the microintegrated circuit IC.

[0111] A suitable polarity of the injected current shifts the voltage level of the potential of the data line TOW relative to the reference potential V DIS the reference potential line GND, i.e. the data line level, from the second voltage range V B2 into the third voltage range V B3. Should there be a simultaneous transmission using such a data stream, and the simultaneous closing of the dominant switch S 1H because of TEN=1 and TCK=1, the dominant switch S 1H Provided it is designed with sufficiently low resistance, it can dissipate the transmission current of the respective transmitter and thus overwrite this voltage level and thus the data line level and possibly also the voltage level generated by the voltage divider. Depending on the switch position, the voltage divider can comprise resistors R1, R2, R3, and R4.

[0112] This results in a clear hierarchy for an exemplary arrangement of the voltage ranges V B1 , to V B4 accordingly Fig. 1: • First, a fixed potential, imposed, for example, by a short circuit between the data line TOW and the reference potential line GND, dominates in the fourth voltage range V B4, which forces the operation of the bus slave in the normal state and reliably prevents an unwanted test state; • otherwise, the bus slave is in the test state and the switching state of the dominant switch S follows second in the hierarchy of the voltage-determining elements for the voltage on the data line TOW 1H , which forces a dominant signaling of the clock TCK; • The third element in the hierarchy of voltage-determining elements for the voltage on the data line TOW are the switches S 2H , S 2L , S 4L to signal the data.

[0113] Referring to the example of Fig. 1 and Fig. 5 In the test state, the first logical state of the data line TOW corresponds to a voltage level V0 and, for example, V R =1 / 3 in the third voltage range V B3 on the data line TOW

[0114] Referring to the example of Fig. 1 and Fig. 5 In the test state, the second logical state of the data line TOW corresponds to a voltage level V M and for example V R =2 / 3 in the second voltage range V B2 on the data line TOW

[0115] Referring to the example of Fig. 1 and Fig. 5 In the test state, the third logical state of the data line TOW corresponds to a voltage level V IO and for example V R =1 in the third voltage range V B3 on the data line TOW.

[0116] According to the proposal, the data interface of the bus master and the interface device SVIC of the microelectronic circuit IC as bus slave use the first logical state on the data line TOW exclusively for transmitting a first logical state, for example “high”, of a test system clock of the clock TCK.

[0117] According to the proposal, the data interface of the bus master and the interface device SVIC of the microelectronic circuit IC as bus slave use the second logical state and the third logical state on the data line TOW for the transmission of a second logical state, for example “low”, of the test system clock TCK.

[0118] According to the proposal, the data interface of the bus master and the interface device SVIC of the microelectronic circuit IC as bus slave use the second logical state on the data line TOW to transmit a first logical state, for example “high”, of a data signal.

[0119] According to the proposal, the data interface of the bus master and the interface device SVIC of the microelectronic circuit IC as bus slave use the third logic state on the data line TOW for the transmission of a third logic state, for example “low”, of the data signal.

[0120] If the data line TOW is in the first logical state, the data interface of the bus master and the interface device SVIC of the microelectronic circuit IC as bus slave preferentially ignore this logical state of the data line TOW for data transmission.

[0121] According to the proposal, the proposed test method uses the first logical state on the data line TOW to transmit a first logical state, for example, "high," of a test system clock signal TCK. According to the proposal, the proposed test method uses the third or second logical state on the data line TOW to transmit a second logical state, for example, "low," of the test system clock signal TCK. If the logical state on the data line TOW changes between the second logical state or the third logical state on the data line TOW, the interface device SVIC of the microelectronic circuit IC, acting as a bus slave, ignores this change. This means that the interface device SVIC of the microelectronic circuit IC preferentially ignores this change for the transmission of the test system clock TCK.The interface device SVIC of the microelectronic circuit IC then typically continues to interpret the state of the data line level of the data line TOW as a second logic state, for example “low”. Proposed procedure

[0122] The document presented here describes a method for activating a single-wire test interface of an integrated circuit IC and for testing this integrated circuit IC. An interface device SVIC of the microintegrated circuit IC represents this single-wire test interface together with a standard JTAG test interface according to IEEE 1149.7. This single-wire test interface preferably has exactly one test data bus connection TEST for preferably a single data line TOW, a positive supply voltage connection VDD for supply voltage V IOand a negative supply voltage terminal GND as a reference potential terminal for a reference potential line GND on a reference potential V DIS In the following, the term “data line level” refers to the data bus voltage between the potential of the data line TOW minus the reference potential V DIS the reference potential line GND. The method comprises connecting the positive supply voltage terminal VDD and the negative supply voltage terminal GND to a power source and supplying the integrated circuit IC with electrical power via these lines. The method further comprises setting a data line level at the beginning of a test with a voltage value in a fourth voltage range V B4 . The four voltage ranges (V B1 , V B2 , V B3 , V B4) that uses the technical teaching of the document presented here can be arranged differently. The technical teaching of the document presented here uses the fourth voltage range V B4 Preferably for signaling the test state and the normal state. Any state that does not correspond to the normal state during normal operation is a test state within the meaning of this document. The first voltage range V B1, the second voltage range V B2 and the third voltage range V B3 form the total voltage range in the sense of this document. Test states preferably use data line levels of the TOW data line in the total voltage range (V B1 , V B2 , V B3 ). Normal states preferentially use data line levels in the fourth voltage range V B4 . The fourth voltage range V B4 can be above or below the total voltage range (V B1 , V B2, V B3 ) to this total voltage range (V B1 , V B2 , V B3 ) are adjacent. The voltage sequence of the first voltage range V B1, of the second voltage range V B2 and the third voltage range V B3 can be used within the total voltage range (V B1 , V B2 , V B3 ) may vary depending on the application. The second voltage range V B2 voltage-wise between the first voltage range V B1 and the third voltage range V B3 arranged in tension.

[0123] Thus, the first voltage range V B1 , the second voltage range V B2 in a first voltage direction and the third voltage range V B3 the second voltage range V B2 in a second voltage direction that is opposite to the first voltage direction.

[0124] The method also includes generating a signal sequence with data line levels for the duration of the test. The data line levels for this signal sequence during data transmission are proposed to be in the total voltage range (V B1 , V B2 , V B3 ). During the test, the data line levels of the signal sequence are always within the total voltage range. The total voltage range, as defined in this document, includes a first voltage range V B1 , and a second voltage range V B2 and a third voltage range V B3 . The first voltage range V B1 , and the second voltage range V B2 and the third voltage range V B3 preferably do not overlap. The fourth voltage range V B4 overlaps with the other voltage ranges (V B1 , V B2 , V B3) preferentially not. A data line level on the data line TOW in the total voltage range activates a test state of the microelectronic circuit IC. A data line level on the data line TOW outside the total voltage range preferentially deactivates the test state of the microelectronic circuit IC. A data line level on the data line TOW in the first voltage range V B1 signals a first logical value to the microelectronic circuit IC. A data line level in the second voltage range V B2 signals a second logical value to the microelectronic circuit IC. A data line level in the third voltage range V B3 signals a third logical value to the microelectronic circuit IC. In the test state of the microelectronic circuit IC, the signal sequence preferably controls a test of the microelectronic circuit IC. A data line level in the fourth voltage range V B4signals a fourth logical value to the microelectronic circuit IC. The first logical value and the second logical value and the third logical value and the fourth logical value preferably differ from one another. The signaling of a fourth logical value to the microelectronic circuit IC thus preferably activates a test state of the microelectronic circuit IC and thus preferably deactivates a normal state of the microelectronic circuit IC. The signaling of a first logical value or a second logical value or a third logical value to the microelectronic circuit IC thus preferably activates a normal state of the microelectronic circuit IC and thus preferably deactivates a test state of the microelectronic circuit IC.Within the meaning of the document presented here, enabling the microelectronic circuit to be influenced, for example by allowing access to a JTAG test controller of the microelectronic circuit, is already an activation of a test state within the meaning of the document presented here and a deactivation of a normal state within the meaning of the document presented here.

[0125] In a first variant, the method comprises generating a signal sequence, in particular in the total voltage range, with data line levels for the duration of the test, signaling a clock TCK and data by means of the first logical value and the second logical value and the third logical value. Variants with fourth voltage range V B4 in the area of ​​the reference potential V DIS

[0126] The next two variants assume that the reference potential V DlS the fourth voltage range V B4according to the Fig. 1 and Fig. 2 limited.

[0127] In a second variant of the method, the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels). Signals in the fourth voltage range V B4 preferably have voltages between the reference potential V DIS e.g. at 0V and a TOW threshold V0. Subvariant of Figure 1

[0128] In the variant of the Fig. 1, the TOW threshold V0 is between the fourth voltage range V B4 and third voltage range V B3 .

[0129] In the variant of the Fig. 1 show signals in the third voltage range V B3 prefers voltages between the TOW threshold V0 and a first threshold V 2H on.

[0130] In the variant of the Fig. 1 separates the first threshold V 2Hthe fourth voltage range V B4 and the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , on the other hand.

[0131] In the variant of the Fig. 1 and in the variant of Fig. 2 have signals in the second voltage range V B2 prefers voltages between the first threshold V 2H and the second threshold V 2L on.

[0132] In the variant of the Fig. 1 separates the second threshold V 2L the first voltage range V B1 , on the one hand from the second voltage range and the third voltage range V B3 and the fourth voltage range V B4 on the other hand.

[0133] In the variant of the Fig. 1 show signals in the third voltage range V B3 prefers voltages between the first threshold V 2Hand the TOW threshold V0.

[0134] In the variant of the Fig. 1 separates the first threshold V 2H the fourth voltage range V B4 and the third voltage range V B3 on the one hand from the second voltage range V B2 and the first voltage range V B1 , on the other hand.

[0135] In a third variant of the procedure in the sub-variant of Fig. 1, the data line level, apart from overshoots and / or noise and other disturbances, only has negative voltage levels (data line levels). Signals in the fourth voltage range V B4 preferably have voltages between 0V and a TOW threshold V0. The TOW threshold V0 is in the variant of the Fig. 1 preferably between fourth voltage range V B4 and third voltage range V B3 .

[0136] In the variant of the Fig. 1 show signals in the third voltage range V B3 Voltages between the TOW threshold V0 and a first threshold V 2H In the variant of the Fig. 1 separates the first threshold V 2H the fourth voltage range V B4 and the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , on the other hand. In the variant of the Fig. 1, the TOW threshold V0 is between the fourth voltage range V B4 and third voltage range V B3 .

[0137] In the variant of the Fig. 1 have signals in the second voltage range V B2 Voltages between the first threshold V 2H and the second threshold V 2L In the variant of the Fig. 1 separates the first threshold V 2H the fourth voltage range V B4 and the third voltage range V B3on the one hand from the second voltage range V B2 and from the first voltage range V B1 , on the other hand. In the variant of the Fig. 1 separates the second threshold V 2L the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2 on the one hand from the first voltage range V B1 , on the other hand.

[0138] In the variant of the Fig. 1 have signals in the first voltage range V B1 Voltages between the second threshold V 2L and the supply voltage V IO In the variant of the Fig. 1 separates the second threshold V 2L the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2 on the one hand from the first voltage range V B1 , on the other hand. Subvariant of Figure 2

[0139] In the variant of the Fig. 2, the TOW threshold V0 is between the fourth voltage range V B4 and first voltage range V B1 .

[0140] In the variant of the Fig. 2 show signals in the third voltage range V B3 prefers voltages between the voltage value of the supply voltage V IO and a first threshold V 2H on.

[0141] In the variant of the Fig. 2 separates the first threshold V 2H the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , and from the fourth voltage range V B4 on the other hand.

[0142] In the variant of the Fig. 2 separates the second threshold V 2L the first voltage range V B1 , and the fourth voltage range V B4on the one hand from the second voltage range and the third voltage range V B3 on the other hand.

[0143] In the variant of the Fig. 2 show signals in the third voltage range V B3 prefers voltages between the first threshold V 2H and the supply voltage V IO on.

[0144] In the variant of the Fig. 2 separates the first threshold V 2H the third voltage range V B3 on the one hand from the second voltage range V B2 and the first voltage range V B1 , and the fourth voltage range V B4 on the other hand.

[0145] In a third variant of the procedure in the sub-variant of Fig. 2, the data line level, apart from overshoots and / or noise and other disturbances, only has negative voltage levels (data line levels). Signals in the fourth voltage range V B4preferably have voltages between the reference potential V DIS and a TOW threshold V0. The TOW threshold V0 is in the variant of the Fig. 2 preferably between fourth voltage range V B4 and first voltage range V B1 .

[0146] In the variant of the Fig. 2 show signals in the third voltage range V B3 Voltages between the supply voltage V IO and a first threshold V 2H In the variant of the Fig. 2 separates the first threshold V 2H the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 and from the fourth voltage range V B4 and on the other hand.

[0147] In the variant of the Fig. 2 have signals in the second voltage range V B2 Voltages between the first threshold V 2H and the second threshold V2L In the variant of the Fig. 2 separates the first threshold V 2H the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , and from the fourth voltage range V B4 On the other hand, in the variant of Fig. 2 separates the second threshold V 2L the fourth voltage range V B4 and the first voltage range V B1 , on the one hand from the third voltage range V B3 and the second voltage range V B2 on the other hand.

[0148] In the variant of the Fig. 2 have signals in the first voltage range V B1 Voltages between the second threshold V 2L and the TOW threshold V0. In the variant of the Fig. 2, the TOW threshold V0 separates the fourth voltage range V B4 on the one hand from the first voltage range V B1, and from the second voltage range V B2 and from the third voltage range V B3 On the other hand, in the variant of Fig. 2 separates the second threshold V 2L the fourth voltage range V B4 and the first voltage range V B1 on the one hand from the third voltage range V B3 and the second voltage range V B2 on the other hand. Variants with fourth voltage range V B4 in the range of the supply voltage V IO

[0149] The next two variants assume that the supply voltage potential V IO the fourth voltage range V B4 according to the Fig. 3 and Fig. 4 limited.

[0150] In a fourth variant of the method, the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels). Signals in the fourth voltage range V B4 preferably have voltages between the supply voltage potential V IO e.g. at 5V and a TOW threshold V0. Subvariant of Figure 3

[0151] In the variant of the Fig. 3 the TOW threshold V0 is between the fourth voltage range V B4 and third voltage range V B3 .

[0152] In the variant of the Fig. 3 show signals in the third voltage range V B3 prefers voltages between the TOW threshold V0 and a first threshold V 2H on.

[0153] In the variant of the Fig. 3 separates the first threshold V 2H the fourth voltage range V B4and the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , on the other hand.

[0154] In the variant of the Fig. 3 and in the variant of Fig. 4 have signals in the second voltage range V B2 prefers voltages between the first threshold V 2H and the second threshold V 2L on.

[0155] In the variant of the Fig. 3 separates the second threshold V 2L the first voltage range V B1 on the one hand from the second voltage range and the third voltage range V B3 and the fourth voltage range V B4 on the other hand.

[0156] In the variant of the Fig. 3 show signals in the third voltage range V B3 prefers voltages between the first threshold V 2H and the TOW threshold V0.

[0157] In the variant of the Fig. 3 separates the first threshold V 2H the fourth voltage range V B4 and the third voltage range V B3 on the one hand from the second voltage range V B2 and the first voltage range V B1 , on the other hand.

[0158] In the fifth variant of the procedure in the sub-variant of Fig. 3, the data line level, apart from overshoots and / or noise and other disturbances, only has negative voltage levels (data line levels). Signals in the fourth voltage range V B4 preferably have voltages between 5V and a TOW threshold V0. The TOW threshold V0 is in the variant of the Fig. 3 preferably between fourth voltage range V B4 and third voltage range V B3 .

[0159] In the variant of the Fig. 3 show signals in the third voltage range V B3Voltages between the TOW threshold V0 and a first threshold V 2H In the variant of the Fig. 3 separates the first threshold V 2H the fourth voltage range V B4 and the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , on the other hand. In the variant of the Fig. 3 the TOW threshold V0 is between the fourth voltage range V B4 and third voltage range V B3 .

[0160] In the variant of the Fig. 3 show signals in the second voltage range V B2 Voltages between the first threshold V 2H and the second threshold V 2L The first threshold V 2H separates in the variant of the Fig. 3 the fourth voltage range V B4 and the third voltage range V B3 on the one hand from the second voltage range V B2and from the first voltage range V B1 , on the other hand. The second threshold V 2L separates in the variant of the Fig. 3 the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2 on the one hand from the first voltage range V B1 , on the other hand.

[0161] In the variant of the Fig. 3 show signals in the first voltage range V B1 Voltages between the second threshold V 2L and the reference potential V DIS In the variant of the Fig. 3 separates the second threshold V 2L the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2 on the one hand from the first voltage range V B1 , on the other hand. Subvariant of Figure 4

[0162] In the variant of the Fig. 4, the TOW threshold V0 is between the fourth voltage range V B4 and first voltage range V B1 .

[0163] In the variant of the Fig. 4 show signals in the third voltage range V B3 prefers voltages between the voltage value and the reference potential V DIS and a first threshold V 2H on.

[0164] In the variant of the Fig. 4 separates the first threshold V 2H the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , and from the fourth voltage range V B4 on the other hand.

[0165] In the variant of the Fig. 4 separates the second threshold V 2L the first voltage range V B1 , and the fourth voltage range V B4 on the one hand from the second voltage range and the third voltage range V B3 on the other hand.

[0166] In the variant of the Fig. 4 show signals in the third voltage range V B3 prefers voltages between the first threshold V 2H and the reference potential V DIS on.

[0167] In the variant of the Fig. 4 separates the first threshold V 2H the third voltage range V B3 on the one hand from the second voltage range V B2 and the first voltage range V B1 , and the fourth voltage range V B4 on the other hand.

[0168] In a fifth variant of the procedure in the sub-variant of Fig. 4, the data line level, apart from overshoots and / or noise and other disturbances, only has negative voltage levels (data line levels). Signals in the fourth voltage range V B4 preferably have voltages between the supply voltage V IOand a TOW threshold V0. The TOW threshold V0 is in the variant of the Fig. 4 preferably between fourth voltage range V B4 and first voltage range V B1 .

[0169] In the variant of the Fig. 4 show signals in the third voltage range V B3 Voltages between the reference potential V DIS and a first threshold V 2H which represents the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , and from the fourth voltage range V B4 and on the other hand separates. In the variant of the Fig. 4 separates the first threshold V 2H the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , and from the fourth voltage range V B4 and on the other hand.

[0170] In the variant of the Fig. 4 have signals in the second voltage range V B2 Voltages between the first threshold V 2H and the second threshold V 2L In the variant of the Fig. 4 separates the first threshold V 2H the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 , and from the fourth voltage range V B4 on the other hand. The second threshold V 2L separates in the variant of the Fig. 4 the fourth voltage range V B4 and the first voltage range V B1 , on the one hand from the third voltage range V B3 and the second voltage range V B2 on the other hand.

[0171] In the variant of the Fig. 4 show signals in the first voltage range V B1 Voltages between the second threshold V 2L and the TOW threshold V0. In the variant of the Fig. 4 separates the second threshold V 2L the fourth voltage range V B4 and the first voltage range V B1 on the one hand from the third voltage range V B3 and the second voltage range V B2 on the other hand. Exemplary interface device SVIC of the microintegrated circuit IC for an exemplary voltage scheme of Figure 2

[0172] In the following, the document presented here describes an interface device SVIC of the micro-integrated circuit IC, which implements the voltage scheme of the Fig. 2. The expert will, if necessary, adapt the circuit by changing the switching levels according to the examples of Fig. 1, Fig. 3 or Fig. 4 adjust.

[0173] In a sixth variant of the method, the microintegrated circuit IC comprises a switching element SV1. The switching element SV1 preferably detects, based on the data line level at the test data bus connection TEST, that the microintegrated circuit IC should activate the test state. The switching element SV1 preferably has a switching threshold with a switching voltage (TOW threshold V0). The switching voltage (TOW threshold V0) preferably relates to the reference potential V DIS The data line level must exceed the switching voltage (TOW threshold V0) in order for the switching element SV1 to detect the test state to be set. The switching voltage (TOW threshold V0) is preferably above the reference potential V DIS. During the test, the data line level at the test data bus connection TEST is preferably always above the switching voltage (TOW threshold V0). The switching voltage (TOW threshold V0) is preferably set to the reference potential V DlS of the reference potential terminal GND. This preferably activates a test state of the microintegrated circuit IC for the duration of the. The magnitude range of the first voltage range V B1 , is preferably above the switching voltage (TOW threshold V0). The switching voltage (TOW threshold V0) preferably refers to the reference potential V DlS the reference potential connection GND.

[0174] In a seventh variant of the method, the magnitude of the data line level at the test data bus connection TEST is preferably always above the magnitude of the switching voltage (TOW threshold V0) plus the magnitude of a positive safety margin voltage in the first voltage range V B1 . In the seventh variant of the method, the magnitude of the data line level at the test data bus connection TEST can preferably always be in the second voltage range V B2 or in the third voltage range V B3 These two options preferentially activate a test state of the microelectronic circuit IC for the duration of the test.

[0175] In an eighth variant, the document presented here discloses a method for providing and using an integrated circuit IC. The method of the eighth variant comprises the step of providing an integrated circuit IC in a housing GH for this integrated circuit IC. The method of the eighth variant comprises the step of testing the integrated circuit IC using a method as previously described. The method of the eighth variant comprises the step of mounting the integrated circuit IC on a circuit carrier PCB. The method of the eighth variant comprises the step of electrically connecting the test data bus connection TEST to the reference potential connection GND.

[0176] In a ninth variant of the method described immediately above, the electrical connection of the test data bus connection TEST to the reference potential connection GND is carried out with an essentially minimal cable length.

[0177] In a ninth variant of the method described immediately above, the reference potential terminal GND is preferably immediately adjacent to the test data bus terminal TEST in the housing of the microintegrated circuit IC. Proposed microintegrated circuit IC

[0178] The document presented here also describes a microintegrated circuit IC with a single-wire test interface. Preferably, the single-wire test interface has exactly one test data bus connection TEST for a data line TOW, a positive supply voltage connection VDD, and a negative supply voltage connection as a reference potential connection for a reference potential line GND at a reference potential V DIS In the following, the term “data line level” refers to the data bus voltage between the potential of the data line TOW minus the reference potential V DISthe reference potential line GND. The integrated circuit IC is preferably configured to be supplied with electrical energy via the positive supply voltage terminal VDD and the negative supply voltage terminal GND. The integrated circuit IC is preferably configured to assume a normal state when the data line level has a voltage value in a fourth voltage range V B4 wherein the fourth voltage range V B4 by a first voltage range V B1 , is limited in a first voltage direction. The integrated circuit IC is preferably configured to assume a test state when the data line level reaches a voltage value in a voltage range (V B1 , V B2 , V B3 ) which is not the fourth voltage range V B4The integrated circuit IC is preferably configured to receive a signal sequence in the test state for the duration of a test. During the test, the data line levels are preferably always in a total voltage range in the first voltage direction from the fourth voltage range V B4 The total voltage range preferably comprises a first voltage range V B1 , and a second voltage range V B2 and a third voltage range V B3 .The first voltage range V B1 , and the second voltage range V B2 and the third voltage range V B3 typically do not overlap. A data line level in the overall voltage range typically activates a test state of the microelectronic circuit IC. A data line level in the first voltage range V B1signals a first logical value to the microintegrated circuit IC. A data line level in the second voltage range V B2 signals a second logical value to the microelectronic circuit IC. A data line level in the third voltage range V B3 signals a third logical value to the microelectronic circuit IC.

[0179] In a first variant of the integrated circuit IC, the signal sequence typically controls the test of the microelectronic circuit IC. The microintegrated circuit IC is preferably configured to extract a clock TCK and data SDI from the signal sequence using the first logical value, the second logical value, and the third logical value and use them for the test. Voltage range arrangementsExemplary interface device SVIC of the microintegrated circuit IC for an exemplary voltage scheme of Figure 1

[0180] In a second variant of the integrated circuit IC, the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels). Signals in the fourth voltage range V B4 preferably have voltages between reference potential V DIS and a TOW threshold V0. Signals in the third voltage range V B3 have voltages between the TOW threshold V0 and a first threshold V 2H Signals in the second voltage range V B2 have voltages between the first threshold V 2H and the second threshold V 2L Signals in the third voltage range V B3 have voltages between the second threshold V 2L and the supply voltage V IO The first threshold V 2H separates the fourth voltage range V B4 and the third voltage range V B3on the one hand from the second voltage range V B2 and from the first voltage range V B1 , on the other hand. The second threshold V 2L separates the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2 on the one hand from the first voltage range V B1 , on the other hand. The TOW threshold V0 lies between the fourth voltage range V B4 and third voltage range V B3 . Exemplary interface device SVIC of the microintegrated circuit IC for an exemplary negated voltage scheme of Figure 1

[0181] In a third variant of the integrated circuit IC, the data line level, apart from overshoots and / or noise and other disturbances, has only negative voltage levels (data line levels). Signals in the fourth voltage range V B4 preferably have voltages between reference potential VDIS and a TOW threshold V0. Signals in the third voltage range V B3 have voltages between the TOW threshold V0 and a first threshold V 2H Signals in the second voltage range V B2 have voltages between the first threshold V 2H and the second threshold V 2L Signals in the third voltage range V B3 have voltages between the second threshold V 2L and the supply voltage V IO The first threshold V 2H separates the fourth voltage range V B4 and the third voltage range V B3 on the one hand from the second voltage range V B2 and from the first voltage range V B1 on the other hand. The second threshold V 2L separates the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2on the one hand from the first voltage range V B1 on the other hand. The TOW threshold V0 lies between the fourth voltage range V B4 and third voltage range V B3 . Exemplary interface device SVIC of the microintegrated circuit IC for an exemplary voltage scheme of Figure 2

[0182] In a fourth variant of the integrated circuit IC, the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels). Signals in the fourth voltage range V B4 show voltages between the reference potential V DIS and a TOW threshold V0. Signals in the first voltage range V B1 have voltages between the TOW threshold V0 and a second threshold V 2L Signals in the second voltage range V B2 have voltages between the second threshold V 2Land the first threshold V 2H Signals in the third voltage range V B3 have voltages between the first threshold V 2H and the supply voltage V IO The first threshold V 2H separates the fourth voltage range V B4 and the first voltage range V B1 and the second voltage range V B2 on the one hand from the third voltage range V B3 on the other hand. The second threshold V 2L separates the fourth voltage range V B4 and the first voltage range V B1 on the one hand from the second voltage range V B2 and from the third voltage range V B3 on the other hand.

[0183] The TOW threshold V0 lies between the fourth voltage range V B4 and first voltage range V B1 . Exemplary interface device SVIC of the microintegrated circuit IC for an exemplary negated voltage scheme of Figure 2

[0184] In a fourth variant of the integrated circuit IC, the data line level, apart from overshoots and / or noise and other disturbances, has only negative voltage levels (data line levels). Signals in the fourth voltage range V B4 show voltages between the reference potential V DIS and a TOW threshold V0. Signals in the first voltage range V B1 have voltages between the TOW threshold V0 and a second threshold V 2L Signals in the second voltage range V B2 have voltages between the second threshold V 2L and the first threshold V 2H Signals in the third voltage range V B3 have voltages between the first threshold V 2H and the supply voltage V IOThe first threshold V 2H separates the fourth voltage range V B4 and the first voltage range V B1 and the second voltage range V B2 on the one hand from the third voltage range V B3 on the other hand. The second threshold V 2L separates the fourth voltage range V B4 and the first voltage range V B1 on the one hand from the second voltage range V B2 and from the third voltage range V B3 on the other hand. The TOW threshold V0 lies between the fourth voltage range V B4 and first voltage range V B1 . Exemplary interface device SVIC of the microintegrated circuit IC for an exemplary voltage scheme of Figure 3

[0185] In a fifth variant of the integrated circuit IC, the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels). Signals in the fourth voltage range V B4 have voltages between the potential of the supply voltage V IO and a TOW threshold V0. Signals in the third voltage range V B3 have voltages between the TOW threshold V0 and a second threshold V 2H Signals in the second voltage range V B2 have voltages between the second threshold V 2L and the first threshold V 2H Signals in the third voltage range V B3 have voltages between the first threshold V 2H and the TOW threshold V0. The first threshold V 2H separates the fourth voltage range V B4 and the third voltage range V B3on the one hand from the second voltage range V B2 and from the third voltage range V B3 on the other hand. The second threshold V 2L separates the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2 on the one hand from the first voltage range V B1 on the other hand. The TOW threshold V0 lies between the fourth voltage range V B4 and third voltage range V B3 . Exemplary interface device SVIC of the microintegrated circuit IC for an exemplary negated voltage scheme of Figure 3

[0186] In a fifth variant of the integrated circuit IC, the data line level, apart from overshoots and / or noise and other disturbances, has only negative voltage levels (data line levels). Signals in the fourth voltage range V B4have voltages between the potential of the supply voltage V IO and a TOW threshold V0. Signals in the third voltage range V B3 have voltages between the TOW threshold V0 and a second threshold V 2H Signals in the second voltage range V B2 have voltages between the second threshold V 2L and the first threshold V 2H Signals in the third voltage range V B3 have voltages between the first threshold V 2H and the TOW threshold V0. The first threshold V 2H separates the fourth voltage range V B4 and the third voltage range V B3 on the one hand from the second voltage range V B2 and from the third voltage range V B3 on the other hand. The second threshold V 2L separates the fourth voltage range V B4 and the third voltage range V B3and the second voltage range V B2 on the one hand from the first voltage range V B1 on the other hand. The TOW threshold V0 lies between the fourth voltage range V B4 and third voltage range V B3 . Exemplary interface device SVIC of the microintegrated circuit IC for an exemplary voltage scheme of Figure 4

[0187] In a fifth variant of the integrated circuit IC, the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels). Signals in the fourth voltage range V B4 have voltages between the potential of the supply voltage V IO and a TOW threshold V0 between the fourth voltage range V B4 and first voltage range V B1 Signals in the first voltage range V B1have voltages between the TOW threshold V0, which is between the fourth voltage range V B4 and first voltage range V B1 and a second threshold V 2H Signals in the second voltage range V B2 have voltages between the second threshold V 2L and the first threshold V 2H Signals in the third voltage range V B3 have voltages between the first threshold V 2H and the reference potential V DIS The first threshold V 2H separates the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2 on the one hand from the third voltage range V B3 on the other hand. The second threshold V 2L separates the fourth voltage range V B4 and the first voltage range V B1 on the one hand from the second voltage range V B2and from the third voltage range V B3 on the other hand. The TOW threshold V0 lies between the fourth voltage range V B4 and first voltage range V B1 . Exemplary interface device SVIC of the microintegrated circuit IC for an exemplary negated voltage scheme of Figure 4

[0188] In a sixth variant of the integrated circuit IC, the data line level, apart from overshoots and / or noise and other disturbances, has only negative voltage levels (data line levels). Signals in the fourth voltage range V B4 have voltages between the potential of the supply voltage V IO and a TOW threshold V0. Signals in the first voltage range V B1 have voltages between the TOW threshold V0 and a second threshold V 2H Signals in the second voltage range V B2 have voltages between the second threshold V2L and the first threshold V 2H Signals in the third voltage range V B3 have voltages between the first threshold V 2H and the reference potential V DIS The first threshold V 2H separates the fourth voltage range V B4 and the third voltage range V B3 and the second voltage range V B2 on the one hand from the third voltage range V B3 on the other hand. The second threshold V 2L separates the fourth voltage range V B4 and the first voltage range V B1 on the one hand from the second voltage range V B2 and from the third voltage range V B3 on the other hand. The TOW threshold V0 lies between the fourth voltage range V B4 and first voltage range V B1 . Example interface device SVIC with switching element for detecting the activity of the test enable signal TEN

[0189] In a sixth variant of the integrated circuit IC, the microintegrated circuit IC has a switching element SV1 that detects, based on the data line level at the test data bus terminal TEST, that the microintegrated circuit IC should activate the test state. The switching element SV1 preferably has a switching threshold with a switching voltage (TOW threshold value V0) relative to the reference potential V DIS which must be exceeded in order for the switching element SV1 to recognize the test state to be set. The switching voltage (TOW threshold V0) is preferably in the examples of Fig. 1 and Fig. 2 above the reference potential V DIS and in the examples of Fig. 3 and Fig. 4 preferably below the potential of the supply voltage line V IO .

[0190] The integrated circuit IC preferably assumes the test state when, in the example of the voltage range arrangements, the Fig. 1 and Fig. 2 the magnitude of the data line level at the test data bus connection TEST is always above the switching voltage (TOW threshold V0). The switching voltage (TOW threshold V0) is typically limited to the reference potential V DIS of the reference potential connection GND.

[0191] The integrated circuit IC preferentially switches to the test state when, in the example of the voltage range arrangements, the Fig. 3 and Fig. 4 the magnitude of the data line level at the test data bus connection TEST is always below the magnitude of the switching voltage (TOW threshold V0). The magnitude of the switching voltage (TOW threshold V0) is typically limited to the reference potential V DIS of the reference potential connection GND.

[0192] In the example of Fig. 1 is the magnitude range of the third voltage range V B3 immediately above the magnitude of the switching voltage (TOW threshold V0) relative to the reference potential V DIS the reference potential connection GND.

[0193] In the example of Fig. 2 is the magnitude range of the first voltage range V B1 immediately above the magnitude of the switching voltage (TOW threshold V0) relative to the reference potential V DIS the reference potential connection GND.

[0194] In the example of Fig. 3 is the magnitude range of the third voltage range V B3 immediately below the magnitude of the switching voltage (TOW threshold V0) relative to the reference potential V DIS the reference potential connection GND.

[0195] In the example of Fig. 4 is the magnitude range of the first voltage range V B1immediately below the magnitude of the switching voltage (TOW threshold V0) relative to the reference potential V DIS the reference potential connection GND. Preferred mounting form on the circuit carrier PCB with a voltage scheme according to Figures 1 and 2

[0196] The document presented here also describes a circuit with a microintegrated circuit IC, as described immediately above in this document. Preferably, the integrated circuit IC is housed in a housing (GH). The housing (GH) with the integrated circuit IC is preferably mounted on a circuit carrier (PCB).

[0197] If the interface device SVIC of the micro-integrated circuit IC has a voltage scheme according to the Fig. 1 or Fig. 2 expected for the test control, a line of the circuit carrier PCB preferably electrically connects the test data bus connection TEST of the integrated circuit IC preferably with the reference potential connection GND of the housing GH of the integrated circuit IC.

[0198] The document presented here further describes a preferred package GH with an integrated circuit IC, as described immediately above in this document. Preferably, the reference potential terminal GND of the package GH is directly adjacent to the test data bus terminal TEST of the package GH of the microintegrated circuit IC, if the interface device SVIC of the microintegrated circuit IC has a voltage scheme corresponding to the Fig. 1 or Fig. 2 expected for test control. Preferred mounting form on the circuit carrier PCB with a voltage scheme according to Figures 3 and 4

[0199] If the interface device SVIC of the micro-integrated circuit IC has a voltage scheme according to the Fig. 3 or Fig. 4 for the test control, a line of the circuit carrier PCB preferably connects the test data bus connection TEST of the integrated circuit IC preferably with the supply voltage connection V IO of the housing GH of the integrated circuit IC electrically.

[0200] This document also describes a preferred package GH with an integrated circuit IC as described immediately above. The supply voltage terminal V IO of the housing GH is immediately adjacent to the test data bus terminal TEST of the housing GH of the micro-integrated circuit IC, if the interface device SVIC of the micro-integrated circuit IC has a voltage scheme corresponding to the Fig. 3 or Fig. 4 expected for test control. Method for providing and using an integrated circuit IC with a voltage scheme according to Figures 1 and 2

[0201] The document presented here describes a method for providing and using an integrated circuit with the following steps: • Providing an integrated circuit IC in a housing GH for this integrated circuit IC, wherein the integrated circuit IC is arranged in the housing GH and wherein the test data bus connection TEST of the integrated circuit IC is connected to a test data bus connection TEST of the housing GH and wherein the reference potential connection GND of the integrated circuit IC is connected to a reference potential connection GND of the housing GH; • Testing of the integrated circuit IC by means of a method by means of one of the methods described above, in which the fourth voltage range VB4 by the reference potential V DIS of the reference potential connection GND is limited; • Mounting the housing GH with the integrated circuit IC on a circuit carrier PCB and • Electrical connection of the test data bus connection TEST with the reference potential connection GND.

[0202] The electrical connection of the test data bus terminal TEST to the reference potential terminal GND is preferably made with a substantially minimal cable length. The reference potential terminal GND is preferably directly adjacent to the test data bus terminal TEST in the housing GH of the microintegrated circuit IC. Setting the test state on the circuit carrier PCB with a voltage scheme according to Figures 1 and 2

[0203] The document presented here thus describes a housing GH for an integrated circuit IC as described above. The integrated circuit IC is preferably arranged in the housing GH. The test data bus terminal TEST of the integrated circuit IC is preferably connected to a test data bus terminal TEST of the housing GH. The reference potential terminal GND of the integrated circuit IC is preferably connected to a reference potential terminal GND of the housing GH.

[0204] Preferably, the reference potential terminal GND is immediately adjacent to the test data bus terminal TEST in the housing GH of the microintegrated circuit IC.

[0205] The document presented here further describes a circuit carrier PCB on which a housing GH is mounted as described above. The technical teaching of the document presented here assumes in this section that the integrated circuit IC has a layer of the fourth voltage range V B4which is determined by the reference potential V DIS according to the Fig. 1 and Fig. 2 is limited. The reference potential terminal GND of the housing GH is then, under this assumption, preferably connected to the test data bus terminal TEST of the housing GH by means of a connecting line VL of the circuit carrier PCB. The length of the connecting line VL is preferably essentially minimal. The ratio of the length of the connecting line VL divided by the length of the direct line between the reference potential terminal GND of the housing GH and the test data bus terminal TEST of the housing GH is then preferably less than 3 and / or better less than 2 and / or better less than 1.5 and / or better less than 1.25. Preferably, an electrical resistor R short the reference potential connection GND of the housing GH by means of a connecting line VL of the circuit carrier PCB with the test data bus connection TEST of the housing GH.

[0206] The circuit carrier PCB is preferably configured to allow testing of the integrated circuit IC in the housing GH using one of the methods described above. This allows testing of the integrated circuit IC after installation on the circuit carrier PCB, even though the housing GH is mounted on the circuit carrier PCB. Preferably, the integrated circuit IC is tested via a test connection TEST of the circuit carrier PCB, to which the housing GH with the integrated circuit IC and to which the electrical resistance R shortThe test terminal TEST of the circuit carrier PCB is typically connected directly or indirectly to the test terminal TEST of the housing GH. The circuit carrier is preferably configured so that the activation of the test terminal TEST of the circuit carrier PCB by means of a test signal source with low internal resistance compensates for the effect of the electrical resistance R short overwrites and can render ineffective. Method for providing and using an integrated circuit IC with a voltage scheme according to Figures 3 and 4

[0207] An alternative method for providing and using an integrated circuit IC accordingly comprises the steps: • Providing an integrated circuit IC in a housing GH for this integrated circuit IC, wherein the integrated circuit IC is arranged in the housing GH and wherein the test data bus terminal TEST of the integrated circuit IC is connected to a test data bus terminal TEST of the housing GH and wherein the supply voltage terminal VDD of the integrated circuit IC is connected to a supply voltage terminal VDD of the housing GH; • Testing the integrated circuit IC using one of the methods described above, in which the fourth voltage range V B4 by the supply voltage potential V IO of the supply voltage terminal VDD; • Mounting the housing GH with the integrated circuit IC on a circuit carrier PCB and • electrically connecting the test data bus connection TEST of the housing GH to the supply voltage connection VDD of the housing GH. Setting the test state on the circuit carrier PCB with a voltage scheme according to Figures 3 and 4

[0208] Preferably, the electrical connection of the test data bus connection TEST of the housing GH to the supply voltage connection VDD of the housing GH is made with a substantially minimal cable length. For this purpose, the supply voltage connection VDD in the housing GH is preferably arranged directly adjacent to the test data bus connection TEST in the housing GH of the microintegrated circuit IC. To ensure testability of the integrated circuit IC after installation on the circuit carrier PCB, the electrical connection of the test data bus connection TEST to the supply voltage connection VDD is preferably made via an electrical resistor R short. After the housing GH with the integrated circuit IC has been installed on the circuit carrier PCB, the micro-integrated circuit IC can still be tested. For this purpose, the previously described procedure is supplemented by the step of testing the integrated circuit IC in the housing GH. During testing of the integrated circuit IC in the housing GH, the housing GH is mounted on the circuit carrier PCB. The step of testing the integrated circuit IC in the housing GH is carried out using the previously described procedure. The test is carried out via a test connection TEST of a circuit carrier PCB, to which the housing GH with the integrated circuit IC and to which the electrical resistance R shortare mounted. Preferably, the test terminal TEST of the circuit carrier PCB is connected to the test terminal TEST of the housing GH. The activation of the test terminal TEST of the circuit carrier PCB by means of a test signal source with low internal resistance overrides the effect of the electrical resistance R during the step of testing the integrated circuit IC in the housing GH. short overwrites and makes the effect of the electrical resistance R short ineffective.

[0209] The document presented here thus describes a housing GH for an integrated circuit IC as described above. The integrated circuit IC is arranged in the housing GH. The test data bus terminal TEST of the integrated circuit IC is connected, for example, to a test data bus terminal TEST of the housing GH. The supply voltage terminal VDD of the integrated circuit IC is connected, for example, to a supply voltage terminal VDD of the housing GH. Preferably, the supply voltage terminal VDD is directly adjacent to the test data bus terminal TEST in the housing GH of the microintegrated circuit IC.

[0210] The document presented here further describes a circuit carrier PCB on which a housing GH is mounted as described above. The document presented here assumes, for example, that the integrated circuit IC has a layer of the fourth voltage range V B4expected, which is determined by the supply voltage potential V IO according to the Fig. 3 and Fig. 4 is limited. The supply voltage terminal VDD of the housing GH is then preferably connected by means of a connecting line VL of the circuit carrier PCB to the test data bus terminal TEST of the housing GH. The length of the connecting line VL is then preferably essentially minimal. The length ratio here is the ratio of the length of the connecting line VL divided by the length of the direct line between the supply voltage terminal VDD of the housing GH and the test data bus terminal TEST of the housing GH. The length ratio is therefore preferably less than 3 and / or better less than 2 and / or better less than 1.5 and / or better less than 1.25. The supply voltage terminal VDD of the housing GH is then preferably connected by means of a connecting line VL of the circuit carrier PCB to the test data bus terminal TEST of the housing GH via an electrical resistor R shortPreferably, the circuit carrier is configured such that a test of the integrated circuit IC in the housing GH, which is mounted on the circuit carrier PCB, can be carried out by means of one of the methods described above. Preferably, the circuit carrier PCB is configured such that the test is carried out via a test connection TEST of the circuit carrier PCB, to which the housing GH with the integrated circuit IC and to which the electrical resistor R short are mounted. Preferably, the test terminal TEST of the circuit carrier PCB is directly or indirectly connected to the test terminal TEST of the housing GH. Preferably, the circuit carrier PCB is configured such that the activation of the test terminal TEST of the circuit carrier PCB by means of a test signal source having a low internal resistance compensates for the effect of the electrical resistance R short overwrites and can render ineffective. Advantage

[0211] Such a test interface allows the necessary connections of the microelectronic circuit to be reduced to a single additional connection. However, the advantages are not limited to this.

[0212] The invention provides an arrangement with a single-wire test data bus for bidirectional transmission on this test data bus, which does not require an additional connection for transmitting a test enable signal. Or, to put it another way: In addition to the usually required and therefore present TEST enable connection, a device corresponding to the technical teaching described in the document presented here does not require an additional connection of the housing GH, so that troubleshooting in programs in the application (application-based debugging) is possible without restriction with a minimal number of connections. This means that such a device also does not need to include a connection of the housing GH, which takes on a different meaning in the test case. List of characters Fig. Figure 1 shows an example signaling via the data line TOW. The example signaling signals the test enable signal TEN using a data line level in the fourth voltage range V B4 . The exemplary signaling signals the clock in the first voltage range V B1 . The exemplary signaling signals the data in the second voltage range V B2 and in the third voltage range V B3 . The third voltage range V B3 borders, for example, on the fourth voltage range V B4 The fourth voltage range V B4 borders, for example, on the reference potential V DIS to. Fig. Figure 2 shows an example signaling via the data line TOW. The example signaling signals the test enable signal TEN using a data line level in the fourth voltage range V B4. The exemplary signaling signals the clock in the first voltage range V B1 . The exemplary signaling signals the data in the second voltage range V B2 and in the third voltage range V B3 . The first voltage range V B1 borders, for example, on the fourth voltage range V B4 The fourth voltage range V B4 borders, for example, on the reference potential V DIS to. Fig. Figure 3 shows an example signaling via the data line TOW. The example signaling signals the test enable signal TEN using a data line level in the fourth voltage range V B4 . The exemplary signaling signals the clock in the first voltage range V B1 . The exemplary signaling signals the data in the second voltage range V B2 and in the third voltage range V B3 . The third voltage range V B3borders, for example, on the fourth voltage range V B4 The fourth voltage range V B4 borders, for example, on the supply voltage potential V IO to. Fig. Figure 4 shows an example signaling via the data line TOW. The example signaling signals the test enable signal TEN using a data line level in the fourth voltage range V B4 . The exemplary signaling signals the clock in the first voltage range V B1 . The exemplary signaling signals the data in the second voltage range V B2 and in the third voltage range V B3 . The first voltage range V B1 borders on the fourth voltage range V B4 in this example. The fourth voltage range V B4 borders on the supply voltage potential V IO in this example. Fig. 5 shows an exemplary interconnection of the driver and receive stages of an exemplary production test system and an exemplary interface device SVIC of an exemplary microintegrated circuit IC. Fig. 6 shows an exemplary package GH in which the microintegrated circuit IC is installed. Fig. 7a shows a housing GH according to the Fig. 6, which is mounted on a circuit carrier PCB, and in which a connecting line VL electrically connects the test connection TEST of the housing GH with the reference potential connection GND of the housing GH in essentially the shortest possible way. Fig. 7b shows a housing GH according to the Fig. 6, which is mounted on a circuit carrier PCB, and in which a connecting line VL electrically connects the test connection TEST of the housing GH with the supply voltage connection VDD of the housing GH in essentially the shortest possible way. Fig. 8a shows a housing GH according to the Fig. 6. The housing GH is mounted on a circuit board PCB. On the circuit board PCB, a connecting line VL electrically connects the test terminal TEST of the housing GH to the reference potential terminal GND of the housing GH, essentially by the shortest possible path, via a resistor R. short . In the circuit carrier PCB, a signal via a test connection TEST of the circuit carrier PCB can determine the effect of this resistor R short overwrite for testing purposes. Fig. 8b shows a housing GH according to the Fig. 6. The housing GH is mounted on a circuit board PCB. On the circuit board PCB, a connecting line VL electrically connects the test terminal TEST of the housing GH to the supply voltage terminal VDD of the housing GH, essentially by the shortest possible path, via a resistor R. short. In the circuit carrier PCB, a signal via a test connection TEST of the circuit carrier PCB can determine the effect of this resistor R short overwrite for testing purposes. Description of the figuresFigure 1

[0213] Fig. Figure 1 shows the basic signal forms of the data protocol according to the invention on the data line TOW. In the upper part of the Fig. Figure 1 shows a schematic diagram of the signal waveforms for a two-wire test bus according to the IEEE 1149 standard, as they are known from the state of the art. The top signal, TDA, represents the data signal. The second signal, TCK, represents the associated clock. Both signals are marked as state of the art and belong to the 2-wire JTAG standard. Below, the digital coding is shown as an example. It does not yet indicate whether the slave or the master is transmitting. Only the signal waveform is sketched here.

[0214] Below, the inventive signal form on the data line TOW of the single-wire data bus is sketched, which combines the clock and the data.

[0215] The different voltage levels (data line levels) are outlined at the very bottom. The signal has three voltage levels (data line levels) when transmitted: 1. A first voltage level (data line level), which is typically equal to a supply voltage V IO Preferably, master and slave should use the same supply voltage as a reference. 2. A second, medium voltage level V M (data line level). 3. A third voltage level (data line level), which is typically equal to a TOW threshold V0. 4. A fourth voltage level (data line level), which is typically equal to a reference potential V DIS is.

[0216] For the extraction of the test system clock, a second threshold voltage V 2L defined between the supply voltage potential V IO and the mean potential V M lies.

[0217] For data extraction, a third threshold voltage V 1H of the bus master and a first threshold voltage V 2H of the bus slave, i.e. the microelectronic circuit IC, which lies between the TOW threshold V0 and the average potential V M and which should be roughly the same.

[0218] The second threshold voltage V 2L of the slave and the supply voltage V IO a first voltage range V B1 defined and limited.

[0219] By the first threshold voltage V 2H of the bus slave, i.e. the micro-integrated circuit IC, or the third threshold voltage V 1Hof the bus master on one side and the second threshold voltage V 2L of the bus slave, i.e. the micro-integrated circuit IC, a second voltage range V B2 defined and limited.

[0220] By the first threshold voltage V 2H of the bus slave, i.e. the micro-integrated circuit IC or the third threshold voltage V 1H of the bus master on the one hand and the TOW threshold V0, a ​​third voltage range V B3 defined and limited.

[0221] The signal on the data line TOW is divided into time-slot packets of a data exchange period T with at least three time slots (TIN0, TIN1, TDO). The time slots (TIN0, TIN1, TDO) of a time-slot packet of a data exchange period T follow one another with a test system clock period T pThe order of the time slots (TIN0, TIN1, TDO) within a time slot packet of the data exchange period T can be chosen arbitrarily for a system, but preferably the same for all time slot packets of a data exchange period T. Each test system clock period T p preferably divided into at least two half-stroke periods T 1H , T 2H , the length of which is preferably but not necessarily equal.

[0222] In one half-cycle period of at least two half-cycle periods T 1H , T 2H The test system clock TCK is preferably transmitted.

[0223] Here, the data line level on the data line TOW is in one half-clock period of at least two half-clock periods T 1H , T 2H in the first voltage range V B1This transmits a first logical value of the test system clock TCK. In this example, it is sufficient that the data line level on the data line TOW is above the second threshold V 2L An upper limit is set by the supply voltage V IO is responsible for deciding whether the data line level on the data line TOW is in the first voltage range V B1 is not relevant and is therefore not used in practice. Therefore, the first voltage range V B1 in many applications can also be considered as open-ended.

[0224] In the other half-cycle period of the at least two half-cycle periods T 1H , T 2H the data line level on the data line TOW is in the second voltage range V B2 or third voltage range V B3This transmits a second logical value of the test system clock TCK, which is different from the first logical value of the test system clock TCK. In this example, it is sufficient that the data line level on the data line TOW is below the second threshold V 2L A lower limit by the TOW threshold V0 is used to decide whether the data line level on the TOW data line is in the second voltage range V B2 or third voltage range V B3 is relevant because it decides whether the test enable signal is active or not active, TEN=1 or TEN=0.

[0225] For the extraction of the test system clock TCK within this other half-clock period of the at least two half-clock periods T 1H , T 2H It is not relevant whether the data line level on the data line TOW is in the third voltage range V B3 or second voltage range V B2Therefore, by distinguishing between the third voltage range V B3 and the second voltage range V B2 within this other half-cycle period of at least two half-cycle periods T 1H , T 2H Data is transferred.

[0226] In this other half-stroke period of the at least two half-stroke periods T 1H , T 2H the data line level on the data line TOW is in the second voltage range V B2 when a first logical data value is transmitted. and in the third voltage range V B3 when a second logical data value is transmitted.

[0227] To the right of the lower signal, exemplary logic states for the three data line levels are shown for better clarity.

[0228] In the example, the upper data line level corresponds to an exemplary logic value of the test system clock TCK of 1 and an exemplary logic value of the data signal TDI of 1.

[0229] In the example, the middle data line level corresponds to an exemplary logical value of the test system clock TCK of 0 and an exemplary logical value of the data signal TDI of 1.

[0230] In the example, the lower data line level corresponds to an exemplary logical value of the test system clock TCK of 0 and an exemplary logical value of the data signal TDI of 0.

[0231] The combination of an exemplary logical value of the test system clock TCK of 1 and an exemplary logical value of the data signal TDI of 0 is not permitted and may indicate a system error.

[0232] If the data line level is below the TOW threshold V0, normal operation is signaled to the microelectronic circuit IC. The interface device SVIC then preferably prevents the microelectronic circuit IC from entering a test state, for example, by means of a locking device BC. Figure 2

[0233] Fig. Figure 2 shows the basic signal forms of the data protocol according to the invention on the data line TOW. In the upper part of the Fig. Figure 2 shows a schematic diagram of the signal waveforms for a two-wire test bus according to the IEEE 1149 standard, as they are known from the state of the art. The top signal, TDA, represents the data signal. The second signal, TCK, represents the associated clock. Both signals are marked as state of the art and belong to the 2-wire JTAG standard. Below, the digital coding is shown as an example. It does not yet indicate whether the slave or the master is transmitting. Only the signal waveform is sketched here.

[0234] Below, the inventive signal form on the data line TOW of the single-wire data bus is sketched, which combines the clock and the data.

[0235] The different voltage levels (data line levels) are outlined at the very bottom. The signal has three voltage levels (data line levels) when transmitted: 5. A first voltage level (data line level), which is typically equal to a supply voltage V IOPreferably, master and slave should use the same supply voltage as a reference. 6. A second, middle voltage level V M (data line level). 7. A third voltage level (data line level), which is typically equal to a TOW threshold V0. 8. A fourth voltage level (data line level), which is typically equal to a reference potential V DIS is.

[0236] For the extraction of the test system clock TCK, a second threshold voltage V 2L defined between the TOW threshold V0 and the mean potential V M lies.

[0237] For data extraction, a third threshold voltage V 1H of the bus master and a first threshold voltage V 2H of the bus slave, i.e. the microelectronic circuit IC, which is located between the supply voltage V IO and the mean potential V Mand which should be roughly the same.

[0238] The second threshold voltage V 2L of the slave and the TOW threshold V0, a ​​first voltage range V B1 defined and limited.

[0239] By the first threshold voltage V 24 of the bus slave, i.e. the micro-integrated circuit IC, or the third threshold voltage V 1H of the bus master on one side and the second threshold voltage V2. of the bus slave, i.e. the micro-integrated circuit IC, a second voltage range V B2 defined and limited.

[0240] By the first threshold voltage V 24 of the bus slave, i.e. the micro-integrated circuit IC or the third threshold voltage V 1H of the bus master on one side and the supply voltage V IO a third voltage range V B3 defined and limited.

[0241] The signal on the data line TOW is divided into time-slot packets of a data exchange period T with at least three time slots (TIN0, TIN1, TDO). The time slots (TIN0, TIN1, TDO) of a time-slot packet of a data exchange period T follow one another with a test system clock period T p The order of the time slots (TIN0, TIN1, TDO) within a time slot packet of the data exchange period T can be chosen arbitrarily for a system, but preferably the same for all time slot packets of a data exchange period T. Each test system clock period T p preferably divided into at least two half-stroke periods T 1H , T ZH , the length of which is preferably but not necessarily equal.

[0242] In one half-cycle period of at least two half-cycle periods T 1H , T 24 The test system clock TCK is preferably transmitted.

[0243] Here, the data line level on the data line TOW is in one half-clock period of at least two half-clock periods T 1H , T 2H in the first voltage range V B1 This transmits a first logical value of the test system clock TCK. In this example, it is sufficient that the data line level on the data line TOW is below the second threshold V 2L In contrast to the state of the art, a lower limit by the TOW threshold V0 is now required to decide whether the data line level on the TOW data line is in the first voltage range V B1 is relevant because it decides whether TEN=1 or TEN=0, i.e. whether the test enable signal is active or not.

[0244] In the other half-cycle period of the at least two half-cycle periods T 1H , T 2H the data line level on the data line TOW is in the second voltage range V B2or third voltage range V B3 This transmits a second logical value of the test system clock TCK, which is different from the first logical value of the test system clock TCK. In this example, it is sufficient that the data line level on the data line TOW is above the second threshold V 2L An upper limit is set by the supply voltage V IO is for deciding whether the data line level on the data line TOW is in the second voltage range V B2 or third voltage range V B3 is not relevant and is therefore not used in practice. Therefore, the third voltage range V B3 in many applications can also be considered as open-ended.

[0245] For the extraction of the test system clock TCK within this other half-clock period of the at least two half-clock periods T 1H , T 2HIt is not relevant whether the data line level on the data line TOW is in the third voltage range V B3 or second voltage range V B2 Therefore, by distinguishing between the third voltage range V B3 and the second voltage range V B2 within this other half-cycle period of at least two half-cycle periods T 1H , T 2H Data is transferred.

[0246] In this other half-stroke period of the at least two half-stroke periods T 1H , T 2H the data line level on the data line TOW is in the second voltage range V B2 when a first logical data value is transmitted. and in the third voltage range V B3 when a second logical data value is transmitted.

[0247] To the right of the lower signal, exemplary logic states for the three data line levels are shown for better clarity.

[0248] In the example, the upper data line level corresponds to an exemplary logic value of the test system clock TCK of 1 and an exemplary logic value of the data signal TDI of 1.

[0249] In the example, the middle data line level corresponds to an exemplary logical value of the test system clock TCK of 1 and an exemplary logical value of the data signal TDI of 0.

[0250] In the example, the lower data line level corresponds to an exemplary logical value of the test system clock TCK of 0 and an exemplary logical value of the data signal TDI of 0.

[0251] The combination of an exemplary logical value of the test system clock TCK of 1 and an exemplary logical value of the data signal TDI of 0 is not permitted and may indicate a system error.

[0252] If the data line level is below the TOW threshold V0, normal operation is signaled to the microelectronic circuit IC. The interface device SVIC then preferably prevents the microelectronic circuit IC from entering a test state, for example, by means of a locking device BC. Figure 3

[0253] Fig. Figure 3 shows the basic signal forms of the data protocol according to the invention on the data line TOW. In the upper part of the Fig. Figure 3 shows a schematic diagram of the signal waveforms for a two-wire test bus according to the IEEE 1149 standard, as they are known from the state of the art. The top signal, TDA, represents the data signal. The second signal, TCK, represents the associated clock. Both signals are marked as state of the art and belong to the 2-wire JTAG standard. Below, the digital coding is shown as an example. It does not yet indicate whether the slave or the master is transmitting. Only the signal waveform is sketched here.

[0254] Below, the inventive signal form on the data line TOW of the single-wire data bus is sketched, which combines the clock and the data.

[0255] The different voltage levels (data line levels) are outlined at the very bottom. The signal has three voltage levels (data line levels) when transmitted: 1. A first voltage level (data line level), which is typically equal to a supply voltage V IOPreferably, master and slave should use the same supply voltage as a reference. 2. A second, medium voltage level V M (data line level). 3. A third voltage level (data line level), which is typically equal to a TOW threshold V0. 4. A fourth voltage level (data line level), which is typically equal to a reference potential V DIS is.

[0256] For the extraction of the test system clock, a second threshold voltage V 2L defined between the reference potential V DIS and the mean potential V M lies.

[0257] For data extraction, a third threshold voltage V 1H of the bus master and a first threshold voltage V 2H of the bus slave, i.e. the microelectronic circuit IC, which lies between the TOW threshold V0 and the average potential V Mand which should be roughly the same.

[0258] The second threshold voltage V 2L of the slave and the reference potential V DIS a first voltage range V B1 defined and limited.

[0259] By the first threshold voltage V 2H of the bus slave, i.e. the micro-integrated circuit IC, or the third threshold voltage V 1H of the bus master on one side and the second threshold voltage V2. of the bus slave, i.e. the micro-integrated circuit IC, a second voltage range V B2 defined and limited.

[0260] By the first threshold voltage V 2H of the bus slave, i.e. the micro-integrated circuit IC or the third threshold voltage V 1H of the bus master on the one hand and the TOW threshold V0, a ​​third voltage range V B3 defined and limited.

[0261] The signal on the data line TOW is divided into time-slot packets of a data exchange period T with at least three time slots (TIN0, TIN1, TDO). The time slots (TIN0, TIN1, TDO) of a time-slot packet of a data exchange period T follow one another with a test system clock period T p The order of the time slots (TIN0, TIN1, TDO) within a time slot packet of the data exchange period T can be chosen arbitrarily for a system, but preferably the same for all time slot packets of a data exchange period T. Each test system clock period T p preferably divided into at least two half-stroke periods T 1H , T 2H , the length of which is preferably but not necessarily equal.

[0262] In one half-cycle period of at least two half-cycle periods T 1H , T 2H The test system clock TCK is preferably transmitted.

[0263] Here, the data line level on the data line TOW is in one half-clock period of at least two half-clock periods T 1H , T 2H in the first voltage range V B1 This transmits a first logical value of the test system clock TCK. In this example, it is sufficient that the data line level on the data line TOW is below the second threshold V 2L A limitation at the bottom by the reference potential V DIS is responsible for deciding whether the data line level on the data line TOW is in the first voltage range V B1 is not relevant and is therefore not used in practice. Therefore, the first voltage range V B1 In many applications, it can also be considered as open at the bottom.

[0264] In the other half-cycle period of the at least two half-cycle periods T 1H , T 2Hthe data line level on the data line TOW is in the second voltage range V B2 or third voltage range V B3 This transmits a second logical value of the test system clock TCK, which is different from the first logical value of the test system clock TCK. In this example, it is sufficient that the data line level on the data line TOW is above the second threshold V 2L A limitation by the TOW threshold V0 is used to decide whether the data line level on the data line TOW is in the second voltage range V B2 or third voltage range V B3 is relevant because it decides whether the test enable signal is active or not active, TEN=1 or TEN=0.

[0265] For the extraction of the test system clock TCK within this other half-clock period of the at least two half-clock periods T 1H , T 2HIt is not relevant whether the data line level on the data line TOW is in the third voltage range V B3 or second voltage range V B2 Therefore, by distinguishing between the third voltage range V B3 and the second voltage range V B2 within this other half-cycle period of at least two half-cycle periods T 1H , T 2H Data is transferred.

[0266] In this other half-stroke period of the at least two half-stroke periods T 1H , T 2H the data line level on the data line TOW is in the second voltage range V B2 when a first logical data value is transmitted. and in the third voltage range V B3 when a second logical data value is transmitted.

[0267] To the right of the lower signal, exemplary logic states for the three data line levels are shown for better clarity.

[0268] In the example, the upper data line level corresponds to an exemplary logic value of the test system clock TCK of 1 and an exemplary logic value of the data signal TDI of 1.

[0269] In the example, the middle data line level corresponds to an exemplary logical value of the test system clock TCK of 1 and an exemplary logical value of the data signal TDI of 0.

[0270] In the example, the lower data line level corresponds to an exemplary logical value of the test system clock TCK of 0 and an exemplary logical value of the data signal TDI of 0.

[0271] The combination of an exemplary logical value of the test system clock TCK of 0 and an exemplary logical value of the data signal TDI of 1 is not permitted and may indicate a system error.

[0272] If the data line level is above the TOW threshold V0, normal operation is signaled to the microelectronic circuit IC. The interface device SVIC then preferably prevents the microelectronic circuit IC from entering a test state, for example, by means of a locking device BC. Figure 4

[0273] Fig. Figure 4 shows the basic signal forms of the data protocol according to the invention on the data line TOW. In the upper part of the Fig. Figure 2 shows a schematic diagram of the signal waveforms for a two-wire test bus according to the IEEE 1149 standard, as they are known from the state of the art. The top signal, TDA, represents the data signal. The second signal, TCK, represents the associated clock. Both signals are marked as state of the art and belong to the 2-wire JTAG standard. Below, the digital coding is shown as an example. It does not yet indicate whether the slave or the master is transmitting. Only the signal waveform is sketched here.

[0274] Below, the inventive signal form on the data line TOW of the single-wire data bus is sketched, which combines the clock and the data.

[0275] The different voltage levels (data line levels) are outlined at the very bottom. The signal has three voltage levels (data line levels) when transmitted: 5. A first voltage level (data line level), which is typically equal to a supply voltage V IOPreferably, master and slave should use the same supply voltage as a reference. 6. A second, middle voltage level V M (data line level). 7. A third voltage level (data line level), which is typically equal to a TOW threshold V0. 8. A fourth voltage level (data line level), which is typically equal to a reference potential V DIS is.

[0276] For the extraction of the test system clock TCK, a second threshold voltage V 2L defined between the TOW threshold V0 and the mean potential V M lies.

[0277] For data extraction, a third threshold voltage V 1H of the bus master and a first threshold voltage V 2H of the bus slave, i.e. the microelectronic circuit IC, which is located between the reference potential V DIS and the mean potential V Mand which should be roughly the same.

[0278] The second threshold voltage V 2L of the slave and the TOW threshold V0, a ​​first voltage range V B1 defined and limited.

[0279] By the first threshold voltage V 2H of the bus slave, i.e. the micro-integrated circuit IC, or the third threshold voltage V 1H of the bus master on one side and the second threshold voltage V 2L of the bus slave, i.e. the micro-integrated circuit IC, a second voltage range V B2 defined and limited.

[0280] By the first threshold voltage V 2H of the bus slave, i.e. the micro-integrated circuit IC or the third threshold voltage V 1H of the bus master on one side and the reference potential V DIS a third voltage range V B3 defined and limited.

[0281] The signal on the data line TOW is divided into time-slot packets of a data exchange period T with at least three time slots (TIN0, TIN1, TDO). The time slots (TIN0, TIN1, TDO) of a time-slot packet of a data exchange period T follow one another with a test system clock period T p The order of the time slots (TIN0, TIN1, TDO) within a time slot packet of the data exchange period T can be chosen arbitrarily for a system, but preferably the same for all time slot packets of a data exchange period T. Each test system clock period T p preferably divided into at least two half-stroke periods T 1H , T 2H , the length of which is preferably but not necessarily equal.

[0282] In one half-cycle period of at least two half-cycle periods T 1H , T 2H The test system clock TCK is preferably transmitted.

[0283] Here, the data line level on the data line TOW is in one half-clock period of at least two half-clock periods T 1H , T 2H in the first voltage range V B1 This transmits a first logical value of the test system clock TCK. In this example, it is sufficient that the data line level on the data line TOW is above the second threshold V 2L In contrast to the state of the art, an upper limit by the TOW threshold V0 is now required to decide whether the data line level on the TOW data line is in the first voltage range V B1 is, however, relevant because it decides on the distinction between TEN=1 or TEN=0, i.e. test enable signal active or not active.

[0284] In the other half-cycle period of the at least two half-cycle periods T 1H , T 2H the data line level on the data line TOW is in the second voltage range VB2 or third voltage range V B3 This transmits a second logical value of the test system clock TCK, which is different from the first logical value of the test system clock TCK. In this example, it is sufficient that the data line level on the data line TOW is below the second threshold V 2L A lower limit by the reference potential V DIS is for deciding whether the data line level on the data line TOW is in the second voltage range V B2 or third voltage range V B3 is not relevant and is therefore not used in practice. Therefore, the third voltage range V B3 In many applications, it can also be considered as open at the bottom.

[0285] For the extraction of the test system clock TCK within this other half-clock period of the at least two half-clock periods T 1H , T 2HIt is not relevant whether the data line level on the data line TOW is in the third voltage range V B3 or second voltage range V B2 Therefore, by distinguishing between the third voltage range V B3 and the second voltage range V B2 within this other half-cycle period of at least two half-cycle periods T 1H , T 2H Data is transferred.

[0286] In this other half-stroke period of the at least two half-stroke periods T 1H , T 2H the data line level on the data line TOW is in the second voltage range V B2 when a first logical data value is transmitted. and in the third voltage range V B3 when a second logical data value is transmitted.

[0287] To the right of the lower signal, exemplary logic states for the three data line levels are shown for better clarity.

[0288] In the example, the upper data line level corresponds to an exemplary logic value of the test system clock TCK of 1 and an exemplary logic value of the data signal TDI of 1.

[0289] In the example, the middle data line level corresponds to an exemplary logical value of the test system clock TCK of 0 and an exemplary logical value of the data signal TDI of 1.

[0290] In the example, the lower data line level corresponds to an exemplary logical value of the test system clock TCK of 0 and an exemplary logical value of the data signal TDI of 0.

[0291] The combination of an exemplary logical value of the test system clock TCK of 1 and an exemplary logical value of the data signal TDI of 0 is not permitted and may indicate a system error.

[0292] If the data line level is above the TOW threshold V0, normal operation is signaled to the microelectronic circuit IC. The interface device SVIC then preferably prevents the microelectronic circuit IC from entering a test state, for example, by means of a locking device BC. Figure 5

[0293] Fig. 5 Shows an exemplary interconnection of the driver and receive stages of an exemplary production test system and an exemplary interface device SVIC of an exemplary microintegrated circuit IC.

[0294] The production test system generates a data level signal on the data line TOW, as used for example in Fig. 2. The production test system feeds the data level signal on the data line TOW via the test terminal TEST into the interface device SVIC of the microelectronic circuit IC. The interface device SVIC changes the time-division multiplexing of the test enable signal TEN, the test data input signal TIN, the test mode signal TM, the test clock TCK, and the test data output signal TDO into a space-division multiplexing.

[0295] By means of the second comparator C1L, the interface device SVIC compares the data line level on the data line TOW with a second threshold value V 2L . and generates a received clock signal SCLK.

[0296] By means of the first comparator C1H, the interface device SVIC compares the data line level on the data line TOW with a first threshold value V 2H. and generates a received data signal SDA_IN.

[0297] A threshold switch SV1, which can also be a comparator, compares the data line level on the data line TOW with a TOW threshold V0 and generates an internal test enable signal TEN_IN, which should correspond to the test enable signal TEN of the bus master, here the production test system. In the example of the Fig. 5, this threshold value is equal to the threshold voltage of the transistor. Instead of this design, a design with a comparator can also be selected. When the internal test enable signal TEN_IN is active, the latch BC generates the internal test clock TCK_I from the received test clock SCLK and the internal test input data TDI_I and the internal test mode data TM_I from the received test data SDA_IN. The internal test mode data TM_I controls the JTAG test controller JTAG-TC via its TM pin according to IEEE 1149.7 of the microintegrated circuit IC. The internal test clock TCK_I drives the JTAG test controller JTAG-TC via its TCK pin. The internal test input data TDI_I feeds the TDI input of the JTAG test controller JTAG-TC.The JTAG test controller JTAG-TC stimulates the remaining microelectronic circuit IC via its JTAG test control terminals JTAG-TC when the internal test enable signal TEN_I is active. When the internal test enable signal TEN_I is inactive, the locking device BC preferentially resets the JTAG test controller JTAG-TC via an internal test reset signal TRST_I at its residual terminal TRST. When the internal test enable signal TEN_IN is active, the JTAG test controller JTAG-TC sends its TDO data via the fourth switch S. 4L via the TOW data bus. Figure 6

[0298] The Fig. 6 shows an exemplary package GH in which the microintegrated circuit IC is installed.

[0299] A bonding wire BD connects the supply voltage terminal VDD of the integrated circuit IC to a supply voltage terminal VDD of the package GH.

[0300] Another bond wire BD connects the further supply voltage terminal VDD of the integrated circuit IC with another supply voltage terminal VDD of the package GH.

[0301] A bonding wire BD connects the reference potential terminal GND of the integrated circuit IC with a reference potential terminal GND of the package GH.

[0302] Another bonding wire BD connects the further reference potential terminal GND of the integrated circuit IC with another reference potential terminal GND of the package GH.

[0303] A bonding wire BD connects the test terminal TEST of the integrated circuit IC with a test terminal TEST of the package GH.

[0304] For example, the GH package can be a QFN package. Figure 7a

[0305] Fig. 7a shows a housing GH according to the Fig. 6, which is mounted on a circuit carrier PCB, and in which a connecting line VL electrically connects the test connection TEST of the housing GH with the reference potential connection GND of the housing GH by essentially the shortest possible path. The connecting line VL is preferably manufactured on the surface of the circuit carrier PCB. The circuit carrier PCB may have further lines and device components. These are shown in the Fig. 7a not shown for clarity. The connecting line VL is typically electrically and mechanically connected to the reference potential terminal GND of the housing GH and the test terminal TEST of the housing GH by means of adhesive bonding, welding, or soldering. The integrated circuit IC of the Fig. 7a preferentially expects data line levels corresponding to the Fig. 1 or Fig. 2 at the test terminal TEST of the package GH and thus at the test terminal TEST of the integrated circuit IC inside the package GH. That is, the reference potential V DIS preferably borders on the fourth voltage range V B4 to. Figure 7b

[0306] Fig. 7b shows a housing GH according to the Fig. 6, which is mounted on a circuit carrier PCB, and in which a connecting line VL electrically connects the test connection TEST of the housing GH with the supply voltage connection VDD of the housing GH by essentially the shortest possible path. The connecting line VL is preferably manufactured on the surface of the circuit carrier PCB. The circuit carrier PCB may have further lines and device components. These are shown in the Fig. 7a is not shown for clarity. The connecting line VL is typically electrically and mechanically connected to the supply voltage terminal VDD of the housing GH and the test terminal TEST of the housing GH by means of adhesives, welding, or soldering. The integrated circuit IC of the Fig. 7b preferentially expects data line levels corresponding to the Fig. 3 or Fig. 4 at the test terminal TEST of the package GH and thus at the test terminal TEST of the integrated circuit IC inside the package GH. That is, the supply voltage potential V IO preferably borders on the fourth voltage range V B4 to. Figure 8a

[0307] shows a housing GH according to the Fig. 7a. The housing GH is preferably mounted on a circuit board PCB. In the circuit board PCB, a connecting line VL preferably electrically connects the test terminal TEST of the housing GH to the reference potential terminal GND of the housing GH, essentially by the shortest possible path, but now via a resistor R. short . In the circuit carrier PCB, preferably a signal via a test connection TEST of the circuit carrier PCB can determine the effect of this resistor R short overwrite for test purposes. The connecting line VL is preferably manufactured on the surface of the circuit carrier PCB and is designed for the electrical resistance R short electrically interrupted. The electrical resistance R short bridges this interruption electrically. The circuit board PCB may contain additional wires and components. These are shown in the Fig. 8a not shown for clarity. The connecting line VL is typically connected by means of adhesive, welding or soldering to the reference potential terminal GND of the housing GH and the test terminal TEST of the housing GH and the terminals of the electrical resistor R short electrically and mechanically connected. The integrated circuit IC of the Fig. 8a preferentially expects data line levels corresponding to the Fig. 1 or Fig. 2 at the test terminal TEST of the package GH and thus at the test terminal TEST of the integrated circuit IC inside the package GH. That is, the reference potential V DIS preferably borders on the fourth voltage range V B4 to. Figure 8b

[0308] shows a housing GH according to the Fig. 6. The housing GH is preferably mounted on a circuit carrier PCB. In the circuit carrier PCB, a connecting line VL preferably electrically connects the test terminal TEST of the housing GH to the supply voltage terminal VDD of the housing GH, essentially by the shortest possible path, via a resistor R. short . Preferably, in the circuit carrier PCB, a signal via a test terminal TEST of the circuit carrier PCB can determine the effect of this resistor R short overwrite for test purposes. The connecting line VL is preferably manufactured on the surface of the circuit carrier PCB and is designed for the electrical resistance R short electrically interrupted. The electrical resistance R short bridges this interruption electrically. The circuit board PCB may contain additional wires and components. These are shown in the Fig. 8b not shown for clarity. The connecting line VL is typically connected by means of adhesive, welding or soldering to the reference potential terminal GND of the housing GH and the test terminal TEST of the housing GH and the terminals of the electrical resistor R short electrically and mechanically connected. The integrated circuit IC of the Fig. 8b preferentially expects data line levels corresponding to the Fig. 3 or Fig. 4 at the test terminal TEST of the package GH and thus at the test terminal TEST of the integrated circuit IC inside the package GH. That is, the supply voltage potential V IO preferably borders on the fourth voltage range V B4 to. Concluding remarks

[0309] The above description is not exhaustive and does not limit this disclosure to the examples shown. Those having ordinary skill in the art can deduce, understand, and practice other co-disclosed variations of the sampled individual examples specifically described in this document based on the drawings, the disclosure, and the claims. The indefinite articles "a" or "an" and their inflections do not exclude a plurality, while the mention of a certain number of elements does not exclude the possibility of more or fewer elements being present. A single unit can perform the functions of several elements mentioned in the disclosure, and conversely, several elements can perform the function of a unit.Numerous alternatives, equivalents, variations and combinations are possible without departing from the scope of the present disclosure.

[0310] Unless otherwise stated, those with ordinary specialist knowledge in the field can freely combine all features of the present invention, provided that such combinations are sensible. This applies to the entire document presented here. Those with ordinary specialist knowledge in the field can also freely combine the features described in the description of the figures, unless otherwise stated, as features of the invention with the other features. A restriction of individual features of the exemplary embodiments to the combination with other features of the exemplary embodiments is expressly not intended. Furthermore, physical features of the device can also be reformulated as method features, and method features can be reformulated as physical features of the device. Such a reformulation is therefore automatically disclosed.

[0311] In the foregoing detailed description, reference is made to the accompanying figures. Those having ordinary skill in the art should consider the examples in the description and figures as illustrative and not as limiting the specific example or element described. Those having ordinary skill in the art may derive several examples from the foregoing description and / or figures and / or claims by modifying, combining, or varying certain elements. Furthermore, a person skilled in the art may derive examples or elements that the document presented herein does not literally describe from the description and / or drawings and / or claims.

[0312] Those with ordinary specialist knowledge in the field can combine features disclosed at different points in this document, and in particular in the list of features, provided that this combination makes sense. The references used in the list of features are exemplary and expressly do not limit the disclosure of possible features and sub-feature combinations. The applicable claim arises from the claims. Those with ordinary specialist knowledge in the field should use the relevant text passages to interpret the claims. Even if no device is disclosed at the corresponding points in this text relating to methods and method steps that perform this method step, this document hereby discloses a device and / or a device part that can perform this method step.Those with ordinary skill in the art may combine this device part with other devices and / or device parts where appropriate. The functions of the devices and device parts disclosed in this document correspond to method steps performed by these device parts. Those with ordinary skill in the art may combine these method steps with each other and with method steps to form methods. Such methods are expressly incorporated into the disclosure. List of reference symbols BD Bond wire. In the Fig. 6, only one bonding wire is designated with the reference symbol for clarity. The other reference symbols for the other bonding wires in the Fig. 6 are not shown for better clarity; BC locking circuit. The locking circuit BC preferably prevents the test input TEST of the microintegrated circuit IC from affecting the normal operation of the microintegrated circuit IC when the test enable signal TEN on the data line TOW is not active. For the purposes of this document, an exemplary logical value of the test enable signal TEN corresponding to a non-active test enable signal TEN is TEN=0. For the purposes of this document, an exemplary logical value of the test enable signal TEN corresponding to an active test enable signal TEN is TEN=1.The locking circuit BC preferably allows, within the microintegrated circuit IC, that the test input TEST of the microintegrated circuit IC does not permit normal operation of the microintegrated circuit IC and allows and initiates an influence on the test operation of the microintegrated circuit IC when the test enable signal TEN on the data line is active. The locking circuit BC preferably generates the internal clock signal TCK_I from the received clock signal SCLK. In simple implementations, the internal clock signal TCK_I can correspond to the received clock signal SCLK. The locking circuit BC preferably generates the internal test mode signal TM_I from the received data SDA_IN, which preferably largely corresponds to the test mode signal of a standard JTAG test controller JTAG-TC according to IEEE 1149.7.The locking circuit BC preferably generates the internal test data input signal TDI_I from the received data SDA_IN, which preferably largely corresponds to the test data input signal TDI of a standard JTAG test controller JTAG-TC according to IEEE 1149.7. C2H first comparator. This is the first comparator on the slave side within the interface device SVIC of the microintegrated circuit IC. The first comparator compares the data line level on the data line TOW with a first threshold value V 2HThe first comparator forwards the data signal SDA_IN received by the interface device SVIC of the microintegrated circuit IC via the preferably present locking circuit BC as an internal data reception signal TDI_I to the interior of the microintegrated circuit IC of the slave. The first comparator particularly preferably forwards the data signal SDA_IN received by the interface device SVIC of the microintegrated circuit IC via the preferably present locking circuit BC as an internal data reception signal TDI_I to a JTAG test controller JTAG-TC according to IEEE 1149.7. The microintegrated circuit IC typically represents the system to be tested or controlled. The first comparator detects the change of the data line level on the data line TOW from the third voltage range V B3 on the one hand into the first voltage range V B1 or second voltage range V B2on the other side and vice versa. The first comparator can be provided with a sampling device at its output, which samples the received data signal thus generated with the received clock signal SCLK, for example with its falling edges, to a sampled and received data signal SDA_IN. The corresponding sampling points are shown in the Fig. 1 to 4 are shown as black dots as examples. C2L second comparator. This is the second comparator on the slave side within the interface device SVIC of the microintegrated circuit IC. The second comparator preferably compares the data line level on the data line TOW with a second threshold value V 2LThe second comparator preferably forwards the clock signal SCLK received by the interface device SVIC of the microintegrated circuit IC via the preferably present latch circuit BC as an internal clock signal TCK_I to the interior of the microintegrated circuit IC of the slave. The second comparator particularly preferably forwards the clock signal SCLK received by the interface device SVIC of the microintegrated circuit IC via the preferably present latch circuit BC as an internal clock signal TCK_I to a JTAG test controller JTAG-TC according to IEEE 1149.7. The microintegrated circuit IC typically represents the system to be tested or controlled. The second comparator detects the change in the voltage level (data line level) on the data line TOW from the first voltage range V B1 on the one hand into the third voltage range V B3 or second voltage range V B2on the other side and vice versa. C 1H third exemplary comparator on the master side. The third comparator compares the data line level on the data line TOW with a third threshold value V 1H and forwards the data signal received by the master (production test system) to the master's circuitry, typically the host processor of the production test system. The third comparator detects the change in the data line level on the data line TOW from the third voltage range V B3 on the one hand into the first voltage range V B1 or second voltage range V B2 on the other side and vice versa. D1, Delay element. This optional delay element preferably performs a phase shift and / or delay of the received data signal SDA_IN to improve sampling quality. GND Reference potential line or reference potential connection. This is typically, but not necessarily, connected to ground. It typically has the reference potential V DIS For the sake of simplicity, this document refers to the functionally identical terminals of the micro-integrated circuit IC and the package GH and the circuit board PCB in the same way with the reference symbol GND; IC microintegrated circuit. The microintegrated circuit is preferably manufactured using CMOS semiconductor technology. The microintegrated circuit preferably comprises the interface device SVIC and a standard JTAG test controller JATG-TC according to IEEE 1149.7, which is controlled by the interface device SVIC and exchanges data TDI, TM, TRST, TDO, and clock signals TCK with the interface device SVIC. In the test state (TEN=1), the production test system can then typically control and monitor the microintegrated circuit IC via the data line TOW, the interface device SVIC, and the standard JTAG test controller JTAG-TC according to IEEE 1149.7 as a host processor. IQ1 current source which is part of the threshold switch SV1; JTAG abbreviation for “Joint Test Action Group”; JTAG-TC JTAG test controller JTAG-TC according to IEEE 1149.7; JTAG-CL control and data lines of the JTAG test controller JTAG-TC according to IEEE 1149.7 for the control and / or test and / or programming of other device parts of the microelectronic circuit IC. OE Output Enable Switch; PCB circuit carrier. Typically, this is an FR4 board or a ceramic carrier; Production test system The production test system represents the bus master, the master circuit. The master is typically the host processor, which controls the integrated circuit, the slave. R1 is the first resistor. Preferably, the first resistor has the same resistance value as the second resistor R2, the third resistor R3, and the fourth resistor R4. R2, second resistor. Preferably, the second resistor has the same resistance value as the first resistor R1, the third resistor R3, and the fourth resistor R4. R3 is the third resistor. Preferably, the third resistor has the same resistance value as the first resistor R1, the second resistor R2, and the fourth resistor R4. R4 is the fourth resistor. Preferably, the fourth resistor has the same resistance value as the first resistor R1, the second resistor R2, and the third resistor R3. R5 resistor; R6 resistor; R7 resistor; R8 resistor; R9 resistor; R short Resistance; S 1H first high-side switch. The dominant first high-side switch typically forces the data line level of the data line TOW to the supply voltage potential of the supply voltage line V IO, when the dominant first high-side switch is closed. The dominant first high-side switch is typically only closed when the test enable signal TEN is active (here, for example, TEN=1) and, at the same time, the clock signal TCK in the bus master is active (here, for example, TCK=1). When the dominant first high-side switch is switched on (=closed), the dominant first high-side switch preferably connects the data line TOW to the supply voltage of the supply voltage line V IO S 1L first low-side switch. The first low-side switch typically pulls the data line level of the data line TOW to the reference potential V DISthe reference potential line GND via the third resistor R3 when the first low-side switch is closed. The first low-side switch is typically only closed when the test enable signal TEN is not active (here, for example, TEN=1) or the clock signal TCK in the bus master is not active (here, for example, TCK=1). When the first low-side switch is switched on (=closed), the first low-side switch preferably connects the data line TOW to the reference potential line GND via the third resistor R3. S 2H second high-side switch. The second high-side switch typically pulls the data line level of the data line TOW to the supply voltage potential of the supply voltage line V IOvia the second resistor R2 when the second high-side switch is closed. The second high-side switch is typically only closed when the test enable signal TEN is active (here, for example, TEN=1) and the data signal TDI in the bus master is active at the same time (here, for example, TDI=1). When the second high-side switch is switched on (=closed), the second high-side switch preferably connects the data line TOW to the supply voltage of the supply voltage line V IO via the second resistor R2. S 2L second low-side switch. The second low-side switch typically pulls the data line level of the data line TOW to the reference potential V DISthe reference potential line GND via the second resistor R2 when the second low-side switch is closed. The second low-side switch is typically only closed when the test enable signal TEN is not active (here, for example, TEN=1) or the data signal TDI in the bus master is not active (here, for example, TDI=1). When the second low-side switch is switched on (=closed), the second low-side switch preferably connects the data line TOW to the reference potential line GND via the second resistor R2. S 3H third high-side switch. The third high-side switch typically pulls the data line level of the data line TOW to the supply voltage potential of the supply voltage line V IOvia the first resistor R1 when the third high-side switch is closed. The third high-side switch is typically only closed when the test enable signal TEN is active (here, for example, TEN=1). When the third high-side switch is turned on (=closed), the third high-side switch preferably connects the data line TOW to the supply voltage of the supply voltage line V IO via the first resistor R1. S 3L third low-side switch. The third low-side switch typically pulls the data line level of the data line TOW to the reference potential V DISthe reference potential line GND via the first resistor R1 when the third low-side switch is closed. The third low-side switch is typically only closed when the test enable signal TEN is not active (here, for example, TEN=1). When the third low-side switch is turned on (=closed), the third low-side switch preferably connects the data line TOW to the reference potential line GND via the first resistor R1. S 4L Fourth low-side switch. The fourth low-side switch is preferably located within the micro-integrated circuit IC. The fourth low-side switch is preferably used to send data from the micro-integrated circuit IC to the bus master in the TDO time slots of the bus protocol. The fourth low-side switch typically pulls the data line level of the TOW data line to the reference potential V DISthe reference potential line GND via the fourth resistor R4 when the fourth low-side switch is closed. The fourth low-side switch is typically only closed when the internal test enable signal TEN_IN of the interface device SVIC is active and the interior of the microintegrated circuit IC provides a corresponding transmit data bit SDA_OUTB. Preferably, the transmit data bit SDA_OUTB in certain operating states of the microintegrated circuit IC is the preferably inverted logical content of the test data output signal TDO of the said preferably present standard JTAG test controller JTAG-TC according to IEEE 1149.7 of the microintegrated circuit. When the fourth low-side switch is switched on (= closed), the fourth low-side switch preferably connects the data line TOW to that of the reference potential line GND within the microintegrated circuit IC via the fourth resistor R4. SCLK received clock signal within the interface device SVIC. SDA_IN received data signal within the interface device SVIC. SDA_OUTB data to be sent. Typically, the data to be sent corresponds to the data of the serial test data output (TDO) of a standard JTAG test controller (JTAG-TC) according to IEEE 1149.7 of the microintegrated circuit IC. However, the data to be sent can also include other data that the microintegrated circuit IC may generate in a different way. SDT state of the art; ST1 optional Schmidt trigger, which is part of the threshold switch SV1; SV1 Threshold switch for extracting the internal test enable signal TEN_IN within the interface device SVIC. In the example of the Fig. 5, an amplifier stage consisting of a transistor and a current source as a load resistor, together with a subsequent Schmidt trigger circuit, forms the threshold switch. Preferably, the threshold switch activates the internal test enable signal TEN_IN when the data line level on the data line TOW exceeds the TOW threshold V0. In the example of Fig. 5, the Schmidt trigger is inverting because the preceding amplifier stage is inverting, so that the internal test enable signal TEN_INT is then active with a high data line level (TEN_INT=1). SVIC interface device. T test system clock period; T1 transistor which is part of the threshold switch SV1; T p Test clock period. T 1H first half-stroke period of at least two half-stroke periods T 1H , T 2H in the example of Fig. 1 to 4 three times two half-stroke periods T 1H, T 2H , the test clock period T p . T 2H second half-cycle period of at least two half-cycle periods T 1H , T 2H , in the example of Fig. 2 and Fig. 3 three times two half-stroke periods T 1H , T 2H , the test clock period T p . TCK test clock. This reference symbol also denotes the test clock input of the JTAG test controller JTAG-TC according to IEEE Standard 1149 of the microelectronic circuit IC. TCK_I internal test clock within the micro-integrated circuit IC. The internal test clock can preferably only influence the rest of the micro-integrated circuit IC if the internal test enable signal TEN_IN TDI is active. The internal test clock is preferably inactive when the internal test enable signal TEN_IN is inactive. The latch circuit BC preferably generates the internal clock signal TCK_I from the received clock signal SCLK. In simple implementations, the internal clock signal TCK_I can correspond to the received clock signal SCLK. The latch circuit BC preferably generates an internal test clock with a constant logic value when the internal test enable signal TEN_IN is inactive. The latch circuit BC preferably generates the internal test clock from the received test clock SCLK when the internal test enable signal TEN_IN is active. Test data input signal. The test data input signal typically contains the serial data that the bus master, for example the production test system, wants to transfer to the JTAG test controller JTAG-TC according to IEEE Standard 1149 of the microelectronic circuit IC.In the figures, this reference symbol also labels the input for the serial test data of the JTAG test controller JTAG-TC according to IEEE Standard 1149 of the microelectronic circuit IC. TDI_I internal test data input signal. If the test enable signal TEN and thus the internal test enable signal TEN_IN of the microelectronic circuit IC are active, the internal test data input signal preferably corresponds to the test data input signal TDI of the bus master, for example, the production test system. The locking circuit BC preferably generates the internal test data input signal TDI_I from the received data SDA_IN, which preferably largely corresponds to the test data input signal TDI of a standard JTAG test controller JTAG-TC according to IEEE 1149.7. TDO third time slot. The technical teacher of the document presented here typically uses the third time slot to transmit the TDO_I TDO signal (test data output) of the JTAG test controller JTAG-TC according to IEEE Standard 1149 from the slave (here, the microelectronic circuit IC) to the master (here, the production test system). However, it is not absolutely necessary that this third time slot also be placed at the third time position. Other temporal sequences are possible. This reference symbol also labels the serial test data output of the JTAG test controller JTAG-TC according to IEEE Standard 1149 of the microelectronic circuit IC in the figures; internal TDO signal of the JTAG test controller JTAG-TC according to IEEE 1149.7; TEN Test Enable Signal. In the technical theory presented here, the bus master and the bus slave (the microintegrated circuit IC) transmit the Test Enable signal along with the test input data TDI, the test clock TCK, the test mode signal TM, and the test output data TDO over the same single-wire data bus. In the example of the Fig. 5, the bus master is the production test system. The single-wire data bus is the TOW data line. The bus slave, in this case the microintegrated circuit IC, extracts the test enable signal TEN from the time history of the data line level on the TOW data line and then generates the internal test enable signal TEN_IN, which preferably corresponds to the test enable signal, within the microintegrated circuit IC. TEN_IN internal test enable signal of the interface device SVIC of the microintegrated circuit IC. In the example of the Fig. 5, the threshold switch SV1 generates the internal test enable signal depending on the data line level on the data line TOW. To do this, the threshold switch SV1 compares the data line level on the data line TOW with the TOW threshold V0. If the data line level of the data line TOW is greater than the TOW threshold V0, the threshold switch SV1 activates the internal test enable signal TEN_IN and thereby signals TEST of the remaining micro-integrated circuit IC that this micro-integrated circuit IC should enter a test state. If the data line level of the data line TOW is below the TOW threshold V0, the threshold switch SV1 deactivates the internal test enable signal TEN_IN and thereby signals to the remaining micro-integrated circuit IC that this micro-integrated circuit IC should enter a normal state. If the data line level of the data line TOW is below the TOW threshold V0, the locking device BC resets the JTAG test controller JTAG-TC, preferably by means of a test reset signal TRST_I. In this way, the micro-integrated circuit IC can receive a test enable signal TEN from the bus master, in the example the Fig. 5 of the production test system. Test connection of the data line TOW to the interface device SVIC of the microintegrated circuit IC. For simplicity, this document refers to the functionally identical terminals of the microintegrated circuit IC and the package GH and the circuit carrier PCB in the same way with the reference symbol TEST. TIN0 first time slot. The technical instructor of the document presented here typically uses the first time slot to transmit the TMS (Test Mode Select) signal of the JTAG test controller JTAG-TC according to IEEE Standard 1149 from the master (in this case, the production test system) to the slave (in this case, the microintegrated circuit). However, it is not mandatory that this time slot be placed at the first time position. Other time sequences are possible. TIN1 second time slot. The technical theory of the document presented here typically uses the second time slot to transmit the TDI (test data input) signal of the JTAG test controller JTAG-TC according to IEEE Standard 1149 from the master (here, the production test system). TM to the slave (here, the microintegrated circuit IC). However, it is not absolutely necessary that this second time slot also be placed at the second time position. Other temporal sequences are possible. Test mode input; This reference symbol also labels the input for the test mode signal of the JTAG test controller JTAG-TC according to IEEE Standard 1149 of the microelectronic circuit IC in the figures. TM_I internal test mode signal. The locking circuit BC preferably generates the internal test mode signal TM_I from the received data SDA_IN, which preferably largely corresponds to the test mode signal of a standard JTAG test controller JTAG-TC according to IEEE 1149.7. TOW data line between slave (here the microelectronic circuit IC) and master (here the production test system). TRST Test Reset. This reference symbol also denotes the input of the test reset signal of the JTAG test controller JTAG-TC according to IEEE Standard 1149 of the microelectronic circuit IC. TRST_I internal reset signal. The internal reset signal allows the BC latch circuit to preferentially reset the JTAG test controller JTAG-TC when the internal test enable signal TEN_IN is inactive. V0 TOW threshold. The TOW threshold is located depending on the arrangement of the voltage ranges (V B1 , V B2, V B3 , V B4 ) for example between fourth voltage range V B4 and first voltage range V B1 (see Fig. 2 and Fig. 4) or for example between fourth voltage range V B4 and third voltage range V B3 (see Fig. 1 and Fig. 2). V 1H third threshold. The third threshold separates the third voltage range V B3 from the second voltage range V B2 and thus V 2H also from the first voltage range V B1 on the master side, i.e. the side of the production test system. The third threshold is preferably equal to or similar to the first threshold V 2H . first threshold. The first threshold separates the third voltage range V B3 from the second voltage range V B2 and thus from the first voltage range V B1on the slave side, i.e. the side of the microintegrated circuit IC. The first threshold is preferably equal to or similar to the third threshold V 1H . V 2L second threshold. The second threshold separates the first voltage range V B1 on the one hand from the second voltage range V B2 and from the third voltage range V B3 on the other hand on the slave side, i.e. the side of the microintegrated circuit IC. V B1 first voltage range, which leads to the second voltage range V B2 through the second threshold V 2L Depending on the arrangement of the voltage ranges (V B1 , V B2 , V B3 , V B4 ) the fourth voltage range V B4 if necessary, the first voltage range V B1 (see Fig. 2 and Fig. 4) or the third voltage range V B3 limit (see Fig. 1 and Fig. 3) VB2 second voltage range between the first voltage range V B1 and the third voltage range V B3 . The second threshold V 2L limits the second voltage range to the first voltage range V B1 The first threshold V 2H of the slave (i.e. the microelectronic circuit IC) limits the second voltage range to the third voltage range V B3 or the third threshold V 1H of the master limits the second voltage range to the third voltage range V B3 there. V B3 third voltage range, which belongs to the second voltage range V B2 through the first threshold V 2H of the slave and / or by the third threshold V 1H of the master. Depending on the arrangement of the voltage ranges (V B1 , V B2 , V B3 , V B4 ) the fourth V B4 Voltage range V B4If necessary, limit the third voltage range. (see Fig. 1 and Fig. 3). Fourth voltage range. A data line signal in the fourth voltage range signals the microelectronic circuit IC that it should enter a test state. VDD supply voltage line or supply voltage connection to supply voltage potential V IO For the sake of simplicity, this document designates the functionally identical terminals of the micro-integrated circuit IC and the package GH and the circuit carrier PCB in the same way with the reference symbol TEST V DIS Reference potential. The reference potential preferably limits the fourth voltage range V B4 on one side of the fourth voltage range V B4 The reference potential line GND is preferably at the reference potential; VL connecting line; V IO Supply voltage or supply potential; VR relative data line level V R . The document presented here defines the relative data line level V R as the ratio of the magnitude of the voltage value of the data line level on the data line TOW relative to the reference potential V DIS the reference potential line GND divided by the magnitude of the voltage value the supply voltage V IO to. V M Center potential in the second voltage range V B2 . In the test state, the second logical state of the data line TOW preferably corresponds to a data line level around the center potential V M around and for example V R =2 / 3 in the second voltage range V B2 on the data line TOW. X any bit value in TDI=X in the Fig. 1 to 4.

Claims

[1] Integrated circuit (IC) wherein the integrated circuit (IC) comprises a single-wire test interface for testing said integrated circuit (IC), wherein the single-wire test interface has exactly one test data bus connection (TEST) for one data line (TOW) and wherein the integrated circuit (IC) has a positive supply voltage terminal (VDD) and wherein the integrated circuit (IC) has a negative supply voltage terminal (GND) as a reference potential terminal for a reference potential line (GND) on a reference potential (V DIS ) and where in the following the term data line level means the data bus voltage between the potential of the data line (TOW) minus the reference potential (V DIS ) of the reference potential line (GND), wherein the integrated circuit (IC) is adapted to be connected to a power source by means of a positive supply voltage terminal (VDD) and a reference potential line (GND), and wherein the integrated circuit (IC) is arranged to be supplied with electrical energy via the positive supply voltage terminal (VDD) and the reference potential line (GND), and wherein the integrated circuit (IC) is configured to detect data line levels that are in a first voltage range (V B1 ) or in a second voltage range (V B2 ) or in a third voltage range (V B3 ) or in a fourth voltage range (V B4 ) relative to the reference potential (V DIS ) of the reference potential line (GND) and where a total voltage range is the first voltage range (V B1 ) and the second voltage range (V B2) and the third voltage range (V B3 ) and where the fourth voltage range (V B4 ) is different from the total voltage range and where the first voltage range (V B1 ) and the second voltage range (V B2 ) and the third voltage range (V B3 ) do not overlap and wherein the integrated circuit (IC) is configured such that a data line level in the overall voltage range activates a test state of the microelectronic circuit, and wherein the integrated circuit (IC) is arranged to have a data line level in the fourth voltage range (V B4 ) deactivates the test state of the microelectronic circuit, and wherein the integrated circuit (IC) is configured to provide a data line level in the first voltage range (V B1 ) signals a first logical value to the microelectronic circuit (IC), and wherein the integrated circuit (IC) is configured to provide a data line level in the second voltage range (V B2 ) signals a second logical value to the microelectronic circuit (IC), and wherein the integrated circuit (IC) is arranged to have a data line level in the third voltage range (V B3 ) signals a third logical value to the microelectronic circuit (IC), and wherein the integrated circuit (IC) is configured such that a temporal sequence of first logical values ​​and / or second logical values ​​and / or third logical values ​​represents a test signal sequence for the integrated circuit (IC), and wherein the integrated circuit (IC) is configured such that this test signal sequence controls a test of the microelectronic circuit (IC) when the microelectronic circuit (IC) is in a test state. [2] Integrated circuit according to claim 1, wherein the integrated circuit (IC) is configured such that generating a test signal sequence with data line levels for the duration of the test comprises signaling a clock (TCK) and data to the microelectronic circuit (IC) by means of the first logical value and the second logical value and the third logical value. [3] Integrated circuit according to claim 1 or claim 2, wherein the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels), and wherein data line levels in the fourth voltage range (V B4 ) Voltages between the reference potential (V DIS ) of the reference potential line (GND) and a TOW threshold value (V0) and where data line levels in the third voltage range (V B3 ) Voltages between the TOW threshold (V0) and a first threshold (V2H ) and where data line levels in the second voltage range (V B2 ) Voltages between the first threshold value (V 2H ) and the second threshold (V 2L ) and where data line levels in the third voltage range (V B3 ) Voltages between the second threshold value (V 2L ) and the supply voltage (V IO ) and where the first threshold (V 2H ) the fourth voltage range (V B4 ) and the third voltage range (V B3 ) on the one hand from the second voltage range (V B2 ) and from the first voltage range (V B1 ) on the other hand separates and where the second threshold (V 2L ) the fourth voltage range (V B4 ) and the third voltage range (V B3 ) and the second voltage range (V B2 ) on the one hand from the first voltage range (V B1 ) on the other hand separates and where the TOW threshold (V0) is between the fourth voltage range (V B4 ) and third voltage range (V B3 ) lies. [4] Integrated circuit according to claim 1 or claim 2, wherein the data line level, apart from overshoots and / or noise and other disturbances, has only negative voltage levels (data line levels) and where data line levels in the fourth voltage range (V B4 ) Voltages between the reference potential (V DIS ) of the reference potential line (GND) and a TOW threshold value (V0) and where data line levels in the third voltage range (V B3 ) Voltages between the TOW threshold (V0) and a first threshold (V 2H ) and wherein data line levels in the second voltage range (V B2 ) Voltages between the first threshold value (V 2H ) and the second threshold (V 2L) and wherein data line levels in the third voltage range (V B3 ) Voltages between the second threshold value (V 2L ) and the supply voltage (V IO ) and wherein the first threshold value (V 2H ) the fourth voltage range (V B4 ) and the third voltage range (V B3 ) on the one hand from the second voltage range (V B2 ) and from the first voltage range (V B1 ) on the other hand separates and where the second threshold (V 2L ) the fourth voltage range (V B4 ) and the third voltage range (V B3 ) and the second voltage range (V B2 ) on the one hand from the first voltage range (V B1 ) on the other hand separates and where the TOW threshold (V0) is between the fourth voltage range (V B4 ) and third voltage range (V B3 ) lies. [5] Integrated circuit according to claim 1 or claim 2, wherein the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels), and wherein data line levels in the fourth voltage range (V B4 ) Voltages between the reference potential (V DIS ) of the reference potential line (GND) and a TOW threshold value (V0) and where data line levels in the first voltage range (V B1 ) Voltages between the TOW threshold (V0) and a second threshold (V 2L ) and wherein data line levels in the second voltage range (V B2 ) Voltages between the first threshold value (V 2H ) and the second threshold (V 2L ) and wherein data line levels in the third voltage range (V B3 ) Voltages between the first threshold value (V 2H ) and the supply voltage (V IO ) and wherein the first threshold value (V 2H) the fourth voltage range (V B4 ) and the first voltage range (V B1 ) and the second voltage range (V B2 ) on the one hand from the third voltage range (V B3 ) on the other hand separates and where the second threshold (V 2L ) the fourth voltage range (V B4 ) and the first voltage range (V B1 ) from the second voltage range (V B2 ) and from the third voltage range (V B3 ) on the other hand separates and where the TOW threshold (V0) is between the fourth voltage range (V B4 ) and first voltage range (V B1 ) lies. [6] Integrated circuit according to claim 1 or claim 2, wherein the data line level, apart from overshoots and / or noise and other disturbances, has only negative voltage levels (data line levels) and where data line levels in the fourth voltage range (V B4) Voltages between the reference potential (V DIS ) of the reference potential line (GND) and a TOW threshold value (V0) and where data line levels in the first voltage range (V B1 ) Voltages between the TOW threshold (V0) and a second threshold (V 2L ) and wherein data line levels in the second voltage range (V B2 ) Voltages between the first threshold value (V 2H ) and the second threshold (V 2L ) and wherein data line levels in the third voltage range (V B3 ) Voltages between the first threshold value (V 2H ) and the supply voltage (V IO ) and wherein the first threshold value (V 2H ) the fourth voltage range (V B4 ) and the first voltage range (V B1 ) and the second voltage range (V B2 ) on the one hand from the third voltage range (V B3 ) on the other hand separates and where the second threshold (V 2L ) the fourth voltage range (V B4 ) and the first voltage range (V B1 ) from the second voltage range (V B2 ) and from the third voltage range (V B3 ) on the other hand separates and where the TOW threshold (V0) is between the fourth voltage range (V B4 ) and first voltage range (V B1 ) lies. [7] Integrated circuit according to claim 1 or claim 2, wherein the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels), and wherein data line levels in the fourth voltage range (V B4 ) Voltages between the supply voltage potential (V IO ) of the supply voltage line (VDD) and a TOW threshold (V0) and where data line levels in the third voltage range (V B3) Voltages between the TOW threshold (V0) and a second threshold (V 2L ) and wherein data line levels in the second voltage range (V B2 ) Voltages between the first threshold value (V 2H ) and the second threshold (V 2L ) and wherein data line levels in the first voltage range (V B1 ) Voltages between the first threshold value (V 2H ) and the reference potential (V DIS ) and wherein the first threshold value (V 2H ) the third voltage range (V B3 ) and the fourth voltage range (V B4 ) on the one hand from the second voltage range (V B2 ) and from the first voltage range (V B1 ) on the other hand separates and where the second threshold (V 2L ) the fourth voltage range (V B4 ) and the third voltage range (V B3 ) and the second voltage range (V B2 ) on the one hand from the first voltage range (VB1 ) on the other hand separates and where the TOW threshold (V0) is between the fourth voltage range (V B4 ) and third voltage range (V B3 ) lies. [8] Integrated circuit (IC) according to claim 1 or claim 2, wherein the data line level, apart from overshoots and / or noise and other disturbances, has only negative voltage levels (data line levels) and where data line levels in the fourth voltage range (V B4 ) Voltages between the supply voltage potential (V IO ) of the supply voltage line (VDD) and a TOW threshold (V0) and where data line levels in the third voltage range (V B3 ) Voltages between the TOW threshold (V0) and a second threshold (V 2L ) and wherein data line levels in the second voltage range (V B2 ) Voltages between the first threshold value (V 2H) and the second threshold (V 2L ) and wherein data line levels in the first voltage range (V B1 ) Voltages between the first threshold value (V 2H ) and the reference potential (V DIS ) and wherein the first threshold value (V 2H ) the third voltage range (V B3 ) and the fourth voltage range (V B4 ) on the one hand from the second voltage range (V B2 ) and from the first voltage range (V B1 ) on the other hand separates and where the second threshold (V 2L ) the fourth voltage range (V B4 ) and the third voltage range (V B3 ) and the second voltage range (V B2 ) on the one hand from the first voltage range (V B1 ) on the other hand separates and where the TOW threshold (V0) is between the fourth voltage range (V B4 ) and third voltage range (V B3 ) lies. [9] Integrated circuit according to claim 1 or claim 2, wherein the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels), and wherein data line levels in the fourth voltage range (V B4 ) Voltages between the supply voltage potential (V IO ) of the supply voltage line (VDD) and a TOW threshold (V0) and where data line levels in the first voltage range (V B1 ) Voltages between the TOW threshold (V0) and a second threshold (V 2L ) and wherein data line levels in the second voltage range (V B2 ) Voltages between the first threshold value (V 2H ) and the second threshold (V 2L ) and wherein data line levels in the third voltage range (V B3 ) Voltages between the first threshold value (V 2H ) and the reference potential (VDIS ) and wherein the TOW threshold value (V0) is between the fourth voltage range (V B4 ) and first voltage range (V B1 ) and where the first threshold value (V 2H ) the fourth voltage range (V B4 ) and the first voltage range (V B1 ) and the second voltage range (V B2 ) on the one hand from the third voltage range (V B3 ) on the other hand separates and where the second threshold (V 2L ) the fourth voltage range (V B4 ) and the first voltage range (V B1 ) on the one hand from the second voltage range (V B2 ) and from the third voltage range (V B3 ) on the other hand. [10] integrated circuit (IC) according to claim 1 or claim 2, wherein the data line level, apart from overshoots and / or noise and other disturbances, has only positive voltage levels (data line levels), and wherein data line levels in the fourth voltage range (V B4 ) Voltages between the supply voltage potential (V IO ) of the supply voltage line (VDD) and a TOW threshold (V0) and where data line levels in the first voltage range (V B1 ) Voltages between the TOW threshold (V0) and a second threshold (V 2L ) and wherein data line levels in the second voltage range (V B2 ) Voltages between the first threshold value (V 2H ) and the second threshold (V 2L ) and wherein data line levels in the third voltage range (V B3 ) Voltages between the first threshold value (V 2H ) and the reference potential (V DIS) and wherein the TOW threshold value (V0) is between the fourth voltage range (V B4 ) and first voltage range (V B1 ) and where the first threshold (V 2H ) the fourth voltage range (V B4 ) and the first voltage range (V B1 ) and the second voltage range (V B2 ) on the one hand from the third voltage range (V B3 ) on the other hand separates and where the second threshold (V 2L ) the fourth voltage range (V B4 ) and the first voltage range (V B1 ) on the one hand from the second voltage range (V B2 ) and from the third voltage range (V B3 ) on the other hand. [11] Integrated circuit (IC) according to one of claims 1 to 10, wherein the micro-integrated circuit (IC) comprises a switching element (SV1) which is configured to detect, based on the data line level at the test data bus terminal (TEST), that the micro-integrated circuit (IC) is to activate the test state, and wherein the switching element (SV1) has a switching threshold with a switching voltage (TOW threshold (V0)) relative to the reference potential (V DIS ) which must be exceeded in order for the switching element (SV1) to recognize the test state to be set, and wherein the magnitude of the switching voltage (TOW threshold (V0)) is above the magnitude of the reference potential (V DIS ) (usually 0V) and wherein the integrated circuit (IC) is configured such that during the duration of the test of the micro-integrated circuit (IC), the magnitude of the data line level at the test data bus terminal (TEST) is always above the magnitude of the switching voltage (TOW threshold (V0)), and wherein the integrated circuit (IC) is arranged so that the immediately preceding feature activates and maintains a test state of the micro-integrated circuit (IC) for the duration of the test if it applies, and where the magnitude of the switching voltage (TOW threshold (V0)) is applied to the reference potential (V DIS ) of the reference potential connection (GND) and where the magnitude range of the first voltage range (V B1 ) above the magnitude of the switching voltage (TOW threshold (V0)) related to the reference potential (V DIS ) of the reference potential connection (GND) and where the magnitude range of the second voltage range (VB2 ) above the magnitude of the switching voltage (TOW threshold (V0)) related to the reference potential (V DIS ) of the reference potential connection (GND) and where the magnitude range of the third voltage range (V B3 ) above the magnitude of the switching voltage (TOW threshold (V0)) related to the reference potential (V DIS ) of the reference potential connection (GND). [12] Integrated circuit (IC) according to claim 11, wherein the integrated circuit (IC) is configured such that during the duration of the test the magnitude of the data line level at the test data bus terminal (TEST) is always above the magnitude of the switching voltage (TOW threshold (V0)) plus the magnitude of a positive safety margin voltage in the first voltage range (V B1 ) or wherein the integrated circuit (IC) is configured such that, during the duration of the test, the magnitude of the data line level at the test data bus terminal (TEST) is always above the magnitude of the switching voltage (TOW threshold (V0)) plus the magnitude of a positive safety margin voltage in the second voltage range (V B2 ) or wherein the integrated circuit (IC) is configured such that during the duration of the test the magnitude of the data line level at the test data bus terminal (TEST) is always above the magnitude of the switching voltage (TOW threshold (V0)) plus the magnitude of a positive safety margin voltage in the third voltage range (V B3 ) and wherein the integrated circuit (IC) is configured to activate and securely keep activated a test state of the microelectronic circuit (IC) for the duration of the test if one of the above three possibilities is present. [13] Housing (GH) for an integrated circuit (IC) according to one of claims 1 to 12 and one of claims 3 to 6, wherein the integrated circuit (IC) is arranged in the housing (GH) and wherein the test data bus terminal (TEST) of the integrated circuit (IC) is connected to a test data bus terminal (TEST) of the housing (GH) and wherein the reference potential terminal (GND) of the integrated circuit (IC) is connected to a reference potential terminal (GND) of the housing (GH). [14] Housing (GH) according to claim 13, wherein the reference potential terminal (GND) is immediately adjacent to the test data bus terminal (TEST) in the housing (GH) of the micro-integrated circuit (IC). [15] Printed Circuit Board (PCB), wherein a housing (GH) according to claim 13 or 14 is mounted on the circuit carrier (PCB) and wherein the reference potential terminal (GND) of the housing (GH) is connected to the test data bus terminal (TEST) of the housing (GH) by means of a connecting line (VL) of the circuit carrier (PCB). [16] Circuit board (PCB) according to claim 15, wherein the length of the connecting line (VL) has a substantially minimum length, this meaning that the ratio of the length of the connecting line (VL) divided by the length of the direct line between the reference potential terminal (GND) of the housing (GH) and the test data bus terminal (TEST) of the housing (GH) is less than 3 and / or less than 2 and / or less than 1.5 and / or less than 1.

25. [17] Circuit carrier (PCB) according to one of claims 15 to 16, wherein the reference potential terminal (GND) of the housing (GH) is connected by means of a connecting line (VL) of the circuit carrier (PCB) to the test data bus terminal (TEST) of the housing (GH) via an electrical resistor (Rshort ) is connected. [18] Circuit board (PCB) according to claim 17, wherein the circuit carrier is designed so that a test of the integrated circuit (IC) in the housing (GH) mounted on the circuit carrier (PCB) can be carried out by means of an integrated circuit (IC) according to one of claims 1 to 11 and by means of an integrated circuit (IC) of claims 7 to 10, and wherein the circuit carrier is designed so that the test is carried out via a test connection (TEST) of the circuit carrier (PCB), to which the housing (GH) with the integrated circuit (IC) and to which the electrical resistance (R short ) are mounted, wherein the test terminal (TEST) of the circuit board (PCB) is connected to the test terminal (TEST) of the housing (GH) and wherein the circuit carrier is designed such that the control of the test connection (TEST) of the circuit carrier (PCB) by means of a test signal source with low internal resistance reduces the effect of the electrical resistance (R short ) and renders it ineffective. [19] Housing (GH) for an integrated circuit (IC) according to one of claims 1 to 12 and one of claims 7 to 10 wherein the integrated circuit (IC) is arranged in the housing (GH) and wherein the test data bus terminal (TEST) of the integrated circuit (IC) is connected to a test data bus terminal (TEST) of the housing (GH) and wherein the supply voltage terminal (VDD) of the integrated circuit (IC) is connected to a supply voltage terminal (VDD) of the housing (GH). [20] Housing (GH) according to claim 19, wherein the supply voltage terminal (VDD) is immediately adjacent to the test data bus terminal (TEST) in the housing (GH) of the micro-integrated circuit (IC). [21] Printed Circuit Board (PCB), wherein a housing (GH) according to claim 19 or 20 is mounted on the circuit carrier (PCB) and wherein the supply voltage connection (VDD) of the housing (GH) is connected to the test data bus connection (TEST) of the housing (GH) by means of a connecting line (VL) of the circuit carrier (PCB). [22] Circuit carrier (PCB) according to claim 21, wherein the ratio of the length of the connecting line (VL) divided by the length of the direct line between the supply voltage terminal (VDD) of the housing (GH) and the test data bus terminal (TEST) of the housing (GH) is less than 3 and / or less than 2 and / or less than 1.5 and / or less than 1.

25. [23] Circuit carrier (PCB) according to one of claims 21 to 22, wherein the supply voltage connection (VDD) of the housing (GH) is connected by means of a connecting line (VL) of the circuit carrier (PCB) to the test data bus connection (TEST) of the housing (GH) via an electrical resistor (R short ) is connected. [24] Circuit board (PCB) according to claim 23, wherein the circuit carrier is designed so that a test of the integrated circuit (IC) in the housing (GH) mounted on the circuit carrier (PCB) can be carried out by means of an integrated circuit (IC) according to one of claims 1 to 11 and by means of an integrated circuit (IC) of claims 3 to 6, and wherein the circuit carrier (PCB) is designed so that the test is carried out via a test connection (TEST) of the circuit carrier (PCB), to which the housing (GH) with the integrated circuit (IC) and to which the electrical resistance (R short ) are mounted, wherein the test terminal (TEST) of the circuit board (PCB) is connected to the test terminal (TEST) of the housing (GH) and wherein the circuit carrier is designed so that the control of the test connection (TEST) of the circuit carrier (PCB) by means of a test signal source having a low internal resistance, the effect of the electrical resistance (R short ) and renders it ineffective.

Images