Method for manufacturing a semiconductor device using multiple CMP processes

Abstract

A method of manufacturing a semiconductor device (400), the method comprising: performing (202) one or more grinding processes on a backside surface (418) of a device wafer (402) to thin the device wafer (402) from a first thickness to a second thickness; Performing (204) a first chemical mechanical polishing process, CMP, on the backside surface (418) of the device wafer (402) to thin the device wafer (402) from the second thickness to a third thickness; and Performing a second CMP process on the backside surface (418) of the device wafer (402) to selectively remove device wafer material disposed over an active device area of ​​the semiconductor device (400), wherein a removal rate of the device wafer material is a function of depth, wherein performing (202) the one or more grinding processes on the backside surface (418) of the device wafer (402) to thin the device wafer (402) from the first thickness to the second thickness comprises performing a first grinding process (500) and a second grinding process (502), the method further comprising at least one of: a) setting at least one first grinding parameter during the performance of the first grinding process (500) based on a first total thickness variation, TTV, wherein the at least one first grinding parameter comprises a rotational speed, rpm, of a spindle in a grinding tool or a wheel type used in the grinding tool; b) setting at least one first grinding parameter during the execution of the first grinding process (500) based on a first total thickness variation, TTV, wherein the at least one first grinding parameter comprises a rotational speed, rpm, of a step of the grinding tool or an inclination of the step of the grinding tool; and c) adjusting at least one second grinding parameter during the performance of the second grinding process (502) based on a second total thickness variation, TTV, wherein the at least one second grinding parameter comprises a rotational speed, rpm, of a spindle in a grinding tool, a wheel type used in the grinding tool, a rotational speed of a stage of the grinding tool, or an inclination of the stage of the grinding tool.

Description

Area of ​​Revelation

[0001] Embodiments of the disclosure generally relate to methods of manufacturing semiconductor devices. More particularly, embodiments of the disclosure relate to semiconductor devices including silicon substrates and to methods of manufacturing semiconductor devices including silicon substrates using multiple chemical mechanical polishing (CMP) processes. General state of the art

[0002] Common semiconductor manufacturing processes use silicon-on-insulator (SOI) substrates or silicon substrates with an etch stop layer that protects an epitaxial layer (e.g., an active device area). The availability and cost limitations of SOI substrates and etch stop layers, such as silicon germanium etch stop layers, can limit the manufacturing volume required to meet demand for semiconductor devices using these features. For example, the use of an etch stop layer in a semiconductor device can increase both the cost and complexity of manufacturing a semiconductor device.

[0003] Document KR 10 2021 0 077 679 A discloses a method for forming an integrated spiral inductor, the method comprising: providing a semiconductor wafer with a semiconductor substrate, the semiconductor substrate having a first surface and a second surface; arranging a multilayer insulation structure on the first surface; forming a metal wiring embedded in the multilayer insulation structure; providing a carrier wafer with high resistivity and attaching the carrier wafer to the semiconductor wafer such that the first surface of the semiconductor substrate faces the carrier wafer; removing the semiconductor substrate from the second surface; creating at least one trench gap in the remaining semiconductor substrate starting from the removed second surface; filling the at least one trench gap with a dielectric layer;Forming a silicon via connecting the metal wirings embedded in the multilayer insulation structure; Forming a spiral inductor on the dielectric layer using at least one conductive layer;

[0004] Document DE 10 2019 121 994 A1 describes a method for performing chemical-mechanical polishing on a wafer. The method comprises: identifying a first zone and a second zone on a surface of the wafer. The first zone has a structural feature that differs from a structural feature of the second zone. A first chemical-mechanical polishing thickness target value on the first zone is achieved by polishing the wafer using a first chemical-mechanical polishing process, wherein the chemical-mechanical polishing process is selective to the structural feature of the second zone. Furthermore, the first chemical-mechanical polishing thickness target value on the second zone is achieved by polishing the wafer using a second chemical-mechanical polishing process.

[0005] Document CN 1 295 762 C discloses a method for grinding a metal layer, comprising providing a structure having an upper patterned dielectric layer in which an opening is formed; forming a barrier layer on the upper patterned dielectric layer and lining the opening; forming a metal layer on the barrier layer and filling the opening; performing a first grinding step using a first suspension composition to remove a portion of the metal layer covering the above-mentioned dielectric layer; performing a second grinding step using the first suspension composition to grind the above-mentioned metal layer until a plane of the barrier layer above the dielectric layer is exposed;Performing a third grinding step using a second suspension composition to remove a planar portion above the exposed barrier layer and expose the portion of the dielectric layer below it; and performing a fourth grinding step using the second suspension composition and a corrosion inhibitor to polish the upper portion of the exposed dielectric layer and protect the surface of the metal layer from corrosion.

[0006] Document DE 10 2021 105 366 A1 discloses a semiconductor package comprising a first stack including a first semiconductor substrate. The semiconductor package further comprises a plurality of through-silicon vias extending through the first semiconductor substrate, and a second stack on the first stack, wherein the second stack includes a second surface facing a first surface of the first stack.Likewise, the semiconductor package further comprises a first contact pad on the first surface of the first stack, the first contact pad in contact with one or more of the plurality of through-silicon vias; a second contact pad on the second surface of the second stack; a bump connecting the first contact pad and the second contact pad; a first redundancy contact pad on the first surface of the first stack, the first redundancy contact pad spaced from the first contact pad and not in contact with the plurality of through-silicon vias; a second redundancy contact pad on the second surface of the second stack, the second redundancy contact pad spaced from the second contact pad; and a redundancy bump connecting the first redundancy contact pad and the second redundancy contact pad.The first contact point and the first redundancy contact point are electrically connected to each other and the second contact point and the second redundancy contact point are electrically connected to each other. Brief description

[0007] The invention is defined in the independent claim. Preferred embodiments of the invention are described in the dependent claims. The present disclosure relates to a method of manufacturing a semiconductor device, comprising a two-step chemical mechanical polishing (CMP) process for selectively removing device wafer material (e.g., silicon material) disposed over an active device area of ​​the semiconductor device during backside processing of the semiconductor device. The manufacturing methods can be used with a variety of semiconductor devices. In one non-limiting, non-exclusive example, the semiconductor device is an integrated radio frequency (RF) power switch. The CMP process is tuned to preserve the active device area after backside processing.The present disclosure removes device wafer material disposed over the active device area without special thin-film stop layers. The manufacturing method according to the present disclosure eliminates the need for SOI and silicon substrates with etch stop layers while providing equal or better device and product characteristics. In addition to reducing manufacturing costs, the process techniques according to the present disclosure remove the availability limitations of SOI and silicon substrates that include etch stop layers.

[0008] In one aspect, a method of manufacturing a semiconductor device includes performing one or more grinding processes on a backside surface of a device wafer to thin the device wafer from a first thickness to a second thickness. A first CMP process is performed on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness. A second CMP process is performed on the backside surface of the device wafer to selectively remove device wafer material disposed over an active device area of ​​the semiconductor device, wherein a removal rate of the device wafer material is a function of depth.

[0009] In some embodiments, performing the one or more grinding processes includes performing a first grinding process and a second grinding process. The first grinding process is a rough or rough grinding process, and the second grinding process is a finish grinding process. One or more first grinding parameters may be set and / or adjusted before and / or during the first grinding process. Similarly, one or more second grinding parameters may be set and / or adjusted before and / or during the second grinding process. Example first grinding parameters and second grinding parameters include, but are not limited to, a rotational speed (RPM) of a spindle of a grinding tool, a wheel type used in the grinding tool, a rotational speed of a stage of the grinding tool, and an inclination of the stage of the grinding tool (e.g., a table inclination).

[0010] In certain embodiments, one or more CMP parameters are determined and / or adjusted at certain times before and / or during performance of the first CMP process. Examples of CMP parameters include, but are not limited to, a thickness profile of the device wafer, a polishing agent flow rate, a rotational speed of a polishing head of a polishing tool, a rotational speed of a platen of the polishing tool, and one or more zone pressures of the polishing head of the polishing tool. The thickness profile may be determined and / or adjusted before and / or during performance of the CMP process. Additionally or alternatively, one or more of the zone pressures of the polishing head may be adjusted based on the thickness profile (e.g., for correction).

[0011] In another aspect, any of the above aspects may be used individually or together, and / or various separate aspects and features as described herein may be combined for additional benefit. Each of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise stated herein.

[0012] Those skilled in the art will understand the scope of the present disclosure and recognize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures. Short description of the drawing figures

[0013] The accompanying drawing figures, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. Fig. 1 illustrates an exemplary first semiconductor device; Fig. 2 illustrates an exemplary method of manufacturing a second semiconductor device according to embodiments of the disclosure; Fig. 3 illustrates an exemplary method for attaching the carrier wafer to the device wafer according to embodiments of the disclosure; Fig. 4 illustrates an exemplary second semiconductor device including a device wafer and a carrier wafer, according to embodiments of the disclosure; Fig. 5 illustrates an exemplary method for performing a first grinding process and a second grinding process according to embodiments of the disclosure; Fig. 6 illustrates the Fig. 4 shows a second semiconductor device after the device wafer has been thinned according to embodiments of the disclosure; Fig. 7 illustrates the Fig. 6 shows a second semiconductor device after the device wafer has been further thinned according to embodiments of the disclosure; Fig. 8 illustrates the Fig. 7 shows a second semiconductor device after a portion of the device wafer has been selectively removed according to embodiments of the disclosure; Fig. 9 illustrates the Fig. 8, after a molding compound has been formed in the trench of the second semiconductor device according to embodiments of the disclosure; and Fig. 10 illustrates the Fig. 9 shows a second semiconductor device after the carrier wafer has been removed according to embodiments of the disclosure; Detailed description

[0014] The embodiments described below provide the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. When the following description is read in conjunction with the accompanying figures, those skilled in the art will understand the concepts of the disclosure and recognize applications of those concepts not specifically addressed herein. These concepts and applications are understood to be within the scope of the disclosure and the appended claims.

[0015] It should be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes all combinations of one or more of the associated listed elements.

[0016] It is to be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it may be directly on or extending onto the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" or extending "directly onto" another element, no intervening elements are present. Likewise, it is to be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "across" another element, it may be directly above or extending directly onto the other element, or there may be intervening elements.Conversely, when an element is described as being "directly above" or extending "directly over" another element, no intervening elements are present. It is also understood that when an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is described as being "directly" "connected" or "directly" "coupled" to another element, no intervening elements are present.

[0017] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as illustrated in the figures. It is understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation illustrated in the figures.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "another," or "the," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, indicate the presence of stated features, integers, steps, acts, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, acts, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is further understood that the terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this patent specification and the relevant prior art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0020] Embodiments are described herein with reference to schematic representations of embodiments of the disclosure. As a result, the actual dimensions of the layers and elements may vary, and deviations from the shapes of the illustrations are expected, for example, due to manufacturing techniques and / or tolerances. For example, an area depicted or described as square or rectangular may include rounded or curved features, and areas depicted as straight lines may include some irregularity. Thus, the areas depicted in the figures are schematic, and their shapes are not intended to illustrate the exact shape of a portion of a device and are not intended to limit the scope of the disclosure.In addition, the sizes of structures or regions relative to other structures or regions may be exaggerated for illustrative purposes and thus provided to illustrate the general structures of the subject matter, and may or may not be drawn to scale. Common elements between figures may be shown here with common element numbers and may not be described again below.

[0021] Fig. 1 illustrates an exemplary first semiconductor device 100. The first semiconductor device 100 includes a device wafer 102 having an etch stop layer 104 and an epitaxial layer 106 formed therein. In one non-limiting, non-exclusive example, the device wafer 102 is a p-type silicon substrate, the etch stop layer 104 is a silicon germanium (SiGe) etch stop layer, and the epitaxial layer 106 is a silicon epitaxial layer. Other embodiments are not limited to this implementation.

[0022] The epitaxial layer 106 is an active device area of ​​the first semiconductor device 100. The epitaxial layer includes first doped regions 108 and a second doped region 110 disposed between the first doped regions 108. In the illustrated embodiment, the first doped regions 108 are n-type source / drain regions, and the second doped region 110 is a p-type gate region. Isolation regions 112 are formed in the device wafer 102 at a front surface 114 of the device wafer 102. In one non-limiting, non-exclusive example, the isolation regions 112 are shallow trench isolation (STI) regions of silicon dioxide.

[0023] An insulating layer 116 is formed over the isolation regions 112 and the epitaxial layer 106. A first conductive contact 118A, a second conductive contact 118B, a third conductive contact 118C, a first conductive line 120A, and a second conductive line 120B are formed over the insulating layer 116. The first conductive contact 118A and the third conductive contact 118C are operatively in contact (e.g., in electrical contact) with the first doped regions 108, and the second conductive contact 118B is operatively in contact with the second doped region 110. The first conductive line 120A is operatively in contact with the first conductive contact 118A, and the second conductive line 120B is operatively in contact with the third conductive contact 118C.The first conductive contact 118A, the second conductive contact 118B, the third conductive contact 118C, the first conductive line 120A, and the second conductive line 120B are made of any suitable conductive material, such as metal or polysilicon. In the illustrated embodiment, the first conductive contact 118A, the second conductive contact 118B, the third conductive contact 118C, the first doped regions 108, and the second doped region 110 together form a transistor 122, and the first conductive line 120A and the second conductive line 120B are signal lines operably connected to the transistor 122.

[0024] The first conductive contact 118A, the second conductive contact 118B, the third conductive contact 118C, the first conductive line 120A, and the second conductive line 120B are disposed in a dielectric layer 124 to electrically isolate the first conductive contact 118A, the second conductive contact 118B, the third conductive contact 118C, the first conductive line 120A, and the second conductive line 120B from each other. A first opening 126A is formed in the dielectric layer 124 to expose a portion of the first conductive line 120A. A second opening 126B is formed in the dielectric layer 124 to expose a portion of the second conductive line 120B. The first opening 126A and the second opening 126B enable electrical connections to be made to the exposed portions of the first conductive trace 120A and the second conductive trace 120B, respectively.

[0025] In general, the first conductive contact 118A, the second conductive contact 118B, and the third conductive contact 118C are formed by patterning a first conductive layer formed over the insulating layer 116. The first conductive line 120A and the second conductive line 120B are formed by patterning a second conductive layer. Although in Fig. While two conductive layers are depicted in Figure 1, other embodiments are not limited to this implementation. A semiconductor device may include more than two conductive layers, with each conductive layer surrounded by a dielectric layer. The conductive layers and the dielectric layers thus form an intermetallic dielectric (IMD) structure.

[0026] As part of the manufacturing process for the first semiconductor device 100, the device wafer 102 is thinned using a grinding process. The device wafer 102 is thinned to a thickness that allows the remaining device wafer 102 to be removed by a subsequent plasma dry etch or a selective wet etch that stops at the etch stop layer 104. Subsequently, another dry etch process is performed to remove the etch stop layer 104, which stops at the epitaxial layer 106. The etch stop layer 104, the plasma dry etch, and / or the selective wet etch may increase the cost and / or complexity of manufacturing the first semiconductor device 100. Embodiments of the present disclosure provide manufacturing techniques that allow the etch stop layer 104 and the plasma dry etch and / or the selective wet etch to be omitted from the manufacturing process.The manufacturing techniques involve performing two CMP processes, where the first CMP process selectively removes bulk wafer material (e.g., bulk silicon) and the second CMP process selectively removes bulk wafer material disposed over an active device area.

[0027] Fig. 2 illustrates an exemplary method for manufacturing a second semiconductor device according to embodiments of the disclosure. The method is described in connection with the Fig. 3-10. First, as shown in block 200, a carrier wafer is attached to a front surface of a device wafer. In certain embodiments, the device wafer is a p-type silicon wafer that includes one or more active components, one or more passive components, or combinations thereof. For example, the device wafer may include one or more transistors, one or more resistors, and / or one or more capacitors in at least one active device area.

[0028] Fig. 3 illustrates an exemplary method for attaching the carrier wafer to the device wafer according to embodiments of the disclosure. In these embodiments, an adhesive used to bond the carrier wafer to the device wafer has a substantially uniform thickness across the device wafer. At block 300, one or more coating parameters for the adhesive material are determined. The one or more coating parameters may be based on improving or optimizing a thickness uniformity of the adhesive material on the device wafer and / or improving or optimizing a bond strength to be achieved during bonding of the carrier wafer to the device wafer. The determination of the one or more coating parameters may also be based on maintaining the ability to remove or separate the carrier wafer from the device wafer.Exemplary coating parameters include a coating thickness of the adhesive material, a rotational speed when coating the device wafer (or the carrier wafer) with adhesive material, and a temperature and / or a viscosity of the adhesive material for coating the device wafer (or the carrier wafer) with adhesive material.

[0029] Next, as shown in block 302, the device wafer (or the carrier wafer) is coated with adhesive material. The adhesive material may have a substantially uniform thickness across the device wafer. In certain embodiments, the front surface of the device wafer (or the back surface of the carrier wafer) is coated with the adhesive material. In certain embodiments, the device wafer is circular, such that the thickness is substantially uniform across a diameter of the device wafer. In one non-limiting, non-exclusive example, the thickness is about thirty (30) micrometers, and the adhesive material has a layer thickness uniformity of about seven-tenths (0.7) micrometers total thickness variation (TTV). In other embodiments, the adhesive material may have a different thickness and / or TTV.

[0030] After coating the surface of the device wafer (or carrier wafer) with adhesive material at block 302, the carrier wafer and the device wafer are bonded together (block 304). In some embodiments, an air pressure bonding chamber is used to create high-pressure uniformity of the adhesive material across the device wafer, and a TAZMO thermal bonding tool is used to bond the carrier wafer and the device wafer together. In a non-limiting, non-exclusive example, a total pressure of twelve thousand (12,000) Newtons (N) at two hundred degrees Celsius was used to bond the carrier wafer and the device wafer together.

[0031] Fig. 4 illustrates an exemplary second semiconductor device 400 including a device wafer 402 and a carrier wafer 404, according to embodiments of the disclosure. The carrier wafer 404 is bonded to a front surface 406 of the device wafer 402. In one non-limiting, non-exclusive example, the device wafer 402 is a silicon wafer. At the front surface 406 of the device wafer 402, a doped region 408 is formed in the device wafer 402. One or more active components, one or more passive components, or combinations thereof may be formed in the doped region 408. For example, the doped region 408 may include source / drain regions for one or more transistors. Thus, the doped region 408 is an active device area of ​​the second semiconductor device 400.

[0032] The exemplary device wafer 402 further includes isolation regions 112 formed on the front surface 406 of the device wafer 402 and adjacent to the lateral or vertical edges of the doped region 408. The doped region 408 is disposed between the isolation regions 112. The insulating layer 116 is formed across the front surface 406 of the device wafer 402 (e.g., across the isolation regions 112 and the doped region 408). Formed above the insulating layer 116 are the exemplary first conductive contact 118A, the second conductive contact 118B, the third conductive contact 118C, the first conductive line 120A, and the second conductive line 120B. The first conductive contact 118A, the second conductive contact 118B, the third conductive contact 118C, the first conductive line 120A and the second conductive line 120B are arranged in the dielectric layer 124.The first opening 126A and the second opening 126B are formed in the dielectric layer 124.

[0033] An adhesive layer 410 is used to bond the carrier wafer 404 to the device wafer 402. Fig. 4 shows the second semiconductor device 400 flipped over onto the adhesive layer 410 such that a front surface 412 of the second semiconductor device 400 is attached to a back surface 414 of the adhesive layer 410. The carrier wafer 404 is attached to a front surface 416 of the adhesive layer 410. Any suitable carrier wafer 404 and adhesive layer 410 may be used. In non-limiting, non-exclusive examples, the carrier wafer 404 is made of glass, quartz, or silicon, and the adhesive layer 410 is a polymer-based adhesive layer. The adhesive layer 410 may be applied to the front surface 412 of the second semiconductor device 400, or the adhesive layer 410 may be a laminate film laminated to the front surface 412 of the second semiconductor device 400.

[0034] As described in more detail below, several processes are performed on a backside surface 418 of the device wafer 402 to transform the device wafer 402 from a Fig. 4 shown first thickness T1 to a second thickness T2 ( Fig. 6) and from the second thickness T2 to a third thickness T3 ( Fig. 7) and the remaining device wafer material ( Fig. 8). The carrier wafer 404 supports and stabilizes the second semiconductor device 400 during the plurality of processes. In one non-limiting, non-exclusive example, T1 is approximately seven hundred twenty-five (725) micrometers.

[0035] With further reference to Fig. 2, one or more grinding operations are performed on the backside surface of the device wafer to thin the device wafer (block 202). The device wafer is thinned from the first thickness to the second thickness. In a non-limiting, non-exclusive example, the first thickness is about seven hundred twenty-five (725) micrometers, and the second thickness is greater than or substantially equal to five (5) micrometers. The first thickness and / or the second thickness may have different values ​​in other embodiments. For example, the first thickness may be about seven hundred (700) micrometers, and / or the second thickness may be substantially equal to or less than five (5) micrometers.

[0036] In certain embodiments, the one or more grinding processes are performed as a first grinding process and a second grinding process. Fig. 5 illustrates an example method for performing the first grinding process and the second grinding process according to embodiments of the disclosure. The first grinding process is performed to thin the device wafer (block 500). The first grinding process is a pre-grinding or rough grinding process, and one or more first grinding parameters may be determined and / or adjusted prior to and / or during performance of the first grinding process. Example first grinding parameters include, but are not limited to, a rotational speed of a spindle of a grinding tool, a wheel type used in the grinding tool, a rotational speed of a stage of the grinding tool, and an inclination of the stage of the grinding tool (e.g., a table tilt). The inclination of the stage may be adjusted or tuned to manipulate the removal rate of device wafer material radially across the device wafer.In some embodiments, the TTV of the device wafer is monitored and controlled continuously or at selected times during the first grinding process. During the first grinding process, one or more of the first grinding parameters may be adjusted based on the TTV. For example, the stage slope may be adjusted during the first grinding operation to produce a particular grinding uniformity (or a substantially particular grinding uniformity). Additionally or alternatively, the spindle speed may be adjusted based on the TTV.

[0037] The second grinding process is performed at block 502 to further thin the device wafer. The second grinding operation is a fine grinding process. At certain times before and / or during performance of the second grinding process, one or more second grinding parameters may be established and / or adjusted. Like the first grinding parameters, example second grinding parameters include, among others, the speed of the spindle of the grinding tool, the type of wheel used in the grinding tool, the speed of the stage of the grinding tool, and the inclination of the stage (e.g., the table tilt). As described above, the inclination of the stage may be set or tuned to manipulate the rate of removal of device wafer material radially across the device wafer.In certain embodiments, the TTV of the device wafer is monitored and controlled continuously or at selected times during the second grinding process. During the second grinding process, one or more of the second grinding parameters may be adjusted based on the TTV. For example, during the second grinding process, the type of wheel used in the grinding tool may be changed to produce a specific grinding uniformity (or a substantially specific grinding uniformity).

[0038] In certain embodiments, the TTV used for the first grinding process (a "first TTV") differs from the TTV used for the second grinding process (a "second TTV"). In one non-limiting, non-exclusive example, the first TTV is one and a half (1.5) micrometers and the second TTV is one (1) micrometer. In other embodiments, the first TTV is identical to the second TTV.

[0039] Fig. 6 illustrates the Fig. 4 after the device wafer 402 has been thinned according to embodiments of the disclosure. In the illustrated embodiment, the backside surface 418 of the device wafer 402 is thinned. The one or more grinding processes remove approximately seven hundred and twenty (720) micrometers of the device wafer 402. T2 is thus approximately five (5) micrometers. In another non-limiting, non-exclusive example, T2 may be greater than five (5) micrometers or less than five (5) micrometers.

[0040] After Block 202 in Fig. 2, the one or more grinding operations have been performed, at block 204, a first CMP process is performed on the backside surface of the device wafer to further thin the device wafer. The first CMP process thins the device wafer from the second thickness to a third thickness. In a non-limiting, non-exclusive example, the device wafer is a silicon wafer, and the first CMP process removes bulk silicon at a polishing head pressure of two (2) pounds per square inch (psi) using a hard pad and a highly selective polishing compound to polish the silicon wafer.

[0041] In certain embodiments, one or more CMP parameters may be set and / or adjusted at certain times before and / or during performance of the first CMP process. Examples of CMP parameters include, but are not limited to, a thickness profile of the device wafer, a polishing agent flow rate, a rotational speed of a polishing head of a polishing tool, a rotational speed of a platen of the polishing tool, and one or more zone pressures of the polishing head of the polishing tool. The thickness profile may be set and / or adjusted before and / or during performance of the CMP process. Adjustments to one or more CMP parameters may reduce or eliminate the formation of defects in the thinner region(s) of the ground device wafer due to puncture during polishing. For example, one or more of the zone pressures of the polishing head may be adjusted based on the thickness profile (e.g., for correction).The first CMP process may continue in this controlled manner until an average thickness at a specific location on the device wafer (e.g., the center of the device wafer) reaches the third thickness.

[0042] Fig. 7 illustrates the Fig. 6 after the device wafer 402 has been further thinned according to embodiments of the disclosure. The first CMP process removes the device wafer 402 overlying the backside surfaces 700 of the isolation regions 112 such that the material in the device wafer is substantially located between the isolation regions 112. The first CMP process thins the device wafer 402 from the thickness T2 to the thickness T3. In a non-limiting, non-exclusive example, T3 is about two hundred fifty (250) nanometers, a width (W1) between the isolation regions 112 is about two (2) to ten (10) micrometers, and a width (W2) of the respective isolation regions 112 is about two (2) to four (4) micrometers.

[0043] With further reference to Fig. 2, at block 206, a second CMP process is performed on the backside surface of the device wafer to remove remaining portions of the device wafer located above the doped region and between the isolation regions. The second CMP process forms a trench between the isolation regions, exposing a backside surface of the doped region. The second CMP process is configured to remove the bulk device wafer material (e.g., bulk silicon material) and prevent or minimize damage to the doped region (e.g., the active device area).

[0044] The second CMP process is operable to remove the device wafer material (e.g., the bulk silicon) to a specific depth. Thus, the second CMP process is controlled at least based on the depth, wherein a removal rate of the device wafer material (e.g., the silicon material) depends on the depth. As the depth of operation of the second CMP process increases, the removal rate of the device wafer material decreases. In a non-limiting, non-exclusive example, the device wafer is a silicon wafer, and the second CMP process removes bulk silicon and bulk silicon in the trench at one-tenth (1.1) psi using a soft pad and a highly selective polishing compound to polish the silicon wafer.

[0045] Fig. 8 illustrates the Fig. 7 after a portion of the device wafer 402 has been selectively removed according to embodiments of the disclosure. The second CMP process removes the device wafer 402 located above the doped region 408 and between the isolation regions 112. The second CMP process forms the trench 800 between the isolation regions 112. The trench 800 exposes a backside surface 802 of the doped region 408. The trench 800 has a depth D, and the doped region 408 has a thickness T4. In a non-limiting, non-exclusive example, the width (W1) of the trench 800 is about two (2) to ten (10) micrometers, D is about one hundred (100) nanometers, and T4 is about one hundred and fifty (150) nanometers.

[0046] After Block 206 in Fig. 2, the second CMP process has been performed, the trench is filled with a potting compound (block 208). In one embodiment, the potting compound is made of a material that is not electrically conductive but is thermally conductive. The potting compound may be part of a heat transfer path for the second semiconductor device when the temperature of the second semiconductor device increases during use. Additionally or alternatively, the potting compound may provide mechanical support (e.g., structural support) for the second semiconductor device.

[0047] Fig. 9 illustrates the Fig. 8, after a molding compound 900 has been formed in the trench 800 of the second semiconductor device 400 according to embodiments of the disclosure. The molding compound 900 fills the trench 800 and is arranged over the backside surfaces 700 of the isolation regions 112. The molding compound 900 extends from the backside surface 802 of the doped region 408 and over the backside surfaces 700 of the isolation regions 112.

[0048] With further reference to Fig. 2, at block 210, the carrier wafer is removed from the semiconductor device. Any suitable method may be used to remove the carrier wafer. In one non-limiting, non-exclusive example, the adhesive layer is removed using a laser or a thermal separation process. Removing the adhesive layer also removes the carrier wafer.

[0049] At block 212, one or more additional processes may be performed on the second semiconductor device. An additional process may include, for example, attaching an interconnect to the portion of the first conductive line exposed in the first opening and / or attaching an interconnect to the portion of the second conductive line exposed in the second opening. Example interconnects include solder balls, copper pillars, and wire bonds. Next, as shown in block 214, the device wafer may then be diced to produce individual device dies.

[0050] In some embodiments, before or after performing any of the Fig. 2, one or more other processes may be performed. In one non-limiting, non-exclusive example, a passivation layer may be formed over the second semiconductor device after the operation of block 206 is performed and before the operation of block 208 is performed.

[0051] Fig. 10 illustrates the Fig. 9 after the carrier wafer has been removed according to embodiments of the disclosure and the interconnects 1000A, 1000B have been brought into contact with the first conductive line 120A and the second conductive line 120B according to embodiments of the disclosure. In certain embodiments, the interconnects 1000A, 1000B are used to form a device die (e.g., one of the individual device dies formed by the dicing process in block 214 of Fig.2) to another die or to a circuit board, such as a printed circuit board.

[0052] It is contemplated that any of the above aspects and / or various separate aspects and features described herein may be combined for additional benefit. Each of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments, unless otherwise stated herein.

Claims

[1] A method of manufacturing a semiconductor device (400), the method comprising: performing (202) one or more grinding processes on a backside surface (418) of a device wafer (402) to thin the device wafer (402) from a first thickness to a second thickness; Performing (204) a first chemical mechanical polishing process, CMP, on the backside surface (418) of the device wafer (402) to thin the device wafer (402) from the second thickness to a third thickness; and Performing a second CMP process on the backside surface (418) of the device wafer (402) to selectively remove device wafer material disposed over an active device area of ​​the semiconductor device (400), wherein a removal rate of the device wafer material is a function of depth, wherein performing (202) the one or more grinding processes on the backside surface (418) of the device wafer (402) to thin the device wafer (402) from the first thickness to the second thickness comprises performing a first grinding process (500) and a second grinding process (502), the method further comprising at least one of: a) setting at least one first grinding parameter during the performance of the first grinding process (500) based on a first total thickness variation, TTV, wherein the at least one first grinding parameter comprises a rotational speed, rpm, of a spindle in a grinding tool or a wheel type used in the grinding tool; b) setting at least one first grinding parameter during the execution of the first grinding process (500) based on a first total thickness variation, TTV, wherein the at least one first grinding parameter comprises a rotational speed, rpm, of a step of the grinding tool or an inclination of the step of the grinding tool; and c) adjusting at least one second grinding parameter during the performance of the second grinding process (502) based on a second total thickness variation, TTV, wherein the at least one second grinding parameter comprises a rotational speed, rpm, of a spindle in a grinding tool, a wheel type used in the grinding tool, a rotational speed of a stage of the grinding tool, or an inclination of the stage of the grinding tool. [2] The method of claim 1, further comprising bonding (304) a carrier wafer (404) to the device wafer (402) prior to performing (202) the one or more grinding processes. [3] The method of claim 2, wherein the carrier wafer (404) is made of silicon, quartz or glass. [4] The method of claim 1, wherein the device wafer (402) comprises: the active device area disposed on a front surface (400) of the device wafer (402); a first isolation region disposed on the front surface (406) of the device wafer (402) and adjacent to a first edge of the active device area; and a second isolation region disposed on the front surface (406) of the device wafer (402) and adjacent to a second edge of the active device area. [5] The method of claim 4, wherein performing the second CMP process on the backside surface (418) of the device wafer (402) to selectively remove device wafer material disposed over the active device area of ​​the semiconductor device (400), creates a trench (800) between the first isolation region and the second isolation region, and exposes a backside surface of the active device area. [6] The method of claim 5, wherein the trench (800) has a depth of about one hundred nanometers. [7] The method of claim 5, further comprising forming a potting compound (900) in the trench (800). [8] The method of claim 7, wherein the encapsulant (900) is thermally conductive and is included in a heat transfer path for the semiconductor device (400). [9] The method of claim 1, further comprising: Bonding a carrier wafer (404) to the device wafer (402) prior to performing (202) the one or more grinding processes; and Removing the carrier wafer (404) after forming the potting compound (900) in the trench (800). [10] The method of claim 1, wherein the device wafer (402) is a silicon wafer. [11] The method of claim 1, wherein the first thickness is about seven hundred twenty-five micrometers and the second thickness is about five micrometers. [12] The method of claim 1, wherein the third thickness is about two hundred and fifty nanometers. [13] The method of claim 1, wherein performing the first CMP process on the backside surface (418) of the device wafer (402) further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer (402), wherein the at least one CMP parameter comprises the thickness profile of the device wafer (402) or a polishing agent flow rate. [14] The method of claim 1, wherein performing the first CMP process on the backside surface (418) of the device wafer (402) further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer (402), wherein the at least one CMP parameter comprises a rotational speed, RPM, of a polishing head of a polishing tool or a rotational speed of a platen of the polishing tool. [15] The method of claim 1, wherein performing the first CMP process on the backside surface (418) of the device wafer (402) further comprises adjusting at least one CMP parameter based on a thickness profile for the device wafer (402), wherein the at least one CMP parameter comprises at least a zone pressure of a polishing head of a polishing tool.

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