Multi-level DC power source for powering multi-level inverters

Abstract

A multi-level inverter control system includes a power storage system with a high-voltage input, a low-voltage input, and an intermediate-voltage input. The intermediate-voltage input is at a voltage between the high-voltage and low-voltage inputs. A multi-level inverter contains several switches, a high-voltage input connected to the high-voltage input, a low-voltage input connected to the low-voltage input, and an intermediate-voltage input connected to the intermediate-voltage input. A controller is coupled to the multi-level inverter and contains at least one processor and memory.The memory stores instructions configured to cause the controller to operate the multi-level inverter in a three-level inverter mode, a full-power two-level inverter mode, a first partial-power two-level inverter mode, and a second partial-power two-level inverter mode.

Description

INTRODUCTION

[0001] The present disclosure relates to a multi-level inverter configured to draw power from direct current (DC) power sources having multi-level outputs, and a control system therefor.

[0002] Electric vehicles and hybrid electric vehicles contain power storage systems that store electrical power and output DC power. However, drive motors and other mechanical features of the vehicle require alternating current (AC) power to operate. To enable the conversion of DC power to alternating current (AC) power, vehicles contain one or more inverters. Inverters use actively controlled switches (e.g., transistors) to convert the DC power into a sinusoidal or approximately sinusoidal AC power output.

[0003] Dual-level voltage-source inverters (and those with multiple levels) have limitations related to efficiency driven by high-voltage losses and current ripple, reliability degradation due to changes in dv / dt (voltage over time), changes in di / dt (current over time), electromagnetic interference, and power density degradation due to capacitance changes. Existing systems attempt to address some of these issues by using multi-level inverters. SUMMARY

[0004] According to an exemplary embodiment, a multi-level inverter control system includes a power storage system having a high-voltage terminal, a low-voltage terminal, and an intermediate-voltage terminal, the intermediate-voltage terminal being at a voltage between the high-voltage terminal and the low-voltage terminal, a multi-level inverter including a plurality of switches, a high-voltage input connected to the high-voltage terminal, a low-voltage input connected to the low-voltage terminal, and an intermediate-voltage input connected to the intermediate-voltage terminal, and a controller controllably coupled to the multi-level inverter, the controller including at least a processor and a memory, the memory storing instructions configured to causethat the controller operates the multi-level inverter in a three-level inverter mode, in a full-power two-level inverter mode, in a first partial-power two-level inverter mode, and in a second partial-power two-level inverter mode.

[0005] In addition to one or more of the features described herein, the power storage system is a battery including a plurality of cells, and the cells are divided into a first group of cells and a second group of cells, wherein a voltage difference between the low voltage terminal and the intermediate voltage terminal is a voltage of the first group of cells and a voltage difference between the intermediate terminal and the high voltage terminal is the voltage of the second group of cells.

[0006] In addition to one or more of the features described herein, the voltage difference of the first group of cells and the voltage difference of the second group of cells are equal.

[0007] In addition to one or more of the features described herein, the memory further includes instructions for identifying a cell fault in a cell in the first group of cells or in the second group of cells and instructions for responding to the identified cell fault by operating the multi-level inverter in the first partial power bi-level inverter mode when the identified cell fault is in the first group of cells and by operating the multi-level inverter in the second partial power bi-level inverter mode when the cell fault is in the second group of cells.

[0008] In addition to one or more of the features described herein, the multi-level inverter is a T-type inverter topology comprising a first capacitor connecting the high voltage input to the intermediate voltage input, a second capacitor connecting the intermediate voltage input to the low voltage input, a first switch connecting the high voltage terminal to an AC output, a pair of second switches connecting the intermediate voltage terminal to the AC output, and a third switch connecting the low voltage input to the AC output.

[0009] In addition to one or more of the features described herein, the first partial power bi-level inverter mode of operation includes keeping the first switch open, thereby electrically removing the first switch and the first capacitor from the multi-level T-type inverter topology, and operating the pair of second switches and the third switch as a bi-level inverter.

[0010] In addition to one or more of the features described herein, the second partial power bi-level inverter mode of operation includes keeping the third switch open, thereby electrically removing the third switch and the second capacitor from the multi-level T-type inverter topology and operating the pair of second switches and the first switch as a bi-level inverter.

[0011] In addition to one or more of the features described herein, the controller is further configured to operate the multi-level inverter in the first partial power mode while discharging a first set of cells in the power storage system until a charge threshold is reached, and configured to alternate operations between the first partial power bi-level inverter mode and the second partial power bi-level inverter mode, thereby maintaining a balance between the first set of cells and a second set of cells.

[0012] According to yet another exemplary embodiment, a method of operating an inverter in a vehicle power system includes operating the inverter in a multi-level mode while the vehicle power system is in a nominal mode, operating the inverter in a full-power bi-level inverter mode or in a first partial-power bi-level inverter mode or in a second partial-power bi-level inverter mode while the power system is in a non-nominal mode, and wherein the inverter is a T-type inverter topology including a first capacitor connecting a high-voltage input to an intermediate-voltage input, a second capacitor connecting the intermediate-voltage input to a low-voltage input, a first switch connecting the high-voltage terminal to an AC output, a pair of second switches,which connects the intermediate voltage terminal to the AC output, and a third switch which connects the low voltage input to the AC output. ,

[0013] In addition to one or more of the features described herein, the inverter is operated in the full-power dual-level inverter mode while the off-nominal mode is an identified fault in the pair of second switches of the inverter.

[0014] In addition to one or more of the features described herein, operation in the full power dual-level inverter mode includes maintaining at least one of the pair of second switches in an open state for a full duration of operation in the full power dual-level inverter mode.

[0015] In addition to one or more of the features described herein, the inverter is operated in the first partial power bi-level inverter mode while the non-nominal mode is a fault in at least one of a first set of power cells of an associated DC battery, a fault in the first capacitor, and a fault in the first switch, and the inverter is operated in the second partial power bi-level inverter mode while the non-nominal mode is a fault in at least one of a second set of power cells of the associated DC battery, a fault in the second capacitor, and a fault in the third switch.

[0016] In addition to one or more of the features described herein, operating in the first partial power bi-level inverter mode comprises maintaining the first switch in an open state for a duration of the first partial power bi-level inverter mode, and operating in the second partial power bi-level inverter mode comprises maintaining the third switch in an open state for a duration of the second partial power bi-level inverter mode.

[0017] In addition to one or more of the features described herein, the power system comprises a DC battery having a plurality of cells divided into a first set of cells and a second set of cells, the first set of cells being connected between the high voltage input and the intermediate voltage input, and the second set of cells being connected between the intermediate voltage input and the low voltage input.

[0018] In addition to one or more of the features described herein, the first partial power bi-level inverter mode is entered in response to a detected fault in the first set of cells and the second partial power bi-level inverter mode is entered in response to a detected fault in the second set of cells.

[0019] In addition to one or more of the features described herein, the first partial power bi-level mode of operation is entered in response to at least one condition that adversely affects inverter thermal characteristics, inverter efficiency, and inverter lifetime.

[0020] One or more of the features described herein further include balancing a battery system connected to the inverter, the battery system including a plurality of cells, the cells being divided into a first group and a second group, wherein a voltage difference between the low-voltage terminal and the intermediate-voltage terminal is a voltage of the first group and a voltage difference between the intermediate-voltage terminal and the high-voltage terminal is the voltage of the second group, by placing the inverter in the first partial-power bi-level inverter mode and discharging the first group until a charge threshold is reached, placing the inverter in the second partial-power bi-level inverter mode and discharging the second group until the charge threshold is reached,and alternating operations between the first partial power mode and the second partial power mode, thereby maintaining a balance between the first set of cells and a second set of cells.

[0021] According to yet another exemplary embodiment, a vehicle includes a power storage system having a high-voltage terminal, a low-voltage terminal, and an intermediate-voltage terminal, the intermediate-voltage terminal being at a voltage between the high-voltage terminal and the low-voltage terminal, at least two electric motors configured to convert AC power into mechanical rotation, a multi-level inverter connected to the power storage system and configured to output AC power, the multi-level inverter including a plurality of switches, a high-voltage input connected to the high-voltage terminal, a low-voltage input connected to the low-voltage terminal, and an intermediate-voltage input connected to the intermediate-voltage terminal, and a controller controllably coupled to the multi-level inverter,wherein the controller includes at least a processor and a memory, the memory storing instructions configured to cause the controller to operate the inverter in a three-level inverter mode, a full-power two-level inverter mode, a first partial-power two-level inverter mode, and a second partial-power two-level inverter mode.

[0022] In addition to one or more of the features described herein, the multi-level inverter is a T-type inverter topology comprising a first capacitor connecting the high voltage input to the intermediate voltage input, a second capacitor connecting the intermediate voltage input to the low voltage input, a first switch connecting the high voltage terminal to an AC output, a pair of second switches connecting the intermediate voltage terminal to the AC output, and a third switch connecting the low voltage input to the AC output.

[0023] In addition to one or more of the features described herein, the first partial power bi-level inverter mode of operation comprises keeping the first switch open and thereby electrically removing the first switch and the first capacitor from the multi-level T-type inverter topology and operating the pair of second switches and the third switch as a bi-level inverter, and the second partial power bi-level inverter mode of operation comprises keeping the third switch open and thereby electrically removing the third switch and the second capacitor from the multi-level T-type inverter topology and operating the pair of second switches and the first switch as a bi-level inverter.

[0024] The above features and advantages and other features and advantages of the disclosure will be readily apparent from the following detailed description when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Further features, advantages and details appear only as examples in the following detailed description, which refers to the drawings; they show: Fig. 1 illustrates an exemplary vehicle including a direct current (DC) power storage system and a pair of alternating current (AC) driven traction motors; Fig. 2 a schematic diagram of a multi-level inverter for converting DC power from the power storage system into AC power for the drive motors; Fig. 3 shows an exemplary single-phase branch of a T-type multi-level inverter topology; Fig. 4 the single-phase branch of a T-type multi-level inverter topology Fig. 3, which operates in a two-level mode without a center point; Fig. 5 the single-phase branch of a T-type multi-level inverter topology Fig. 3, which is operated in a first two-level partial power mode; and Fig. 6 a full T-type multi-level inverter topology using the phase branches from Fig. 3, which operates in a second two-level partial power mode. DETAILED DESCRIPTION

[0026] The following description is merely exemplary in nature and is not intended to limit the present disclosure, its application, or uses. It should be understood that corresponding reference numerals designate like or corresponding parts and features throughout the drawings. As used herein, the term module refers to processing circuitry that may include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory executing one or more software or firmware programs, combinational logic circuitry, and / or other suitable components that provide the described functionality.

[0027] According to some example embodiments, the multi-level inverter systems described herein generally utilize an intermediate voltage node at a lower voltage level than the high-voltage terminal and at a higher voltage level than the low-voltage (zero-voltage) terminal. The intermediate voltage node is directly connected to an intermediate voltage tap in a corresponding power source. According to some examples, the intermediate voltage tap is at a split in a split battery pack, where the battery pack includes multiple cells, and where the voltage at the split is a combined voltage of a subset of cells in the battery.Providing the direct connection to an intermediate voltage tap enables the multi-level inverter to operate more efficiently and allows the inverter to continue operating as a two-level inverter in additional operating modes during one or more fault conditions.

[0028] Fig. 1 shows an embodiment of a motor vehicle 10 including a vehicle body 12 that at least partially defines an occupant compartment 14. The vehicle body 12 also supports various vehicle subsystems, including a propulsion system 16, a battery system 22, and other subsystems for supporting functions of the propulsion system 16 and other vehicle components such as a braking subsystem, a suspension system, a steering subsystem, a fuel injection subsystem, an exhaust subsystem, and others.

[0029] The vehicle 10 may be an internal combustion engine vehicle, an electric vehicle (EV), or a hybrid vehicle. According to one embodiment, the vehicle 10 is a hybrid vehicle that includes an internal combustion engine system 18 and at least one electric motor assembly. For example, the propulsion system 16 includes a first electric motor 20 and a second electric motor 21. The motors 20 and 21 may be configured to drive wheels on opposite sides of the vehicle 10. Additionally, any number of motors positioned at various locations throughout the vehicle 10 may be used.

[0030] Battery system 22 may be electrically connected to motors 20 and 21 and / or to other components such as vehicle electronics. Battery system 22 may be configured as a rechargeable energy storage system (RESS) and includes multiple cells divided into sections and multiple voltage outputs (tap points).

[0031] Continue with Fig. 1 represents Fig. 2 illustrates an exemplary inverter system 200 including a multi-level inverter 210 for converting DC power from the battery system 22 into an AC power output 216 to one or more phases of the one or more motors 20, 21. The AC power output 216 provides drive power for the motor(s) 20, 21 to which the AC power output 216 is connected. The battery system 22 includes a high-voltage output terminal 202 and a low-voltage output terminal 204, each of which is connected to corresponding input terminals 212, 214 of the topology of the multi-level inverter 210. The connection between the high-voltage output terminal 202 and the high-voltage input 212 and a switch 344 (in Fig. 3-6, alternatively referred to as a first switch) connecting the high-voltage input 212 to the AC output 216 is referred to as the first high-voltage branch 404. Similarly, the connection between the low-voltage output terminal 204 and the low-voltage input 214 and the switch 346 (in Fig. 3-6, alternatively referred to as a third switch), which connects the low-voltage input to the AC output 216, is referred to as a low-voltage branch 406. The direct connection between the intermediate input 228 and the intermediate terminal 208 as well as the two switches 340, 342 (in Fig. 3-6, alternatively referred to as a pair of second switches) connecting the input 228 to the AC output 216 are referred to as the intermediate branch 402.

[0032] As used herein, "high voltage" refers to the voltage potential of the battery system 22 when fully charged, "low voltage" refers to a zero or approximately zero voltage potential, and "intermediate voltage" refers to a voltage potential between the high and low voltages. Switching within the inverter 210 is actively controlled by an active inverter controller 260 for converting the DC power to an AC power output at the AC power output 216. The inverter controller 260 may be a dedicated inverter controller, a module within a power system controller, a module within a general controller, a distributed control architecture, or any similar control system within the vehicle 10.

[0033] A pair of series-connected capacitors 222, 224 are connected across terminals 212, 214. Capacitors 222, 224 are connected at an intermediate voltage node 228. Intermediate voltage node 228 is directly connected to a corresponding intermediate voltage output terminal 208 of battery system 22. The intermediate voltage output node 208 may be provided at a midpoint between sets of cells 22', 22", modules, or packs within the battery system 22. According to alternative examples, the intermediate voltage output 208 may be a node connecting two series-connected battery systems 22 or any electrically similar power storage systems. The two sets of cells 22', 22" may have equal voltage potentials, the first set of cells 22' may have higher ones than the second set of cells 22", or the second set of cells 22" may have a higher voltage potential than the first set of cells 22'.As used herein, the voltage potential of a set of cells 22', 22" or other similar component refers to the voltage difference output by the set of cells 22', 22" while the set of cells 22', 22" is at full capacity.

[0034] The direct connection between the intermediate voltage node 228 and the intermediate voltage terminal 208 provides three stable voltage levels to power the inverter 210, whereby the intermediate voltage level is independent of the charge state of the capacitors 222, 224. The three stable voltage levels, in turn, allow the capacitors 222, 224 to function solely as high-frequency ripple current filters. Limiting them to the ripple filtering function enables a significant reduction in the physical size, volume, capacitance, and weight of the capacitors 222, 224.

[0035] Continue with Fig. 2 represents Fig. 3 illustrates a single phase branch of an exemplary multi-level inverter topology 310, which is used as the inverter 210 of the Fig. 2, wherein the topology 310 is a T-type inverter. In a three-phase example, the illustrated phase branch is repeated once for each phase. It will be appreciated that operations of the individual phase shown here are repeated simultaneously in each phase during operation of the full three-phase arrangement. The illustrated phase branch of the topology 310 is in the context of the inverter system 200 of Fig. 2 and is actively controlled by a controller within the vehicle in accordance with known control processes to produce AC power at an AC output of 216.

[0036] More specifically, the phase branch 310 contains, based on the T-type inverter phase branch 310 of Fig. 3 includes a first MOSFET switch 340 having a drain connected to the intermediate voltage node 228 and a source connected to the source of a second MOSFET switch 342. The drain of the second MOSFET switch 342 is connected to the power output 216. Furthermore, the phase branch 310 includes a third MOSFET switch 344 having a drain connected to the high-voltage output terminal 202 and a source connected to the AC power output 216. A fourth MOSFET switch 346 has a drain connected to the power output 216 and a source connected to the low-voltage output terminal 204.

[0037] Each of the switches 340, 342, 344, 346 is controlled by a control signal provided by a controller 260 to the corresponding gate. The controller 260 adjusts the control signals and switching rates in accordance with known inverter control methodologies to achieve desired AC power output characteristics at the power output 216.

[0038] In addition to the increased voltage stability at the intermediate node 228 due to the direct connection to an intermediate voltage output of the battery system 22, multi-tap connections to the battery system 22 enable the inclusion of additional operating modes of the T-type inverter 310 in response to various possible operating conditions (e.g., short circuits, overcurrents, charging demands, capacitor temperatures, etc.), thereby improving the operation of the vehicle power system.

[0039] Continue with Fig. 3 represent the Fig. 4-6 different additional operating modes, each of which Fig. 4, Fig. 5 and Fig. 6 represents a different operating mode.

[0040] Under some circumstances, a fault may occur at one or more points within the battery system 22 and the inverter 210. Depending on the location and type of fault, the required response may range from immediately terminating operations to continuing to operate indefinitely in a bi-level mode and monitoring. When such a fault occurs, the controller 260 electrically removes a section of the inverter 210 from the topology and operates the remaining sections as a bi-level inverter at either full or partial capacity, depending on the location and type of fault or the purpose for entering the bi-level mode. The section is electrically removed by holding open one or more switches 340, 342, 344, 346 within the section being removed, thereby preventing current from flowing through the section.

[0041] Continue with Fig. 1-3 represents Fig. 4 illustrates operation of the T-type inverter phase leg 410 as a bi-level inverter without a midpoint by holding open one or both of the pair of switches 344, 346 on the intermediate leg 402, thereby electrically removing the intermediate leg 402 from the circuit. This operation may be selected when a fault occurs in the intermediate leg 402. When this type of fault occurs, the controller 260 switches the inverter 210 to a bi-level inverter without a midpoint. The remaining two switches 344, 346, along with the capacitors 222, 224, are operated by the controller 260 as a conventional bi-level inverter providing an AC output 216.

[0042] The Fig. The operating mode illustrated in Figure 4 allows the inverter 210 to continue operating at full power level, but as a dual-level inverter, until the fault is corrected or can be addressed in another way. According to yet further examples, the Fig. The dual-level inverter operating mode shown in Figure 4 may be entered without a midpoint in response to a problem with branch 402. In some cases, the mode may be entered if conventional dual-level inverter operation is desired to achieve an efficiency, speed, or torque operating point.

[0043] According to alternative examples, the controller 260 may switch the inverter 210 to a Fig. 5 shown first partial power two-level inverter operating mode or in a Fig. 6 when there is a fault in either the high leg 404 or the low leg 406, or when there is a fault condition within one or more sets of cells 22', 22" of the battery system 22. The illustrated partial power bi-level inverter mode phase legs 510, 610 operate in a fundamentally similar manner due to the similar resulting circuit construction.

[0044] If a fault occurs in either the high leg 404 or the low leg 406, the controller 260 electrically removes the portion of the inverter 210 in which the fault occurred and shifts operation to the corresponding partial power dual-level inverter mode phase legs 510, 610. If the fault occurs in the first set of battery cells 22', in the first capacitor 222, or in the third switch 344, the controller 260 keeps the third switch 344 open, thereby preventing current from passing through the high voltage input leg 202 and in the Fig. 5. In contrast, when a fault occurs in the second set of battery cells 22', in the second capacitor 224, or in the fourth switch 346, the controller 260 keeps the fourth switch 346 open, thereby preventing current from passing through the low-voltage phase leg 406. Electrically isolating the third switch 344 or the fourth switch 346 ensures zero current in one direction. However, the switch 344, 346 may still conduct under positive bias. Appropriate gating of active switches prevents such positive bias from occurring and can be achieved according to known conventional techniques.

[0045] In the specific case of a fault within a cell 22', 22" in one of the sets of cells 22', 22" in the battery system 22, the partial power dual-level inverter mode phase leg 510, 610 electrically removes the corresponding sets of battery cells 22', 22", thereby enabling continued operation of the vehicle 10 without risking the propagation of the fault in the battery cell 22 to other cells 22', 22" or potentially further damage to the vehicle. The severity and cause of the battery cell fault influence how long the inverter 210 operates in the partial power mode from Fig. 5 and Fig. 6 can continue to operate. In connection with this, keeping the corresponding switch open removes the faulty capacitor from the circuit and prevents the fault from causing further damage to the inverter if a fault occurs in one of the capacitors 222, 224.

[0046] Although described above with respect to detected fault conditions, it will be appreciated that there is sensing technology for identifying other conditions that can utilize temporarily switching to a dual-level mode of operation. For example, the controller 260 may include a sensor input corresponding to the temperatures of the capacitors 222, 224 or otherwise determining the temperature of portions of the inverter 210. When such information is available, the controller 260 may switch to a dual-level mode of operation 510, 610 that electrically removes an overheating capacitor 222, 224 from the inverter 210 until the temperature of the capacitor 222, 224 has decreased, the mode of operation consisting of Fig. 5 is used when the capacitor 222 overheats, and the operating mode from Fig. 6 is used when capacitor 224 overheats. The cooling time may be either predetermined or based on a measured or derived temperature threshold. A similar process may be applied to any thermal detection within inverter 210 and is not limited to the specific example of capacitors 224, 222.

[0047] According to yet another example, the controller 260 may determine that there is an imbalance in the battery system 22 while the vehicle 10 is operating. If the imbalance is a result of the battery cell 22" having a higher charge, the controller 260 initially places the vehicle 10 in the first partial power dual-level inverter mode phase leg 510. Fig. 5 and discharges the first set of cells 22' in the battery system 22. When a sufficient charge threshold and a sufficient balance between the upper side and the lower side have been reached, a unity balance is then reached in the state of charge for the set of cells 22', 22". If the imbalance is a result of the battery cells 22' having a higher charge, the controller 26 orders the vehicle 10 in the Fig. 6 and the equilibrium is achieved in the same way.

[0048] According to yet another example, if one of the switches 340, 342, 344, 346 is inadvertently desaturated, the controller 260 may determine a saturation condition in one of the switches 340, 342, 344, 346 and allow the inverter 210 to continue operating in one of the dual-level inverter mode phase legs 410, 510, 610. The selected mode depends on the specific switch being desaturated, with the mode being Fig. 4 corresponds to the desaturation of switches 340 and 342, the operating mode from Fig. 5 corresponds to the desaturation of the switch 344 and the operating mode from Fig. 6 corresponds to the desaturation of the switch 346. As in the previous examples, the controller 260 detects the desaturation and places the inverter 210 in the appropriate operating mode that electrically removes the switch experiencing the saturation fault, and the inverter 210 can continue to operate when a desaturation fault occurs.

[0049] In certain cases, operation in the two-level partial power modes ( Fig. 5 and Fig.6) to achieve greater efficiency of low-speed operation of the motor(s) 20, 21. When the motor is operating at low speeds, half of the battery 22 can be reused with less DC bus voltage to power the motor(s) 20, 21. Applying a lower DC voltage improves inverter and motor efficiency. According to alternative control embodiments, the two-level partial power mode can be entered to prevent overheating of the inverter switches due to aging or faulty operation.

[0050] According to alternative examples, multi-level inverter 210 may include up to N intermediate voltage connections for an N-level inverter, where N is a total available voltage output from battery system 22. According to such examples, an extended form of the methodology described above may be utilized by controller 260 to switch an N-level inverter mode of operation to an N-1 level inverter in response to similar disturbances or conditions.

[0051] The terms "a" and "an" do not imply a limitation on the quantity, but rather denote the presence of at least one of the mentioned objects. Unless the context clearly indicates otherwise, the term "or" means "and / or." Reference throughout the specification to "an aspect" means that a particular element described in connection with the aspect (e.g., feature, structure, step, or property) is included in at least one aspect described herein and may or may not be included in other aspects. It is also understood that the described elements according to the various aspects may be combined in any suitable manner.

[0052] When an element, such as a layer, film, region, or substrate, is referred to herein as being "on" another element, it may be directly on top of the other element or may also have intervening elements present. In contrast, when an element is referred to as being "directly on" another element, no intervening elements are present.

[0053] Unless otherwise specified herein, all examination standards are the most recent examination standards in effect as of the filing date of this application or the filing date of the earliest priority application in which the examination standard appears, if priority is claimed.

[0054] Unless otherwise defined, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0055] Although the above disclosure has been described with reference to exemplary embodiments, those skilled in the art will understand that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope thereof. Furthermore, many changes may be made to adapt a particular situation or material to the teachings of the disclosure without departing from its essential scope. Thus, the present disclosure is not intended to be limited to the particular embodiments disclosed, but is intended to include all embodiments falling within its scope.

Claims

[1] Multi-level inverter control system comprising: a power storage system having a high voltage terminal, a low voltage terminal, and an intermediate voltage terminal, wherein the intermediate voltage terminal is at a voltage between the high voltage terminal and the low voltage terminal; a multi-level inverter including a plurality of switches, a high-voltage input connected to the high-voltage terminal, a low-voltage input connected to the low-voltage terminal, and an intermediate-voltage input connected to the intermediate-voltage terminal; and a controller controllably coupled to the multi-level inverter, the controller including at least a processor and a memory, the memory storing instructions configured to cause the controller to operate the multi-level inverter in a three-level inverter mode, a full-power two-level inverter mode, a first partial-power two-level inverter mode, and a second partial-power two-level inverter mode. [2] The multi-level inverter control system according to claim 1, wherein the power storage system is a battery including a plurality of cells, and wherein the cells are divided into a first group of cells and a second group of cells, wherein a voltage difference between the low voltage terminal and the intermediate voltage terminal is a voltage of the first group of cells, and a voltage difference between the intermediate terminal and the high voltage terminal is the voltage of the second group of cells. [3] The multi-level inverter control system of claim 2, wherein the voltage difference of the first group of cells and the voltage difference of the second group of cells are the same; and wherein the memory further includes instructions for identifying a cell fault in a cell in the first group of cells or in the second group of cells and instructions for responding to the identified cell fault by operating the multi-level inverter in the first partial power bi-level inverter mode when the identified cell fault is in the first group of cells and by operating the multi-level inverter in the second partial power bi-level inverter mode when the cell fault is in the second group of cells. [4] The multi-level inverter control system of claim 1, wherein the multi-level inverter is a T-type inverter topology comprising a first capacitor connecting the high voltage input to the intermediate voltage input, a second capacitor connecting the intermediate voltage input to the low voltage input, a first switch connecting the high voltage terminal to an AC output, a pair of second switches connecting the intermediate voltage terminal to the AC output, and a third switch connecting the low voltage input to the AC output. [5] The multi-level inverter control system of claim 4, wherein the first partial power bi-level inverter mode of operation comprises keeping the first switch open and thereby electrically removing the first switch and the first capacitor from the multi-level T-type inverter topology and operating the pair of second switches and the third switch as a bi-level inverter, and wherein the second partial power bi-level inverter mode of operation comprises keeping the third switch open and thereby electrically removing the third switch and the second capacitor from the multi-level T-type inverter topology and operating the pair of second switches and the first switch as a bi-level inverter. [6] The multi-level inverter control system of claim 1, wherein the controller is further configured to operate the multi-level inverter in the first partial power mode while discharging a first set of cells in the power storage system until a charge threshold is reached, and is configured to alternate operations between the first partial power bi-level inverter mode and the second partial power bi-level inverter mode, thereby maintaining a balance between the first set of cells and a second set of cells. [7] A method of operating an inverter in a vehicle power system, comprising: Operating the inverter in a multi-level mode while the vehicle power system is in a nominal mode; Operating the inverter in a full-power dual-level inverter mode or in a first partial-power dual-level inverter mode or in a second partial-power dual-level inverter mode while the power system is in a non-nominal mode; and wherein the inverter is a T-type inverter topology comprising a first capacitor connecting a high voltage input to an intermediate voltage input, a second capacitor connecting the intermediate voltage input to a low voltage input, a first switch connecting the high voltage terminal to an AC output, a pair of second switches connecting the intermediate voltage terminal to the AC output, and a third switch connecting the low voltage input to the AC output. [8] The method of claim 7, wherein the inverter is operated in the full-power bi-level inverter mode while the non-nominal mode is an identified fault in the pair of second switches of the inverter, and wherein operation in the full-power bi-level inverter mode comprises maintaining at least one switch of the pair of second switches in an open state for a full duration of operation in the full-power bi-level inverter mode. [9] The method of claim 7, wherein the inverter is operated in the first partial power bi-level inverter mode while the non-nominal mode is a fault in at least one of a first set of power cells of an associated DC battery, a fault in the first capacitor, and a fault in the first switch, and wherein the inverter is operated in the second partial power bi-level inverter mode while the non-nominal mode is a fault in at least one of a second set of power cells of the associated DC battery, a fault in the second capacitor, and a fault in the third switch,wherein operating in the first partial power bi-level inverter mode comprises maintaining the first switch in an open state for a duration of the first partial power bi-level inverter mode, and wherein operating in the second partial power bi-level inverter mode comprises maintaining the third switch in an open state for a duration of the second partial power bi-level inverter mode. [10] The method of claim 7, further comprising balancing a battery system connected to the inverter, the battery system including a plurality of cells, the cells being divided into a first group and a second group, a voltage difference between the low voltage terminal and the intermediate voltage terminal being a voltage of the first group and a voltage difference between the intermediate voltage terminal and the high voltage terminal being the voltage of the second group, by: Putting the inverter into the first partial power dual-level inverter mode and discharging the first group until a charging threshold is reached; Putting the inverter into the second partial power dual-level inverter mode and discharging the second group until the charging threshold is reached; and Alternating operations between the first partial power mode and the second partial power mode, thereby maintaining a balance between the first set of cells and a second set of cells.

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