Method for transmitting a message using a working memory used by at least two computing units

Abstract

The invention relates to a method for transmitting a message using a working memory (16a, 16b, 16c) used by at least two computing units (12, 14a, 14b, 14c, 26, 28), where each queue (20a, 20b, 20c) includes multiple places for indices, where the indices refer to messages in the message pool (18), wherein a first arithmetic unit (12) and a second arithmetic unit (14a, 14b and 14c) of the at least two arithmetic units (12, 14a, 14b, 14c, 26, 28) access the main memory (16a, 16b and 16c), the procedure comprises the following steps: - Allocating a storage space (S10); - Writing a message (p. 12); - Indexing the message and writing an index (S14) to a place in the queue (20a, 20b, 20c); - Reading the index (S16); - Determining the message (S18) using the index; - Use of the message (S20) by the second computing unit (14a, 14b, 14c).

Description

[0001] The invention lies in the field of interprocessor communication.

[0002] Interprocessor communication (IPC) refers to the exchange of information, data, and signals between different processes or processors in a computer system. It enables collaboration, coordination, and data exchange between running processes running on different processors or cores of a multiprocessor or distributed system.

[0003] IPC is independent of whether they run on the same system or on different systems. IPC can be both synchronous (blocking) and asynchronous (non-blocking).

[0004] Various mechanisms and methods for interprocessor communication are known.

[0005] In a shared memory mechanism, the participating processes share a common memory area to which they have read and write access. By reading and writing data to the shared memory, the processes can communicate with each other and exchange information.

[0006] In a message-passing mechanism, processes communicate by sending and receiving messages. There are two basic approaches: synchronous sending, in which the sending process blocks until the message is received, and asynchronous sending, in which the sending process sends the message and continues its execution without blocking.

[0007] Pipes and FIFOs (First-In-First-Out) are also mechanisms for communication between processes. Pipes are unidirectional and enable data transfer between a writing and a reading process. FIFOs are similar, but enable communication between multiple processes. Pipes are Linux / Unix-specific software implementations of a FIFO to enable IPC between two processes. However, a FIFO for IPC can also be created in the file system as a file.

[0008] The invention particularly relates to an IPC with shared memory. However, known embodiments are usually limited to a single operating system. A heterogeneous overall system with different operating systems and hardware architectures is generally not supported. Furthermore, such IPCs require a synchronization mechanism to ensure data integrity. This is typically achieved using mechanisms such as spinlocks, semaphores, and mutexes, but also via the operating system's scheduling.

[0009] In any case, the data is copied during IPC, which is complex. Furthermore, 1:n transmission cannot be supported. 1:n transmission means that a sender makes its data available to multiple receivers in parallel. If the sender and receiver write to the same memory, freedom from interference can be difficult in mixed ASIL applications. Furthermore, synchronization can cause one participant to slow down the other's runtime, which can result in undesirable interference.

[0010] The object of the invention is therefore to propose a mechanism that enables interprocessor communication between different processes and / or processors without copying and without a synchronization mechanism.

[0011] The problem is solved by the subject matter of the independent claims. Disclosure of the invention

[0012] According to a first aspect of the invention, this object is achieved by a method, in particular a computer-implemented method, for transmitting a message using a working memory used by at least two processing units. The working memory comprises at least one memory area configured as a message pool. Each message pool is assigned at least one queue. Each queue, in turn, comprises several locations for indices that refer to messages in the message pool. A first processing unit and a second processing unit of the at least two processing units access the working memory. To this end, the method comprises the following steps: - Allocating a storage space in the message pool by the first processing unit; - Writing a message into the allocated memory space by the first processing unit; - Indexing the message and writing an index of the message into a place in the queue by the first processing unit; - Reading the index from the queue by the second processing unit; - Determining the message using the index by the second computing unit; - using the message by the second processing unit; and - Checking for release of the message and marking the place in the queue for reuse by the first processing unit.

[0013] In the context of this invention, a computing unit can be a physical or a virtual computing unit. In particular, two or more computing units can comprise cores of a CPU. Furthermore, computing units can be implemented by virtual machines, GPUs, microprocessors, or microcontrollers.

[0014] Each queue connects two processing units communicatively. One of the processing units is a sender, and the other is a receiver of the message to be transmitted. At least one queue is thus part of the memory management system, and each queue is linked to a message pool.

[0015] Each message pool contains a set of messages or storage locations into which messages can be written. A message and a storage location for a message are two sides of the same coin. The message is a piece of information consisting of bits. The storage location is the physical representation of that message, an area on a piece of hardware in which bits are stored in a volatile or non-volatile manner. The terms storage location and message are therefore interchangeable.

[0016] If the processing units have different hardware architectures and / or operating systems, it may happen that the memory is accessed differently by the processing units. This obstacle is overcome by transferring the message from one processing unit to the other via an index.

[0017] The index refers to a position within a data structure, in particular to a position in a table. According to the invention, a pointer pointing to the storage location of a specific data area in the main memory is stored at the position to which the index refers, using a look-up table, or, using a conversion function, a pointer is calculated that also points to the storage location of a specific data area in the main memory.

[0018] A pointer provides direct access to the value or data stored at a specific memory address in the main memory. In particular, it contains information about the position or address of the memory area it points to.

[0019] If the second processing unit cannot use the index directly because it accesses the main memory differently than the first processing unit, then the step of determining the message can be performed, for example, by assigning or translating the index using a look-up table or a conversion function that translates the position of the memory location marked with the index for the second processing unit.

[0020] According to the present invention, the index is used to enable access to shared resources or data structures. By passing the index between the computing units, they can access the same memory area and exchange data without having to create a copy of the data. In the context of the main memory, the use of the index in a queue enables the dynamic allocation and management of memory resources without copying. The transfer of the message from the first to the second computing unit therefore comprises at least the first computing unit providing the message and a corresponding index, reading the index, and the second computing unit determining the provided, indexed message. Using the message can, for example, comprise reading data from the message and / or forwarding the message.Overall, the proposed mechanism solves the problem of the invention.

[0021] In one embodiment, the following steps precede checking for message release: - Assigning a usage value for the index when the index is written by the first computing unit; - Assigning a release value for the index after the message has been used by the second processing unit; and - Transferring the release value from the second computing unit to the first computing unit.

[0022] The release check includes a comparison of the release value and the usage value.

[0023] For each message, a special memory area can preferably be reserved for a usage indicator, which indicates whether the message is still needed or whether it can be replaced by another message. The usage indicator can preferably comprise one bit and thus the values ​​"0" for "unused" and "1" for "used." The first computing unit releases the indexed space in the message pool by setting the usage indicator to "unused" or "0." According to this embodiment, it can do this in particular when the release value and the usage value of an index match. Only unused messages can be allocated for further transmissions and overwritten with new information.

[0024] When a message is allocated, a usage value is assigned. In some embodiments, this can be incremented, for example, so that the usage value indicates how often an index has been passed for use. For example, if an index has been passed to another processing unit, a usage value of 1 is assigned, or the usage value of 0 is incremented to 1.

[0025] After use, the second processing unit assigns the release value. A release value of 1 means that a user of the message (the second processing unit) is no longer using the message. In one embodiment, the second processing unit can adopt the usage value as the release value, so that they are identical and the message is released.

[0026] If the usage value and the release value match, this means that no user is using the message anymore. It can therefore be marked as "unused" and released for allocation.

[0027] The transfer of the release value from the second computing unit to the first computing unit can be carried out in particular via the shared main memory.

[0028] Advantageously, comparing the usage value with the release value prevents a shortage of messages, as the first processing unit can regularly check for messages that are no longer in use and release them for re-allocation.

[0029] In an alternative embodiment, the second processing unit can forward the message to another processing unit. To do this, the method is extended by the following steps before releasing the message: - Assigning a usage value for the index when allocating the message by the first processing unit; - indexing the message and writing the index of the message to a location in another queue by the second processing unit after the message has been used by the second processing unit; - Reading the index from the further queue by the further processing unit; - Determining the message based on the index by the further processing unit; - Use of the message by the further processing unit; - Assigning a release value for the index after the message has been used by the further processing unit; and - Transferring the release value from the further computing unit to the first computing unit.

[0030] The release check includes a comparison of the release value and the usage value.

[0031] In principle, this embodiment is similar to the embodiment with two processing units. They differ in that in this embodiment, the enable value is assigned by the additional processing unit.

[0032] In principle, this implementation could also be implemented with any number of processing units. The principle is therefore expandable by passing the index from one processing unit to the next, which then, in turn, determines the message based on the received index and uses it. As long as the release value is not assigned, the message is considered used and can be used consecutively by any number of processing units. Only the last processing unit in a working chain of processing units assigns the release value, so that the message can then be marked as unused by the first processing unit and allocated for the transmission of further messages.

[0033] The transfer of the release value from the further computing unit to the first computing unit can be carried out in particular via the shared main memory.

[0034] In another embodiment, indexing the message comprises adding a timestamp to the message. Checking for release may then comprise checking the timestamp of the message, such that the first computing unit releases the indexed space in the queue when checking the timestamp indicates that the message has reached a defined age.

[0035] It's possible for processes to be interrupted or stop unexpectedly. In particular, if the first processing unit is waiting for a message's release value, the value might not be assigned, meaning that a message couldn't be marked as "unused" without the release value being assigned. If this happens too frequently, a data leak would occur, resulting in the memory eventually becoming completely full, preventing a new message from being written to the message pool.

[0036] Assigning and subsequently checking the timestamp of a message solves this problem because after a certain time has elapsed, i.e. when the message has reached a certain age, the message can be reallocated independently of its use by the second or another processing unit.

[0037] In a further embodiment, at least one further second processing unit accesses the main memory. In this embodiment, the process between the first processing unit and the at least one further second processing unit is carried out using a separate queue.

[0038] The at least one additional second processing unit is treated in the same way as the "first" second processing unit. This means that all second processing units are co-located and receive an index from the first processing unit. In each pairing of first processing unit and second processing unit, a queue is used to transfer the indexes. Accordingly, as many queues are required as the number of second processing units that can receive indexes.

[0039] In another embodiment, each queue is associated with the same message pool.

[0040] The advantageous effect of assigning identical message pools is that even later-joining processing units with a pre-allocated memory area in the main memory shared with the first processing unit can use messages from the first processing unit. This can also be referred to as a late-joining service.

[0041] Alternatively, this embodiment can also be used to offload the workload of one processing unit to other processing units. For example, if one processing unit is over-utilized, a second processing unit can be added, using the messages from the first processing unit instead of the originally intended processing unit.

[0042] As a further alternative, this embodiment enables copy-free distribution of a message to multiple processing units in parallel. This process is then also referred to as multiplexing or multicasting.

[0043] When multiple processing units are expecting the same message, this embodiment can be used to accelerate the transmission of messages to multiple processing units. Because the process is copy-free, the time between writing the message and its use by the receiving processing unit is minimized.

[0044] In this embodiment, in particular, the allocation of the release value can be performed by every second processing unit. The first processing unit then checks whether the sum of the release values ​​equals the usage value. For example, if the first processing unit has distributed an index to three second processing units, it can set the usage value to 3. In particular, the usage value will be set after the message has been allocated and before it is sent to the second processing units.

[0045] After the message has been used, the three second processing units assign the release value so that the first processing unit can count the assigned release values. When the first processing unit counts three release values, the usage value and the release values ​​match, so the first processing unit recognizes that the message is no longer being used by any processing unit. It can now mark the message as "unused" and thus release it for allocation.

[0046] This embodiment can advantageously be used to transmit a message to several computing units in parallel without copying.

[0047] In one embodiment, a system can comprise multiple processing units, some of which are arranged in parallel and some of which are arranged in series. For example, a first processing unit can provide a message to three second processing units. Of these three second processing units, two can forward the message to further processing units, and so on. The proposed method allows any number of processing units to be arranged in parallel and / or in series, each of which accesses a shared main memory.

[0048] In one embodiment, the computing units are operated with different operating systems.

[0049] This embodiment enables the operation of so-called system-on-a-chip applications (SoCs). In SoCs, different computing units are built into a single chip, which then share common resources, including, in particular, RAM. For example, one computing unit can be a microprocessor and another a microcontroller.

[0050] A microcontroller and a microprocessor are two different types of integrated circuits used in electronic devices. Although they can perform similar tasks, there are fundamental differences in their structure, architecture, and functionality.

[0051] A microcontroller is a single integrated circuit that combines a processor (CPU), memory (ROM, RAM), and various input and output interfaces. It is therefore a complete unit specifically designed for a specific application or task. A microcontroller is typically designed to perform tasks independently. It contains the program code and data required to control a specific application or system, for example. Microcontrollers are often found in embedded systems, such as household appliances, automobiles, industrial controllers, etc. They offer easy programmability and are specialized to perform specific tasks efficiently and deterministically.

[0052] In contrast, a microprocessor consists only of the CPU and lacks the integrated memory or peripherals of a microcontroller. Microprocessors are designed to be used in conjunction with external components to form a complete system. This makes a microprocessor more flexible and can be used in a variety of applications. Microprocessors are commonly used in general-purpose computers, laptops, smartphones, and other devices that require high processing power and flexibility. They can perform a wide variety of tasks but may not be as efficient in specific applications as microcontrollers.

[0053] In SoCs, the advantages of both computing units are combined in a single chip design, which, however, requires the shared memory to be handled by different operating systems.

[0054] In one embodiment, the distance between the storage locations for the indices in the queue corresponds at least to the largest data bus width of the computing units accessing the main memory.

[0055] The lower limit for the spacing of the memory locations set in this embodiment advantageously ensures that the arithmetic units can read the indices consistently from the main memory despite different data bus widths, since the readout width (memory alignment) is adapted to the largest data bus width. Otherwise, with smaller memory readout widths, arithmetic units with larger data bus widths might not be able to read the indices consistently.

[0056] For example, if the data bus width of a processing unit is 64 bits and the distance between the memory locations in the main memory is 32 bits, then the processing unit would access the index in an overlapping manner, since the read bits would contain parts of two indices.

[0057] For example, if a 64-bit system accesses a 32-bit index with a 32-bit memory alignment, two indexes are read or written during a memory access. The correct location of the index in memory is ensured by the hardware. However, since only 64-bit data can be read or written at the hardware level in a 64-bit system, two 32-bit indexes would always be accessed. However, because only one index is to be written during a write operation, a potential race situation arises for the second index with another processing unit accessing the second index.

[0058] In a further embodiment, the allocated memory space for an index corresponds at most to the smallest data bus width of the computing units accessing the main memory.

[0059] This embodiment advantageously ensures that even computing units in the system with a small data bus width can read the indices consistently.

[0060] For example, if a processing unit with a 32-bit data bus width were to read a 64-bit index, it would have to do so in two 32-bit steps. However, since indices should always be read as a whole and consistently, it is advantageous to adjust the size of the indices to the smallest data bus width from the outset.

[0061] Overall, it's not a problem for reading the indices if the distances between the indices are larger than the indices themselves. For example, 32-bit indices can be stored at 64-bit intervals. A processing unit with a 64-bit data bus width would read a 32-bit index and 32 additional empty or unused bits. This doesn't affect the reading process, but may result in increased memory requirements for the messages. This prevents a potential race situation with other processing units accessing the same or adjacent value.

[0062] In one embodiment, the queue is designed as a ring buffer.

[0063] A circular buffer is a data structure used to manage data of a fixed size. It is based on the concept of a cyclic arrangement of memory locations organized like a ring. The circular buffer is particularly useful in situations where continuous data acquisition or processing is required while older data is discarded.

[0064] The function of a ring buffer is to store, read, and manage data. A defined memory area is used cyclically, enabling a continuous flow of data. The ring buffer has a fixed capacity that is defined in advance.

[0065] The circular buffer uses two indexes, the read index (also called the "head") and the write index (also called the "tail"), to track the state of the data structure. The write index points to the position where new data is inserted, while the read index points to the position where data is read.

[0066] In one embodiment, the distance between the read and write indices corresponds at least to the largest data bus width of the processing unit accessing the main memory. Furthermore, the data bus width corresponds to the smallest data bus width of the processing unit accessing the main memory.

[0067] This advantageously prevents a potential race situation with another processing unit that accesses the same or an adjacent value.

[0068] New data is inserted at the current position of the write index. The write index is then moved to the next position in the circular buffer. When the write index reaches the end of the buffer, it is reset to the beginning, enabling the cyclic nature of the buffer. When the buffer is full—that is, when the write index catches up with the read index—the write operation is suspended until there is room for new data.

[0069] If the data or message index is overwritten, this message index can no longer be read by secondary processing units. As a result, this message can no longer be released by the secondary processing units. This corresponds to a memory leak in the messages. However, the number of messages in the message pool and the number of entries in the ring buffer can fundamentally differ.

[0070] The data is retrieved and read from the current position of the read index. The read index is then moved to the next position in the circular buffer. When the read index reaches the end of the buffer, it is also reset to the beginning. Once the read index has caught up with the write index, the buffer is empty.

[0071] A key advantage of a ring buffer is its minimal storage space. Because the buffer has a fixed size and older data can be overwritten, it's particularly suitable when the most recent data is more important than the older data. The ring buffer is preferably used in various applications, such as audio processing, sensor technology, and many other situations where continuous data acquisition and processing is required.

[0072] In one embodiment, the message is a parameter of a system, in particular a motor vehicle. The parameter can be, for example, but not limited to, the current speed, the steering angle, the charge level of a vehicle battery, or a similar quantity.

[0073] A specific application could, for example, involve continuously recording the speed using a microcontroller and writing it to a RAM. Microprocessors then decide, depending on the current speed, whether and, if so, how the measured value is further processed. This further processing could, for example, include saving the speed in persistent memory, thus creating a history of the speed traveled.

[0074] In a further aspect, the invention relates to a computer program with program code for carrying out a computer-implemented method for transmitting a message by means of a working memory used by at least two computing units as described above when the computer program is executed on a computer.

[0075] In a further aspect, the invention relates to a computer-readable data carrier with program code of a computer program for carrying out a method for transmitting a message by means of a working memory used by at least two computing units as described above when the computer program is executed on a computer.

[0076] In a further aspect, the invention relates to a system for transmitting a message by means of a working memory used by at least two computing units, the system comprising: - a RAM, - a first computing unit, and - a second computing unit, wherein the system comprises means for carrying out the method as described above.

[0077] Overall, a method, a computer program, a computer-readable data carrier and a device are specified.

[0078] The described designs and further training courses can be combined as desired.

[0079] Further possible embodiments, developments and implementations of the invention also include combinations of features of the invention described previously or below with regard to the embodiments that are not explicitly mentioned. Short description of the drawings

[0080] The accompanying drawings are intended to provide a further understanding of embodiments of the invention. They illustrate embodiments and, in conjunction with the description, serve to explain principles and concepts of the invention.

[0081] Other embodiments and many of the aforementioned advantages will become apparent upon review of the drawings. The elements illustrated in the drawings are not necessarily drawn to scale.

[0082] They show: Fig. 1 a schematic representation of the proposed method according to an embodiment; Fig. 2 schematically shows the structure of a system comprising two computing units according to an embodiment; Fig. Figure 3 schematically shows three messages stored in adjacent memory areas; Fig. 4 schematically shows a further embodiment with a system having four computing units connected concurrently to one another via three main memories; Fig. 5 schematically shows a further embodiment with a system having four computing units that are connected concurrently to one another via a common main memory; Fig. 6 schematically shows a further embodiment with a system having four computing units that are sequentially connected to one another via a common main memory.

[0083] In the figures of the drawings, the same reference symbols designate the same or functionally equivalent elements, parts or components, unless otherwise stated.

[0084] Fig. Figure 1 schematically shows the flow of a method according to one embodiment. In a first step S10, a first processing unit allocates a memory location in a message pool. The first processing unit then writes a message to the allocated memory location in step S12 and writes information to it.

[0085] In the next step S14, the message is indexed by the first processing unit. Indexing means converting the message's memory address or the pointer pointing to it into an index. This index can be recalculated by the second processing unit(s) in its address space as the message's memory address.

[0086] The first processing unit writes the message index to a location in a queue. This location in the queue can be empty or contain an index of a no longer used message.

[0087] A second processing unit can access the main memory and reads a location from the queue or the index stored therein in step S16. Using the index, the second processing unit retrieves the message from the main memory in step S18 for use in step S20. The message can, for example, be used for a computing operation, forwarded to a peripheral (e.g., CAN, Ethernet), or transferred to persistent storage.

[0088] A message that is no longer needed can be released by the second processing unit.

[0089] In the final step S22, the first processing unit checks whether the message can be released. If so, the memory location containing the message can be reallocated and the index in the queue can be reassigned.

[0090] Fig. 2 schematically shows the structure of a system 10 with a first computing unit 12 and a second computing unit 14. The computing units 12 and 14 share a common memory 16, which they can both access.

[0091] In one embodiment, the access rights of the computing units 12, 14 to the main memory 16 are restricted or partially restricted. For example, the first computing unit 12 can be configured such that it can write messages but not read them. Furthermore, the second computing unit 14 can be configured, for example, such that it can only read the main memory 16 but not write to it. Preferably, the second computing unit 14 is equipped with the right to write to at least part of the main memory 16, in particular an enable value. The enable value indicates whether a respective message is still being used by the second computing unit 14 or not.

[0092] Memory 16 is reserved for a message pool 18, in which the messages are stored. A queue 20 comprising several locations for indexes of the messages from the message pool 18 is assigned to the message pool 18. The indexes thus indicate the exact location in the memory 16 where the messages are stored.

[0093] In principle, entire messages could also be transferred directly from the first processing unit 12 to the second processing unit 14 via the queue. However, this would take significantly more time, measured in clock cycles, because the indices are much smaller than the actual messages.

[0094] In Fig. 3 shows, according to one embodiment, the intervals at which 22 indices 24 can be arranged in a queue or the values ​​in a message pool.

[0095] The 24 indices or values ​​have a length of 1. The length of 1 is chosen so that it corresponds at most to the smallest data bus width of the processing units accessing the message pool and the queue. This ensures that even processing units with small data bus widths can read the indices completely, uninterruptibly, and in one go.

[0096] The indices 24 are arranged at a distance of length L. The length L corresponds to at least the largest data bus width of the processing units accessing the main memory. Processing units with a data bus width that is too small could also write to the neighboring indices 24, especially during a write operation. However, this should be avoided at all costs.

[0097] Preferably, all processing units accessing the memory have the same data bus width, so that the lengths L and I can be identical. In this case, the memory used as a spacer would be minimized.

[0098] Fig. Figure 4 shows an embodiment of a system 10 with a first processing unit 12 and three second processing units 14a, 14b, and 14c. The first processing unit 12 communicates with the second processing units 14a, 14b, and 14c, each via its own memory 16a, 16b, and 16c. It can offer its services to the second processing units 14a, 14b, and 14c independently of one another and operate in a distribution function.

[0099] Each second processing unit 14a, 14b, and 14c generally only has access to the memory 16a, 16b, and 16c shared with the first processing unit 12. Messages from the other second processing units 14a, 14b, and 14c are beyond the access horizon. Due to this separation of the memory 16a, 16b, and 16c, this embodiment is suitable for applications with different security requirements for the second processing units 14a, 14b, and 14c. Furthermore, additional second processing units 14a, 14b, and 14c, each with its own memory 16a, 16b, and 16c, can be added at a later time.

[0100] In Fig. Figure 5 schematically illustrates another embodiment. In this embodiment, the system 10 comprises a first processing unit 12, a main memory 16, and three second processing units 14a, 14b, and 14c. Each of the second processing units 14a, 14b, and 14c communicates with the first processing unit 12 via the shared main memory 16 and a shared message pool 18. However, a separate queue 20a, 20b, and 20c is provided for each second processing unit 14a, 14b, and 14c.

[0101] In this embodiment, although all messages originate from one sender, the first processing unit 12, they can have one or more receivers, the second processing units 14a, 14b, and 14c. Individual messages can thus be sent to multiple recipients simultaneously without copying.

[0102] This embodiment is suitable, for example, for routing messages when the message storage space for data reception must be made available before the actual recipient is known. For computationally intensive tasks, another embodiment constructed in this way can be used to dynamically add or remove resources in the form of second computing units 14a, 14b, and 14c.

[0103] In this embodiment, a message can be used multiple times. It is therefore all the more important that the first computing unit 12 uses a usage value that keeps track of the number of indices per message.

[0104] For example, if an index of a message has been passed via two queues to two of the second processing units 14a, 14b, and 14c, the first processing unit 12 must wait until none of the processing units 14a, 14b, and 14c is using the message anymore. To enable this, every second processing unit 14a, 14b, and 14c can assign a release value. The sum of all release values ​​is then compared by the first processing unit 12 with the usage value. If the values ​​are equal, the number of second processing units 14a, 14b, and 14c that have released the message equals the number of times it was distributed. This ensures that the message is no longer being used. The first processing unit 12 can then release the message.

[0105] Fig. Figure 6 shows an embodiment of a system 10 with four computing units 12, 14, 26, and 28 connected in series. All computing units 12, 14, 26, and 28 share a common memory 16 and access a shared message pool 18.

[0106] In contrast to the embodiment from Fig.5, the processing units 12, 14, 26, and 28 are connected sequentially via the queues 20a, 20b, and 20c. The first processing unit 12 can, for example, write a message from the message pool 18, so that the second processing unit 14 can process this message after receiving it. Instead of releasing the message after use, the processing unit 14 can, in turn, pass the message on to the next processing unit 26 by writing a corresponding index to the queue 20b. The processing unit 26 can then also retrieve the message from the message pool 18, whereby the message itself does not need to be copied.

[0107] In the illustrated embodiment, there is another processing unit 28 that uses the message one last time. To do so, it receives an index of the queue 20c from the processing unit 26.

[0108] The last processing unit 14, 26 and 28 that uses the message and passes it on unindexed to the next processing unit marks the message as released so that the first processing unit 12 can mark the message as unused and reallocate the storage space.

Claims

[1] Method for transmitting a message by means of a working memory (16a, 16b, 16c) used by at least two computing units (12, 14a, 14b, 14c, 26, 28), wherein the working memory (16a, 16b and 16c) comprises at least one memory area configured as a message pool 18, wherein each message pool 18 is assigned at least one queue (20a, 20b, 20c), wherein each queue (20a, 20b, 20c) comprises a plurality of locations for indices, the indices referring to messages in the message pool (18), wherein a first computing unit (12) and a second computing unit (14a, 14b and 14c) of the at least two computing units (12, 14a, 14b, 14c, 26, 28) access the main memory (16a, 16b and 16c), the method comprising the following steps: - allocating a storage space (S10) in the message pool (18) by the first computing unit (12); - writing a message (S12) into the allocated memory space by the first computing unit (12); - indexing the message and writing an index (S14, 24) of the message into a place in the queue (20a, 20b, 20c) by the first computing unit (12); - reading the index (S16, 24) from the queue (20a, 20b, 20c) by the second computing unit (14a, 14b, 14c); - determining the message (S18) using the index (24) by the second computing unit (14a, 14b, 14c); - using the message (S20) by the second computing unit (14a, 14b, 14c); and - Checking for release (S22) of the message and marking the place in the queue (20a, 20b, 20c) for reuse by the first computing unit (12). [2] Method according to claim 1, wherein the checking for release (S22) of the message is preceded by the following steps: - Assigning a usage value for the index (24) by the first computing unit (12); - Assigning a release value for the index (24) after the message has been used by the second computing unit (14a, 14b, 14c); and - transmitting the release value from the second computing unit (14a, 14b, 14c) to the first computing unit (12), wherein the check for the release (S22) comprises a comparison of the release value and the usage value. [3] Method according to claim 1, wherein a further computing unit (26, 28) accesses the working memory (16a, 16b, 16c), wherein the checking for the release (S22) of the message is preceded by the following steps: - Assigning a usage value for the index (24) when the index is written by the first computing unit (12); - indexing the message and writing the index (24) of the message into a location in a further queue (20a, 20b, 20c) by the second computing unit (14a, 14b, 14c) after the message has been used by the second computing unit (14a, 14b, 14c); - reading the index (24) from the further queue (20a, 20b, 20c) by the further computing unit (26, 28); - Determining the message using the index (24) by the further computing unit (26, 28); - using the message by the further computing unit (26, 28); - Assigning a release value for the index (24) after the message has been used by the further computing unit (26, 28); and - transmitting the release value from the further computing unit (26, 28) to the first computing unit (12), wherein the check for the release comprises a comparison of the release value and the usage value. [4] Method according to one of the preceding claims, wherein indexing the message (S14) comprises adding a timestamp to the message and wherein checking the release (S22) comprises checking the time stamp of the message, wherein the first computing unit (12) releases the indexed space in the queue (20a, 20b, 20c) when checking the timestamp indicates that the message has reached a defined age. [5] Method according to one of the preceding claims, wherein at least one further second computing unit (14a, 14b, 14c) accesses the main memory, wherein the method is carried out between the first computing unit (12) and the at least one further second computing unit (14a, 14b, 14c), each with its own queue (20a, 20b, 20c). [6] Method according to claim 5, wherein each queue (20a, 20b, 20c) is associated with the same message pool (18). [7] Method according to one of the preceding claims, wherein the computing units (12, 14a, 14b, 14c, 26, 28) are operated with different operating systems. [8] Method according to one of the preceding claims, wherein the distance between the memory locations for the indices (24) in the queue (20) corresponds at least to the largest data bus width of the computing units (12, 14a, 14b, 14c, 26, 28) accessing the main memory (16a, 16b, 16c). [9] Method according to one of the preceding claims, wherein the memory space for an index (24) in the queue (20) corresponds at most to the smallest data bus width of the computing units (12, 14a, 14b, 14c, 26, 28) accessing the main memory (16a, 16b, 16c). [10] Method according to one of the preceding claims, wherein the queue (20a, 20b, 20c) is arranged as a ring buffer. [11] Computer program with program code for carrying out a computer-implemented method for transmitting a message by means of a working memory (16a, 16b, 16c) used by at least two computing units (12, 14a, 14b, 14c, 26, 28) according to one of the preceding claims when the computer program is executed on a computer. [12] Computer-readable data carrier with program code of a computer program for carrying out a method for transmitting a message by means of a working memory (16a, 16b, 16c) used by at least two computing units (12, 14a, 14b, 14c, 26, 28) according to one of claims 1 to 10 when the computer program is executed on a computer. [13] System for transmitting a message by means of a working memory (16a, 16b, 16c) used by at least two computing units (12, 14a, 14b, 14c, 26, 28), the system comprising: - a main memory (16a, 16b, 16c), - a first computing unit (12), and - a second computing unit (14a, 14b, 14c), the system comprising means for carrying out the method according to one of claims 1 to 10. [14] System according to 13, where - the first computing unit (12) is a microprocessor and the second computing unit (14a, 14b, 14c) is a microcontroller or - the first computing unit (12) is a microcontroller and the second computing unit (14a, 14b, 14c) is a microprocessor.

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