Method for manufacturing a component

Abstract

A method for fabricating a component (100) comprises a provisioning step, a deposition step, an attachment step, and an ignition step. In the provisioning step, a structured layer (105) with at least one terminal (110, 120, 130) is provided, forming at least one power semiconductor device (135). In the attachment step, a heat dissipation nanolayer (115) is deposited onto the terminal (110, 120, 130) such that the terminal (110, 120, 130) is covered with the heat dissipation nanolayer (115). In the attachment step, a printed circuit board (200) is attached to the power semiconductor device (135) such that the heat dissipation nanolayer (115) is arranged between the terminal (110, 120, 130) of the power semiconductor device (135) and at least one terminal surface (210, 220, 230) of the printed circuit board (200).In the ignition step, the heat dissipation nanolayer (115) is ignited to electrically contact the terminal (110, 120, 130) of the power semiconductor device (135) and the connection area (210, 220, 230) of the printed circuit board (200).

Description

[0001] The present invention relates to a method for manufacturing a component using a reactive multilayer system and to a component, for example a chip.

[0002] DE10 2012 110 549 A1 discloses a device for ignition and reaction transfer in reactive multilayer systems.

[0003] Further state of the art is disclosed in DE11 2008 002 377 T5 and DE102009006822 A1.

[0004] Against this background, the present invention provides an improved method for manufacturing a component and an improved component according to the main claims. Advantageous embodiments are described in the dependent claims and the following description.

[0005] The main advantage achievable with the approach presented here is that it enables improved heat dissipation within a component. This, in turn, can improve the component's functionality.

[0006] A method for fabricating a component comprises a provisioning step, a deposition step, an attachment step, and an ignition step. In the provisioning step, a structured layer is provided that forms at least one power semiconductor device with at least one terminal. In the deposition step, a reactive heat dissipation nanolayer is deposited onto the at least one terminal to cover it. In the attachment step, the structured layer is attached to a printed circuit board (PCB) having at least one terminal pad, with the heat dissipation nanolayer positioned between the at least one terminal of the power semiconductor device and at least one terminal pad of the PCB.In the ignition step, the heat dissipation nanolayer is ignited to electrically and thermally contact at least one terminal of the power semiconductor component and at least one connection surface of the circuit board.

[0007] The component can be a single chip, such as a transistor or a diode. The structured layer can be a single-crystal layer or a non-crystalline layer. For example, the structured layer can be an epitaxial layer, which can be grown epitaxially or fabricated using epitaxy. The structured layer can be a single portion of a wafer. The structured layer can have only a single terminal. In the example of a diode, for instance, there is only one terminal on the top side (anode) and one terminal on the opposite bottom side (cathode). Alternatively, the structured layer can have, for example, two or three terminals. A transistor would typically have two terminals on the top side and then one more on the opposite bottom side. These two terminals (e.g.,The gate and source (in MOSFETs) or gate and emitter (in IGBTs) can be configured differently, e.g., a gate pad and a source pad; or four source pads surrounding a gate pad, etc. If multiple connections are provided, they can be spaced apart. The reactive heat dissipation nanolayer can be a reactive multilayer system (RMS) in which at least one highly reactive nanoscale layer can be grown onto the connections. This can be achieved by sputtering, for example, using reactive sputtering. The reactive heat dissipation nanolayer can consist of at least two layers of two materials with individual layer thicknesses of a few nanometers. Advantageously, the reactive heat dissipation nanolayer can be produced directly on the connections, eliminating the need for a pre-fabricated heat dissipation nanolayer film.Ignition can be achieved by a short-circuit current through the heat dissipation nanolayer or by laser ignition, thereby electrically and thermally contacting the terminals with the connection surfaces.

[0008] The approach presented here describes a method for improving precision and heat dissipation in power semiconductor devices using a heat-dissipating nanolayer. Power semiconductors can generate a significant amount of heat on the top surface of the device. To ensure sufficient cooling and thus adequate performance, cooling can be achieved from the top surface, i.e., the source side. In this way, the heat does not flow through the substrate with low thermal conductivity, but rather the device can be cooled from the interconnect side.

[0009] In the step of applying the heat dissipation nanolayer to the terminals, short circuits between two terminals, such as the gate pad and source pad of a transistor chip, or leakage from a terminal onto the edge termination or epitaxial layer of the chip can be avoided. The approach presented here can therefore enable precise deposition of the layer to prevent gaps and short circuits, thus facilitating efficient cooling. In other words, the heat dissipation nanolayer can be directly applied to the terminals, for example, by sputtering, to improve heat transfer and to allow for reliable size matching between the heat dissipation nanolayer and the terminals. Applying the heat dissipation nanolayer can lead to a reduction in layer thickness, thereby improving the manufacturing process.

[0010] Furthermore, during the assembly step, good thermal and electrical contact between the terminals and contact surfaces can be established without exerting pressure on the components. The approach presented here can enable the production of interconnect-cooled assemblies for common surface metallizations such as aluminum, silver, gold, and copper. For certain surfaces, a pre-soldering process is performed, e.g., with tin, to ensure adhesion of the subsequent nanolayers.

[0011] In the heat dissipation nanolayer application step, the nanolayer is deposited onto the connections using reactive sputtering. This allows the nanolayer to be applied directly to the connections with nanometer precision. This results in a precise application without gaps on the connections. Consequently, the material consumption of the nanolayer can be reduced, and the component can be cooled efficiently. Advantageously, no film is required for applying the nanolayer.

[0012] During the application step, the heat dissipation nanolayer can be applied in multiple layers. By sputtering or, more generally, by waxing, it is possible to adjust the thickness and thus find the optimal trade-off between heat dissipation, as well as the strength and manageability of the bond.

[0013] The process can include a step of removing a metal oxide layer from the surfaces of the terminals. This removal step can be performed before the deposition step. The removal can be carried out using plasma etching. Subsequently, the heat dissipation nanolayer can be reliably applied to the terminals, further improving its functionality. Alternatively or additionally, pre-soldering can be performed.

[0014] The power semiconductor device can be configured as a diode or a transistor. Therefore, the connection can be configured as a diode terminal of a diode, or as transistor terminals of a transistor. Advantageously, such a diode or transistor can be cooled via its terminal(s).

[0015] The process can include a step of applying a protective layer surrounding at least one terminal to the structured layer. This protective layer can shield the structured layer from contact with the heat dissipation nanolayer, thus preventing a short circuit. The protective layer can also insulate the at least one terminal to further prevent a short circuit. This protective layer can also be considered a passivation layer, protecting the surface of the structured layer from external influences.

[0016] In the provisioning step, the structured layer can be provided as a wafer capable of forming multiple power semiconductor devices, each with at least one connection. In the deposition step, the heat dissipation nanolayer can be applied to the connections of these multiple devices, covering them with the heat dissipation nanolayer. A singulation step for the power semiconductor devices can be performed after the deposition step. The heat dissipation nanolayer can be grown directly on the wafer before singulation, which can also simplify the handling of the bare chip.

[0017] A component comprises a structured layer that forms at least one power semiconductor device with at least one terminal, wherein the structured layer is arranged on a printed circuit board having at least one terminal pad, and wherein the at least one terminal of the power semiconductor device and the at least one terminal pad of the printed circuit board are electrically contacted by means of an ignited reactive heat dissipation nanolayer. Such a component can advantageously be manufactured using a previously mentioned method. According to one embodiment, the component is implemented as a single chip, for example as a transistor or diode, and not as an integrated circuit.

[0018] Advantageously, junction-side cooled assemblies can thus be realized for any common surface metallization, for example Al, Ag, Au, Cu, and therefore for almost all standard chips and advanced chips.

[0019] The invention is explained in more detail by way of example with reference to the accompanying drawings. These show: Fig. 1 a schematic cross-sectional representation of a section of an exemplary embodiment of a component; Fig. 2 a schematic cross-sectional representation of an exemplary embodiment of a component; Fig. 3. A top view of a wafer to illustrate an embodiment of a component; and Fig. 4 a flowchart of an exemplary embodiment of a method for manufacturing a component.

[0020] In the following description of preferred embodiments of the present invention, the same or similar reference numerals are used for the elements shown in the various figures and having a similar effect, without repeating these elements.

[0021] Fig. Figure 1 shows a schematic cross-sectional representation of a section of an embodiment of a component 100.

[0022] Component 100 has a structured layer 105, which can also be referred to as an epitaxial layer. Optionally, the structured layer 105 is implemented as a single-crystal layer. The layer 105 forms a power semiconductor device with at least one terminal 110, 120. In this and the following embodiments, only exemplary embodiments with two terminals 110, 120 are shown. By way of example, the power semiconductor device is implemented as a transistor with two terminals 110, 120 on the structured layer 105. Terminal 120 is, for example, implemented as a gate and terminal 110 as a source. The other terminal 130 is, for example, also implemented as a source.

[0023] The structured layer 105 is on a substrate in Fig. 1 substrate (not shown). Another connection of the power semiconductor device is typically located on the side of the substrate opposite the structured layer 105. In this case, for example, a drain connection.

[0024] Terminals 110, 120, and 130 are merely examples of transistor terminals. A reactive heat dissipation nanolayer 115 is applied to each of these terminals. The heat dissipation nanolayer 115 is applied to the terminals such that it covers them. In one embodiment, the heat dissipation nanolayer 115 covers only the terminals 110, 120, and 130. In another embodiment, the heat dissipation nanolayer 115 is applied to the terminals 110, 120, and 130 by reactive sputtering.

[0025] Optionally, a protective layer 125 is applied to the structured layer 105 such that the protective layer 125 at least partially covers the structured layer 105 and surrounds the terminals 110, 120, 130. The protective layer 125 thus insulates the terminals 110, 120, 130 from each other and protects the structured layer 105 from external influences and from contact with the heat dissipation nanolayer 115.

[0026] According to one embodiment, the protective layer 125 has a greater thickness than the connections 110, 120, 130, such that the protective layer 125 at least partially surrounds the heat dissipation nanolayer 115. The surfaces of the connections 110, 120, 130 are covered with the heat dissipation nanolayer 115, with the connections 110, 120, 130 and the heat dissipation nanolayer 115 having an identical thickness only as an example.

[0027] According to one embodiment, the terminals 110, 120, 130 have a surface consisting of a metal oxide layer. This metal oxide layer is removed before the application of the heat dissipation nanolayer 115, for example by plasma etching, in order to subsequently apply the heat dissipation nanolayer 115 reliably to the terminals 110, 120, 130. According to one embodiment, a second heat dissipation nanolayer can be applied to the heat dissipation nanolayer 115.

[0028] The heat dissipation nanolayer 115 is designed to enable reliable heat dissipation from the terminals 110, 120, 130 and to allow electrical contact between the terminals 110, 120, 130 and a printed circuit board, as is the case, for example, in Fig. 2 is shown and described in more detail. For this purpose, the printed circuit board is attached to the structured layer 105, or conversely, such that the heat dissipation nanolayer 115 is arranged between the terminals 110, 120, 130 and the terminal pads of the printed circuit board, see Figure 2. Fig. 2. Subsequently, the reactive heat dissipation nanolayer 115 is ignited to mechanically and electrically connect the terminals 110, 120, 130 and the connection surfaces of the printed circuit board.

[0029] Fig. Figure 2 shows a schematic cross-sectional view of an embodiment of component 100. Component 100 corresponds to or resembles the component from Fig. 1 except that component 100 is shown rotated and component 100 is arranged on a circuit board 200.

[0030] The printed circuit board 200 can also be referred to as a substrate, substrate layer, or PCB and is formed, for example, from a direct-bonded copper structure (DBC). The printed circuit board 200 has, by way of example, three contact pads 210, 220, 230, which are designed to electrically contact the terminals 110, 120, 130 of the structured layer 105. For this purpose, the heat dissipation nanolayer 115 between the terminals 110, 120, 130 and the contact pads 210, 220, 230 of the printed circuit board 200 is activated. For example, a short-circuit current is passed through the heat dissipation nanolayer 115, and the component 100 is contacted with the printed circuit board 200. Alternatively, the heat dissipation nanolayer 115 can be activated in another way.

[0031] Due to the arrangement of the heat dissipation nanolayer 115 or the connections 110, 120, 130, a space 240 is formed between the first connection surface 210 and the second connection surface 220, and a further space 250 is formed between the second connection surface 220 and the third connection surface 230.

[0032] The approach presented here can be understood as a method for improving precision and heat dissipation in power semiconductor devices through reactive multilayer systems.

[0033] In other words, a wafer, as in Fig. Figure 3 is shown and provided. The wafer consists of materials such as silicon, silicon carbide, gallium nitride and / or gallium oxide, as well as semiconductor structures, such as transistor structures or diode structures.

[0034] According to one embodiment, the heat dissipation nanolayer 115 grows directly on the wafer, making it possible to realize any shape with high precision in cleanroom growth processes.

[0035] The component pads on the wafer surface, for example the gate and source pads of a transistor, can be precisely separated. At the same time, the entire pad area can be precisely filled to achieve optimized thermal coupling and heat dissipation, and to avoid high thermal peak temperatures.

[0036] Since the heat dissipation nanolayer 115 is grown directly onto the wafer or the connections 110, 120, 130, the heat transfer between the chip surface and the heat dissipation nanolayer 115 is optimized compared to the connection created by deposition of a separate RMS foil or other connection techniques such as soldering or sintering. This improves heat dissipation.

[0037] The thickness and support layer of the heat dissipation nanolayer 115 can be varied as desired, wherein the heat dissipation nanolayer 115 comprises at least two layers according to one embodiment.

[0038] According to one embodiment, the wafer is separated to separate the individual structured layers, of which in the Fig. 1 and Fig. 2 each shows a structured layer 105, and thus to obtain the power semiconductor devices, which can also be called power electronics chips, each of which has a heat dissipation nanolayer 115 on at least one side.

[0039] The component 100 with the heat dissipation nanolayer 115 is simply placed onto the desired printed circuit board 200, for example, a circuit board, a directly bonded copper substrate, etc. This eliminates the need to cut the heat dissipation nanolayer 115 and also eliminates the need for a pick-and-place process.

[0040] The heat dissipation nanolayer 115 is ignited by a standard method, for example by a short-circuit current through the heat dissipation nanolayer 115. The actual bonding process then takes place: the component 100 is connected to the circuit board 200.

[0041] If the chip surface, or pad surface, is made of a metal prone to oxidation, such as aluminum, the surface oxides are first removed, for example by plasma etching. Then the growth and bonding process can take place even on such surfaces.

[0042] In summary, a bond with nanometer precision and high quality is achieved. Handling is simplified because no additional pick-and-place process for the RMS foil is required. This also leads to cost reductions. For existing chips already individually cut by the manufacturer, the heat dissipation nanolayer 115 is also applied to the individual component 100, as shown in [reference missing]. Fig. 1 and Fig. 2 shown, instead of on the entire wafer, see Fig. 3, bred.

[0043] Fig. Figure 3 shows a top view of a wafer 300 to illustrate an embodiment of a component 100. The marked section 305 is shown in Fig. 1 shown.

[0044] The structured layer is provided only as an example section of a 300-wafer. The 300-wafer forms a plurality of power semiconductor devices, each with at least two connections.

[0045] According to an alternative embodiment, the power semiconductor devices are separated after the heat dissipation nanolayer has been applied to the terminals of all power semiconductor devices of the wafer 300.

[0046] According to one embodiment, the power semiconductor components are separated before the heat dissipation nanolayer is applied to the terminals.

[0047] Fig. Figure 4 shows a flowchart of an embodiment of method 400 for manufacturing a component. The component corresponds to or is similar to the component shown in one of the figures described above.

[0048] The procedure 400 comprises a step 405 of provisioning, a step 410 of applying, a step 415 of attaching and a step 420 of ignition.

[0049] In step 405 of the provisioning process, a structured layer with at least one connection is provided, which forms at least one power semiconductor device. According to one embodiment, at least two connections are provided, which are configured as transistor connections of a transistor.

[0050] In step 410 of the application process, a heat dissipation nanolayer is applied to the terminal(s) such that the terminal(s) are covered with the heat dissipation nanolayer. The heat dissipation nanolayer is applied to the terminal(s) in step 410, for example, by reactive sputtering.

[0051] According to one embodiment, in step 410 of the application process, at least a second heat dissipation nanolayer is applied to the heat dissipation nanolayer, or the heat dissipation nanolayer is applied in multiple layers.

[0052] In step 415 of the attachment process, a printed circuit board is attached to the power semiconductor device such that the heat dissipation nanolayer is arranged between the terminal(s) of the power semiconductor device and a number of terminal pads of the printed circuit board corresponding to the terminals.

[0053] In step 420 of the ignition process, the heat dissipation nanolayer is ignited to electrically and thermally contact corresponding terminals of the power semiconductor component with corresponding contact surfaces of the circuit board.

[0054] According to one embodiment, method 400 comprises a removal step 425. Removal step 425 is performed when the connection(s) have a surface consisting of a metal oxide layer. In this step, the metal oxide layer is removed from the surface(s) of the connection(s) before application step 410.

[0055] According to one embodiment, method 400 comprises a step 430 of applying a protective layer. The protective layer is applied to the structured layer. The protective layer surrounds, for example, the terminal(s). According to one embodiment, step 430 of applying the protective layer is performed before step 410 of applying the protective layer.

[0056] According to a further embodiment, in step 405 of the provisioning process, a wafer is provided which has at least one section forming the structured layer. In this case, the method 400 comprises a singulation step 435, which is performed after the deposition step 410. Reference sign 100 components 105 structured layers 110 first connection 115 Heat dissipation nanolayer 120 second connection 125 Protective layer 130 third connection 135 Power semiconductor device 200 circuit boards 210 first connection area 220 second connection surface 230 third connection surface 240 space 250 additional spaces 300 wafers 305 Excerpt 400 methods for manufacturing a component Step 405 of deployment 410th step of the application Step 415 of the application process 420th step of ignition Step 425 of the removal process 430th step of the application 435 Step of singulation

Claims

[1] Method (400) for producing a component (100), the method (400) comprising the following steps: Providing (405) a structured layer (105) which forms at least one power semiconductor component (135) with at least one terminal (110, 120, 130); Applying (410) a reactive heat dissipation nanolayer (115) to the at least one terminal (110, 120, 130), wherein the heat dissipation nanolayer (115) precisely covers the at least one terminal (110, 120, 130), wherein the heat dissipation nanolayer (115) is applied to the at least one terminal (110, 120, 130) by reactive sputtering; Attaching (415) the structured layer (105) to a circuit board (200) having at least one connection surface (210, 220, 230), wherein the heat dissipation nanolayer (115) is arranged between the at least one connection (110, 120, 130) of the power semiconductor component (135) and the at least one connection surface (210, 220, 230) of the circuit board (200); and Igniting (420) the heat dissipation nanolayer (115) to electrically and thermally contact the at least one terminal (110, 120, 130) of the power semiconductor component (135) and the at least one connection surface (210, 220, 230) of the circuit board (200). [2] Method (400) according to one of the preceding claims, wherein in the step (410) of applying the heat dissipation nanolayer (115) is applied in multiple layers. [3] Method (400) according to one of the preceding claims, comprising a step (425) of removing a metal oxide layer from the surface of the at least one terminal (110, 120, 130), wherein the step (425) of removing is carried out before the step (410) of applying. [4] Method (400) according to one of the preceding claims, wherein the power semiconductor component (135) is designed as a diode or as a transistor. [5] Method (400) according to one of the preceding claims, comprising a step (430) of applying a protective layer (125) surrounding the at least one terminal (110, 120, 130) to the structured layer (105). [6] Method (400) according to one of the preceding claims, wherein in the step (405) of providing the structured layer (105) is provided as a wafer (300) which forms a plurality of power semiconductor components (135) each having at least one terminal (110, 120, 130), wherein in the step of applying (410) the heat dissipation nanolayer (115) is applied to the at least one terminal (110, 120, 130) of the plurality of power semiconductor components (135) in order to cover the at least one terminal (110, 120, 130) with the heat dissipation nanolayer (115), and with a step (435) of singulating the power semiconductor components (135) after the step (410) of applying.

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