Power semiconductor device and method for manufacturing a power semiconductor device

Abstract

A power semiconductor device (1), comprising: a semiconductor body (10) having a drift region (100) of a first conductivity type; a first load terminal (11) on a first side (110) of the semiconductor body (10); a second load terminal (12) on a second side (120) of the semiconductor body (10) opposite the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12); a trench grid structure (13) extending from the first side (110) into the semiconductor body (10), the trench grid structure comprising a plurality of macrocells (130), each macrocell (130) comprising at least one microcell (131) of the first type configured for forward load current conduction and a number of microcells (132) of the second type not configured for forward load current conduction.Each of the microcells (131) of the first type and the microcells (132) of the second type is laterally delimited by a respective section of the trench grid structure (13). In each of the macrocells (130), the number of microcells (132) of the second type is equal to or greater than the number of microcells (131) of the first type.

Description

TECHNICAL FIELDThis description relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device.BACKGROUNDMany functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving an electric motor or an electric machine, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name just a few, have been used for various applications including, but not limited to, switches in power supplies and power converters.A power semiconductor device typically comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted by means of an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region that is terminated by an edge of the chip.In the case of a controllable power semiconductor device, e.g. a transistor, the load current path may be controlled by means of an insulated electrode commonly referred to as gate electrode. For example, upon receiving a corresponding control signal, e.g. from a driver unit via a control terminal of the device, the control electrode may put the power semiconductor device in one of a forward conducting state and a blocking state.Further, some devices provide a reverse load current capability; i.e., the active region of the semiconductor body is further configured to conduct a reverse load current along a reverse load current path between the two load terminals of the device. For example, the RC (reverse current) IGBT is representative of such devices. In an RC-IGBT, a single chip combines an IGBT structure and a diode structure.With respect to IGBTs, a trend can be observed to further reduce the pitch and subsequently the mesa width in a typical strip cell design referred to as microstructure trench (MPT) IGBTs, resulting in lower V ce,sat and increased hole confinement. In this case, several approaches are implemented to restore dV / dt and / or dI / dt control (e.g., n-doped regions in the mesas or p-doped regions at the trench bottom). This is supported by elaborate contact schemes, e.g. by applying trenches to gate or source potential and placing or omitting contact grooves in the various mesas.SUMMARYThe subject matter of the independent claims is presented. Features of exemplary embodiments are defined in the dependent claims.According to an embodiment, a power semiconductor device comprises: a semiconductor body having a drift region of a first conductivity type; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, the power semiconductor device being configured to conduct a forward load current between the first load terminal and the second load terminal; a trench grid structure extending from the first side into the semiconductor body, the trench grid structure comprising a plurality of macrocells, each macrocell comprising at least one microcell of the first type configured for the forward load current line and a number of microcells of the second type not configured for the forward load current line. Each of the first type microcells and the second type microcells is laterally bounded by a respective portion of the trench grid structure. In each of the macrocells, the number of microcells of the second type is equal to or larger than the number of microcells of the first type.According to another embodiment, a method of manufacturing a power semiconductor device comprises forming the following components: a semiconductor body having a drift region of a first conductivity type; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, the power semiconductor device being configured to conduct a forward load current between the first load terminal and the second load terminal; a trench grid structure extending from the first side into the semiconductor body, the trench grid structure comprising a plurality of macrocells, each macrocell comprising at least one microcell of the first type configured for the forward load current line and a number of microcells of the second type not configured for the forward load current line. Each of the first type microcells and the second type microcells is laterally bounded by a respective portion of the trench grid structure. In each of the macrocells, the number of microcells of the second type is equal to or larger than the number of microcells of the first type.According to some embodiments described herein, a simple and low cost cell design based on a simple square cell that retains important features of MPT technology is proposed herein. For example, the new cell designs exceed previous solutions in maintaining good dV / dt and dI / dt control.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe parts in the figures are not necessarily to scale, emphasis instead being placed upon illustrating principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings, there are shown: FIG. 1 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 2 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 3(A) schematically and exemplarily shows a perspective projection of a power semiconductor device according to one or more embodiments; FIG. 3(B) schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 4 schematically and exemplarily shows a perspective projection of a power semiconductor device according to one or more embodiments; FIG. 5 schematically and exemplarily shows a perspective projection of a power semiconductor device according to one or more embodiments; FIG. 6 schematically and exemplarily shows a horizontal cross section of a power semiconductor device according to one or more embodiments; FIG. 7 schematically and exemplarily shows a vertical cross section of a power semiconductor device according to one or more embodiments; FIG. 8(A) schematically and exemplarily illustrates a horizontal cross section of a power semiconductor device according to one or more embodiments; FIG. 8(B) schematically and exemplarily shows a perspective projection of a power semiconductor device according to one or more embodiments; and FIG. 9 schematically and exemplarily shows a horizontal cross section of a power semiconductor device according to one or more embodiments.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.In this regard, directional terminology such as "top", "bottom", "below", "front", "rear", "rear", "leading", "trailing", "over", etc. may be used with reference to the orientation of the figures being described. Since portions of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided for illustration and is not intended to limit the invention. For example, features illustrated or described as part of one embodiment may be used in or in conjunction with other embodiments to yield yet another embodiment. It is intended that the present invention encompasses such modifications and variations. The examples are described using a specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or fabrication steps have been designated by the same reference numerals throughout the several drawings, unless otherwise indicated.The term "horizontal" as used in this specification intends to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may be, for example, the surface of a semiconductor wafer or a die or a chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, and the first lateral direction X and the second lateral direction Y may be perpendicular to each other.The term "vertical" as used in this specification intends to describe an orientation arranged substantially perpendicular to the horizontal surface, i.e. parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extending direction Z mentioned below may be an extending direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.In this specification, n-doped is referred to as "first conductivity type", while p-doped is referred to as "second conductivity type". Alternatively, opposite doping relationships may be employed such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.In the context of the present description, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe that there is a low ohmic electrical connection or a low ohmic current path between two regions, portions, zones, portions or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or a metallization or an electrode and a portion or part of a semiconductor device, wherein "low ohmic" may mean that the properties of the respective contact are substantially not affected by the ohmic resistance. Further, in the context of the present description, the term "in contact" is intended to describe that there is a direct physical connection between two elements of the respective semiconductor device; e.g., a transition between two elements in contact with each other may not include a further intermediate element or the like.Additionally, in the context of the present specification, unless otherwise indicated, the term "electrical isolation" is used in the context of its generally valid understanding and is thus intended to describe that two or more components are positioned separately from each other and that there is no ohmic connection connecting these components. However, components that are electrically isolated from each other may still be coupled to each other, for example mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (for example in the case of a transition). To give an example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, e.g. by means of an insulation, e.g. a dielectric.Specific embodiments described in this specification relate to, but are not limited to, a power semiconductor device that can be used within a power converter or power supply. Thus, in one embodiment, such a power semiconductor device may be configured to carry a load current to be supplied to a load and / or which is respectively provided by a power source. For example, the power semiconductor device may comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell, a monolithically integrated transistor cell, e.g. a monolithically integrated IGBT or MOSFET cell and / or derivatives thereof. Such diode / transistor cells may be integrated within a single chip. A plurality of such cells may form a cell array disposed within an active region of the power semiconductor device.The term "blocking state" of the power semiconductor device may refer to conditions when the power semiconductor is in a state configured to block a load current flow while an external voltage is applied. In particular, the power semiconductor device may be configured to block a forward load current through the power semiconductor device while applying a forward voltage bias. In comparison, the power semiconductor device may be configured to conduct the forward load current in a "conducting state" of the power semiconductor device while applying a forward voltage bias voltage. A transition between the blocking state and the conductive state may be controlled by a control electrode or, in particular, a potential of the control electrode. The electrical characteristics can naturally only hold within a predetermined operating range of the external voltage and the current density within the power semiconductor device. The term "forward biased blocking state" may therefore refer to conditions in which the power semiconductor device is in the blocking state while a forward voltage bias is applied.The term "power semiconductor device" as used in this specification intends to describe a power semiconductor device on a single chip having high voltage blocking and / or high current carrying capacities. In other words, such a power semiconductor device is intended for high current, typically in the Ampere range, e.g. up to several tens or hundreds of Ampere, and / or high voltages, typically above 15 V, more typically 100 V and above, e.g. up to at least 400 V or even more, e.g. up to at least 3 kV or even up to 10 kV or more, depending on the respective application.For example, the term "power semiconductor device" as used in this specification is not directed to logic semiconductor devices used, e.g., to store data, compute data, and / or other types of semiconductor-based data processing.For example, the power semiconductor device described below may be a single semiconductor chip having, e.g., a rectangular cell configuration, a square cell configuration, or a hexagonal cell configuration and may be configured to be employed as a power component in a low, medium, and / or high voltage application.Referring first to FIGS. 6 and 7, a possible general configuration of the power semiconductor device 1 will be explained:The power semiconductor device 1, also referred to herein as "device", comprises, e.g., in a single chip, a semiconductor body 10 configured to conduct a load current between a first load terminal 11 at a first side 110 of the semiconductor body 10 and a second load terminal 12 at a second side 120 of the semiconductor body 10.The first side 110 and the second side 120 may be disposed opposite each other. For example, the first side 110 is a front side of the device 1 and the second side 120 is a back side of the device 1. The semiconductor body 10 may be enclosed between the first load terminal 11 and the second load terminal 12 and have a vertical extension d, e.g. in the range of 50 μm to 700 μm, depending on the designated maximum blocking voltage.The device 1 further comprises a drift region 100 of a first conductivity type within the semiconductor body 10. For example, the vertical extension of the drift region 100 affects the voltage blocking capabilities (e.g. the maximum blocking voltage) of the device 1.The device 1 further comprises a trench grid structure 13 extending from the first side 110 into the semiconductor body 10 to the second side 120, e.g. along the vertical direction Z. The trench grid structure 13 is described in more detail below. The trench grid structure 13 may include at least one trench control electrode 141 (cf. FIG. 3 ) electrically isolated from the first load terminal 11 and configured to receive a control signal. To this end, the trench control electrode 141 may be electrically connected to a control terminal (not shown) of the device 1, according to an embodiment.At the first side 110, the semiconductor body 10 further comprises a semiconductor body region 102 of the second conductivity type electrically connected to the first load terminal 11 and a semiconductor source region 101 of the first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is insulated from the drift region 100 by at least the semiconductor body region 102. The trench control electrode 141 of the trench grid structure 13 may be configured to induce an inversion channel in the semiconductor body region 102 when exposed to a corresponding ON control signal. This process may put the device 1 in the forward conducting state. The trench control electrode 141 may be further configured to, when exposed to a corresponding OFF control signal, turn off the inversion channel in the semiconductor body region 102, which may put the device 1 in the forward blocking state.A doped region 108 of the semiconductor body 10 below the drift region 100 adjoining the second load terminal 12 on the second side 120 may be configured according to the designated characteristic of the device 1. For example, the doped region 108 may be an emitter region of the second conductivity type if the device 1 is to have an IGBT configuration. The emitter region is arranged in contact with the second load terminal 12.In addition, a field stop region (not shown) of the first conductivity type may be provided between the drift region 100 and the second load terminal 12, wherein the field stop region has a larger dopant concentration than the drift region 100.If the device 1 is to have a MOSFET configuration, the emitter region is omitted, so that the field stop region (or another highly doped region of the first conductivity type) would be adjacent to the second load terminal 12. If the device 1 is to have an RC-IGBT configuration, the emitter region may have sub-portions of the first conductivity type, as is known to the person skilled in the art.The above-described components of the power semiconductor device 1 are arranged in the active region 1- 2 of the device 1 (cf. FIG. 6 ) surrounded by an edge termination region 1- 3. In the active region 1- 2, the trench grid structure ( 13) may form a cell array, which is explained further below. The edge termination region 1- 3 is typically not used for the load current line, as is known to the person skilled in the art. The edge termination region 1- 3 is terminated by the chip edge 1- 4.FIGS. 1 and 2 both schematically and exemplarily illustrate a horizontal projection of the power semiconductor device according to one or more embodiments. Illustrated are examples of the trench grid structure 13 extending from the first side 110 into the semiconductor body 10. The trench grid structure 13 includes a plurality of macrocells 130, one of which is illustrated in FIGS. 1 and 2, respectively.Each macrocell 130 includes at least one microcell 131 of the first type configured for the forward load current line and a number of microcells 132 of the second type not configured for the forward load current line. The number of microcells 132 of the second type may be zero, one, or more than one. In these microcells of the second type, there is no forward load current conduction. For example, for this purpose, the semiconductor source regions 101 are implemented only in the microcells 131 of the first type, but not in the microcells of the second type according to an embodiment. Further, each of the microcells 131 of the first type is electrically connected to the first load terminal 11, e.g. based on an ohmic contact, according to an embodiment. The microcells 132 of the second type are not necessarily electrically connected to the first load terminal 11.In an embodiment, none of the microcells 132 of the second type is electrically connected to the first load terminal 11. For example, this variant may be suitable if the device 1 has an IGBT configuration.In an embodiment, some or all of the second type microcells 132 are also electrically connected to the first load terminal 11. For example, this variant may be suitable if the device 1 has an RC-IGBT configuration. However, in this embodiment, none of the second type microcells 132 includes a semiconductor source region 101.As illustrated in both FIGS. 1 and 2, each of the first type microcells 131 and the second type microcells 132 is laterally bounded by a respective portion of the trench grid structure 13. Further, in each of the macrocells 130, the number of the microcells 132 of the second type, if implemented, is equal to or greater than the number of the microcells 131 of the first type.In an embodiment, each of the microcells 131 of the first type has a rectangular horizontal cross-sectional area with an aspect ratio between the side surfaces of at most 2:1. For example, each of the microcells 131 of the first type has a square horizontal cross-sectional area. For example, each of the microcells 131 of the first type has a rectangular horizontal cross-sectional area with an aspect ratio between the side surfaces of greater than 1:1 (such that the microcells 131 of the first type are not square) and at most 2:1. Similarly, each of the second type microcells 132 may have a rectangular horizontal cross-sectional area with an aspect ratio between the side surfaces of at most 2:1. For example, each of the second type microcells 132 has a square horizontal cross-sectional area. For example, each of the second type microcells 132 has a rectangular horizontal cross-sectional area with an aspect ratio between the side surfaces of greater than 1:1 (such that the second type microcells 131 are not square) and at most 2:1.Referring to FIG. 9, in one embodiment, each of the first type macrocells 131 and the second type macrocells 132 have the same size and shape, namely, a hexagonal shape. The macrocells 131 of the first type and the macrocells 132 of the second type may be arranged according to a hexagonal packing within the active region 1- 2. For example, each side of each hexagon may have a length a hex within the range of 2 μm to 4 μm, such as 3 μm.With further reference to FIG. 9, according to an embodiment, it may be ensured that the source regions 101 only extend along portions of the trench structure 13 having the same orientation, such as along the first lateral direction X, as illustrated in FIG. 9. Thereby, a variation of the threshold voltage V th of the device 1 due to possible variations of the thickness of the trench insulator 142 may be reduced or even avoided. This variant may also be provided for the embodiments illustrated in FIGS. 1 and 2, for example, in contrast to the exemplary illustrations there.Further, referring to both FIGS. 1 and 2, each of the macrocells 130, each of the first type microcells 131, and each of the second type microcells 132, according to an embodiment, has at least one substantially rectangular horizontal cross-sectional area. For example, the microcells 132 of the second type in FIG. 1 have a rectangular horizontal cross-sectional area, whereas the microcells 132 of the second type in FIG. 2 have a substantially rectangular horizontal cross-sectional area, wherein small portions are "worked out" by the microcell 131 of the first type.For example, each of the microcells 131 of the first type (e.g., having a rectangular horizontal cross-section or a square horizontal cross-section) has a horizontal cross-sectional area of less than 5 μm*5 μm, less than 4 μm*4 μm, less than 3 μm*3 μm, or even less than 2 μm*2 μm. Similarly, each of the second type microcells 132 (e.g., having a rectangular horizontal cross-section or a square horizontal cross-section) has a horizontal cross-sectional area of less than 5 μm*5 μm, less than 4 μm*4 μm, less than 3 μm*3 μm, or even less than 2 μm*2 μm.Further, according to an embodiment, each portion of the grid structure 13 laterally delimiting one of the microcells 131 of the first type and / or one of the microcells 132 of the second type and continuously extending along either the first lateral direction X or the second lateral direction Y until adjoining another portion of the grid structure 13 extending perpendicular thereto is shorter than 10 μm.In an embodiment, in each of the macrocells 130, the at least one microcell 131 of the first type is surrounded by microcells 132 of the second type. For example, as best illustrated in FIGS. 1, 2 and 8, it may be provided that in each of the macrocells 130, the at least one microcell 131 of the first type is surrounded only by the microcells 132 of the second type.In another embodiment, in each of the macrocells 130, the at least one microcell 131 of the first type has a horizontal cross-sectional area that is smaller than each of the horizontal cross-sectional areas of the microcells 132 of the second type. In another embodiment, in each of the macrocells 130, the at least one microcell 131 of the first type has a horizontal cross-sectional area that is equal to the horizontal cross-sectional area of at least one of the microcells 132 of the second type; for example, each of the microcells 131 of the first type and microcells 132 of the second type have the same size. In yet another embodiment, the at least one microcell 131 of the first type has a horizontal cross-sectional area that is greater than each of the horizontal cross-sectional areas of the microcells 132 of the second type.In another embodiment, in each of the macrocells 130, the ratio of the number of second type microcells 132 to the number of first type microcells 131 is at least 3 / 1.With reference to FIGS. 3(A) and 3(B), further optional aspects of the trench grid structure 13 will be explained. FIG. 3(B) corresponds to FIG. 2 explained above, and FIG. 3(A) illustrates a related perspective view of a part of FIG. 3(B) indicated by the broken line in FIG. 3(A).Accordingly, the trench grid structure 13 may house the trench control electrode 141 and a trench insulator 142 electrically insulating the trench control electrode 141 from the semiconductor body 10. In an embodiment, at least each microcell 131 of the first type is surrounded by a respective portion of the lattice structure 13. For example, at least each microcell 131 of the first type is surrounded by a portion of the trench control electrode 141. As explained above with reference to FIGS. 1 and 2, the trench control electrode 141 is configured to, when exposed to a control signal, induce an inversion channel within each of the microcells 131 of the first type.In an embodiment, it may even be provided that the trench grid structure 13 exclusively accommodates the trench control electrode 141, wherein, for example, the trench control electrode 141 forms a continuous electrically conductive structure within the trench grid structure 13. For example, the design proposed herein enables avoiding the implementation of source trenches or other trench types, which in turn facilitates the contacting scheme.Further, each of the microcells 131 of the first type may be electrically connected to the first load terminal 11, e.g. based on an ohmic contact, such as the contact plug 111, which may have a closed course substantially following an outer perimeter of the respective microcell 131 of the first type, as schematically illustrated in FIG. 3. Instead of the contact plug 111, a flat contact may be used.Each of the microcells 131 of the first type may further include the semiconductor source region 101 of the first conductivity type and the semiconductor body region 102 of the second conductivity type. The semiconductor body region 102 isolates the semiconductor source region 101 from the drift region 100, and wherein both the semiconductor source region 101 and the semiconductor body region 102 are electrically connected to the first load terminal 11, e.g. based on the contact plug 111.The doping and size of the source region 101 may be adjusted according to the designated characteristic of the device. For example, as for the contact plug 111, it may also be provided that the source region 101 also has a closed course, which substantially follows the outer periphery of the respective microcell 131 of the first type, in contrast to only about 50% thereof, as schematically illustrated in FIG. 3. Then, the microcell 131 of the first type would be "surrounded" by the semiconductor source region 101.The body region 102 may extend into both the microcells 131, 132 of the first and second types.Both the semiconductor source region 101 and the semiconductor body region 102 are electrically connected to the first load terminal 11.For example, the body region 102 has a highly doped subsection 1021 at the first side 110 in order to improve the electrical contact to the first load terminal 11. In an embodiment, it is further ensured that the body region 102 within the macrocells 130 has a depth of less than 50% of the depth of the trench grid structure 13. For example, it is ensured that the bottom of the trench grid structure 13 terminates in the drift region 100 or a differently doped subsection thereof, for example a barrier region or the like.Further, as illustrated, the trench grid structure 13 according to an embodiment has a constant depth along a vertical direction Z, wherein the constant depth varies locally by less than 1 μm. The variation may also be significantly less than 1 μm.Portions of the trench grid structure 13 are filled with an insulating material instead of electrode material used for forming the trench control electrode 141, e.g., to adjust a total gate charge.Figure 4 shows a slightly modified version of the first type microcell 131. The microcell 131 of the first type also has a square horizontal cross-sectional area, with the semiconductor source region 101 extending only between two of the four corners (only one of which is illustrated in FIG. 4 ). In this embodiment, the macrocell 130 does not include a microcell 132 of the second type; accordingly, due to the comparatively high density of the microcells 131 of the first type, the size of the source region 101 in each microcell 131 of the first type is kept comparatively small. According to other embodiments, regions exist on the semiconductor device 10 that are completely constructed by microcells 131 of the first type and separated from each other by regions that consist of microcells 132 of the second type.In an embodiment, in each of the first type microcells 131, the ratio between the lateral length of the source region 101 and the horizontal cross-sectional area of the first type microcell 131 is less than 1 / 5 μm.FIG. 5 shows a variant of the macrocell 130 comprising three microcells 132 of the second type and one microcell 131 of the first type, each having a square horizontal cross-sectional area and being separated from each other based on the trench grid structure 13. For example, in this variant, the size of the source region 101 in each microcell 131 of the first type is increased compared to the variant of FIG. 4.FIGS. 8(A) and (B) show still another variant of the macrocell 130 including eight second type microcells 132 and a first type microcell 131 each having a rectangular / square horizontal cross-sectional area and separated from each other based on the trench lattice structure 13. For example, in this variant, the size of the source region 101 in each microcell 131 of the first type is increased compared to the variant of FIG. 4. Further, FIG. 8 illustrates a feature of the above-described embodiments according to which a portion of the trench grid structure is filled with the insulating material 143 instead of electrode material.Of course, the illustration in FIGS. 8(A) and (B) is only schematic and exemplary; depending on the designated characteristic of the device 1, the portions and positions of the trench grid structure comprising the insulating material 143 may be varied. For example, the insulating material 143 could also be deposited at the bottom region of the trench grid structure 13, e.g. before filling the trench grid structure with the electrode material to form the trench control electrode 141.Herein, a method for manufacturing a power semiconductor device is also presented. For example, the method of manufacturing a power semiconductor device comprises forming the following components: a semiconductor body having a drift region of a first conductivity type; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, the power semiconductor device being configured to conduct a forward load current between the first load terminal and the second load terminal; a trench grid structure extending from the first side into the semiconductor body, the trench grid structure comprising a plurality of macrocells, each macrocell comprising at least one microcell of the first type configured for the forward load current line and a number of microcells of the second type not configured for the forward load current line. Each of the first type microcells and the second type microcells is laterally bounded by a respective portion of the trench grid structure. In each of the macrocells, the number of microcells of the second type is equal to or larger than the number of microcells of the first type.Embodiments of the method described above correspond to the embodiments of the power semiconductor device 1 described above. Accordingly, these embodiments of the method are not described literally herein, but reference is made to the above.As stated above, the proposed trench grid structure enables a comparatively low-complexity manufacturing procedure, e.g. according to an embodiment, since no source trenches or other trenches need to be contacted, for example. Further, in an embodiment, only one gate runner is needed in the edge termination region 1- 3 to electrically contact the control electrodes 141 in the trench structure 13. For example, the control electrodes 141 are continuously connected to each other via the macrocells 130. Thereby, gate fingers (or other structures) extending into the active region 1- 2 to contact the control electrodes 141 thereat may be avoided, and the processing complexity for manufacturing the power semiconductor device 1 is accordingly low.In the above, embodiments related to power semiconductor devices and respective manufacturing methods have been explained.For example, these power semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g. the semiconductor body and its regions / zones, e.g. regions etc., may be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.However, it is to be understood that the semiconductor body and its regions / zones may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, without being limited thereto, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), Aluminium gallium indium nitride (AlGaInN) or Indiumgalliumarsenidphosphid (InGaAsP) and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The above-mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are mainly used at present.Spatially relative terms such as "below," "below," "lower," "above," "upper," and the like, are used to simplify the description to explain the positioning of an element relative to a second element. These terms are intended to encompass different orientations of the respective device in addition to orientations other than those depicted in the figures. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms may refer to like elements throughout the specification.

Claims

A power semiconductor device (1) comprising: - a semiconductor body (10) having a drift region (100) of a first conductivity type; - a first load terminal (11) on a first side (110) of the semiconductor body (10); - a second load terminal (12) on a second side (120) of the semiconductor body (10) opposite the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12); a trench grid structure (13) extending from the first side (110) into the semiconductor body (10), the trench grid structure comprising a plurality of macrocells (130), each macrocell (130) comprising at least one microcell (131) of a first type configured for the forward load current conduction and a number of microcells (132) of a second type not configured for the forward load current conduction, wherein: ◯ each of the microcells (131) of the first type and the microcells (132) of the second type is laterally bounded by a respective portion of the trench grid structure (13); and ◯ in each of the macrocells (130), the number of microcells (132) of the second type is equal to or greater than the number of microcells (131) of the first type.The power semiconductor device (1) according to claim 1, wherein the trench grid structure (13) houses a trench control electrode (141) and a trench insulator (142) electrically insulating the trench control electrode (141) from the semiconductor body (10).The power semiconductor device (1) according to claim 2, wherein at least each microcell (131) of the first type is surrounded by a portion of the trench control electrode (141).The power semiconductor device (1) according to claim 2 or 3, wherein the trench control electrode (141) is configured to, when subjected to a control signal, induce an inversion channel within each of the microcells (131) of the first type.The power semiconductor device (1) according to any one of the preceding claims 2 to 4, wherein the trench grid structure (13) exclusively houses the trench control electrode (141), and wherein the trench control electrode (141) forms a continuous electrically conductive structure within the trench grid structure (13).The power semiconductor device (1) according to any of the preceding claims, wherein each of the microcells (131) of the first type is electrically connected to the first load terminal (11), e.g. based on an ohmic contact.The power semiconductor device (1) according to any one of the preceding claims, wherein each of the microcells (131) of the first type includes a semiconductor source region (101) of the first conductivity type and a semiconductor body region (102) of the second conductivity type, wherein the semiconductor body region (102) isolates the semiconductor source region (101) from the drift region (100), and wherein both the semiconductor source region (101) and the semiconductor body region (102) are electrically connected to the first load terminal (11).The power semiconductor device (1) according to any one of the preceding claims, wherein none of the second type microcells (132) comprises a region of the first conductivity type electrically connected to the first load terminal (11).The power semiconductor device (1) according to any one of the preceding claims, wherein each of the microcells (131) of the first type has a rectangular horizontal cross-sectional area with an aspect ratio between the side surfaces of at most 2:1.The power semiconductor device (1) according to any one of the preceding claims, wherein each of the macrocells (130), each of the first type microcells (131), and each of the second type microcells (132) has a rectangular horizontal cross-sectional area.The power semiconductor device (1) according to any one of the preceding claims, wherein each of the microcells (131) of the first type has a horizontal cross-sectional area of less than 5 μm * 5 μm.The power semiconductor device (1) according to any one of the preceding claims, wherein in each of the macrocells (130), the at least one microcell (131) of the first type has a horizontal cross-sectional area smaller than each of the horizontal cross-sectional areas of the microcells (132) of the second type.The power semiconductor device (1) according to any one of the preceding claims, wherein in each of the macrocells (130), the at least one microcell (131) of the first type is surrounded by the microcells (132) of the second type.The power semiconductor device (1) according to any one of the preceding claims, wherein in each of the macrocells (130), the ratio of the number of the microcells (132) of the second type to the number of the microcells (131) of the first type is at least 3 / 1.The power semiconductor device (1) according to any of the preceding claims, wherein the trench grating structure (13) has a constant depth along a vertical direction (Z), wherein the constant depth varies locally by less than 1 μm.The power semiconductor device (1) according to any of the preceding claims, wherein portions of the trench grid structure (13) are filled with an insulating material (143), e.g. to adjust a total gate charge.The power semiconductor device (1) according to any one of the preceding claims, wherein each of the microcells (131) of the first type has a square horizontal cross-sectional area.The power semiconductor device (1) according to any one of the preceding claims, wherein each of one or more of the microcells (131) of the first type is surrounded by the semiconductor source region (101) within the respective microcell (131) of the first type.The power semiconductor device (1) according to any of the preceding claims, wherein the semiconductor body region (102) within the macrocells (130) has a depth of less than 50% of the depth of the trench grid structure (13).A method of manufacturing a power semiconductor device (1) comprising forming the following components: - a semiconductor body (10) having a drift region (100) of a first conductivity type; - a first load terminal (11) on a first side (110) of the semiconductor body (10); - a second load terminal (12) on a second side (120) of the semiconductor body (10) opposite the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12); a trench grid structure (13) extending from the first side (110) into the semiconductor body (10), the trench grid structure comprising a plurality of macrocells (130), each macrocell (130) comprising at least one microcell (131) of the first type configured for forward load current conduction and a number of microcells (132) of the second type not configured for forward load current conduction, wherein: ◯ each of the microcells (131) of the first type and the microcells (132) of the second type is laterally bounded by a respective portion of the trench grid structure (13); and ◯ in each of the macrocells (130), the number of microcells (132) of the second type is equal to or greater than the number of microcells (131) of the first type.

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