Storage circuit and method for operating this

Abstract

A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a rising or falling edge of a word line signal in response to at least one initial clock signal. The control circuit includes: an initial clock circuit configured to generate a second clock signal in response to an initial reset signal and a clock signal; and an adjustable delay circuit configured to set a delay between the second and third clock signals in response to the second clock signal and an activation signal. The third clock signal is a delayed version of the second clock signal.The amount of delay between the second and third clock signals is based on a voltage difference between a first supply voltage, which has a first fluctuation, and a second supply voltage, which has a second fluctuation.

Description

PRIORITY CLAIM

[0001] This application claims priority to Chinese Application No. 202310782406.9, filed on June 29, 2023, which is incorporated herein by reference in its entirety. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has manufactured a wide variety of digital devices to address problems in a number of different areas. Some of these digital devices, such as memory macros, are configured to store data. As ICs become smaller and more complex, the resistance of conductive lines within these digital devices also changes, affecting the operating voltages of these digital devices and overall IC performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for the sake of clarity. Fig. 1 is a block diagram of a memory circuit, according to some embodiments. Fig. 2 is a circuit diagram of a memory circuit, according to some embodiments. Fig. 3 is a timing diagram of signal waveforms of a memory circuit, such as the memory circuit in Fig. 2 or the memory circuit in Fig. 4, according to some embodiments. Fig. 4 is a circuit diagram of a control circuit, according to some embodiments. Fig. 5 is a circuit diagram of a circuit, according to some embodiments. Fig. 6 is a timing diagram of signal waveforms of a circuit such as the circuit in Fig. 5, the circuit in Fig. 7, the circuit in Fig. 8 or the circuit in Fig. 9, according to some embodiments. Fig. 7 is a circuit diagram of a circuit, according to some embodiments. Fig. 8 is a circuit diagram of a circuit, according to some embodiments. Fig. 9 is a circuit diagram of a circuit, according to some embodiments. Fig. 10 is a circuit diagram of a memory cell used in Fig. 1 and Fig. 2 may be used, according to some embodiments. Fig. 11 is a timing diagram of signal waveforms of a memory circuit such as the memory circuit in Fig. 2, according to some embodiments. Fig. 12A-12B are a flow diagram of a method of operating a circuit, according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides various embodiments, or examples, for implementing features of the present subject matter. Specific examples of components, materials, values, steps, arrangements, or the like are described below to simplify the present disclosure. These, of course, are examples and are not limiting. Other components, materials, values, steps, arrangements, or the like are contemplated. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is done for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0006] According to some embodiments, a memory circuit includes a wordline driver circuit coupled to a wordline and a control circuit coupled to the wordline driver circuit.

[0007] In some embodiments, the control circuit is configured to delay a rising edge or a falling edge of a wordline signal in response to at least a first clock signal.

[0008] In some embodiments, the control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal.

[0009] In some embodiments, the control circuit further comprises an adjustable delay circuit configured to adjust a delay between the second clock signal and a third clock signal in response to the second clock signal and an activation signal. In some embodiments, the third clock signal is a delayed version of the second clock signal.

[0010] In some embodiments, the third clock signal is delayed relative to the second clock signal by the memory circuit including the adjustable delay circuit. In some embodiments, by delaying the third clock signal, a wordline clock signal is also delayed without reducing a pulse width of the wordline clock signal, resulting in a more flexible memory design than other approaches.

[0011] In some embodiments, an amount of delay between the second clock signal and the third clock signal is based on a voltage difference between a first supply voltage and a second supply voltage. In some embodiments, the first supply voltage has a first variation. In some embodiments, the second supply voltage has a second variation.

[0012] Fig. 1 is a block diagram of a memory circuit 100, according to some embodiments.

[0013] Fig. 1 is simplified for illustrative purposes. In some embodiments, the memory circuit 100 includes various elements in addition to those shown in Fig. 1, or it is arranged in another manner to perform the operations discussed below.

[0014] The memory circuit 100 is an IC that includes memory partitions 102A to 102D, a global control circuit 100GC, and global input / output (GIO) circuits 100BL.

[0015] Each memory partition 102A to 102D includes memory banks 110U and 110L adjacent to a word line driver (WL) circuit 110AC and a local control circuit 110LC. Each memory bank 110U and 110L includes a memory cell array 110AR and a local input / output (LIO) circuit 110BS.

[0016] A memory partition, e.g., a memory partition 102A to 102D, represents a portion of the memory circuit 100 that contains a subset of memory devices (in Fig. 1 not shown) and adjacent circuits configured to selectively access the subset of memory devices during programming and reading operations. In the Fig. In the embodiment illustrated in Figure 1, the memory circuit 100 has a total of four partitions. In some embodiments, the memory circuit 100 has a total number of partitions that is greater or less than four.

[0017] GIO circuitry 100BL represents circuitry configured to control access to one or more electrical paths, e.g., bit lines, to each memory device of the corresponding memory bank 110U or 110L of each memory partition 102A to 102D, e.g., by generating one or more bit line signals. In some embodiments, GIO circuitry 100BL includes a global bit line driver circuit. In some embodiments, GIO circuitry 100BL is coupled to each memory bank 110U and 110L by a corresponding global bit line (not shown).

[0018] The global control circuit 100GC represents a circuit configured to control some or all of the programming and reading operations on each memory partition 102A through 102D, e.g., by generating and / or asserting one or more control and / or enable signals.

[0019] In some embodiments, global control circuit 100GC includes one or more analog circuits configured to interface with memory partitions 102A-102D, cause data to be programmed into one or more memory devices, and / or use data received from one or more memory devices in one or more circuit operations. In some embodiments, global control circuit 100GC includes one or more global address decode or predecode circuits configured to output one or more address signals to WL driver circuit 110AC of each memory partition 102A-102D.

[0020] Each WL driver circuit 110AC is configured to generate wordline signals on corresponding wordlines WL. In some embodiments, each WL driver circuit 110AC is configured to output wordline signals on corresponding wordlines WL to the adjacent memory banks 110U and 110L of the respective memory partition 102A to 102D.

[0021] Each local control circuit 110LC represents an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate signals corresponding to adjacent subgroups of memory devices identified by the one or more address signals. In some embodiments, the adjacent subgroups of memory devices correspond to columns of memory devices. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary pair of signals. In some embodiments, each local control circuit 110LC is configured to output the signals to corresponding wordline driver circuits within the adjacent WL driver circuit 110AC of the respective memory partition 102A-102D.In some embodiments, the local control circuit 110LC includes a bank decoder circuit.

[0022] Each LIO circuit 110BS is configured to access one or more bit lines (shown in Fig. 2) coupled to adjacent subgroups of memory devices of the respective memory cell array 110AR, in response to the GIO circuit 110BL, e.g., based on one or more BL control signals. In some embodiments, the adjacent subgroups of memory devices correspond to rows of memory devices. In some embodiments, the LIO circuit 110BS includes a bit line selection circuit.

[0023] Each LIO circuit 110BS includes one or more circuits 114. For simplicity of illustration, circuitry 114 in memory bank 110U and 110L of memory partitions 102, 102C, and 102D is not shown. In some embodiments, each circuit 114 includes at least one sense amplifier circuit or a write latch circuit. During a write operation, according to some embodiments, the write latch circuit is configured to write data to at least one memory cell 112 in a corresponding column of memory cells in the respective memory cell array 110AR. During a read operation, according to some embodiments, the sense amplifier circuit is configured to read data from at least one memory cell 112 in a corresponding column of memory cells in the respective memory cell array 110AR.In some embodiments, each circuit 114 in the LIO circuit 110BS is coupled to a corresponding column of memory devices 112 in the memory cell array 110AR.

[0024] Each memory bank 110U and 110L includes the corresponding memory cell array 110AR, which includes memory cells or memory devices 112 configured to be accessed in programming and reading operations by the adjacent LIO circuit 110BS and the adjacent WL driver circuit 110AC.

[0025] Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. The rows of cells in the memory cell array 110AR are arranged in a first direction X. The columns of cells in the memory cell array 110AR are arranged in a second direction Y. The second direction is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (not shown). In some embodiments, each column of memory devices 112 in the memory cell array 110AR is coupled to a corresponding circuit 114 in the LIO circuit 110BS.

[0026] A memory device 112 is shown in memory bank 110U and 110L of memory partition 102A. For simplicity of illustration, the memory device 112 is not shown in memory bank 110U and 110L of memory partitions 102B, 102C, and 102D.

[0027] The memory device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logical states. At least one logical state of the memory device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, a logical state corresponds to a voltage level of an electrical charge stored in a given memory device 112. In some embodiments, a logical state corresponds to a physical property, e.g., a voltage, a current, a resistance, or a magnetic orientation, of a component of a given memory device 112.

[0028] In some embodiments, the memory device 112 includes one or more single-port static random access memory (SP-SRAM) cells. In some embodiments, the memory device 112 includes one or more dual-port SRAM (DP-SRAM) cells. In some embodiments, the memory device 112 includes one or more multi-port SRAM (multi-port SRAM) cells. Various types of memory cells in the memory device 112 are within the contemplated scope of the present disclosure. In some embodiments, the memory device 112 includes one or more dynamic random access memory (DRAM) cells. In some embodiments, the memory device 112 includes one or more one-time programmable (OTP) memory devices, such asElectronic fuse or antifuse devices (e-fuse or antifuse devices), flash memory devices, random access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, or the like. In some embodiments, memory device 112 is an OTP memory device having one or more OTP memory cells.

[0029] Other embodiments of the memory circuit 100 are within the scope of the present disclosure.

[0030] Fig. 2 is a circuit diagram of a memory circuit 200, according to some embodiments.

[0031] The memory circuit 200 is an embodiment of a portion of at least one of the memory partitions 102A, 102B, 102C or 102D of Fig. 1, and a similar detailed description is therefore omitted. For example, the memory circuit 200 is an embodiment of the local control circuit 110LC of Fig. 1, of the memory cell array 110AR of Fig. 1, the LIO circuit 110BS of Fig. 1, and the WL driver circuit 110AC of Fig. 1, and a similar detailed description is therefore omitted.

[0032] In some embodiments, the memory circuit 200 shows a non-limiting example in which a control circuit 202 comprises an embodiment of the local control circuit 110LC of Fig. 1, a memory cell array 206 illustrates an embodiment of the memory cell array 110AR of Fig. 1, the WL driver circuit 208 is an embodiment of the WL driver circuit 110AC of Fig. 1, and the IO circuit 204 represents the LIO circuit 110BS of Fig. 1, and a similar detailed description is therefore omitted.

[0033] The memory circuit 200 includes a control circuit 202 coupled to an IO circuit 204, a memory cell array 206, and a WL driver circuit 208. The control circuit 202 is coupled to the IO circuit 204 by at least one tracking word line TWL. The control circuit 202 is further coupled to the memory cell array 206 by at least one tracking bit line TBL. The control circuit 202 is further coupled to the WL driver circuit 208 by at least one decoder line (not labeled).

[0034] The control circuit 202 is configured to control the WL driver circuit 208 by a decoder signal DEC_X. The control circuit 202 is configured to generate the decoder signal DEC_X in response to at least one of a tracking bit line signal TRKBL, a clock signal CLK, an enable signal DWL_EN, or a clock signal CKP_WL. The control circuit 202 is further configured to generate the tracking word line signal TRKWL in response to the clock signal CKP_WL.

[0035] The control circuit 202 has an inverter I1 and an inverter I2.

[0036] The inverter I1 is configured to generate an inverted clock signal CKP_WLB in response to the clock signal CKP_WL. In some embodiments, the clock signal CKP_WL is inverted with respect to the inverted clock signal CKP_WLB. In some embodiments, the clock signal CKP_WL can be used to generate the wordline signal WL. An input terminal of the inverter I1 is configured to receive the clock signal CKP_WL. The input terminal of the inverter I1 is coupled to an output terminal of the inverter I6. For simplicity of illustration, it is not shown that the input terminal of the inverter I1 is coupled to the output terminal of the inverter I6. An output terminal of the inverter I1 is coupled to an input terminal of the inverter I2 and is configured to output the inverted clock signal CKP_WLB.

[0037] Inverter I2 is further configured to generate the tracking wordline signal TRKWL in response to the inverted clock signal CKP_WLB. In some embodiments, the tracking wordline signal TRKWL is inverted by the inverted clock signal CKP_WLB. An input terminal of inverter I2 is coupled to the output terminal of inverter I1 and is configured to receive the inverted clock signal CKP_WLB. An output terminal of inverter I2 is coupled to the tracking wordline TWL and the IO circuit 204. In some embodiments, the output terminal of inverter I2 is further coupled to the memory cell array 206 and the WL driver circuit 208 at least through the tracking wordline TWL. The output terminal of inverter I2 is configured to output the tracking wordline signal TRKWL.

[0038] The control circuit 202 further includes P-type metal oxide semiconductor (PMOS) transistors P2, P3, and P4, and an N-type metal oxide semiconductor (NMOS) transistor N5.

[0039] In some embodiments, at least one of the PMOS transistor P2, the PMOS transistor P3, the PMOS transistor P4, or the NMOS transistor N5 is configured to assert a signal TRKBL1B in response to the tracking bit line signal TRKBL.

[0040] A source of PMOS transistor P2 is coupled to a first voltage supply having a supply voltage VDD. All of a gate of PMOS transistor P2, a gate of PMOS transistor P4, and a gate of NMOS transistor N5 are coupled together and configured to receive the tracking bit line signal TRKBL on the tracking bit line TBL. All of the gate of PMOS transistor P2, the gate of PMOS transistor P4, and the gate of NMOS transistor N5 are coupled to the tracking bit line TBL. All of the gate of the PMOS transistor P2, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N5 are coupled to at least one of a drain of the PMOS transistor P1, a drain / source of the NMOS transistor N1, a drain / source of the NMOS transistor N2, a drain / source of the NMOS transistor N3, or a drain / source of the NMOS transistor N4 through the tracking bit line TBL.

[0041] All of a drain of the PMOS transistor P2, a source of the PMOS transistor P4 and a drain / source of the PMOS transistor P3 are coupled together.

[0042] All of a drain of the PMOS transistor P4, a drain of the NMOS transistor N5, and a gate of the PMOS transistor P3 are coupled together and are further coupled to an input terminal of a delay chain circuit 220.

[0043] At least one of the drain of the PMOS transistor P4 or the drain of the NMOS transistor N5 is configured to output the signal TRKBL1B to the input terminal of the delay chain circuit 220. In some embodiments, at least one of the drain of the PMOS transistor P4 or the drain of the NMOS transistor N5 is configured to assert the signal TRKBL1B.

[0044] A source of NMOS transistor N5 is coupled to a reference voltage supply VSS. A source / drain of PMOS transistor P3 is coupled to the reference voltage supply VSS.

[0045] The control circuit 202 further includes the delay chain circuit 220.

[0046] The delay chain circuit 220 is configured to generate a signal RSC in response to the signal TRKBL1B. In some embodiments, the signal RSC represents a delayed version of the signal TRKBL1B. In some embodiments, the delay chain circuit 220 comprises a delay chain circuit, such as the delay chain circuit 602 (described below) of Fig. 6. In some embodiments, the RSC signal is a reset signal that can be used to reset the clock generation circuit 222.

[0047] An input terminal of delay chain circuit 220 is configured to receive signal TRKBL1B. The input terminal of delay chain circuit 220 is coupled to the drain of PMOS transistor P4, the drain of NMOS transistor N5, and the gate of PMOS transistor P3.

[0048] An output terminal of delay chain circuit 220 is configured to output the RSC signal. The output terminal of delay chain circuit 220 is coupled to a first input terminal of a clock generation circuit 222.

[0049] The control circuit 202 further includes the clock generation circuit 222, which is coupled to an inverter I3, an inverter I4, a NOR logic gate NOR1, and an adaptive WL delay circuit 230.

[0050] Clock generation circuit 222 is configured to generate a clock signal CKPB in response to the signal RSC and a clock signal CLK. Clock signal CKPB is a generated clock signal that can be used by control circuit 202 to generate the decoder signal DEC_X. Clock signal CLK is an internal clock signal of integrated circuit 200.

[0051] The first input terminal of clock generation circuit 222 is configured to receive the RSC signal. A second input terminal of clock generation circuit 222 is configured to receive the CLK signal.

[0052] The first input terminal of clock generation circuit 222 is coupled to the output terminal of delay chain circuit 220. The second input terminal of clock generation circuit 222 is coupled to a source (not shown) of the clock signal CLK.

[0053] An output terminal of the clock generation circuit 222 is configured to output the clock signal CKPB. The output terminal of the clock generation circuit 222 is coupled to at least one of an input terminal of an inverter I3, an input terminal of an inverter I4, a first input terminal of a NOR logic gate NOR1, or a first input terminal of an adaptive WL delay circuit 230.

[0054] The inverter I3 is configured to generate a clock equalization signal CKP_BLEQ in response to the clock signal CKPB. In some embodiments, the clock equalization signal CKP_BLEQ is inverted by the clock signal CKPB. An input terminal of the inverter I3 is configured to receive the clock signal CKPB. The input terminal of the inverter I3 is coupled to the output terminal of the clock generation circuit 222. An output terminal of the inverter I3 is configured to output the clock equalization signal CKP_BLEQ. In some embodiments, the output terminal of the inverter I3 is coupled to one or more other components (not shown). In some embodiments, the output terminal of the inverter I3 is coupled to one or more equalization circuits (not shown).

[0055] The inverter I4 is configured to generate a clock signal CKP_WY in response to the clock signal CKPB. In some embodiments, the clock signal CKP_WY is inverted by the clock signal CKPB. An input terminal of the inverter I4 is configured to receive the clock signal CKPB. The input terminal of the inverter I4 is coupled to the output terminal of the clock generation circuit 222. An output terminal of the inverter I4 is configured to output the clock signal CKP_WY. In some embodiments, the output terminal of the inverter I4 is coupled to one or more other components (not shown). In some embodiments, the output terminal of the inverter I4 is coupled to one or more Y decoder circuits (not shown).

[0056] The adaptive WL delay circuit 230 is configured to generate a clock signal CKPBD in response to the clock signal CKPB and an enable signal DWL_EN. In some embodiments, the clock signal CKPBD represents a delayed version of the clock signal CKPB. In some embodiments, an amount of delay of the clock signal CKPBD with respect to the clock signal CKPB can be adjusted by at least one of the adaptive WL delay circuit 230 or the circuit 500, as shown in Fig. 5 to 6 discussed.

[0057] The first input terminal of the adaptive WL delay circuit 230 is configured to receive the clock signal CKPB. The first input terminal of the adaptive WL delay circuit 230 is coupled to the output terminal of the clock generation circuit 222.

[0058] A second input terminal of the adaptive WL delay circuit 230 is configured to receive the activation signal DWL_EN. The second input terminal of the adaptive WL delay circuit 230 is coupled to a source (not shown) of the activation signal DWL_EN.

[0059] An output terminal of the adaptive WL delay circuit 230 is configured to output the clock signal CKPBD. The output terminal of the adaptive WL delay circuit 230 is coupled to a second input terminal of the NOR logic gate NOR1.

[0060] The second input terminal of the adaptive WL delay circuit 230 is a test pin and is used to enable and disable the adaptive WL delay circuit 230. The adaptive WL delay circuit 230 is enabled or disabled in response to a value of the enable signal DWL_EN. For example, in some embodiments, the adaptive WL delay circuit 230 is enabled in response to the enable signal DWL_EN being a logic 1, and the adaptive WL delay circuit 230 is disabled in response to the enable signal DWL_EN being a logic 0. In some embodiments, the adaptive WL delay circuit 230 is enabled in response to the enable signal DWL_EN being a logic 0, and the adaptive WL delay circuit 230 is disabled in response to the enable signal DWL_EN being a logic 1.

[0061] When the adaptive WL delay circuit 230 is enabled, the adaptive WL delay circuit 230 is configured to delay the clock signal CKPBD compared to the clock signal CKPB. In some embodiments, when the adaptive WL delay circuit 230 is enabled, the adaptive WL delay circuit 230 is configured to delay at least one of the falling edge of the clock signal CKPBD or the rising edge of the clock signal CKPBD compared to the clock signal CKPB. In some embodiments, when the adaptive WL delay circuit 230 is enabled, the adaptive WL delay circuit 230 is configured to delay at least one of a rising edge of a clock signal CLK_WL or a falling edge of the clock signal CLK_WL.

[0062] In some embodiments, when the adaptive WL delay circuit 230 is deactivated, the clock signal CKPBD is not a delayed version of the clock signal CKPB, and the clock signal CKPBD is set to a logic 0 by the adaptive WL delay circuit 230. Other values ​​for the clock signal CKPB are within the scope of the present disclosure when the adaptive WL delay circuit 230 is deactivated. In some embodiments, when the adaptive WL delay circuit 230 is deactivated, the adaptive WL delay circuit 230 is configured not to delay at least one of the rising edge of the clock signal CLK_WL or the falling edge of the clock signal CLK_WL, and the clock signal CLK_WL represents an inverted version of the clock signal CKPB.

[0063] The first input terminal of the NOR logic gate NOR1 is configured to receive the clock signal CKPB. The first input terminal of the NOR logic gate NOR1 is coupled to the output terminal of the clock generation circuit 222.

[0064] A second input terminal of the NOR logic gate NOR1 is configured to receive the clock signal CKPBD. The second input terminal of the NOR logic gate NOR1 is coupled to the output terminal of the adaptive WL delay circuit 230.

[0065] An output terminal of the NOR logic gate NOR1 is configured to output the clock signal CK1. The NOR logic gate NOR1 is configured to generate the clock signal CK1 based on the clock signal CKPB and the clock signal CKPBD. An output terminal of the NOR logic gate NOR1 is coupled to an input terminal of an inverter I5.

[0066] The control circuit 202 further comprises an inverter I5 and an inverter I6.

[0067] Inverter I5 is configured to generate a clock signal CK2 in response to clock signal CK1. In some embodiments, clock signal CK2 is inverted by clock signal CK1. An input terminal of inverter I5 is configured to receive clock signal CK1. The input terminal of inverter I5 is coupled to the output terminal of NOR logic gate NOR1. An output terminal of inverter I5 is coupled to an input terminal of inverter I6 and is configured to output clock signal CK2. Inverter I5 and NOR logic gate NOR1 are part of a circuit 201.

[0068] The inverter I6 is configured to generate the clock signal CKP_WL in response to the clock signal CK2. In some embodiments, the clock signal CKP_WL is inverted by the clock signal CK2. In some embodiments, the clock signal CKP_WL represents a delayed version of the clock signal CK1. An input terminal of the inverter I6 is coupled to the output terminal of the inverter I5 and is configured to receive the clock signal CK2. An output terminal of the inverter I6 is coupled to a first input terminal of the NAND logic gate NAND1 and the input terminal of the inverter I1. For simplicity of illustration, it is not shown that the input terminal of the inverter I1 is coupled to the output terminal of the inverter I6. The output terminal of the inverter I6 is configured to output the clock signal CKP_WL.

[0069] The control circuit 202 further includes a NAND logic gate NAND1.

[0070] The first input terminal of the NAND logic gate NAND1 is configured to receive the clock signal CKP_WL. The first input terminal of the NAND logic gate NAND1 is coupled to the output terminal of inverter I6.

[0071] A second input terminal of the NAND logic gate NAND1 is configured to receive the decoder signal pdec_x. The second input terminal of the NAND logic gate NAND1 is coupled to a source of the decoder signal pdec_x (not shown). In some embodiments, the decoder signal pdec_x can be used to select a corresponding row of memory cells in the memory cell array 206.

[0072] An output terminal of the NAND logic gate NAND1 is configured to output the decoder signal ND1. The NAND logic gate NAND1 is configured to generate the decoder signal ND1 based on the clock signal CKP_WL and the decoder signal pdec_x. An output terminal of the NAND logic gate NAND1 is coupled to an input terminal of an inverter I7.

[0073] The control circuit 202 further comprises an inverter I7.

[0074] The inverter I7 is configured to generate a decoder signal DEC_X in response to the decoder signal ND1. In some embodiments, the decoder signal DEC_X is inverted by the decoder signal ND1. An input terminal of the inverter I7 is configured to receive the decoder signal ND1. The input terminal of the inverter I7 is coupled to the output terminal of the NAND logic gate NAND1. An output terminal of the inverter I7 is coupled to an input terminal of a post-decoder circuit 240 and is configured to output the decoder signal DEC_X. In some embodiments, the decoder signal DEC_X is an address signal of a corresponding row of memory cells in the memory cell array 206. In some embodiments, the decoder signal DEC_X can be used to select a corresponding row of memory cells in the memory cell array 206.

[0075] Other configurations, other types of circuit elements, or other numbers of circuit elements in the control circuit 202 are within the scope of the present disclosure.

[0076] The WL driver circuit 208 is coupled to the control circuit 202 by at least one decoder line (not labeled) and the tracking bit line TBL. The WL driver circuit 208 is further coupled to the memory cell array 206 by at least the word line WL. For ease of illustration, the WL driver circuit 208 is illustrated as being coupled to the memory cell array 206 by a single word line WL, but multiple word lines are coupled between the WL driver circuit 208 and the memory cell array 206. The WL driver circuit 208 is further coupled to the IO circuit 204 by at least the tracking word line TWL.

[0077] The WL driver circuit 208 is configured to control the memory cell array 206 by at least one word line signal WL. The WL driver circuit 208 is configured to generate the word line signal WL in response to the decoder signal DEC_X.

[0078] In some embodiments, the WL driver circuit 208 is further configured to control the control circuit 202 at least through the tracking bit line signal TRKBL. In some embodiments, the WL driver circuit 208 is further configured to generate the tracking bit line signal TRKBL in response to the tracking word line signal TRKWL.

[0079] The WL driver circuit 208 has a post-decoder circuit 240.

[0080] The post-decoder circuit 240 is configured to generate an inverted word line signal WLB in response to the decoder signal DEC_X.

[0081] In some embodiments, post-decoder circuit 240 includes one or more wordline decoder circuits coupled to a corresponding wordline rail / wordline and a corresponding row of memory cells in memory cell array 206. In some embodiments, post-decoder circuit 240 is configured to select a corresponding row of memory cells in memory cell array 206 by a corresponding wordline signal WL. In some embodiments, each of the one or more wordline decoder circuits includes a corresponding NAND logic gate (not shown) or NOR logic gate (not shown). Other types of wordline decoder circuits in post-decoder circuit 240 are within the scope of the present disclosure.

[0082] An input terminal of the post-decoder circuit 240 is configured to receive the decoder signal DEC_X. The input terminal of the post-decoder circuit 240 is coupled to the output terminal of the inverter I7.

[0083] An output terminal of post-decoder circuit 240 is configured to output the inverted word line signal WLB. The output terminal of post-decoder circuit 240 is coupled to a gate of PMOS transistor P6 and a gate of NMOS transistor N6.

[0084] The WL driver circuit 208 further includes the PMOS transistor P6 and the NMOS transistor N6.

[0085] The PMOS transistor P6 and the NMOS transistor N6 are configured as an inverter (not labeled) and are configured to generate the wordline signal WL in response to the inverted wordline signal WLB. In some embodiments, the wordline signal WL is inverted by the inverted wordline signal WLB.

[0086] A source of the PMOS transistor P6 is coupled to a second voltage supply having a supply voltage VDDM. In some embodiments, the supply voltage VDDM is greater than the supply voltage VDD. In some embodiments, the supply voltage VDDM is less than the supply voltage VDD. In some embodiments, the supply voltage VDDM has a voltage swing in the range from VDDM to VSS. In some embodiments, the supply voltage VDD has a voltage swing in the range from VDD to VSS. In some embodiments, the memory circuit 200 is a dual-rail circuit implementation that uses signals (e.g., the word line WL and the signal TRKBL1B) of two different voltage domains.

[0087] All of a gate of the PMOS transistor P6 and a gate of the NMOS transistor N6 are coupled together and are configured to receive the word line signal WLB from the output terminal of the post-decoder circuit 240.

[0088] A drain of PMOS transistor P6 and a drain of NMOS transistor N6 are coupled together and are further coupled to memory cell array 206 through word line WL. A source of NMOS transistor N6 is coupled to a reference voltage supply VSS.

[0089] The WL driver circuit 208 further includes a PMOS transistor P1.

[0090] A source of PMOS transistor P1 is coupled to the second voltage supply, which has the supply voltage VDDM. In some embodiments, PMOS transistor P1 is configured to set the tracking bit line signal TRKBL on the tracking bit line TBL to the supply voltage VDDM.

[0091] All of the gates of PMOS transistor P1, NMOS transistor N3, NMOS transistor N4, tracking word line TWL, and an output terminal of inverter I2 are coupled together. All of the gates of PMOS transistor P1, NMOS transistor N3, and NMOS transistor N4 are configured to receive the tracking word line signal TRKWL from the tracking word line TWL.

[0092] All of a drain of the PMOS transistor P1, a drain / source of the NMOS transistor N1, a drain / source of the NMOS transistor N2, a drain / source of the NMOS transistor N3, a drain / source of the NMOS transistor N4, the gate of the PMOS transistor P2, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N5 are coupled together.

[0093] At least one of the drain of the PMOS transistor P1, the drain / source of the NMOS transistor N1, the drain / source of the NMOS transistor N2, the drain / source of the NMOS transistor N3, or the drain / source of the NMOS transistor N4 is coupled to at least one of the gate of the PMOS transistor P2, the gate of the PMOS transistor P4, or the gate of the NMOS transistor N5 through the tracking bit line TBL.

[0094] Other configurations, other types of circuit elements, or other numbers of circuit elements in the WL driver circuit 208 are within the scope of the present disclosure.

[0095] The memory cell array 206 is coupled to the control circuit 202 through the tracking bit line TBL. The memory cell array 206 is further coupled to the WL driver circuit 208 through at least the word line WL. The memory cell array 206 is further coupled to the IO circuit 204 through at least the tracking word line TWL.

[0096] The memory cell array 206 includes tracking cells 206a and memory cells 206b.

[0097] The tracking cells 206a are configured to track one or more memory cells 206b of the memory cell array 206. The tracking cells 206a include one or more of the NMOS transistor N1, the NMOS transistor N2, the NMOS transistor N3, or the NMOS transistor N4. In some embodiments, at least one of the NMOS transistor N1, the NMOS transistor N2, the NMOS transistor N3, or the NMOS transistor N4 is configured to set the tracking bitline signal TRKBL on the tracking bitline TBL to a logic 0 or to approximately the reference supply voltage VSS.

[0098] In some embodiments, each of the gate of NMOS transistor N1 and the gate of NMOS transistor N2 is configured to receive a logic 0. In some embodiments, each of the gate of NMOS transistor N1 and the gate of NMOS transistor N2 is configured to receive the reference supply voltage VSS from a reference voltage supply. In some embodiments, each of the gate of NMOS transistor N1 and the gate of NMOS transistor N2 is coupled to each other.

[0099] At least one of the source / drain of NMOS transistor N1, the source / drain of NMOS transistor N2, the source / drain of NMOS transistor N3, or the source / drain of NMOS transistor N4 is configured to receive a logic 0. At least one of the source / drain of NMOS transistor N1, the source / drain of NMOS transistor N2, the source / drain of NMOS transistor N3, or the source / drain of NMOS transistor N4 is configured to receive the reference supply voltage VSS from a reference voltage supply. At least one of the source / drain of NMOS transistor N1, the source / drain of NMOS transistor N2, the source / drain of NMOS transistor N3, or the source / drain of NMOS transistor N4 are coupled to each other.

[0100] The memory cells 206b comprise one or more memory cells (not shown). In some embodiments, the memory cells 206b comprise one or more memory cells separated from the memory cell 112 in Fig. 1 on.

[0101] Other configurations, other types of circuit elements, or other numbers of circuit elements in the memory cell array 206 are within the scope of the present disclosure.

[0102] The IO circuit 204 is coupled to at least one of the control circuit 202, the WL driver circuit 208, or the memory cell array 206 through the tracking word line TWL. The IO circuit 204 is configured to set the tracking word line signal TRKWL on the tracking word line TWL.

[0103] Other configurations, other types of circuit elements, or other numbers of circuit elements in the IO circuit 204 are within the scope of the present disclosure.

[0104] In some embodiments, the memory circuit 200 including the adaptive WL delay circuit 230 may delay the clock signal CKPBD from the clock signal CKPB. In some embodiments, by delaying the clock signal CKPBD, the clock signal CKP_WL may also be delayed without reducing a pulse width of the clock signal CKP_WL, resulting in a more flexible memory design than other approaches. SIGNAL TRAILS

[0105] Fig. 3 is a timing diagram 300 of signal waveforms of a memory circuit, such as the memory circuit 200 in Fig. 2 or the memory circuit 400 in Fig. 4, according to some embodiments.

[0106] In some embodiments, one or more read operations or write operations are performed on at least one memory cell in a single column of the memory cell array 206b at least in the memory circuit 200 of Fig. 2, and the timing diagram 300 corresponds to signal waveforms during the one or more read operations or write operations of the at least one memory cell in the single column of the memory cell array 206b at least in the memory circuit 200 of Fig. 2.

[0107] In some embodiments, one or more read operations or write operations of the memory banks are performed at least in the memory circuit 100 by Fig. 1 is applied to at least one of the memory partitions 102A, 102B, 102C, or 102D, and the timing diagram 300 corresponds to signal waveforms during the read operations or memory partitions of at least one of the memory partitions 102A, 102B, 102C, or 102D.

[0108] The timing diagram 300 includes waveforms of the clock signal CKPB, the clock signal CKPBD, the clock signal CKP_WL, the tracking word line signal TRKWL, the tracking bit line signal TRKBL, the signal TRKBL1B, or the signal RSC.

[0109] In some embodiments, at time To, the enable signal DWL_EN is logic high, enabling the adaptive WL delay circuit 230. At time To, the clock signal CKPB is logic high, the clock signal CKPBD is logic high, the clock signal CKP_WL is logic low, the tracking word line signal TRKWL is logic low, the tracking bit line signal TRKBL is logic high, the signal TRKBL1B is logic low, and the line signal RSC is logic low.

[0110] In some embodiments, at time T1, the clock signal CKP1 is logic low and the enable signal DWL_EN is logic high, thereby enabling the circuit 500.

[0111] At time T1, the clock signal CKPB transitions from logic high to logic low. In some embodiments, at time T1, the adaptive WL delay circuit 230 is enabled by at least the enable signal DWL_EN. In some embodiments, the transition of the clock signal CKPB from logic high to logic low causes the adaptive WL delay circuit 230 to responsively cause the clock signal CKPBD to transition from logic high to logic low at time T3. In some embodiments, because the adaptive WL delay circuit 230 is enabled, the transition of the clock signal CKPBD from logic high to logic low occurs at time T3 (described below), which is a delay from time T1.In some embodiments, if the adaptive WL delay circuit 230 were disabled, the transition of the clock signal CKPBD from logic high to logic low would occur at time T1.

[0112] At time T2, the clock signal CKPB is at logic low.

[0113] At time T3, the clock signal CKPBD transitions from logic high to logic low. In response to at least the clock signal CKPB transitioning from logic high to logic low, the adaptive WL delay circuit 230 causes the clock signal CKPBD to transition from logic high to logic low because the adaptive WL delay circuit 230 is enabled.

[0114] At time T4, the clock signal CKPBD is logic low.

[0115] At time T5, in response to the clock signal CKPB being logic low and the clock signal CKPBD transitioning from logic high to logic low, the clock signal CKP_WL transitions from logic low to logic high. For example, in response to the clock signal CKPB being logic low and the clock signal CKPBD transitioning from logic high to logic low, the NOR logic gate NOR1 causes the clock signal CK1 to transition to logic high. In response to the clock signal CK1 being logic high, the inverter I5 causes the clock signal CK2 to transition to logic low. In response to the clock signal CK2 being logic low, the inverter I6 causes the clock signal CKP_WL to transition from logic low to logic high.

[0116] At time T6, the clock signal CKP_WL is logic high.

[0117] At time T7, in response to the clock signal CKP_WL transitioning from logic low to logic high, the tracking wordline signal TRKWL transitions from logic low to logic high. For example, in response to the clock signal CKP_WL transitioning from logic low to logic high, inverter I1 causes the clock signal CKP_WLB to transition from logic high to logic low. In response to the clock signal CKP_WLB transitioning from logic high to logic low, inverter I2 causes the tracking wordline signal TRKWL to transition from logic low to logic high.

[0118] At time T8, the tracking word line signal TRKWL is logic high.

[0119] In response to the tracking wordline signal TRKWL transitioning from logic low to logic high, the tracking bitline signal TRKBL transitions from logic high to logic low at time T8. For example, in response to the tracking wordline signal TRKWL transitioning from logic low to logic high, the PMOS transistor P1 is turned off, thereby decoupling the voltage supply VDDM from the tracking bitline TBL. In some embodiments, in response to the tracking wordline signal TRKWL transitioning from logic low to logic high, the NMOS transistors N3 and N4 are turned on, thereby coupling the drain / source of each of the NMOS transistors N3 and N4 to the tracking bitline TBL.In some embodiments, by coupling the drain / source of each of the NMOS transistors N3 and N4 to the tracking bit line TBL, the NMOS transistors N3 and N4 are configured to pull the tracking bit line signal TRKBL toward the drain / source voltage of each of the NMOS transistors N3 and N4 (e.g., logic 0), which is logic low. In these embodiments, the NMOS transistors N3 and N4 are turned off.

[0120] In response to the tracking bit line signal TRKBL transitioning from logic high to logic low, the signal TRKBL1B transitions from logic low to logic high at time T9.

[0121] In some embodiments, the tracking bitline signal TRKBL is sufficiently low at time T9 to thereby cause the NMOS transistor N5 to begin turning off and the PMOS transistors P2 and P4 to begin turning on. In some embodiments, in response to the NMOS transistor N5 beginning to turn off and the PMOS transistors P2 and P4 beginning to turn on, the PMOS transistors P2 and P4 begin pulling a node N2-1 toward the first supply voltage VDD, thereby causing the signal TRKBL1B to transition from logic low to logic high and the PMOS transistor P3 to turn off.

[0122] At time T10, the TRKBL1B signal is logic high.

[0123] At time T11, the tracking bit line signal TRKBL is logic low.

[0124] In response to the TRKBL1B signal transitioning from a logic low to a logic high, the RSC signal transitions from a logic low to a logic high at time T11. In some embodiments, the RSC signal is delayed relative to the TRKBL1B signal.

[0125] In response to the RSC signal transitioning from logic low to logic high, the clock signal CKPB transitions from logic low to logic high at time T12. In some embodiments, the clock generation circuit 222 is reset by the RSC signal transitioning from logic low to logic high, causing the clock generation circuit 222 to cause the clock signal CKPB to transition from logic low to logic high.

[0126] At time T13, the RSC signal is logic high.

[0127] In response to the RSC signal transitioning from logic low to logic high, the clock signal CKPB transitions from logic low to logic high at time T13.

[0128] In some embodiments, in response to the clock signal CKPB transitioning from logic low to logic high, the adaptive WL delay circuit 230 causes the clock signal CKPBD to transition from logic low to logic high at time T19. In some embodiments, because the adaptive WL delay circuit 230 is enabled, the transition of the clock signal CKPBD from logic low to logic high occurs at time T19 (described below), which is delayed from time T13. In some embodiments, if the adaptive WL delay circuit 230 were disabled, the transition of the clock signal CKPBD from logic low to logic high would occur approximately at time T13.

[0129] In some embodiments, in response to the clock signal CKPB transitioning from logic low to logic high, the NOR logic gate NOR1 causes the clock signal CK1 to transition from logic high to logic low, which causes the inverter I5 to cause the clock signal CK2 to transition from logic low to logic high, which causes the inverter I6 to cause the clock signal CKP_WL to transition from logic high to logic low at time T15 (described below).

[0130] At time T14, the clock signal CKPB is logic high.

[0131] In response to the clock signal CKPB transitioning from logic low to logic high, the clock signal CKP_WL transitions from logic high to logic low at time T15.

[0132] At time T16, the clock signal CKP_WL is logic low.

[0133] In response to the clock signal CKP_WL transitioning from logic high to logic low, the tracking wordline signal TRKWL transitions from logic high to logic low at time T16a. For example, in response to the clock signal CKP_WL transitioning from logic high to logic low, inverter I1 causes the clock signal CKP_WLB to transition from logic low to logic high. In response to the clock signal CKP_WLB transitioning from logic low to logic high, inverter I2 causes the tracking wordline signal TRKWL to transition from logic high to logic low.

[0134] At time T17, the tracking word line signal TRKWL is logic low.

[0135] In response to the tracking wordline signal TRKWL transitioning from logic high to logic low, the tracking bitline signal TRKBL transitions from logic low to logic high at time T17. For example, in response to the tracking wordline signal TRKWL transitioning from logic high to logic low, the PMOS transistor P1 is turned on, thereby coupling the PMOS transistor P1 to the voltage supply VDDM. In some embodiments, in response to the tracking wordline signal TRKWL transitioning from logic high to logic low, the NMOS transistors N3 and N4 are turned off, thereby decoupling the drain / source of each of the NMOS transistors N3 and N4 from the tracking bitline TBL.

[0136] At time T18, the tracking bit line signal TRKBL is logic high.

[0137] At time T19, the clock signal CKPBD transitions from logic low to logic high. The transition of the clock signal CKPBD from logic low to logic high causes the clock signal CKPBD to transition from logic low to logic high through the adaptive WL delay circuit 230 because the adaptive WL delay circuit 230 is enabled.

[0138] At time T20, the clock signal CKPBD is logic high.

[0139] At time T21, in response to the tracking bit line signal TRKBL transitioning from logic low to logic high, the signal TRKBL1B transitions from logic high to logic low.

[0140] For example, in response to the tracking bitline signal TRKBL transitioning from logic low to logic high, NMOS transistor N5 turns on and PMOS transistors P2 and P4 turn off. In some embodiments, in response to NMOS transistor N5 turning on and PMOS transistors P2 and P4 turning off, NMOS transistor N5 pulls node N2-1 toward the reference supply voltage VSS, causing the signal TRKBL1B to transition from logic high to logic low and PMOS transistor P3 to turn on.

[0141] At time T22, the TRKBL1B signal is logic low.

[0142] At time T23, in response to the TRKBL1B signal transitioning from logic high to logic low, the RSC signal transitions from logic high to logic low.

[0143] At time T24, the RSC signal is logic low.

[0144] After time T24, the next read operation or write operation of the at least one memory cell in the single column of the memory cell array 206b takes place at least in the memory circuit 200 of Fig. 2 instead.

[0145] In some embodiments, after time T24, the waveform 300 is repeated and is therefore similar to time To, and a similar detailed description is therefore omitted.

[0146] In some embodiments, timing diagram 300 causes at least memory circuit 200 or 400 to achieve one or more of the advantages described herein.

[0147] Although the timing diagram 300 is described with respect to the memory circuit 200, in some embodiments the timing diagram 300 may also be applied to the memory circuit 400 in a similar manner and is not described for brevity.

[0148] Other embodiments of the timing diagram 300 are within the scope of the present disclosure. CONTROL CIRCUIT

[0149] Fig. 4 is a circuit diagram of a control circuit 400, according to some embodiments.

[0150] The control circuit 400 represents a modification of the control circuit 202 of Fig. 2, and a similar detailed description is therefore omitted. For example, the control circuit 400 shows a non-limiting example in which a circuit 402 controls the circuit 201 (e.g., the NOR logic gate NOR1 and the inverter I5) of the control circuit 202 of Fig. 2, and a similar detailed description is therefore omitted.

[0151] The control circuit 400 includes the circuit 402, the inverter I1, the inverter I2, the PMOS transistor P2, the PMOS transistor P3, the PMOS transistor P4, the NMOS transistor N5, the delay chain circuit 220, the clock generation circuit 222, the inverter I3, the inverter I4, the adaptive WL delay circuit 230, the inverter I6, the NAND logic gate NAND1, and the inverter I7.

[0152] In comparison with the control circuit 202 of Fig. 2 replaces circuit 402 of Fig. 4 the circuit 201 of Fig. 2, and a similar detailed description is therefore omitted. In some embodiments, the circuit 402 is similar to the NOR logic gate NOR1 and the inverter I5 of the circuit 201 of Fig. 2 functionally equivalent.

[0153] The circuit 402 comprises an inverter I8, an inverter I9, and a NAND logic gate NAND2.

[0154] The inverter I8 is configured to generate a clock signal CKPB1 in response to the clock signal CKPB. In some embodiments, the clock signal CKPB1 is inverted by the clock signal CKPB. An input terminal of the inverter I8 is configured to receive the clock signal CKPB. The input terminal of the inverter I8 is coupled to the output terminal of the clock generation circuit 222. An output terminal of the inverter I8 is configured to output the clock signal CKPB1. The output terminal of the inverter I8 is coupled to a first input terminal of the NAND logic gate NAND2.

[0155] Inverter I9 is ​​configured to generate a clock signal CKPBD1 in response to clock signal CKPBD. In some embodiments, clock signal CKPBD1 is inverted by clock signal CKPBD. An input terminal of inverter I9 is ​​configured to receive clock signal CKPBD. The input terminal of inverter I9 is ​​coupled to the output terminal of adaptive WL delay circuit 230. An output terminal of inverter I9 is ​​configured to output clock signal CKPBD1. The output terminal of inverter I9 is ​​coupled to a second input terminal of NAND logic gate NAND2.

[0156] The first input terminal of the NAND logic gate NAND2 is configured to receive the clock signal CKPB1. The first input terminal of the NAND logic gate NAND2 is coupled to the output terminal of the inverter I8.

[0157] The second input terminal of the NAND logic gate NAND2 is configured to receive the clock signal CKPBD1. The second input terminal of the NAND logic gate NAND2 is coupled to the output terminal of the inverter I9.

[0158] An output terminal of the NAND logic gate NAND2 is configured to output the clock signal CK2a. In some embodiments, the clock signal CK2a is the clock signal CK2 of Fig. 2. The NAND logic gate NAND2 is configured to generate the clock signal CK2a based on the clock signal CKPB1 and the clock signal CKPBD1. An output terminal of the NAND logic gate NAND2 is coupled to the input terminal of the inverter I6.

[0159] In some embodiments, control circuit 400 operates to achieve one or more of the advantages described herein.

[0160] Other configurations of the control circuit 400 are within the scope of the present disclosure. In some embodiments, the operation of the control circuit 400 is similar to the operation of the control circuit 202, and therefore the timing diagram 300 of Fig. 3 can also be applied to the control circuit 400 and will not be described for the sake of brevity. CIRCUIT:

[0161] Fig. 5 is a circuit diagram of a circuit 500, according to some embodiments.

[0162] The circuit 500 represents an embodiment of the adaptive WL delay circuit 230 of Fig. 2 and Fig. 4, and a similar detailed description is therefore omitted. The circuit 700 of Fig. 7 (described below), the circuit 800 of Fig. 8 (described below) and the circuit 900 of Fig. 9 (described below) are embodiments of the adaptive WL delay circuit 230 of Fig. 2 and Fig. 4, and a similar detailed description is therefore omitted.

[0163] The circuit 500 has a NAND logic gate NAND3.

[0164] The NAND logic gate NAND3 is coupled to the clock generation circuit 222. The NAND logic gate NAND3 is coupled to the first voltage supply, which has the supply voltage VDD.

[0165] A first input terminal of the NAND logic gate NAND3 is configured to receive the clock signal CKPB. The first input terminal of the NAND logic gate NAND3 is coupled to the output terminal of the clock generation circuit 222.

[0166] A second input terminal of the NAND logic gate NAND3 is configured to receive the enable signal DWL_EN. The second input terminal of the NAND logic gate NAND3 is coupled to a source (not shown) of the enable signal DWL_EN.

[0167] An output terminal of the NAND logic gate NAND3 is configured to output the clock signal CKP1. The NAND logic gate NAND3 is configured to generate the clock signal CKP1 based on the clock signal CKPB and the enable signal DWL_EN. All of the output terminal of the NAND logic gate NAND3, a gate of the PMOS transistor MPo, and a gate of the NMOS transistor MNo are coupled to each other. In some embodiments, the NAND logic gate NAND3 is replaced by a NOR logic gate similar to the NOR logic gate NOR1, and a similar detailed description is omitted.

[0168] Circuit 500 further includes a PMOS transistor MPo, a PMOS transistor MP1, a PMOS transistor MP2, an NMOS transistor MNo, an NMOS transistor MN1, and an NMOS transistor MN2. The PMOS transistor MP0, the PMOS transistor MP1, the PMOS transistor MP2, the NMOS transistor MNo, the NMOS transistor MN1, and the NMOS transistor MN2 are part of circuit 502. In some embodiments, circuit 502 is a delay circuit.

[0169] The PMOS transistor MPo and the NMOS transistor MN0 are configured as an inverter (not labeled) and are configured to generate the clock signal CKPB1 in response to the clock signal CKP1. In some embodiments, the clock signal CKPB1 is inverted by the clock signal CKP1.

[0170] A source of the PMOS transistor MPo is coupled to the first voltage supply, which has the supply voltage VDD. A source of the NMOS transistor MN0 is coupled to a reference voltage supply VSS.

[0171] All of a gate of the PMOS transistor MP0 and a gate of the NMOS transistor MN0 are coupled together and are configured to receive the clock signal CKP1 from the output terminal of the NAND logic gate NAND3.

[0172] All of a drain of the PMOS transistor MP0, a drain of the NMOS transistor MN0, a source of the NMOS transistor MN1, a gate of the PMOS transistor MP2 and a gate of the NMOS transistor MN2 are coupled together.

[0173] A source of the PMOS transistor MP1 is coupled to the first power supply, which has the supply voltage VDD.

[0174] All of a gate of PMOS transistor MP1, a drain of PMOS transistor MP2, a drain of NMOS transistor MN2, and an input terminal of inverter I10a of a delay chain circuit 504 are coupled together. The gate of PMOS transistor MP1 is configured to receive a clock signal CKP2 from the drain of PMOS transistor MP2 and the drain of NMOS transistor MN2.

[0175] A drain of the PMOS transistor MP1 and a drain of the NMOS transistor MN1 are coupled together.

[0176] A gate of the NMOS transistor MN1 is coupled to the second voltage supply, which has the supply voltage VDDM. The gate of the NMOS transistor MN1 is configured to receive the supply voltage VDDM from the second voltage supply.

[0177] In some embodiments, at least one of the PMOS transistor MP0 or the NMOS transistor MN0 is configured to adjust or set the clock signal CKPB1 in response to the clock signal CKP1.

[0178] In some embodiments, at least one of the PMOS transistor MP1 or the NMOS transistor MN1 is configured to adjust or set the clock signal CKPB1 in response to at least the clock signal CKP2.

[0179] In some embodiments, the NMOS transistor MN1 is configured to delay a transition of the clock signal CKPB1 from logic high to logic low (shown in Fig. 6 - see curves 602a, 602b, 602c or 602d), which delays a transition of the clock signal CKP2 from logic low to logic high (shown in Fig. 6 - curves 604a, 604b, 604c or 604d).

[0180] In some embodiments, a difference or distance between the second voltage of the power supply VDDM and the first voltage of the power supply VDD causes the NMOS transistor MN1 to turn on, thereby causing a delay in transitions of the clock signal CKP2, which further causes a delay in transitions of the clock signal CKPBD. Further details of the operation of the NMOS transistor MN2 are described below in Fig. 6 discussed.

[0181] The PMOS transistor MP2 and the NMOS transistor MN2 are configured as an inverter (not labeled) and are configured to generate the clock signal CKP2 in response to the clock signal CKPB1. In some embodiments, the clock signal CKP2 is inverted by the clock signal CKPB1.

[0182] A source of PMOS transistor MP2 is coupled to the first power supply, which has the supply voltage VDD. A source of NMOS transistor MN2 is coupled to a reference voltage supply VSS.

[0183] All of a gate of the PMOS transistor MP2 and a gate of the NMOS transistor MN2 are coupled together and are configured to receive the clock signal CKPB1.

[0184] All of the drains of PMOS transistor MP2 and NMOS transistor MN2 are coupled together and configured to output clock signal CKP2. Clock signal CKP2 is applied to the gate of PMOS transistor MP1 as part of a feedback loop.

[0185] The circuit 500 further includes a delay chain circuit 504.

[0186] Delay chain circuit 504 is configured to generate a clock signal CKPBD in response to clock signal CKP2. In some embodiments, clock signal CKPBD represents a delayed and inverted version of clock signal CKP2. Delay chain circuit 504 is coupled to the first voltage supply having supply voltage VDD.

[0187] The delay chain circuit 504 has N stages (collectively referred to as "a set of stages" (unlabeled)), where N is an integer corresponding to the number of stages and inverters I10a, I10b, ..., I10N in the delay chain circuit 504. Each stage of the set of stages is configured to generate a corresponding clock signal CKPBDa, CKPBDb, ..., CKPBDN. In some embodiments, the clock signal CKPBDN is the clock signal CKPBD. The number of stages N of the set of stages (unlabeled) is odd. A number of clock signals CKPBDa, CKPBDb, ..., CKPBDN is odd and equals the integer N. Other numbers of stages N or clock signals CKPBDa, CKPBDb, ..., CKPBDN are within the scope of the present disclosure.

[0188] The delay chain circuit 504 includes N inverters I10a, I10b, ..., I10N (collectively referred to as "a set of inverters I10") coupled in series. The set of inverters I10 is coupled to the first power supply, which has the supply voltage VDD.

[0189] In some embodiments, each inverter of the set of inverters I10 corresponds to a stage N of the set of stages (not labeled). The number of inverters of the set of inverters I10 is odd. Each inverter of the set of inverters I10 is configured to generate a corresponding clock signal CKPBDa, CKPBDb, ..., CKPBDN. In some embodiments, the Nth inverter of the set of inverters I10 is configured to generate a corresponding clock signal, which is the clock signal CKPBD.

[0190] Each inverter I10a, I10b, ..., I10N of the set of inverters is configured to invert the clock signal (e.g., CKP2, CKPBDa, ..., CKPBDN-1) received at the corresponding input terminal, thereby generating an inverted clock signal (e.g., CKPBDa, CKPBDb, ..., CKPBDN), and output the inverted clock signal (e.g., CKPBDa, CKPBDb, ..., CKPBDN) at the corresponding output terminal.

[0191] An input terminal of inverter I10a is configured to receive the clock signal CKP2. An output terminal of inverter I10a is coupled to an input terminal of inverter I10b. An output terminal of inverter I10b is coupled to an input terminal of inverter I10N-1. An output terminal of inverter I10N-1 is coupled to an input terminal of inverter I10N.

[0192] Other configurations, other types of circuit elements, or other numbers of circuit elements in at least one of circuit 502, delay chain circuit 504, or circuit 500 are within the scope of the present disclosure.

[0193] In some embodiments, circuit 500 operates to achieve one or more of the advantages described herein.

[0194] Other embodiments of circuit 500 are within the scope of the present disclosure. SIGNAL TRAILS

[0195] Fig. 6 is a timing diagram 600 of signal waveforms of a circuit, such as the circuit 500 in Fig. 5, the circuit 700 of Fig. 7, the circuit 800 of Fig. 8 or the circuit 900 in Fig. 9, according to some embodiments.

[0196] In some embodiments, Fig. 6 is a timing diagram 600 of at least the adaptive WL delay circuit 230, according to some embodiments. In some embodiments, Fig. 6 illustrates a timing diagram 600 of at least the memory circuit 100, according to some embodiments.

[0197] In some embodiments, one or more read operations or write operations are performed on at least one memory cell in a single column of the memory cell array 206b at least in the memory circuit 200 of Fig. 2, and the timing diagram 600 corresponds to signal waveforms during the one or more read operations or write operations of the at least one memory cell in the single column of the memory cell array 206b at least in the memory circuit 200 of Fig. 2.

[0198] In some embodiments, one or more read operations or write operations of the memory banks are performed at least in the memory circuit 100 by Fig. 1 is applied to at least one of the memory partitions 102A, 102B, 102C, or 102D, and the timing diagram 600 corresponds to signal waveforms during the read operations or memory partitions of at least one of the memory partitions 102A, 102B, 102C, or 102D.

[0199] The timing diagram 300 includes waveforms of the clock signal CKP1, the clock signal CKPB1, and the clock signal CKP2.

[0200] The timing diagram 600 includes curves 602a, 602b, 602c and 602d of the clock signal CKPB1, and curves 604a, 604b, 604c and 604d of the clock signal CKP2.

[0201] In some embodiments, curve 602a represents clock signal CKPB1 when supply voltage VDDM of the second supply voltage is equal to a voltage V1, curve 602b represents clock signal CKPB1 when supply voltage VDDM of the second supply voltage is equal to a voltage V2, curve 602c represents clock signal CKPB1 when supply voltage VDDM of the second supply voltage is equal to a voltage V3, and curve 602d represents clock signal CKPB1 when supply voltage VDDM of the second supply voltage is equal to a voltage V4.

[0202] In some embodiments, voltage V4 is greater than voltage V3, voltage V3 is greater than voltage V2, and voltage V2 is greater than voltage V1.

[0203] In some embodiments, curve 604a represents clock signal CKB2 when supply voltage VDDM of the second supply voltage is equal to voltage V1, curve 604b represents clock signal CKP2 when supply voltage VDDM of the second supply voltage is equal to voltage V2, curve 604c represents clock signal CKP2 when supply voltage VDDM of the second supply voltage is equal to voltage V3, and curve 604d represents clock signal CKP2 when supply voltage VDDM of the second supply voltage is equal to voltage V4.

[0204] Before time T1, clock signal CKP1 is logic low, clock signal CKPB1 (curves 602a, 602b, 602c, and 602d) is logic high, and clock signal CKP2 (604a, 604b, 604c, and 604d) is logic low. For example, before time T1, clock signal CKP1 is logic low, causing PMOS transistor MP0 to turn on and pull node ND5-1 toward the first voltage of the power supply VDD, thus maintaining curves 602a, 602b, 602c, and 602d at logic high. Before time T1, in response to curves 602a, 602b, 602c, and 602d being at logic high, NMOS transistor MN2 is turned on, and curves 604a, 604b, 604c, and 604d are at logic low. In response to curves 604a, 604b, 604c, and 604d being at logic low, PMOS transistor MP1 is turned on, coupling the drain of NMOS transistor MN1 to the voltage supply VDD.In some embodiments, before time T1, since the PMOS transistor MPo is turned on, whereby the voltage of the node N5-1 is set to the first voltage of the power supply VDD, and since the second voltage (V1, V2, V3, V4) of the power supply VDDM is greater than the first voltage of the power supply VDD, the VGS of the NMOS transistor MN1 is then greater than a threshold voltage of the NMOS transistor MN1, and therefore the NMOS transistor MN1 is slightly turned on.

[0205] In some embodiments, the clock signal CKPB is logic high before time T1 (as in Fig. 3 at time T0), the clock signal CKP1 is logic low and the enable signal DWL_EN is logic high. In some embodiments, the circuit 500 is enabled by the enable signal DWL_EN being logic high. In some embodiments, the enable signal DWL_EN is logic high before time T1, causing the circuit 500 to be enabled. In some embodiments, prior to time T1, the enable signal DWL_EN is logic low, causing the circuit 500 to be disabled.

[0206] In some embodiments, at time T1, the clock signal CKP1 is logic low and the enable signal DWL_EN transitions to logic high, thereby activating the circuit 500.

[0207] At time T1, the clock signal CKP1 transitions from logic low to logic high. In some embodiments, at time T1, in response to a transition of the clock signal CKPB from logic high to logic low, as at time T1 in Fig. 3, the clock signal CKP1 changes from logic low to logic high.

[0208] In response to at least the transition of clock signal CKP1 from logic low to logic high, at time T2a, NMOS transistor MN0 begins to turn on, and PMOS transistor MP0 begins to turn off. When NMOS transistor MNo begins to turn on, NMOS transistor MN0 attempts to pull node N5-1 toward reference supply voltage VSS, causing curves 602a, 602b, 602c, and 602d to begin transitioning from logic high to logic low.

[0209] At time T2b, the clock signal CKP1 is logic high. At time T2b, curves 602a, 602b, 602c, and 602d are between logic high and logic low.

[0210] In some embodiments, at time T2b, because the second voltage (V1, V2, V3, V4) of the power supply VDDM is greater than the first voltage of the power supply VDD and the curves 602a, 602b, 602c, and 602d are between logic high and logic low, the VGS of the NMOS transistor MN1 rises and is even greater than the threshold voltage of the NMOS transistor MN1, and therefore causes the NMOS transistor MN1 to turn on more than before time T2b. In some embodiments, at time T2b, although the NMOS transistor MNo is turned on, the NMOS transistor MN0 is unable to pull the node N5-1 fully toward the reference supply voltage VSS because the NMOS transistor MN1 is also turned on and pulling the node N5-1 toward the first supply voltage. Therefore, the NMOS transistor MN1 delays a transition of the clock signal CKPB1 (e.g.Curves 602a, 602b, 602c, or 602d) from logic high to logic low, thereby delaying a transition of clock signal CKP2 (e.g., curves 604a, 604b, 604c, or 604d) from logic low to logic high. In other words, a difference or distance between the second voltage (V1, V2, V3, V4) of power supply VDDM and the first voltage of power supply VDD causes NMOS transistor MN1 to turn on, thereby delaying transitions of clock signal CKP2 (e.g., curves 604a, 604b, 604c, or 604d), causing a delay of transitions of clock signal CKPBD.

[0211] At time T2c, curve 602a is sufficiently low to thereby cause curve 604a to begin transitioning from logic low to logic high. For example, at time T2c, curve 602a is sufficiently low to thereby cause NMOS transistor MN2 to begin turning off and PMOS transistor MP2 to begin turning on. In response to NMOS transistor MN2 beginning to turn off and PMOS transistor MP2 beginning to turn on, PMOS transistor MP2 begins pulling node N5-2 toward the first supply voltage VDD, thereby causing curve 604a to begin transitioning from logic low to logic high.

[0212] At time T2c, in response to curve 604a beginning to transition from logic low to logic high, PMOS transistor MP1 is caused to begin to turn off, thereby decoupling the drain of the NMOS transistor from the first voltage supply. In some embodiments, by decoupling the drain of the NMOS transistor from the first voltage supply and with NMOS transistor MN0 turned on, NMOS transistor MN0 no longer competes with NMOS transistor MN1, and NMOS transistor MN0 is able to cause curve 602a to further transition to logic low.

[0213] At time T3, curve 602a is logically low and curve 604a is almost logically high.

[0214] At time T3, curve 602b is sufficiently low to cause curve 604b to begin transitioning from logic low to logic high. At time T3, the operation of circuit 502 for curve 602b and curve 604b is the same as for the corresponding curve 602a and curve 604a at time T2c, and a similar detailed description is therefore omitted.

[0215] At time T4, curve 602b is logically low and curves 604a and 604b are logically high.

[0216] At time T5, curve 602c is sufficiently low to cause curve 604c to begin transitioning from logic low to logic high. At time T5, the operation of circuit 502 for curve 602c and curve 604c is the same as for the corresponding curve 602a and curve 604a at time T2c, and a similar detailed description is therefore omitted.

[0217] At time T6, curve 602d is sufficiently low to cause curve 604d to begin transitioning from logic low to logic high. At time T6, the operation of circuit 502 for curve 602d and curve 604d is the same as for the corresponding curve 602a and curve 604a at time T2c, and a similar detailed description is therefore omitted.

[0218] At time T7, curve 602c and curve 602b are at logic low, curve 604c is at logic high, and curve 604a is almost at logic high.

[0219] At time T8, curve 604a is at a logical high.

[0220] As in Fig. 6, curve 602b is delayed relative to curve 602a, curve 602c is delayed relative to curve 602b, and curve 602b is delayed relative to curve 602c. In some embodiments, a delay amount of curve 602b, 602c, or 602d relative to curve 602a may be adjusted by at least NMOS transistor MN1 by a corresponding voltage V2, V3, or V4.

[0221] As in Fig. As shown in Figure 6, curve 604b is delayed relative to curve 604a, curve 604c is delayed relative to curve 604b, and curve 604d is delayed relative to curve 604c. In some embodiments, a delay amount of curve 604b, 604c, or 604d relative to curve 604a may be adjusted by at least NMOS transistor MN1 by a corresponding voltage V2, V3, or V4.

[0222] A difference or distance between the second voltage (V1, V2, V3, V4) of the power supply VDDM and the first voltage of the power supply VDD causes the delay of transitions of the clock signal CKPB1 (e.g. curves 602a, 602b, 602c or 602d) and CKP2 (e.g. curves 604a, 604b, 604c or 604d), thereby causing a delay of transitions of the clock signal CKPBD (in Fig. 3). In some embodiments, the difference or distance between the second voltage (V1, V2, V3, V4) of the power supply VDDM and the first voltage of the power supply VDD causes the NMOS transistor MN1 to turn on, thereby delaying transitions of the clock signal CKP2 (e.g., curves 604a, 604b, 604c, or 604d), thereby causing a delay of transitions of the clock signal CKPBD.

[0223] Then, in some embodiments, as the difference or distance between the second voltage (V1, V2, V3, V4) of the power supply VDDM and the first voltage of the power supply VDD increases, the delay amount of the clock signal CKB1 (e.g., curves 602a, 602b, 602c, or 602d) transitioning from logic high to logic low increases, and the delay amount of the clock signal CKP2 (e.g., curves 604a, 604b, 604c, or 604d) transitioning from logic low to logic high increases.

[0224] Then, in some embodiments, as the difference or distance between the second voltage (V1, V2, V3, V4) of the power supply VDDM and the first voltage of the power supply VDD decreases, the delay amount of the clock signal CKB1 (e.g., curves 602a, 602b, 602c, or 602d) transitioning from logic high to logic low increases, and the delay amount of the clock signal CKP2 (e.g., curves 604a, 604b, 604c, or 604d) transitioning from logic low to logic high decreases.

[0225] In some embodiments, the circuit 500 may be used in a dual-rail supply scheme, and by using the circuit 500 and the waveform 600, the rising edge and the falling edge of the wordline signal WL are delayed by at least the clock signal CKPBD, and therefore the circuit 500 is not affected by write margin degradation because the pulse width of the wordline signal WL is not reduced compared to other approaches.

[0226] In some embodiments, circuit 500 may be used in a dual-rail supply scheme, and increases in the VDDM-VDD margin due to the dual-rail supply schemes do not cause early read issues because increases in the VDDM-VDD margin in circuit 500 also cause increases in the delay of at least the clock signal CKPBD, thereby causing the word line signal WL to be delayed with respect to the clock signal CKP_WY compared to other approaches.

[0227] In some embodiments, by operating circuit 500, waveform 600 causes at least one of circuit 500, 700, 800, or 900 to achieve one or more benefits described herein.

[0228] Although timing diagram 600 is described with respect to circuit 500, in some embodiments, timing diagram 600 may also be applied in a similar manner to one or more of circuits 700, 800, or 900 and is not described for brevity.

[0229] Other embodiments of the timing diagram 600 are within the scope of the present disclosure. CIRCUIT:

[0230] Fig. 7 is a circuit diagram of a circuit 700, according to some embodiments.

[0231] The circuit 700 represents a modification of the circuit 500 of Fig. 5, and a similar detailed description is therefore omitted. For example, the circuit 700 shows a non-limiting example in which, in comparison with the circuit 500 of Fig. 5, an additional delay chain circuit 702 is incorporated in the formwork 700, and a similar detailed description is therefore omitted.

[0232] The circuit 700 represents an embodiment of the adaptive WL delay circuit 230 of Fig. 2 and Fig. 4, and a similar detailed description is therefore omitted.

[0233] The circuit 700 includes the NAND logic gate NAND3, the delay chain circuit 702, the circuit 502, and the delay chain circuit 504.

[0234] Compared with the circuit 500 of Fig. 5 is the delay chain circuit 702 of Fig. 7 between the NAND logic gate NAND3 and the circuit 502, and a similar detailed description is therefore omitted.

[0235] Delay chain circuit 702 is configured to generate a clock signal CKP1 in response to clock signal CKP1a. In some embodiments, clock signal CKP1 represents a delayed version of clock signal CKP1a. Delay chain circuit 702 is coupled to the first voltage supply having supply voltage VDD.

[0236] The delay chain circuit 702 has M stages (collectively referred to as "a set of stages" (unlabeled)), where M is an integer corresponding to the number of stages and inverters I11a, I11b, ..., I11M in the delay chain circuit 702. Each stage of the set of stages is configured to generate a corresponding clock signal CKPD1a, CKPD1b, ..., CKPD1M. In some embodiments, the clock signal CKPD1M is the clock signal CKP1. The number of stages M of the set of stages (unlabeled) is even. A number of clock signals CKPD1a, CKPD1b, ..., CKPD1M is even and equals the integer M. Other numbers of stages M or clock signals CKPD1a, CKPD1b, ..., CKPD1M are within the scope of the present disclosure.

[0237] The delay chain circuit 702 includes M inverters I11a, I11b, ..., I11M (collectively referred to as "a set of inverters I11") coupled in series. The set of inverters I11 is coupled to the first power supply, which has the supply voltage VDD.

[0238] In some embodiments, each inverter of the set of inverters I11 corresponds to a stage M of the set of stages (not labeled). The number of inverters of the set of inverters I11 is even. Each inverter of the set of inverters I11 is configured to generate a corresponding clock signal CKPD1a, CKPD1b, ..., CKPD1M. In some embodiments, the Mth inverter of the set of inverters I11 is configured to generate a corresponding clock signal CKPD1M, which is the clock signal CKP1.

[0239] Each inverter I11a, I11b, ..., I11M of the set of inverters is configured to invert the clock signal (e.g., CKP1a, CKPD1a, ..., CKPD1M-1) received at the corresponding input terminal, thereby generating an inverted clock signal (e.g., CKPD1a, CKPD1b, ..., CKPD1M), and output the inverted clock signal (e.g., CKPD1a, CKPD1b, ..., CKPD1M) at the corresponding output terminal.

[0240] An input terminal of the inverter I11a is coupled to the output terminal of the NAND logic gate NAND3. The input terminal of the inverter I11a is configured to receive the clock signal CKP1a. In some embodiments, the clock signal CKP1a is Fig. 7 the clock signal CKP1 from Fig. 5, and a similar detailed description is therefore omitted. An output terminal of the inverter I11a is coupled to an input terminal of the inverter I11b. An output terminal of the inverter I11b is coupled to an input terminal of the inverter I11M-1. An output terminal of the inverter I11M-1 is coupled to an input terminal of the inverter I11M. The output terminal of the inverter I11M is coupled to the gate of the PMOS transistor MPo and the gate of the NMOS transistor MN0.

[0241] Other configurations, other types of circuit elements, or other numbers of circuit elements in at least one of circuit 502, delay chain circuit 702, delay chain circuit 504, or circuit 700 are within the scope of the present disclosure.

[0242] In some embodiments, circuit 700 operates to achieve one or more of the advantages described herein.

[0243] Other configurations of circuit 700 are within the scope of the present disclosure. In some embodiments, the operation of circuit 700 is similar to the operation of circuit 500, and therefore the timing diagram 600 of Fig. 6 can also be applied to the circuit 700 and will not be described for the sake of brevity.

[0244] Fig. 8 is a circuit diagram of a circuit 800, according to some embodiments.

[0245] The circuit 800 represents a modification of the circuit 500 of Fig. 5, and a similar detailed description is therefore omitted. For example, circuit 800 shows a non-limiting example in which, compared with the circuit 500 of Fig. 5, an additional circuit 802 is incorporated in the formwork 800, and a similar detailed description is therefore omitted.

[0246] Circuit 800 represents an embodiment of the adaptive WL delay circuit 230 of Fig. 2 and Fig. 4, and a similar detailed description is therefore omitted.

[0247] The circuit 800 includes the NAND logic gate NAND3, the circuit 502, the circuit 802, and the delay chain circuit 504.

[0248] Compared with the circuit 500 of Fig. 5 is the circuit 802 of Fig. 8 between the circuit 502 and the delay chain circuit 504, and a similar detailed description is therefore omitted.

[0249] The circuit 802 represents a modification of the circuit 502 of Fig. 5, and a similar detailed description is therefore omitted. In some embodiments, the operation of circuit 802 is similar to circuit 502, and a similar detailed description is therefore omitted.

[0250] Circuit 802 includes a PMOS transistor MP3, a PMOS transistor MP4, a PMOS transistor MP5, an NMOS transistor MN3, an NMOS transistor MN4, and an NMOS transistor MN5. The PMOS transistor MP3, the PMOS transistor MP4, the PMOS transistor MP5, the NMOS transistor MN3, the NMOS transistor MN4, and the NMOS transistor MN5 are part of circuit 802.

[0251] Compared with the circuit 502 of Fig. 5, the PMOS transistor MP3 is similar to the PMOS transistor MP0, the PMOS transistor MP4 is similar to the PMOS transistor MP1, the PMOS transistor MP5 is similar to the PMOS transistor MP2, the NMOS transistor MN3 is similar to the NMOS transistor MN0, the NMOS transistor MN4 is similar to the NMOS transistor MN1, and the NMOS transistor MN5 is similar to the NMOS transistor MN2, and similar detailed description is therefore omitted.

[0252] The PMOS transistor MP3 and the NMOS transistor MN3 are configured as an inverter (not labeled) and are configured to generate the clock signal CKPB2 in response to the clock signal CKP2. In some embodiments, the clock signal CKPB2 is inverted by the clock signal CKP2.

[0253] A source of PMOS transistor MP3 is coupled to the first voltage supply, which has the supply voltage VDD. A source of NMOS transistor MN3 is coupled to a reference voltage supply VSS.

[0254] Compared with Fig. 5 are all coupled together by a gate of the PMOS transistor MP3, a gate of the NMOS transistor MN3, the gate of the PMOS transistor MP2, the gate of the NMOS transistor MN2 and the gate of the PMOS transistor MP1.

[0255] All of the gate of the PMOS transistor MP3 and the gate of the NMOS transistor MN3 are configured to receive the clock signal CKP2 from the PMOS transistor MP3 and the NMOS transistor MN3.

[0256] All of a drain of the PMOS transistor MP3, a drain of the NMOS transistor MN3, a source of the NMOS transistor MN4, a gate of the PMOS transistor MP5 and a gate of the NMOS transistor MN5 are coupled together.

[0257] A source of the PMOS transistor MP4 is coupled to the first power supply, which has the supply voltage VDD.

[0258] All of the gate of PMOS transistor MP4, the drain of PMOS transistor MP5, the drain of NMOS transistor MN5, and the input terminal of inverter I10a of delay circuit 504 are coupled together. The gate of PMOS transistor MP4 is configured to receive a clock signal CKP2 from the drain of PMOS transistor MP5 and the drain of NMOS transistor MN5.

[0259] A drain of the PMOS transistor MP4 and a drain of the NMOS transistor MN4 are coupled together.

[0260] A gate of the NMOS transistor MN4 is coupled to the second voltage supply, which has the supply voltage VDDM. The gate of the NMOS transistor MN4 is configured to receive the supply voltage VDDM from the second voltage supply.

[0261] In some embodiments, the effect of arranging the gate of NMOS transistor MN4 to receive the supply voltage VDDM from the second voltage supply is similar to the effect of arranging the gate of NMOS transistor MN1 to receive the supply voltage VDDM from the second voltage supply, and a similar detailed description is therefore omitted. In some embodiments, adding additional circuitry 802 to circuitry 800 causes circuitry 800 to generate the clock signal CKPBD with an additional tuning delay compared to other approaches.

[0262] In some embodiments, at least one of the PMOS transistor MP4 or the NMOS transistor MN4 is configured to adjust or set the clock signal CKPB2.

[0263] The PMOS transistor MP5 and the NMOS transistor MN5 are configured as an inverter (not labeled) and are configured to generate the clock signal CKP3 in response to the clock signal CKPB2. In some embodiments, the clock signal CKP3 is inverted by the clock signal CKPB2.

[0264] A source of PMOS transistor MP5 is coupled to the first voltage supply, which has the supply voltage VDD. A source of NMOS transistor MN5 is coupled to the reference voltage supply VSS.

[0265] All of a gate of the PMOS transistor MP5 and a gate of the NMOS transistor MN5 are coupled together and are configured to receive the clock signal CKPB2.

[0266] All of the drains of PMOS transistor MP5 and NMOS transistor MN5 are coupled together and configured to output clock signal CKP3 to the input terminal of inverter I10a. Clock signal CKP3 is applied to the gate of PMOS transistor MP4 as part of a feedback loop.

[0267] The input terminal of the inverter I10a of Fig. 8 is configured to receive the clock signal CKP3. Compared with the inverter I10a of Fig. 5 replaces the clock signal CKP3 of Fig. 8 the clock signal CKP2 at the input terminal of the inverter I10a of Fig. 5, and a similar detailed description is therefore omitted. Therefore, the delay chain circuit 504 in Fig. 8 is configured to generate the clock signal CKPBD in response to the clock signal CKP3. In some embodiments, the clock signal CKPBD represents an inverted and a delayed version of the clock signal CKP3.

[0268] Other configurations, other types of circuit elements, or other numbers of circuit elements in at least one of circuit 502, circuit 802, delay chain circuit 504, or circuit 800 are within the scope of the present disclosure.

[0269] In some embodiments, circuit 800 operates to achieve one or more of the advantages described herein.

[0270] Other configurations of circuit 800 are within the scope of the present disclosure. In some embodiments, the operation of circuit 800 is similar to the operation of circuit 500, and therefore, timing diagram 600 of Fig. 6 can also be applied to the circuit 800 and will not be described for the sake of brevity.

[0271] Fig. 9 is a circuit diagram of a circuit 900, according to some embodiments.

[0272] The circuit 900 represents a modification of the circuit 500 of Fig. 5, and a similar detailed description is therefore omitted. For example, circuit 900 shows a non-limiting example in which circuit 902 is compared with circuit 502 of Fig. 5 additional inverters (e.g., inverters I12 and I13), and a similar detailed description is therefore omitted. In some embodiments, adding inverters (e.g., inverters I12 and I13) to circuit 900 causes circuit 900 to generate clock signal CKPBD with an additional tuning delay compared to other approaches.

[0273] The circuit 900 includes the NAND logic gate NAND3, the circuit 902 and the delay chain circuit 504.

[0274] Compared with the circuit 500 of Fig. 5, the circuit 902 replaces the circuit 502 of Fig. 5, and a similar detailed description is therefore omitted.

[0275] The circuit 902 represents a modification of the circuit 502 of Fig. 5, and a similar detailed description is therefore omitted. In comparison with the circuit 502 of Fig. 5, circuit 902 further includes inverter I12 and inverter I13, and a similar detailed description is therefore omitted. In some embodiments, the operation of circuit 902 is similar to circuit 502, and a similar detailed description is therefore omitted.

[0276] Compared with the circuit 502 of Fig. 5 are in Fig. 9 are all coupled to each other by the gate of the PMOS transistor MP1, an output terminal of the inverter I13 and the input terminal of the inverter I10a of the delay circuit 504.

[0277] Compared with the circuit 502 of Fig. 5, the gate of PMOS transistor MP1 is configured to receive clock signal CKP2 from the output terminal of inverter I13, and a similar detailed description is therefore omitted. Clock signal CKP2 is supplied to the gate of PMOS transistor MP1 as part of a feedback loop.

[0278] Compared with the circuit 502 of Fig. 5 are all connected to the drain of the PMOS transistor MP2, the drain of the NMOS transistor MN2 and an input terminal of the inverter I12 in Fig. 9 linked together.

[0279] Compared with the circuit 502 of Fig. 5 are in Fig. 9 all of the drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 are configured to output the clock signal CKP2a. In some embodiments, the clock signal CKP2a is Fig. 9 the clock signal CKP2 at the drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 of Fig. 5, and a similar detailed description is therefore omitted. In some embodiments, the clock signal CKP2a is inverted from the clock signal CKPB1.

[0280] Inverter I12 is configured to generate a clock signal CKP2b in response to clock signal CKP2a. In some embodiments, clock signal CKP2b is inverted by clock signal CKP2a. An input terminal of inverter I12 is configured to receive clock signal CKP2a. The input terminal of inverter I12 is coupled to the drain of PMOS transistor MP2 and the drain of NMOS transistor MN2. An output terminal of inverter I12 is coupled to an input terminal of inverter I13 and is configured to output clock signal CKP2b.

[0281] Inverter I13 is configured to generate clock signal CKP2 in response to clock signal CKP2b. In some embodiments, clock signal CKP2 is inverted by clock signal CKP2b. In some embodiments, clock signal CKP2 represents a delayed version of clock signal CKP2a. An input terminal of inverter I13 is coupled to the output terminal of inverter I12 and is configured to receive clock signal CKP2b. An output terminal of inverter I13 is coupled to the input terminal of inverter I10a and the gate of PMOS transistor MP1. The output terminal of inverter I13 is configured to output clock signal CKP2.

[0282] Each of the inverter I12 and the inverter I13 is coupled to the first power supply having the supply voltage VDD.

[0283] Compared with the circuit 500 of Fig. 5 is the input terminal of the inverter I10a of Fig. 9 is configured to receive the clock signal CKP2 from the output terminal of the inverter I13.

[0284] Other configurations, other types of circuit elements, or other numbers of circuit elements in at least one of circuit 902, delay chain circuit 504, or circuit 900 are within the scope of the present disclosure.

[0285] In some embodiments, circuit 900 operates to achieve one or more advantages described herein.

[0286] Other configurations of circuit 900 are within the scope of the present disclosure. In some embodiments, the operation of circuit 900 is similar to the operation of circuit 500, and therefore, timing diagram 600 of Fig. 6 can also be applied to the circuit 900 and will not be described for the sake of brevity. MEMORY CELL

[0287] Fig. 10 is a circuit diagram of a memory cell 1000 used in Fig. 1 and Fig. 2 may be used, according to some embodiments.

[0288] The memory cell 1000 may be configured as one or more memory cells MCB in at least one of the memory cell array 110AR of Fig. 1, the storage device 112 of Fig. 1, the memory cell MCB of Fig. 2 or the memory cell array 206b of Fig. 2 can be used.

[0289] Memory cell 1000 is a single-port SRAM (SP-SRAM) memory cell with six transistors (6T), which is used for illustration purposes. In some embodiments, memory cell 1000 uses a number of transistors other than six. Other memory types are within the scope of various embodiments.

[0290] Memory cell 1000 includes two PMOS transistors P10-1 and P10-2, and four NMOS transistors N10-1, N10-2, N10-3, and N10-4. Transistors P10-1, P10-2, N10-1, and N10-2 form a cross-latch or a pair of cross-coupled inverters. For example, PMOS transistor P10-1 and NMOS transistor N10-1 form a first inverter, while PMOS transistor P10-2 and NMOS transistor N10-2 form a second inverter.

[0291] A source terminal of each of the PMOS transistors P10-1 and P10-2 is configured as a power supply node NODE_1. Each power supply node NODE_1 is coupled to a first power supply VDDI. A drain terminal of the PMOS transistor P10-1 is coupled to a drain terminal of the NMOS transistor N10-1, a gate terminal of the PMOS transistor P10-2, a gate terminal of the NMOS transistor N10-2, and a source terminal of the NMOS transistor N10-3, and is configured as a storage node ND.

[0292] A drain terminal of the PMOS transistor P10-2 is coupled to a drain terminal of the NMOS transistor N10-2, a gate terminal of the PMOS transistor P10-1, a gate terminal of the NMOS transistor N10-1, and a source terminal of the NMOS transistor N10-4, and is configured as a storage node NDB. A source terminal of each of the NMOS transistors N10-1 and N10-2 is configured as a supply reference voltage node (not labeled) having a supply reference voltage VSS. The source terminal of each of the NMOS transistors N10-1 and N10-2 is also coupled to the reference voltage supply VSS.

[0293] A word line WL is coupled to a gate terminal of each of the NMOS transistors N10-3 and N10-4. The word line WL is also referred to as a write control line because the NMOS transistors N10-3 and N10-4 are configured to be controlled by a signal on the word line WL to transfer data between bit lines BL, BLB and corresponding nodes ND, NDB.

[0294] A drain terminal of NMOS transistor N10-3 is coupled to a bit line BL. A drain terminal of NMOS transistor N10-4 is coupled to a bit line BLB. Bit lines BL and BLB are configured as both data input and output for memory cell 1000. In some embodiments, during a write operation, applying a logical value to one bit line BL and the opposite logical value to the other bit line BLB enables the logical values ​​on the bit lines to be written to memory cell 1000. Each of bit lines BL and BLB is referred to as a data line because the data carried on bit lines BL and BLB is written to and read from the corresponding nodes ND and NDB.

[0295] The word line WL corresponds to one or more word lines WL in Fig. 2.

[0296] Other configurations of the memory cell 1000 are within the scope of the present disclosure. SIGNAL TRAILS

[0297] Fig. 11 is a timing diagram 1100 of signal waveforms of a memory circuit, such as the memory circuit 200 in Fig. 2, according to some embodiments. In some embodiments, Fig. 11 shows a timing diagram 1100 of at least one of circuit 400, circuit 500, circuit 700, circuit 800, or circuit 900, according to some embodiments. In some embodiments, Fig. 11 is a timing diagram 1100 of at least the memory circuit 100, according to some embodiments.

[0298] In some embodiments, one or more read operations or write operations are performed on at least one memory cell in a single column of the memory cell array 206b at least in the memory circuit 200 of Fig. 2, and the timing diagram 1100 corresponds to signal waveforms during the one or more read operations or write operations of the at least one memory cell in the single column of the memory cell array 206b at least in the memory circuit 200 of Fig. 2.

[0299] The timing diagram 1100 includes curves 1102a and 1102b of an equalization signal BLEQB and curves 1104a and 1104b of a word line signal WL.

[0300] In some embodiments, curve 1102a represents an equalization signal BLEQB that corresponds to the clock equalization signal CKP_BLEQ of Fig. 2 when the adaptive WL delay circuit 230 is deactivated, and the curve 1102b represents the equalization signal BLEQB, which corresponds to the clock equalization signal CKP_BLEQ of Fig. 2 when the adaptive WL delay circuit 230 is activated.

[0301] As in Fig. As shown in Figure 11, curve 1102b is delayed relative to curve 1102a. In some embodiments, a delay amount of curve 1102b relative to curve 1102a may be adjusted by at least one of adaptive WL delay circuit 230 or circuit 500, 700, 800, or 900.

[0302] In some embodiments, curve 1104a represents a word line signal WL of Fig. 2 when the adaptive WL delay circuit 230 is deactivated; and the curve 1104b represents a word line signal WL of Fig. 2 when the adaptive WL delay circuit 230 is activated.

[0303] As in Fig. As shown in Figure 11, curve 1104b is delayed relative to curve 1104a. In some embodiments, an amount of delay of curve 1104b relative to curve 1104a may be adjusted by at least one of adaptive WL delay circuit 230 or circuit 500, 700, 800, or 900.

[0304] Although the timing diagram 1100 is described with respect to the memory cell array 206b, in some embodiments the timing diagram 1100 may also be applied in a similar manner to one or more of memory banks 110L or 110R and is not described for brevity.

[0305] Other embodiments of the timing diagram 1100 are within the scope of the present disclosure. PROCEDURE

[0306] Fig. 12A-12B are a flow diagram of a method 1200 for operating a circuit, according to some embodiments.

[0307] In some embodiments, Fig. 12A-12B are flow diagrams of a method 1200 for operating at least one of the memory circuit 100 of Fig. 1, the memory circuit 200 of Fig. 2 or the memory circuit 400 of Fig. 4 or the memory cell 1000 of Fig. 10.

[0308] In some embodiments, Fig. 12A-12B are flow diagrams of a method 1200 for operating at least one of the circuit 500 of Fig. 5, the circuit 700 of Fig. 7, the circuit 800 of Fig. 8, or the circuit 900 of Fig. 9. In some embodiments, Fig. 12A-12B are flow diagrams of a method 1200 for operating a memory circuit, and the method 1200 includes the features of at least one of the timing diagram 300 of Fig. 3, the timing diagram 600 of Fig. 6 or the time diagram 1100 of Fig. 11, and a similar detailed description is omitted for brevity.

[0309] It is understood that additional processes may occur before, during and / or after the Fig. 12A-12B, and that some other operations may be described only briefly here. It is understood that the method 1200 may include features of one or more of at least one of the memory circuit 100 of Fig. 1, the memory circuit 200 of Fig. 2, the memory circuit 400 of Fig. 4, the circuit 500 of Fig. 5, the circuit 700 of Fig. 7, the circuit 800 of Fig. 8, the circuit 900 of Fig. 9, or the memory cell 1000 of Fig. 10, and a similar detailed description is omitted for brevity.

[0310] In some embodiments, a different order of operations of method 1200 is within the scope of the present disclosure. Method 1200 includes example operations, but the operations are not necessarily performed in the order presented. Operations may be added, substituted, changed in order, and / or eliminated as appropriate, consistent with the spirit and scope of disclosed embodiments. In some embodiments, one or more of the operations of method 1200 are not performed.

[0311] In operation 1202 of method 1200, a first clock signal is generated in response to a first reset signal and a clock signal.

[0312] In some embodiments, the process 1202 is performed by a first clock circuit. In some embodiments, the first clock circuit of the method 1200 includes the clock generation circuit 222.

[0313] In some embodiments, the first clock signal of method 1200 comprises the clock signal CKPB. In some embodiments, the first reset signal of method 1200 comprises the signal RSC. In some embodiments, the clock signal of method 1200 comprises the clock signal CLK.

[0314] At operation 1204 of method 1200, a delay between the first clock signal and a second clock signal is set in response to the first clock signal and an enable signal.

[0315] In some embodiments, process 1204 is performed by an adjustable delay circuit. In some embodiments, the adjustable delay circuit of method 1200 comprises adaptive WL delay circuit 230 or circuit 500, 700, 800, or 900.

[0316] In some embodiments, the second clock signal of method 1200 comprises the clock signal CKPBD. In some embodiments, the enable signal of method 1200 comprises the enable signal DWL_EN.

[0317] In some embodiments, operation 1204 includes generating the second clock signal in response to the first clock signal and the activation signal.

[0318] In some embodiments, operation 1204 includes at least one of operations 1206, 1208, or 1210.

[0319] At operation 1206 of method 1200, a first intermediate clock signal is generated in response to the first clock signal and the enable signal.

[0320] In some embodiments, the process 1206 is performed by a first NAND logic gate. In some embodiments, the first NAND logic gate of the method 1200 includes at least the NAND logic gate NAND3.

[0321] In some embodiments, the first intermediate clock signal of method 1200 comprises at least one of the clock signal CKP1 or CKP1a.

[0322] In operation 1208 of method 1200, a first delayed clock signal is generated in response to at least the first intermediate clock signal.

[0323] In some embodiments, process 1208 is performed by at least one of a first delay circuit or a second delay circuit. In some embodiments, the first delay circuit of process 1200 comprises at least one of circuit 502 or 902. In some embodiments, the second delay circuit of process 1200 comprises at least one of delay chain circuit 702 or circuit 802.

[0324] In some embodiments, the first delayed clock signal of method 1200 comprises the clock signal CKP2.

[0325] In operation 1210 of method 1200, the second clock signal is generated in response to the first delayed clock signal.

[0326] In some embodiments, process 1210 is performed by at least one of a third delay circuit. In some embodiments, the third delay circuit of method 1200 comprises at least one of delay chain circuit 504. In some embodiments, the second clock signal is delayed and inverted with respect to the first delayed clock signal.

[0327] In operation 1212 of method 1200, a third clock signal is generated in response to the first clock signal and the second clock signal.

[0328] In some embodiments, the process 1212 is performed by a first circuit. In some embodiments, the first circuit of the process 1200 includes at least the NOR logic gate NOR1 and the inverter I5. In some embodiments, the first circuit of the process 1200 includes at least the NAND logic gate NAND2 and the inverters I8 and I9.

[0329] In some embodiments, the third clock signal of method 1200 comprises at least one of the clock signal CK2 or CK2a.

[0330] In operation 1214 of method 1200, a fourth clock signal is generated in response to the third clock signal.

[0331] In some embodiments, operation 1214 is performed by a first inverter. In some embodiments, the first inverter of method 1200 includes at least inverter 16.

[0332] In some embodiments, the fourth clock signal of method 1200 includes at least one of the clock signal CKP_WL.

[0333] In operation 1216 of method 1200, a tracking wordline signal is generated in response to the fourth clock signal.

[0334] In some embodiments, operation 1216 is performed by a pair of inverters. In some embodiments, the pair of inverters of method 1200 includes at least inverters I1 and I2.

[0335] In some embodiments, the tracking wordline signal of method 1200 comprises the tracking wordline signal TRKWL.

[0336] In operation 1218 of method 1200, a first decoder signal is generated in response to a second decoder signal and the fourth clock signal.

[0337] In some embodiments, operation 1218 is performed by a first NAND logic gate. In some embodiments, the first NAND logic gate of method 1200 comprises NAND logic gate NAND1.

[0338] In some embodiments, the first decoder signal of method 1200 comprises the decoder signal ND1. In some embodiments, the second decoder signal of method 1200 comprises the decoder signal pdec_x.

[0339] At operation 1220 of method 1200, a third decoder signal is generated in response to the first decoder signal.

[0340] In some embodiments, the process 1220 is performed by a second inverter. In some embodiments, the second inverter of the method 1200 comprises the second inverter I7.

[0341] In some embodiments, the third decoder signal of method 1200 comprises the decoder signal DEC_X.

[0342] At operation 1222 of method 1200, a wordline rail signal WLB is generated in response to the third decoder signal.

[0343] In some embodiments, operation 1222 is performed by a wordline post-decoder circuit. In some embodiments, the wordline post-decoder circuit of method 1200 includes post-decoder circuit 240.

[0344] In operation 1224 of method 1200, a wordline signal WL is generated in response to the wordline rail signal.

[0345] In some embodiments, operation 1224 is performed by a third inverter. In some embodiments, the third inverter of method 1200 includes NMOS transistor N6 and PMOS transistor P6.

[0346] At operation 1226 of method 1200, a pull-up transistor is turned off in response to the tracking wordline signal TRKWL, and a tracking bitline signal TRKBL is set by a set of tracking cells in response to the tracking wordline signal TRKWL.

[0347] In some embodiments, the pull-up transistor of method 1200 comprises PMOS transistor P1. In some embodiments, the set of tracking cells of method 1200 comprises tracking cells 206a.

[0348] In some embodiments, operation 1226 includes turning on the pull-up transistor in response to the tracking wordline signal TRKWL, thereby setting the tracking bitline signal TRKBL in response to the tracking wordline signal TRKWL, and turning off the set of tracking cells in response to the tracking wordline signal TRKWL.

[0349] At operation 1228 of method 1200, a first signal is asserted in response to the tracking bit line signal.

[0350] In some embodiments, operation 1228 is performed by at least a first P-type transistor or a first N-type transistor. In some embodiments, the first P-type transistor comprises at least one of PMOS transistors P4, P2, or P3. In some embodiments, the first N-type transistor comprises NMOS transistor N5.

[0351] In some embodiments, the first signal of method 1200 comprises the signal TRKBL1B.

[0352] At operation 1230 of method 1200, the first reset signal is generated in response to the first signal.

[0353] In some embodiments, operation 1230 is performed by delay circuit 220.

[0354] By the operating method 1200, at least one of the memory circuit 100 operates from Fig. 1, the memory circuit 200 of Fig. 2 or the memory circuit 400 of Fig. 4 to achieve the benefits discussed here.

[0355] In some embodiments, one or more of the acts of method 1200 are not performed. In addition, for illustrative purposes, various Fig. 2, 4 to 5 and 7 to 10, the PMOS or NMOS transistors illustrated have a particular dopant type (e.g., N-type or P-type). Embodiments of the disclosure are not limited to a particular transistor type, and one or more of the Fig. The PMOS or NMOS transistors illustrated in Figures 2, 4 to 5, and 7 to 10 may be replaced by a corresponding transistor of a different transistor / dopant type. Likewise, the low or high logic value of various signals used in the above description is also for illustrative purposes. Embodiments of the disclosure are not limited to a particular logic value when a signal is enabled and / or disabled. The selection of other logic values ​​is within the scope of various embodiments. The selection of other numbers of inverters in Fig. 2, 4 to 5 and 7 to 10 is within the scope of various embodiments. The choice of other numbers of transistors in Fig. 2, 4 to 5 and 7 to 10 is within the scope of various embodiments. The choice of other numbers of NAND or NOR logic gates in Fig.2, 4 to 5 and 7 to 10 are within the scope of various embodiments.

[0356] It will be readily apparent to one of ordinary skill in the art that one or more of the disclosed embodiments will achieve one or more of the advantages set forth above. After reading the above description, one of ordinary skill in the art will be able to suggest various modifications, substitutions of equivalents, and various other embodiments as generally disclosed herein. Therefore, the scope of protection granted hereunder is intended to be limited only by the definition included in the appended claims and their equivalents.

[0357] One aspect of this description relates to a memory circuit. The memory circuit includes a wordline driver circuit coupled to a wordline and a control circuit coupled to the wordline driver circuit. In some embodiments, the control circuit is configured to delay a rising edge or a falling edge of a wordline signal in response to at least a first clock signal. In some embodiments, the control circuit includes: a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second clock signal and a third clock signal in response to the second clock signal and an enable signal.In some embodiments, the third clock signal is a delayed version of the second clock signal. In some embodiments, an amount of delay between the second clock signal and the third clock signal is based on a voltage difference between a first supply voltage having a first variation and a second supply voltage having a second variation.

[0358] Another aspect of this description relates to a memory circuit. The memory circuit includes: a memory cell array including a set of memory cells and a set of tracking cells, a wordline driver circuit coupled to the memory cell array, and a control circuit coupled to the wordline driver circuit and configured to delay a rising edge or a falling edge of a wordline signal in response to at least a first clock signal. In some embodiments, the control circuit includes: a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second clock signal and a third clock signal in response to the second clock signal and an enable signal.In some embodiments, the third clock signal is a delayed version of the second clock signal. In some embodiments, an amount of delay between the second clock signal and the third clock signal is based on a voltage difference between a first supply voltage having a first variation and a second supply voltage having a second variation.

[0359] Yet another aspect of this description relates to a method of operating a memory circuit. The method comprises generating, by a first clock circuit, a first clock signal in response to a first reset signal and a clock signal. In some embodiments, the method further comprises setting, by an adjustable delay circuit, a delay between the first clock signal and a second clock signal in response to the first clock signal and an enable signal, wherein the second clock signal is a delayed version of the first clock signal, wherein an amount of the delay between the first clock signal and the second clock signal is based on a voltage difference between a first supply voltage having a first variation and a second supply voltage having a second variation.In some embodiments, the method further comprises generating, by a first circuit, a third clock signal in response to the first clock signal and the second clock signal. In some embodiments, the method further comprises generating, by a first inverter, a fourth clock signal in response to the third clock signal, wherein the fourth clock signal is inverted by the third clock signal. In some embodiments, the method further comprises generating, by a pair of inverters, a tracking wordline signal in response to the fourth clock signal.

[0360] The foregoing outlines features of several embodiments so that one skilled in the art can better understand aspects of the present disclosure. One skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same tasks and / or achieve the same advantages of the embodiments presented herein. One skilled in the art should also understand that such equivalent embodiments do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] CN 202310782406.9

[0001]

Claims

[1] Memory circuit, comprising: a word line driver circuit coupled to a word line, and a control circuit coupled to the word line driver circuit and configured to delay a rising edge or a falling edge of a word line signal in response to at least a first clock signal, the control circuit comprising: a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to receive a first supply voltage and a second supply voltage, and configured to set a delay between the second clock signal and a third clock signal in response to the second clock signal and an activation signal, wherein the third clock signal is a delayed version of the second clock signal, wherein an amount of delay between the second clock signal and the third clock signal is based on a voltage difference between the first supply voltage and the second supply voltage, the first supply voltage having a first swing and the second supply voltage having a second swing. [2] A memory circuit according to claim 1, wherein the adjustable delay circuit comprises: a first NAND logic gate configured to generate a first intermediate clock signal in response to the second clock signal and the activation signal, the first NAND logic gate comprising: a first NAND input terminal coupled to an output terminal of the first clock circuit and configured to receive the second clock signal, and a second NAND input terminal configured to receive the activation signal, and a first NAND output terminal configured to output the first intermediate clock signal. [3] The memory circuit of claim 2, wherein the adjustable delay circuit further comprises: a first delay circuit configured to generate a first delayed clock signal in response to the first intermediate clock signal, wherein the first delayed clock signal is delayed with respect to the first intermediate clock signal. [4] The memory circuit of claim 3, wherein the adjustable delay circuit further comprises: a second delay circuit coupled to the first delay circuit and configured to generate the third clock signal in response to the first delayed clock signal, wherein the third clock signal is delayed and inverted with respect to the first delayed clock signal, and the second delay circuit comprises an odd number of inverters coupled in series with each other. [5] A memory circuit according to claim 4, wherein the first delay circuit comprises: a first inverter coupled to a voltage supply of the first supply voltage and configured to generate a second intermediate clock signal in response to the first intermediate clock signal, the second intermediate clock signal being inverted from the first intermediate clock signal, the first inverter comprising: a first input terminal of the first inverter coupled to the first NAND output terminal and configured to receive the first intermediate clock signal, and a first output terminal of the first inverter configured to output the second intermediate clock signal. [6] The memory circuit of claim 5, wherein the first delay circuit further comprises: a second inverter coupled to the voltage supply of the first supply voltage and configured to generate the first delayed clock signal in response to the second intermediate clock signal, wherein the first delayed clock signal is inverted from the second intermediate clock signal, the second inverter comprising: a first input terminal of the second inverter coupled to the first output terminal of the first inverter and configured to receive the second intermediate clock signal, and a first output terminal of the second inverter coupled to the second delay circuit and configured to output the first delayed clock signal. [7] The memory circuit of claim 6, wherein the first delay circuit further comprises: a first N-type transistor comprising: a gate of the first N-type transistor coupled to a voltage supply of the second supply voltage, a drain of the first N-type transistor, and a source of the first N-type transistor coupled to the first output terminal of the first inverter and the first input terminal of the second inverter. [8] The memory circuit of claim 7, wherein the first delay circuit further comprises: a first P-type transistor comprising: a gate of the first P-type transistor coupled to the first output terminal of the second inverter and configured to receive the first delayed clock signal, a source of the first P-type transistor coupled to the voltage supply of the first supply voltage, and a drain of the first P-type transistor coupled to the drain of the first N-type transistor. [9] Memory circuit, comprising: a memory cell array comprising a set of memory cells and a set of tracking cells, a word line driver circuit coupled to the memory cell array, and a control circuit coupled to the word line driver circuit and configured to delay a rising edge or a falling edge of a word line signal in response to at least a first clock signal, the control circuit comprising: a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to receive a first supply voltage and a second supply voltage, and configured to set a delay between the second clock signal and a third clock signal in response to the second clock signal and an activation signal, wherein the third clock signal is a delayed version of the second clock signal, wherein an amount of delay between the second clock signal and the third clock signal is based on a voltage difference between the first supply voltage and the second supply voltage, the first supply voltage having a first variation and the second supply voltage having a second variation. [10] The memory circuit of claim 9, wherein the control circuit further comprises: a NOR logic gate coupled to the adjustable delay circuit and the first clock circuit, the NOR logic gate comprising: a first NOR input terminal coupled to an output terminal of the first clock circuit and configured to receive the second clock signal, and a second NOR input terminal coupled to an output terminal of the adjustable delay circuit and configured to receive the third clock signal, and a first NOR output terminal configured to output a fourth clock signal. [11] The memory circuit of claim 10, wherein the control circuit further comprises: a first inverter configured to generate a fifth clock signal in response to the fourth clock signal, the fifth clock signal being inverted from the fourth clock signal, the first inverter comprising: a first input terminal of the first inverter coupled to the first NOR output terminal and configured to receive the fourth clock signal, and a first output terminal of the first inverter configured to output the fifth clock signal. [12] The memory circuit of claim 11, wherein the control circuit further comprises: a second inverter configured to generate the first clock signal in response to the fifth clock signal, the first clock signal being inverted from the fifth clock signal, the second inverter comprising: a first input terminal of the second inverter coupled to the first output terminal of the first inverter and configured to receive the fifth clock signal, and a first output terminal of the second inverter configured to output the first clock signal. [13] The memory circuit of claim 12, wherein the control circuit further comprises: a NAND logic gate configured to generate a first decoder signal in response to a second decoder signal and the first clock signal, the NAND logic gate comprising: a first NAND input terminal coupled to the output terminal of the second inverter and configured to receive the first clock signal, and a second NAND input terminal configured to receive the second decoder signal, and a first NAND output terminal configured to output the first decoder signal. [14] The memory circuit of claim 13, wherein the control circuit further comprises: a third inverter configured to generate a third decoder signal in response to the first decoder signal, the first decoder signal being inverted with respect to the third decoder signal, the third inverter comprising: a first input terminal of the third inverter coupled to the first NAND output terminal and configured to receive the first decoder signal, and a first output terminal of the third inverter configured to output the third decoder signal. [15] The memory circuit of claim 14, wherein the word line driver circuit comprises: a wordline post-decoder circuit coupled to the third inverter and configured to generate a wordline rail signal in response to the third decoder signal, a fourth inverter coupled between the wordline post-decoder circuit and a wordline and configured to generate the wordline signal in response to the wordline rail signal, and a first P-type transistor comprising: a gate of the first P-type transistor coupled to a tracking wordline and configured to receive a tracking wordline signal, a source of the first P-type transistor coupled to a voltage supply of the second supply voltage, and a drain of the first P-type transistor coupled to a tracking bitline and configured to adjust a tracking bitline signal in response to the tracking wordline signal. [16] A memory circuit according to claim 15, wherein the set of tracking cells comprises: a first N-type transistor comprising: a gate of the first N-type transistor configured to receive a reference voltage of a reference voltage supply, a source of the first N-type transistor configured to receive the reference voltage of the reference voltage supply, and a drain of the first N-type transistor coupled to the tracking bit line, a second N-type transistor comprising: a gate of the second N-type transistor configured to receive the reference voltage of the reference voltage supply, a source of the second N-type transistor configured to receive the reference voltage of the reference voltage supply, and a drain of the second N-type transistor coupled to the tracking bit line, a third N-type transistor comprising: a gate of the third N-type transistor coupled to the tracking word line and configured to receive the tracking word line signal, a source of the third N-type transistor configured to receive the reference voltage of the reference voltage supply, and a drain of the third N-type transistor coupled to the tracking bit line, and a fourth N-type transistor comprising: a gate of the fourth N-type transistor coupled to the tracking wordline and configured to receive the tracking wordline signal, a source of the fourth N-type transistor configured to receive the reference voltage of the reference voltage supply, and a drain of the fourth N-type transistor coupled to the tracking bitline. [17] The memory circuit of claim 16, wherein the control circuit further comprises: a second P-type transistor comprising: a gate of the second P-type transistor coupled to the tracking bit line and configured to receive the tracking bit line signal, a source of the second P-type transistor coupled to a voltage supply of the first supply voltage, and a drain of the second P-type transistor, a third P-type transistor comprising: a gate of the third P-type transistor coupled to the tracking bit line and the gate of the second P-type transistor and configured to receive the tracking bit line signal, a source of the third P-type transistor coupled to the drain of the second P-type transistor, and a drain of the third P-type transistor, a fourth P-transistor comprising: a gate of the fourth P-transistor, a source of the fourth P-transistor coupled to the drain of the second P-transistor and the source of the third P-transistor, and a drain of the fourth P-transistor coupled to the reference voltage supply, and a fifth N-type transistor comprising: a gate of the fifth N-type transistor coupled to the gate of the second P-type transistor, the gate of the third P-type transistor, and the tracking bit line and configured to receive the tracking bit line signal, a source of the fifth N-type transistor coupled to the reference voltage supply, and a drain of the fifth N-type transistor coupled to the drain of the third P-type transistor and the gate of the fourth P-type transistor, wherein the drain of the third P-transistor and the drain of the fifth N-transistor are configured to set a first signal, and the gate of the fourth P-transistor is configured to receive the first signal. [18] The memory circuit of claim 17, wherein the control circuit further comprises: a delay circuit that is connected between the first clock circuit and coupled to the drain of the third P-transistor and the drain of the fifth N-transistor, wherein the delay circuit is configured to delay the first signal, thereby generating the first reset signal, wherein the first reset signal is a delayed version of the first signal. [19] A method of operating a memory circuit, the method comprising: Generating, by a first clock circuit, a first clock signal in response to a first reset signal and a clock signal, Setting, by an adjustable delay circuit, a delay between the first clock signal and a second clock signal in response to the first clock signal and an activation signal, wherein the second clock signal is a delayed version of the first clock signal, wherein an amount of the delay between the first clock signal and the second clock signal is based on a voltage difference between a first supply voltage and a second supply voltage, wherein the first supply voltage has a first fluctuation and the second supply voltage has a second fluctuation, Generating, by a first circuit, a third clock signal in response to the first clock signal and the second clock signal, Generating, by a first inverter, a fourth clock signal in response to the third clock signal, wherein the fourth clock signal is inverted by the third clock signal, and Generating, by a pair of inverters, a tracking word line signal in response to the fourth clock signal. [20] The method of claim 19, wherein adjusting the delay between the first clock signal and the second clock signal comprises: Generating, by a first NAND logic gate, a first intermediate clock signal in response to the first clock signal and the activation signal, Generating, by at least one of a first delay circuit or a second delay circuit, a first delayed clock signal in response to at least the first intermediate clock signal, and Generating, by a third delay circuit, the second clock signal in response to the first delayed clock signal, wherein the second clock signal is delayed and inverted with respect to the first delayed clock signal.

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