Packaging architecture for the realization of superconducting electronic systems

Abstract

Packaging architecture for superconducting systems, featuring a) a dielectric core substrate (0001) with a first surface forming a functional side (B) and an opposing second surface forming a connection side (A), wherein the core substrate (0001) is equipped with a prefabricated internal wiring comprising vertical connections (0002) and horizontal contact layers (0009), b) a passive plane (0100) connected to the first surface of the core substrate (0001), comprising at least one dielectric buffer layer (0101), wherein the buffer layer has a reduced surface roughness compared to the first surface of the core substrate (0001), c) an active layer (0200) connected to the passive layer (0100), which has at least one active superconducting functional layer (0250) from which active superconducting components (0205, 0215) can be extracted, d) at least one conductive vertical connection (0002) between the connection side (A) of the core substrate (0001) and at least one conductive vertical connection (0110) passing through the passive plane (0100), e) at least one contacting element (0006, 0007) arranged on the connection side (A) and connected to the conductive vertical connection (0002) according to feature d) to the next subordinate packaging hierarchy level, characterized in that the dielectric core substrate (0001) is selected from a list of ceramic, glass-ceramic and glassy materials, which includes high-temperature multilayer single-fire ceramics (HTCC), low-temperature multilayer single-fire ceramics (LTCC) and ultra-low-temperature multilayer single-fire ceramics (ULTCC).

Description

Field of invention

[0001] The invention relates to superconducting quantum electronics, which will offer solutions for highly sensitive quantum sensing and efficient quantum computing in the future. Since the superconducting effect, due to its small energy gap, is suitable for the sensitive detection of minute amounts of energy, the invention also enables the efficient integration of photonic transducers such as single-photon detectors into electronic systems. State of the art

[0002] Circuits for quantum sensing and quantum computing include both superconducting components, such as components with qubits for quantum computing, and normal-conducting components, such as normal-conducting circuit carriers. Packaging options for realizing complex electronic circuits at low temperatures feature a hybrid design, meaning that discrete components are mounted on a circuit carrier using interposers and conventional assembly and interconnection techniques like soldering or wire bonding. However, these conventional techniques have limitations, as the use of lossy interconnects like solder joints or wire bonds causes even minute amounts of energy from the utilized quantum effects to be masked by thermal noise, rendering the signals unidentifiable.Low-noise, fault-tolerant, and low-loss interconnection of cryogenic, superconducting components to normal-conducting components and circuits is currently one of the biggest gaps that needs to be closed to realize complex circuits with optimized signal routing. This requires a paradigm shift in circuit architecture, replacing hybrid assembly solutions with heterogeneous system integration. Realizing such heterogeneous systems with a multitude of functional components in a planar monolithic electronic environment is an insurmountable challenge due to material and thermodynamic mismatches between the various elements. The complex signal routing generates parasitic interference fields through interactions, leading to reduced coherence of the quantum components and thus preventing the readout of the system state [1].

[0003] Specifically, the following requirements arise for the practical implementation of heterogeneous systems for superconducting electronics: 1. Operating temperature of 77 K or below 2. Low losses of the dielectric circuit carrier at operating temperature [2], [3] 3. Stable permittivity (low dispersion) across the entire frequency and temperature range 4. Multilayer capability of the dielectric circuit carrier 5. Large-area, 3-dimensional superconducting wiring [4] 6. Feasibility of effective shielding structures 7. Short transmission paths, high integration density

[0004] Cryogenic multi-chip modules based on silicon technology are known as interposers for complex chip assembly, where the interposer is a passive circuit carrier with vertical wiring for connecting two discrete chips. US patent US10381541B2 [5], "Cryogenic electronic packages and assemblies," claims a non-superconducting substrate used for the conventional chip mounting of superconducting components, e.g., by bumps made of low-melting-point specialty solders. The non-superconducting substrate can be an LTCC (low-temperature co-fired ceramic) substrate.Similarly, patents US9836699B1 [6], “Microwave integrated quantum circuits with interposer” and US9971970B1 [7], “Microwave integrated quantum circuits with VIAS and methods for making the same”, claim the use of LTCC multilayer circuit carriers as a reliable package variant for superconducting semiconductor chips in the form of a non-silicon-based interposer (non-Si interposer). This approach corresponds to the prior art technology using ceramic multilayer circuit carriers. Patent US10396269B2 [8], “Assembly of semiconductor interconnect structures for structures including superconducting integrated circuits”, protects vertical contact variants using silicon wafers as typical semiconductor substrates. The patent “Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages” US 10242968B2 [9] protects underbump variants in connection with LTCC substrates, each as 2.Packaging layer for superconducting chips. These two patents thus describe “non-Si interposers” as known from US9971970B1 [7], column 50, lines 9-34 and . Fig. 22, where LTCC is mentioned as a material class for a “non-Si interposer” as a variant.

[0005] All the solutions mentioned above propose an interposer strategy that aims for a high integration density of superconducting electronic components while maintaining CMOS compatibility. However, the interposer only implements the fan-out (i.e., spreading the wiring density) to the next lower packaging hierarchy level. This interposer strategy is frequently used in practice [4],

[10] ,

[11] . Interposers made from single-crystal substrates are not multilayer capable and always require the use of chip assembly techniques. Multilayer technologies such as printed circuit boards or ceramic multilayer circuit carriers have so far always required the assembly of chips that host superconducting electronics on semiconductor substrates made of silicon and sapphire and must be joined using conventional interconnect techniques. For the use of amorphous substrates, such as…Thin glass, methods have been presented in the literature which deposit electronic layers of the required quality using transfer technologies such as exfoliation or chemical lift-off

[12] ,

[13] .

[0006] The use of LTCC substrates for mounting electronic components has so far been limited by the excessively high surface roughness of these substrates. Recent publications in the literature describe the realization of microelectromechanical systems (MEMS) directly on polished LTCC surfaces

[14] . In this application, the surface roughness, which can range from 100 nm to 400 nm due to pores of the sintered material exposed during polishing, is not critical.

[0007] In addition, a packaging architecture for photonic platforms is known from the prior art

[19] , comprising a) a dielectric core substrate in the form of a back-end-of-line (BEOL) with a first, functional-side, top surface of the wafer and an opposing second, interconnection-side, surface in the form of an integrated electronic component in the front-end-of-line (FEOL), wherein the wafer has a front-end-of-line (FEOL) in which the majority of integrated electronic components are arranged and a back-end-of-line (BEOL) above it in which the integrated electronic components of the front-end-of-line are interconnected by means of different metal layers. b) a planarization layer produced on the top surface of the wafer facing away from the front-end-of-line and made of a dielectric material, comprising at least one dielectric buffer layer, wherein the buffer layer has a reduced surface roughness compared to the first surface of the core substrate c) an active layer connected to the passive layer in the form of titanium dioxide (TiO2) deposited over the entire top surface of the obtained planarization layer, which has at least one active superconducting or photonic functional layer from which active superconducting or photonic components can be extracted, d) at least one conductive vertical connection between the connection side of the core substrate and at least one conductive vertical connection passing through the passive plane, e) a metal plane comprising a plurality of connecting elements, which in this case are provided by so-called VIAs, which is the abbreviation for Vertical Interconnect Access, which are formed in the form of front-end-of-lines to the next subordinate packaging hierarchy level.

[0008] The following limitations therefore arise from the current state of the art: 1. Single-crystal interposers are not multilayer capable, so interconnection structures are required between the individual hierarchy levels of the package architecture. These structures are either realized by wire bonding, soldering, or flip-chip bumps, or by using organic polymer layers to build wiring hierarchies. 2. Wire bond connections represent parasitic inductances that degrade the signal-to-noise ratio of the transmission structures between superconducting components and the circuit environment. 3. Solder joints and flip-chip bumps introduce heat that can impair the function of sensitive superconducting electronics and photonic components. 4. Standard silicon and the necessary passivation layers have high dielectric losses, which limits the realization of high-frequency transmission lines and their signal-to-noise ratio. Silicon with high electrical resistance serves as an alternative, but is significantly more expensive. The realization of shielded vertical signal lines using silicon technology is not known. 5. Thermal management at the chip level is not possible because the (usually single-crystal) substrate material has unchanging thermal properties. 6. Alternative materials for interposers (sapphire, aluminum nitride) do not have the technological maturity; corresponding substrates are only available in small sizes and are therefore expensive.

[0009] The applicant was involved in several projects aimed at improving the surface quality of LTCC circuit carriers. The following approaches were pursued: • Improvement of the surface quality of LTCC circuit carriers by coating with colloidal SiO2 precursor

[15] . A surface roughness R was achieved. q of approximately 50 nm is achieved by liquid phase deposition using immersion or spin-on processes. • Direct deposition of polycrystalline III nitrides on LTCC

[16] ,

[17] . • Use of LTCC ceramics after sputtering of AlN, backpolishing and coating of GaN with molecular beam epitaxy (MBE)

[18] .

[0010] These preliminary studies already open up possibilities for the use of LTCC substrates in monolithically integrated systems

[14] , but do not yet allow for the integration of electronic components. The realization of a heterogeneous packaging architecture for superconducting systems using LTCC substrates is prevented by the following disadvantages: 1. The surface roughness R qThe polished ceramic surface renders layers deposited on it using PVD (sputtering) processes unusable for electronic applications. 2. Chemical-mechanical polishing does not reduce surface roughness, as pores in the ceramic material make a significant contribution and PVD layers exhibit growth defects at these pores. 3. Layers can be produced on these PVD layers by molecular beam epitaxy, however, the layer quality is not suitable for superconducting applications requiring high coherence due to the continuation of growth defects. Object of the invention

[0011] The object of the invention is therefore to realize a multilayer packaging architecture for cryogenic, superconducting electronics, which connects active cryoelectronic components (e.g., Josephson transistors or single-photon detectors) to a conventional electronic environment via superconducting contacts with low noise. For this purpose, the packaging architecture is to be provided with a functional side that exhibits the required surface quality, i.e., a surface roughness described by the root mean square of the average amplitude of the surface in the vertical direction, R. qThe packaging architecture has a cross-sectional area of ​​< 5 nm. The use of lossy connection elements, such as solder contacts, flip-chip bumps, or bond wires, on the functional side is to be avoided. Furthermore, it is an object of the invention to equip the packaging architecture with effective thermal management that ensures its operation at operating temperatures of 77 K or below. Finally, it is an object of the invention to provide a method for manufacturing such a packaging architecture that eliminates disadvantageous process steps such as soldering, flip-chip bumps, and wire bonding. Solution to the task

[0012] The object of the invention is achieved by a packaging architecture with the features specified in claim 1. Advantageous embodiments of the packaging architecture are disclosed in dependent claims 2 to 8. Furthermore, the object of the invention is achieved by a method for manufacturing such a packaging architecture according to claim 9. Advantageous embodiments of this method are disclosed in dependent claims 10 to 12.

[0013] The packaging architecture is thus realized through the heterogeneous integration of an electronic circuit on a core substrate, based on a multilayer circuit carrier, utilizing multilayer technologies and multilayer-capable materials that exhibit low dielectric losses. The core substrate is obtained by processing the surface of the multilayer circuit carrier through lapping, polishing, and chemical-mechanical polishing. Subsequently, the surface is further refined by reducing the surface roughness of the core substrate through the application of a passive layer and an active layer comprising high-quality functional layers for active cryoelectronic components. Effective signal shielding and the shielding of external electromagnetic interference can be implemented within one or more layers of the packaging architecture. Detailed description of the solution

[0014] A novel packaging architecture for a cryogenic package is proposed. This architecture utilizes a multilayer circuit carrier, fabricated by sintering multilayer ceramics (HTCC, LTCC, ULTCC) with pre-fabricated internal wiring, to realize superconducting electronic circuits or cryogenic photonic converter circuits with direct contact between the internal wiring of the multilayer circuit carrier and a superconducting circuit. After sintering, the multilayer circuit carrier exhibits an undesirably high thickness variance, typically above 10 µm. Thickness variance is defined as the difference in thickness between the thickest and thinnest points of the multilayer circuit carrier. Lapping and polishing the multilayer circuit carrier produces a core substrate with a thickness variance of 5 µm or less. However, this core substrate still exhibits an excessively high surface roughness (R). a, which is typically above 10 nm. Both parameters cannot be further reduced by methods known from the prior art, such as chemical-mechanical polishing (CMP). The inventive proposal is to reduce the surface roughness of the core substrate by depositing at least one dielectric buffer layer on a functional side of the core substrate. This deposition can be carried out by liquid-phase deposition, nanoimprint lithography, or two-photon polymerization. The deposition of the first dielectric buffer layer enables the deposition of further buffer layers on the functional side to achieve the necessary layer quality for the fabrication of cryoelectronic components. The necessary layer quality is characterized by a surface roughness R q< 5 nm. The buffer layers can have an electrical or optical function. If the first buffer layer does not yet achieve the required surface roughness, further buffer layers are applied using thin-film processes such as CVD, PVD, or ALD until the required surface roughness of R is reached. q < 5 nm is reached. The last deposited buffer layer, i.e., the upper buffer layer, therefore has a surface roughness R q< 5 nm. Due to the pre-fabricated internal wiring in the core substrate, disadvantageous assembly and interconnection steps such as soldering, wire bonding, or flip-chip assembly are eliminated. Highly functional layers for realizing active cryogenic components such as 2D materials or single-crystal metal oxides or heterostructures made of monolayers are deposited in the required quality using transfer technologies such as exfoliation or chemical lift-off and can be reinforced by epitaxy, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). Structuring is achieved either through the transfer process itself or by plasma etching processes such as reactive ion etching (RIE), atomic layer etching (ALE), or by wet chemical processes. Optionally, repolishing by chemical-mechanical polishing is performed to achieve the required surface quality, i.e., a surface roughness R. q< 5 nm, to ensure for further process steps.

[0015] The proposed architecture combines several packaging hierarchy levels of conventional chip assembly within a ceramic, glass-ceramic, or glass-based core substrate with pre-wired internal connections. This enables the complex integration of a cryogenic electronic system with a core substrate featuring pre-wired internal connections. On one side, the substrate offers reliable mounting options for high-frequency transmission lines and / or conventional chips. On the other side, its surface architecture allows for the direct integration of active cryogenic components. The hierarchy levels of the packaging architecture comprise the core substrate, a passive layer, and an active layer.The passive layer comprises a sequence of buffer layers, and the active layer comprises active functional layers and / or active components, as well as other components to ensure their functionality. These layers are interconnected in a heterogeneous system such that the signals from the active cryogenic components are transmitted with minimal loss through all layers to the connection side of the core substrate via vertical and horizontal connections. Effective signal shielding and the protection against external electromagnetic interference are implemented within all layers of the packaging architecture.

[0016] The core substrate can consist of ceramic, glass-ceramic and glassy materials, in particular high-temperature co-fired ceramics (HTCC), low-temperature co-fired ceramics (LTCC), and ultra-low-temperature co-fired ceramics (ULTCC).

[0017] The multilayer circuit carrier is designed as a multilayer ceramic with internal wiring, preferably thick-film wiring (HTCC, LTCC, ULTCC). The core substrate is obtained by lapping and polishing a multilayer circuit carrier. Wiring materials for the multilayer circuit carrier can be conventional thick-film pastes made of Au, Ag, Pt, W, Mo, or their alloys; furthermore, low-temperature pastes such as Al or high-temperature superconductors such as YBa₂Cu₃O₆ can be used. 7-xThe dimensional tolerance of the core substrate is ensured by abrasive processes such as lapping and polishing of the multilayer circuit carrier, which thereby achieves a high degree of parallelism between the interconnect and functional sides. The maximum variance in the thickness of the core substrate (thickness variation) is 5 µm.

[0018] The core substrate can include not only electrical connections and interfaces to conventional (CMOS) logic, but also superconducting RF transmission lines such as coplanar lines or microstrip lines, and their connection to the superconducting electronics. Shielded routing and short signal paths improve the signal-to-noise ratio. The shielded routing can include horizontal shielding elements, such as microstrip lines, and vertical shielding elements, such as via fences. For thermal management, the core substrate can incorporate thermal vias.

[0019] The interconnection side can feature classic assembly and connection elements such as solder bumps, connectors for external cables, connections to heat sinks, connections for flip-chip mounting of semiconductor chips, or the mounting of semiconductor chips by wire bonding. Solder bumps, wire bond connections, and connectors are also collectively referred to as contact elements. These contact elements form interfaces to conventional (CMOS) logic and / or to the next lower level of the packaging hierarchy, e.g., an organic printed circuit board.

[0020] The functional side can include active components, such as superconducting components like Josephson junctions / transistors, shielding structures, photonic elements, and / or superconducting elements, as well as contacts for these elements. The contacts can be implemented as metallizations or high-temperature superconductors.

[0021] The function of the core substrate is to: 1. the realization of complex wiring between the active cryogenic components and other electronic components on the functional side with conventional semiconductor chips, such as amplifier circuits based on high electron mobility transistors (HEMT) or CMOS circuits, and classic contact elements on the interconnection side for connection to the next lower level of the packaging hierarchy, e.g., an organic printed circuit board, 2. the dissipation of heat to ensure the operating temperature, e.g. through thermal vias, 3. the compensation of thermomechanical stresses.

[0022] According to the invention, the required surface roughness R is qThe thickness of the core substrate (< 5 nm) for the fabrication of superconducting electronics and photonics is ensured by creating a layered structure of dielectric materials on the functional side of the core substrate prior to the fabrication of the superconducting electronics / photonics components. This layered structure, which forms the passive layer, comprises a series of dielectric buffer layers deposited on the surface of the functional side of the core substrate using liquid phase deposition, PVD, and / or CVD processes. These buffer layers are then treated with chemical-mechanical polishing (CMP) to refine the surface quality. In addition to surface leveling, the function of these buffer layers includes stress control during the subsequent deposition of the active layer layers and can encompass physical functions such as thermal management, minimization of dielectric losses, and electromagnetic waveguiding.Liquid phase deposition encompasses materials such as inorganic-organic hybrid polymers, water glass layers, and inorganic sol-gel layers produced from precursors based on soluble oxides or alkoxides, glass-forming compounds such as SiO2, TiO2, ZrO2, and hydroxides like boric acid or sodium hydroxide to create inorganic layers with a thickness of approximately 100 nm to several µm. Deposition can be carried out, for example, as dip coating, spin coating, by printing processes, or plasma-enhanced liquid phase deposition. Structured deposition by nanoimprint lithography or two-photon polymerization (2PP) is another deposition option. By applying several buffer layers sequentially, their surface roughness Rg can be adjusted. q , can be gradually reduced. A first buffer layer can have a surface roughness R q < 20 nm, a second buffer layer can provide a surface roughness R q< 10 nm, a third buffer layer can provide a surface roughness R q < 5 nm. In conjunction with shielding elements implemented as microstrip lines, further buffer layers can be deposited, achieving the desired, very low surface roughness R. q < 5 nm is maintained or further reduced. The buffer layer sequence can contain oxide or nitride passivation layers, e.g., based on Si, Al, Ti, Zr, Hf, which are produced by conventional plasma coating processes such as PECVD, PVD, CVD, or ALD. Typical layer thicknesses of the passivation layers are in the range of < 5 µm. The surface quality required for the further development of the active layer is achieved by CMP processes. Both the outer passivation layer itself and a superconducting layer (in the operating range T < 77 K) such as Nb or TiN can be treated to achieve the required surface quality R. q < 5 nm can be polished.

[0023] Vertical electrical contact between the core substrate wiring and the passive and active layers is achieved through vertical openings (vias) in the dielectric buffer layers and passivation layers. This is accomplished using conventional gas-phase etching processes such as reactive ion etching (RIE), deep reactive etching (DRIE), or atomic layer etching (ALE), or wet chemical etching processes. The coating for creating the electrical contact is achieved by depositing suitable layer sequences (metallic or superconducting). Possible methods include conventional plasma deposition processes such as PECVD, PVD, CVD, or ALD, as well as masked and / or direct-printing processes for high-resolution thick-film inks.

[0024] The connection to the next lower level of the packaging hierarchy is made via RF-compatible connecting elements (e.g. coaxial SMD connectors), via flip-chip assembly or other compatible interfaces on the connection side.

[0025] The key feature of the packaging architecture according to the invention, suitable for cryogenic applications, is the realization of complex wiring of active superconducting functional elements prior to the deposition and structuring of the necessary conductor traces, active functional layers, and passivation layers. This avoids temperature stress on the critical elements caused by packaging steps. The architecture thus enables the realization of complex structures and targeted thermal management. Functionally, the solution shortens signal paths and minimizes parasitic influences that can lead to loss of coherence. Furthermore, the CMP steps required for high complexity after processing of the active superconducting components are minimized, thereby increasing the reliability of complex circuits.

[0026] The inventive method for manufacturing the packaging architecture thus utilizes multilayer technology to produce a multilayer circuit carrier that already incorporates complex wiring. The multilayer circuit carrier is transformed into a core substrate with the required dimensional tolerance by lapping and polishing. The novelty lies in the combination of using multilayer ceramics (HTCC, LTCC, ULTCC), which on the one hand possess necessary functional properties such as low dielectric losses and stability in vacuum processes, and on the other hand, which, through a surface architecture based on a sequence of buffer layers produced by a combination of liquid-phase deposition with plasma processes as well as transfer techniques (exfoliation, chemical lift-off) and polishing steps, ensure the required surface quality for the heterogeneous integration of superconducting / photonic functional layers.The buffer layers continue to ensure minimal dielectric losses. Passivation layers prevent the diffusion of highly mobile ions into the active layer. The three packaging hierarchy levels are interconnected by direct electrically conductive or superconducting contacts, without the use of typical chip assembly techniques such as wire bonding, soldering, or flip-chip assembly. Advantages of the invention 1. The packaging architecture offers short signal paths and the possibility of integrating structures for signal shielding in the horizontal direction, e.g. by microstrip lines, and in the vertical direction, e.g. by via fences, at all hierarchy levels. 2. Direct contact between active cryogenic components and the electrical connections on a circuit carrier reduces signal propagation times and increases transmission quality. 3. Effective thermal management is made possible by thermal vias. 4. Implementation of structures for effective shielding of electromagnetic interference fields is possible at all hierarchy levels. 5. Targeted variation of dielectric properties and minimization of dielectric losses through the available variety of materials in ceramic multilayer circuits.

[0027] The invention is described in more detail below by means of an exemplary embodiment with reference to the drawings. Description of the drawings Fig. Figure 1a shows a cross-section of the packaging architecture, comprising a core substrate 0001 to which external peripheral elements (chips 0004, 0005, connectors / HF connectors 0006) are attached, a passive layer 0100 and an active layer 0200 for connecting (not shown) superconducting and / or photonic elements. Fig. Figure 1b shows a cross-section of the core substrate 0001 with prefabricated internal wiring, comprising vertical connections 0002 and buried horizontal contact layers 0009, prefabricated thermal vias 0003 and a prefabricated cavity 0013 for chip mounting. Fig. Figure 2a shows an enlarged cross-section of a detailed view of the passive layer 0100 deposited on the core substrate 0001, comprising a sequence of buffer layers 0101, 0102, 0103, wherein the buffer layers 0102 and 0103 can additionally function as passivation layers. The layer sequence further includes a conductive layer 0104, which is connected via a vertical conductive connection 0110 to the internal wiring, comprising vertical connections 0002 and horizontal contact layers 0009 of the core substrate 0001. The Fig. 2b, Fig. 2c and Fig. Figure 2d shows further detailed representations of the passive layer 0100 arranged on the core substrate 0001: Fig. 2b shows the passive layer 0100, equipped with horizontal conductive elements for the signal line 0105 and for the signal shielding 0106. Fig. 2c shows the passive plane 0100 according to Fig. 2b, additionally equipped with a buried horizontal signal shielding element 0106a between buffer layers 0102 and 0103. The central, grey-shown vertical signal feedthrough 0110a contacts the signal line 0105 and has no contact with the buried signal shield 0106a. Fig. Figure 2d shows the passive plane 0100 according to Fig. 2c, wherein the buffer layer 0103 is implemented as a sequence of buffer layers 103-1, ..., 103-n. The arrangement may include further buried elements, including a structure 0107 for shielding against electromagnetic interference fields. The Fig. Figures 3a, b and c show enlarged cross-sections of detailed representations of the active plane 0200 connected to the passive plane 0100: Fig. Figure 3a shows the functional layer 0250 required for an active element, whereby the necessary contacts for its operation are realized by vias in the form of vertical connections 0110 or horizontal contacts in the form of conductive layers 0104 of the passive layer 0100. The functional layer 0250 can, for example, be a tunnel barrier such as Al x O y , a heterostructure made of 2D materials or a photonically active layer such as WSi. In the simplest case, the functional layer can be contacted via the vertical connections 0110 to ensure functionality. Fig. Figure 3b shows, as an example for a superconducting application, a Josephson transistor 0205 positioned and contacted on the dielectric 0201. Fig. Figure 3c shows, as an example of a photonic application, a single-photon detector 0215 positioned and contacted on the dielectric 0211, e.g., Si3N4. The active element consists of a functional layer and the necessary contacts for its operation. The functional layer can, for example, be a tunnel barrier such as Al x O y , a heterostructure made of 2D materials or a photonically active layer such as WSi. In the simplest case, the functional layer can be contacted via the vertical vias 0110, 0110a for functional assurance. The arrangement can include optical functional layers 0214, e.g., for reflection. Example of implementation

[0028] A schematic representation of the cross-section of the overall structure of an embodiment of the packaging architecture according to the invention, comprising the core substrate 0001, the passive layer 0100 and the active layer 0200, shows Fig. 1a. Core substrate 0001

[0029] The core substrate 0001 ( Fig.1b) is based on a multilayer circuit carrier made of a ceramic sintered material, in this case a low-temperature single-firing ceramic (LTCC), with internal wiring based on a printed thick-film metallization of silver. This multilayer circuit carrier is manufactured by co-sintering a multilayer ceramic with conductor tracks and printed pastes for thermal vias 0003, vertical feedthroughs 0002, and buried horizontal contact layers 0009. It contains buried transmission elements for shielded signal transmission, in this case microstrip lines 0008. The process technology is known as LTCC technology. Since the conductor routing depends on the specific application circuit, the design and fabrication of the multilayer circuit carrier is part of the manufacturing process for realizing the package. After sintering, the multilayer circuit carrier can still have a high dimensional deviation of 10 µm to 100 µm.Lapping and polishing reduce this shape deviation to achieve a maximum thickness variance of 5 µm. This creates the core substrate 0001, which, due to its achieved shape tolerance, can be further processed with typical thin-film equipment. The shape tolerance of the core substrate 0001 encompasses its thickness variance as well as the parallelism of its connection side A and functional side B. The polishing process establishes the required surface quality on the functional side B. For processing the core substrate 0001 in thin-film systems, a maximum thickness variance of 5 µm and a high surface quality, characterized by a surface roughness R, are required. q < 500 nm on functional side B is necessary.

[0030] The core substrate 0001 has a connection side A to the external periphery and a functional side B for the assembly of the superconducting electronics. Connection side A contains a cavity 0013 for chip mounting. On connection side A, conventional assembly and connection elements such as solder bumps 0007, connectors for external cables 0006, connections to heat sinks 0012, for flip-chip mounting 0005, or for mounting semiconductor chips by wire bonding 0004 are implemented. Connection side A requires no further surface treatment. In contrast, functional side B of the core substrate 0001 is not yet suitable for the assembly of active cryogenic components because it exhibits excessive surface roughness after polishing. Functional side B therefore requires surface refinement to reduce its surface roughness.According to the invention, this surface refinement is achieved by applying a passive layer 0100 to the functional side B. The connection of the active layer 0200 to the core substrate 0001 is effected by the realization of interconnected vertical vias 0110, 0110a and 0202 through these two layers 0100, 0200 and horizontal conductive layers 0104, 0105, 0106, which enable signal transmission between active components on the active layer 0200 and the core substrate 0001. Passive level 0100

[0031] The passive level 0100 has the following functions: 1. To even out the surface roughness after polishing the core substrate 0001 and to produce the required nanoscale surface quality for the active layer 0200. 2. To ensure the contacting of the active layer 0200 with the core substrate 0001 by means of vertical connections 0110. 3. To provide optimal crystallographic starting conditions for the growth of electronic functional layers 0250. 4. To ensure optimal surface properties for the transfer of 2D materials, functional layers or starter layers for controlled growth.

[0032] The passive layer 0100 consists of at least one buffer layer 0101, which facilitates the gradual adaptation of the functional layer B to the conditions necessary for processing the active layer 0200. Further buffer layers 0102, ..., 0103 are possible. The first buffer layer 0101 consists of the dielectric SiO2:MTMS, an inorganic-organic hybrid polymer, which is applied to the core substrate 0001 by dip coating. SiO2:MTMS is a layer based on an inorganic-organic hybrid solution of colloidal SiO2 and the silicon alkoxide compound methyltrimethoxysilane (MTMS). The required functional properties are achieved through a annealing step. The temperature for this step can range from 200°C to 500°C, and the residence time from 10 minutes to 2 hours. This first buffer layer 0101 has a thickness of 2 µm and serves to reduce the surface roughness of the core substrate 0001 after polishing.Before applying the second buffer layer 0102, this first buffer layer 0101 is processed by chemical-mechanical polishing to achieve a surface roughness R. q , of 20 nm. The second buffer layer 0102, with a thickness of up to 3 µm, consists of another dielectric, which in this embodiment is applied by plasma deposition. It serves to compensate for defects in the first buffer layer 0101 and can also be processed by chemical-mechanical polishing. The surface roughness R qis 10 nm or smaller. The buffer layer 0102 consists of SiO2 and forms the transition to the third buffer layer 0103. This layer consists of Si3N4 and serves to further improve the surface quality, as a diffusion barrier, and to provide optimal conditions for the application of the next functional layers for horizontal contacts in the form of conductive layers 0104, 0105, and 0106, which in this example consist of Nb. The layer thickness is between 100 nm and 3 µm. Treatment by chemical-mechanical polishing increases the surface quality. The surface roughness R qis 5 nm or smaller. The vertical connections 0110 between the active layer 0200 and the core substrate 0001 are created by reactive ion etching (RIE) of the buffer layers 0101, ..., 0103 and subsequent metallization with Nb by sputtering. Within the passive layer 0100, signal transmission structures, such as microstrip lines, comprising signal shielding structures 0106 and signal transmission structures 0105, can be arranged by constructing additional dielectric buffer layers 0103-1, ..., 0103-n and conductive layers 0105 and 0106. Furthermore, functional structures for shielding electromagnetic interference fields 0107, so-called moats and / or metamaterials, can be implemented in the passive layer 0100. The buffer layers 0102 and 0103-1, ..., 0103-n can additionally perform the function of a passivation layer.The surface quality of the upper buffer layer in contact with the active layer 0200 can be refined by chemical-mechanical polishing, so that the surface roughness R. q 5 nm or less. Active level 0200

[0033] The active layer 0200 implements the actual function of the active components, e.g., a Josephson transistor 0205 or a single-photon detector 0215. To realize the active components, active functional layers 0250 are applied, which implement the actual electronic (e.g., tunnel barrier) or photonic (e.g., photon detection) function. The active layer can include a further dielectric 0201, e.g., niobium pentoxide Nb₂O₅, which is deposited by PVD. Vertical contacts through the dielectric 0202 are created, e.g., by lifting off the dielectric and subsequently coating it with a contact layer, e.g., niobium, by sputtering. The functional layer 0250 can be partially removed, leaving only the active component or multiple active components exposed. The active component is connected via signal contacts under 0204 and signal contacts on 0203 of the active component 0205 or 0215, which, for example,The active functional layer can be applied by sputtering niobium and / or aluminum, and contacted via contacts for signal shielding 0206. Furthermore, functional structures for shielding electromagnetic interference fields 0207, e.g., by sputtering niobium, can be integrated at this level. In the case of the Josephson transistor 0205, the active functional layer is formed by PVD deposition of aluminum onto niobium layers and subsequent oxidation of the aluminum to Al. x O y manufactured. The single-photon detector 0215 can be realized by exfoliation of active functional layers consisting of 2D materials, e.g. MoS2. Cited literature [1] S. Anders et al., “European roadmap on superconductive electronics - status and perspectives,” Physica C: Superconductivity, vol. 470, 23-24, pp. 2079-2126, 2010, doi: 10.1016 / j.physc.2010.07.005. [2] P. Magnard et al., „Microwave Quantum Link between Superconducting Circuits Housed in Spatially Separated Cryogenic Systems,“ Physical review letters, vol. 125, no. 26, p. 260502, 2020, doi: 10.1103 / PhysRevLett.125.260502. [3] C. R. H. McRae et al., „Materials loss measurements using superconducting microwave resonators,“ The Review of scientific instruments, vol. 91, no. 9, p. 91101, 2020, doi: 10.1063 / 5.0017378. [4] T. Brecht et al., „Multilayer microwave integrated quantum circuits for scalable quantum computing,“ npj Quantum Inf, vol. 2, no. 1, 2016, doi: 10.1038 / npjqi.2016.2. [5] R. Das, „Cryogenic electronic packages and methods for fabricating cryogenic electronic packages,“ US10381541B2. [6] Rigetti et al., „Microwave integrated quantum circuits with interposer“, US9836699B1 [7] Rigetti Chad T. and M. Vahidpour, „Microwave integrated quantum circuits with VIAS and methods for making the same“, US11121301B1. [8] Oliver et.al., „Assembly of semiconductor interconnect structures for structures including superconducting integrated circuits“, US10396269B2 [9] Rabindra et al., „Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages“, US10242968B2

[10] J. A. Alfaro-Barrantes et al., „Superconducting High-Aspect Ratio Through-Silicon Vias with DC-Sputtered Al for Quantum 3D integration,“ IEEE Electron Device Lett., p. 1, 2020, doi: 10.1109 / LED.2020.2994862.

[11] C Thomas et al., „Superconducting routing platform for large-scale integration of quantum technologies,“ Materials for Quantum Technology, vol. 2, no. 3, p. 35001, 2022, doi: 10.1088 / 2633-4356 / ac88ae.

[12] K. M. Cheung et al., „Chemical Lift-Off Lithography of Metal and Semiconductor Surfaces,“ ACS materials letters, vol. 2, no. 1, pp. 76-83, 2020, doi: 10.1021 / acsmaterialslett.9b00438.

[13] H. S. Kum et al., „Heterogeneous integration of single-crystalline complex-oxide membranes,“ Nature, vol. 578, no. 7793, pp. 75-81, 2020, doi: 10.1038 / s41586-020-1939- z.

[14] E. Fallahnia and A. B. Kouki, „A Monolithic LTCC-MEMS Microfabrication Process,“ J. Microelectromech. Syst., vol. 32, no. 6, pp. 612-621, 2023, doi: 10.1109 / JMEMS.2023.3310932.

[15] H. Bartsch, U. Brokmann, B. Goj, R. Weiss, E. Rädlein, and J. Müller, „Sol gel thin films on LTCC ceramic multilayers enable their use as thin film substrates,“ in 2015 European Microelectronics Packaging Conference (EMPC): Date: 14-16 Sept. 2015, 2015, pp. 1-6.

[16] J. M. Manuel et al., „Engineering of III-Nitride Semiconductors on Low Temperature Co-fired Ceramics,“ Scientific reports, vol. 8, no. 1, p. 6879, 2018, doi: 10.1038 / s41598-018-25416-6.

[17] J. J. Jiménez et al., „Comprehensive (S)TEM characterization of polycrystalline GaN / AIN layers grown on LTCC substrates,“ Ceramics International, vol. 45, no. 7, pp. 9114-9125, 2019, doi: 10.1016 / j.ceramint.2019.01.250.

[18] H. Bartsch et al., „LTCC as substrate - enabling semiconductor and packaging integration,“ in 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC), 2019, pp. 1-4.

[19] DE 10 2020 102 534 A1

Claims

[1] Packaging architecture for superconducting systems, featuring a) a dielectric core substrate (0001) with a first surface forming a functional side (B) and an opposing second surface forming a connection side (A), wherein the core substrate (0001) is equipped with a prefabricated internal wiring comprising vertical connections (0002) and horizontal contact layers (0009), b) a passive plane (0100) connected to the first surface of the core substrate (0001), comprising at least one dielectric buffer layer (0101), wherein the buffer layer has a reduced surface roughness compared to the first surface of the core substrate (0001), c) an active layer (0200) connected to the passive layer (0100), which has at least one active superconducting functional layer (0250) from which active superconducting components (0205, 0215) can be extracted, d) at least one conductive vertical connection (0002) between the connection side (A) of the core substrate (0001) and at least one conductive vertical connection (0110) passing through the passive plane (0100), e) at least one contacting element (0006, 0007) arranged on the connection side (A) and connected to the conductive vertical connection (0002) according to feature d) to the next subordinate packaging hierarchy level characterized by , that the dielectric core substrate (0001) is selected from a list of ceramic, glass-ceramic and vitreous materials, which includes high-temperature multilayer single-firing ceramics (HTCC), low-temperature multilayer single-firing ceramics (LTCC) and ultra-low-temperature multilayer single-firing ceramics (ULTCC). [2] Packaging architecture according to claim 1, characterized by , that the core substrate (0001) contains thermal vias (0003) and / or shielding structures (0008). [3] Packaging architecture according to claim 1 or 2, characterized by , that the elements arranged on the connection side (A) include normally conductive elements such as CMOS chips, passive components and / or connecting elements to the next lower packaging hierarchy level such as solder bumps or connectors. [4] Packaging architecture according to one of claims 1 to 3, characterized by , that the core substrate (0001) has a thickness variance < 5 µm and is therefore suitable for thin-film processing as is common in electronics manufacturing. [5] Packaging architecture according to one of claims 1 to 4, characterized by , that the conductive vertical connections (0200, 0110) consist of materials that are superconducting or non-superconducting at an operating temperature of 77 K or below. [6] Packaging architecture according to one of claims 1 to 5, characterized by, that the passive plane (0100) is formed as a sequence of planarly interconnected dielectric buffer layers (0101, 0102, 0103-1, ..., 0103-n), wherein the upper buffer layer has a surface roughness R q < 5 nm, with the individual buffer layers being the materials SiO2:MTMS, SiO x C y H z , TiO x , SiO2, AlN, AlN x O y , SiO x N y , Si3N4, TiO2, ZrO2, or Al2O3, with the thickness of the individual buffer layers ranging from a few hundred nm to a few micrometers. [7] Packaging architecture according to one of claims 1 to 6, characterized by, that at least one active superconducting functional layer (0250) arranged in the active plane is connected to at least one vertical connection (0110) passing through the passive plane (0100) and / or at least one horizontal connection (0104) in the passive plane (0100), such that at least one electrical contact between the active superconducting layer (0250) and at least one contacting element (0006, 0007) is ensured. [8] Packaging architecture according to one of claims 1 to 7, characterized by, that the active superconducting components (0205, 0215) arranged in the active layer (0200) comprise superconducting elements such as Josephson junctions (0205) machined from the functional layer (0250) and connected via at least one vertical connection (0202) passing through the active layer (0200) and / or horizontal connections (0203, 0204) to at least one vertical connection (0110) passing through the passive layer (0100) and / or at least one horizontal connection (0104) in the passive layer (0100). [9] Method for manufacturing a packaging architecture according to any one of claims 1 to 8, comprising at least the following process steps: a) Production of a multilayer circuit carrier suitable for realizing superconducting circuits with low dielectric losses and pre-fabricated internal wiring, b) Lapping and polishing of the multilayer circuit carrier to obtain a core substrate (0001) with the necessary dimensional tolerance and surface quality for processing in thin-film systems, c) Formation of a passive layer (0100) by depositing at least one buffer layer on the functional side (B) of the core substrate (0001) by liquid phase deposition, PVD and / or CVD processes for the purpose of reducing the surface roughness of the functional side (B) of the core substrate (0001) and chemical-mechanical polishing for the purpose of reducing the surface roughness of the functional side (B), d) Production of vertical connections (0110) through the passive plane (0100) by generating vertical openings in the same by microtechnological processes such as UV lithography, nanoimprint lithography, lift-off, plasma etching or wet chemical processes and deposition of contact layers by PVD and / or CVD and / or electrochemical processes, e) Application of at least one active superconducting functional layer (0250) by means of transfers through exfoliation and / or ALD, PVD, CVD processes, which is suitable for realizing active superconducting components (0205). [10] Method for producing a packaging architecture according to claim 9, comprising the following optional process steps: Deposition of a superconducting and / or non-superconducting conductive layer (0104) in the working area onto one of the buffer layers (0101, 0102, 0103) following process step c), structuring of the conductive layer (0104) by microtechnological processes such as lift-off, plasma etching or wet chemical processes, sequential deposition of further dielectric buffer layers (0103-1, ..., 0103-n-1), fabrication of vertical vias (0110) by the same analogous to process step d), deposition of superconducting and / or non-superconducting conductive layers (0104, 0105, 0107) in the working area, structuring of the same by microtechnological processes such as lift-off, plasma etching or wet chemical processes, deposition of an upper buffer layer (0103-n) and an optional superconducting and / or non-superconducting conducting layer (0106). [11] Method for manufacturing a packaging architecture according to one of claims 9 or 10, comprising the following optional process steps: Chemical-mechanical polishing of buffer layers of the passive plane (0100) and / or the optionally applied superconducting and / or non-superconducting conduction layers (0105, 0106) to produce a surface roughness R q of 5 nm or less. [12] Method for manufacturing a packaging architecture according to one of claims 9, 10 or 11, comprising the following further method steps: a) Deposition of a photonically functional dielectric (0211) or a dielectric with low dielectric losses (0201) on the upper buffer layer of the passive plane (0100) by means of transfers by exfoliation and / or ALD, PVD, CVD processes, b) Forming vertical connections (0202) and / or horizontal layers for contacting (0204) and signal shielding (0206, 0207) by structuring the dielectric (0201, 0211) by microtechnological processes such as lift-off, plasma etching or wet chemical processes and subsequent deposition of a conducting layer (0203) that is superconducting and / or non-superconducting at operating temperature, structuring the same by microtechnological processes such as lift-off, plasma etching or wet chemical processes, c) Production of optical functional layers (0214) by means of transfers through exfoliation and / or ALD, PVD, CVD processes, and / or optional structuring thereof by microtechnological processes such as lift-off, plasma etching or wet chemical processes to form active superconducting components (0205), d) Deposition of active functional layers (0250), comprising superconducting single layers and layer sequences by means of transfers by exfoliation and / or ALD, PVD, CVD processes, and / or optional structuring thereof by microtechnological processes such as lift-off, plasma etching or wet chemical processes, e) Deposition of a superconducting and / or non-superconducting conduction layer (0203) at operating temperature to realize contacts between the top surface of the active superconducting components (0205) and horizontal (0206, 0207) and / or vertical (0202) connections.

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