THERMISTOR WITH INTEGRATED BIAS RESISTOR

Abstract

An electronic device comprising a thermistor and a bias reference resistor in a voltage divider configuration integrated into a single die, and a method for fabricating the same. In one example, the electronic device comprises a substrate including an n-well region, a thermistor formed in the n-well region, and a bias resistor connected in series with the thermistor, the bias resistor being formed in a region of the substrate isolated from the n-well region.

Description

AREA OF REVELATION

[0001] Disclosed implementations generally relate to the field of semiconductor devices and manufacturing. In particular, but not exclusively, the disclosed implementations relate to an IC device having an integrated thermistor and a bias resistor in a voltage divider configuration. BACKGROUND

[0002] Thermistors are temperature-sensing components that have a resistance configured to change with temperature, for example, with a high temperature coefficient of resistance (TCR) over a suitable range. Thermistors are sometimes used in voltage divider circuits with a bias reference resistor whose resistance does not change (or changes very little) with respect to temperature within an operating range, thus demonstrating a low or zero TCR. Thermistors and reference resistors are often manufactured as blocks of a ceramic material or blocks of silicon, provided as separate, discrete components on a printed circuit board, requiring additional space for sourcing and assembling two separate products. SUMMARY

[0003] A simplified summary is presented below to provide a basic understanding of some examples of the present disclosure. This summary is not a comprehensive overview of the examples and is not intended to identify key or critical elements of the examples, nor to delimit the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the present disclosure in a simplified form as a prelude to a more detailed description presented in subsequent sections below.

[0004] In one example, an electronic device is disclosed that includes a thermistor and a bias reference resistor in a voltage divider configuration integrated into a single die. In a representative implementation, the electronic device may comprise a substrate including an n-well region, a thermistor formed in the n-well region, and a bias reference resistor connected in series with the thermistor, wherein the bias reference resistor is formed in a region of the substrate that is isolated from the n-well region, e.g., either laterally, horizontally, and / or vertically. In one arrangement, the thermistor may comprise a well resistor in the n-well region doped with suitable dopants to provide a high TCR.In one arrangement, the bias reference resistor may comprise a polysilicon resistor doped with boron to provide a low TCR or zero TCR. In one arrangement, the series-coupled thermistor and bias reference resistor may be disposed between a first voltage rail and a second voltage rail. In another example, a method of fabricating an integrated thermistor and a bias reference resistor in the same process flow is disclosed, wherein the thermistor and / or the bias reference resistor may be independently tuned to achieve appropriate respective target resistance values. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Implementations of the present disclosure are illustrated in the figures of the accompanying drawings by way of example and not limitation. It should be noted that various references to "a" implementation throughout this disclosure are not necessarily to the same implementation, and such references may mean at least one. Furthermore, where a particular feature, structure, or characteristic is described in connection with one implementation, it is understood that it is within the skill of one of ordinary skill in the art to effect such feature, structure, or characteristic in connection with other implementations, whether explicitly described or not.

[0006] The accompanying drawings are incorporated in and constitute a part of the specification to illustrate one or more implementation examples of the present disclosure. Various advantages and features of the disclosure will become apparent from the following detailed description, taken in conjunction with the appended claims and with reference to the accompanying drawings of the figures, in which: Fig. 1 illustrates the layout of an electronic device including a thermistor integrated with a bias resistor, according to some examples; Fig. Figure 2 is a circuit diagram of a voltage divider included in the electronic device Fig. 1, according to some examples; Fig. 3A-3N illustrate cross-sectional views of a partially formed semiconductor device at various manufacturing stages for fabricating a thermistor coupled to a bias resistor in an integrated process flow, according to some examples; Fig. 4A and Fig. 4B illustrates example potentiometer schemes for tuning a thermistor and / or a bias resistor based on respective fuse codes to achieve appropriate resistance characteristics according to some examples; Fig. 5A and Fig. 5B illustrates a flowchart of a method of manufacturing an electronic device including an integrated thermistor with a bias resistor, according to some examples of the present disclosure; and Fig. 6 illustrates a cross-sectional view of an electronic device in which an integrated thermistor and bias resistor are vertically oriented relative to each other, according to another example of the present disclosure. DETAILED DESCRIPTION

[0007] Examples of the disclosure are described with reference to the attached figures, where like reference numerals are used generally to refer to like elements. The figures are not drawn to scale and are provided merely to illustrate examples. Numerous specific details, relationships, and techniques are set forth below in order to provide an understanding of one or more examples. However, it should be understood that some examples may be practiced without such specific details. In other instances, well-known subsystems, components, structures, and techniques have not been shown in detail in order not to obscure the understanding of the examples. Accordingly, one skilled in the art will understand that the examples of the present disclosure may be practiced without such specific components.

[0008] Additionally, terms such as "coupled" and "connected," along with their derivatives, may be used in the following description, the claims, or both. It should be understood that these terms are not necessarily intended to be synonyms for one another. "Coupled" may be used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, cooperate or interact with each other. "Connected" may be used to indicate the establishment of communication, that is, a communicative relationship, between two or more elements that are coupled together. "Directly connected" may be used to convey that two or more physical features touch or share an interface between each other.

[0009] Various examples involve the integration of a reference resistor and a thermistor over a single semiconductor substrate or die. Such integration has been difficult to achieve, at least due to the disparate materials required for the resistor and thermistor and their different processing requirements, e.g., conflicting thermal budget limits. While such examples provide materials and processes that advantageously allow such integration, no particular result is required unless explicitly stated in a particular claim.

[0010] Fig. 1 illustrates an electronic device 100, also referred to herein as an integrated circuit (IC) device, including a thermistor 102 coupled to a bias resistor 104 in a voltage divider arrangement, where the thermistor 102 and the bias resistor 104 may be integrated into a single semiconductor die according to an example process flow detailed below. In one implementation, the electronic device 100 may comprise a 3-terminal die having, for example, pads 106-1 to 106-3, where an electrostatic discharge (ESD) protection diode 114 may optionally be provided in association with a pad, for example, pad 106-1. Depending on an implementation, the electronic device 100 may have a die size, for example, 10 mm. B. approximately 300 µm by 500 µm, but not limited to this.Although the bias resistor 104, also referred to as a reference resistor, and the thermistor 102 are each shown in this figure as having generally rectangular shapes, each with corresponding length and width dimensions, the electronic device 100 may include a reference / bias resistor and a thermistor having other shapes integrated into a voltage divider circuit formed on a single die in additional and / or alternative arrangements. Furthermore, in some additional and / or alternative arrangements, the thermistor 102 and the bias resistor 104 may each comprise a multi-segment component. Regardless of the implementation, the thermistor 102 is operable as a "high" TCR component and the bias resistor 104 is operable as a "low" or zero TCR component, wherein, according to the illustrated examples, each component can be independently and individually trimmed (e.g.,in fine-tuning and / or coarse-tuning operations) in an integrated voltage divider configuration that can be used in a wide variety of applications.

[0011] In one arrangement, the thermistor 102 may comprise a high-TCR component with a positive resistance coefficient of approximately 6000 ppm / °C with a tolerance of 0.2% over a suitable temperature range, for example, -40°C to +150°C, wherein a nominal resistance of approximately 10 kΩ at room temperature (~25°C) may be provided by appropriate doping (and trimming, if necessary) during manufacturing, as set forth below. In one arrangement, the bias resistor 104 may comprise a low-TCR component with a resistance coefficient in a range of ± 100 ppm / °C, with a resistance value equal to the nominal resistance of the thermistor 102, for example, 10 kΩ at room temperature, which may be achieved in the same manufacturing flow using a separate doping process (and trimming, if necessary) with respect to forming a polysilicon resistor body.In one implementation example where thermistor 102 and bias resistor 104 each comprise a resistive component with a target resistance of 10 kΩ at room temperature, the resistive components may be fabricated as rectangular structures having a width of approximately 20-25 µm and a length of approximately 65-75 µm, although other dimensions, sizes, shapes, or form factors may be used in additional and / or alternative arrangements without limitation. Furthermore, thermistor 102 and bias resistor 104 may be oriented in a variety of configurations relative to each other and / or to an orientation of electronic device 100.

[0012] In one implementation example, the tunable thermistor 102 may be provided with a first terminal region 103A having a first plurality of contact lines 105A, each comprising a respective one of fuse links 107A, e.g., arranged in a fuse bank, for enabling selective coupling to a pad, e.g., pad 106-2. Similarly, a second terminal region 103B of the tunable thermistor 102 may also be provided with a second plurality of contact lines 105B, each comprising a respective one of fuse links 107B, e.g., arranged in a fuse bank, for enabling selective coupling to a pad, e.g., pad 106-3. In some arrangements, the first plurality of contact lines 105A and second plurality of contact lines 105B may comprise an equal number of lines, although this is not a requirement.Furthermore, in some arrangements, either the first terminal region 103A or the second terminal region 103B may comprise only a single contact line operable to connect to a respective pad, e.g., without a fuse link disposed therebetween. As will be seen further below, the individual contact lines of respective multiple contact lines 105A and / or 105B may be positioned apart from each other with predetermined spacings placed therebetween during manufacturing to enable a potentiometer-like resistance lead sequence between the terminal regions 103A / 103B of the thermistor 102.In some arrangements, the resistance ladder sequence associated with the thermistor 102 at a terminal region 103A / 103B may be trimmed to effect fine and / or coarse tuning operations related to setting and / or achieving a target resistance value of the thermistor 102 by selectively activating and deactivating appropriate fuse links relative to respective terminal regions 103A / 103B.

[0013] As in the illustrated example from Fig. 1, the contact leads 105A are relatively closely spaced and the contact leads 105B are relatively widely spaced. Each contact lead of the respective grouping can be connected to a first or a second pad, e.g., pad 106-2 and pad 106-3, via a corresponding one of the fuse links 107A and 107B. The total resistance provided by the thermistor 102 can be adjusted or "trimmed" by selectively severing the connection of a subset of the contact leads to the corresponding pads 106-2 / 106-3, for example, by opening, or "blowing" a subset of the fuses of respective fuse links 107A, 107B, while maintaining only one fuse lead in a closed state.Accordingly, the thermistor 102 is operable as a potentiometer because the effective length of the thermistor 102 is modulated by the trimming process due to the additive properties of the additional resistor segments at the terminal regions added to the main resistor body. It will be appreciated that the trimming increment is larger for the contact lines with wider spacings and smaller for the relatively closer connection lines. Thus, the more widely spaced contact lines provide coarse trimming or tuning, and the more closely spaced contact lines provide fine trimming or tuning. In some arrangements, an objective of the trimming process may include establishing a resistance value of the thermistor 102 that is close to a predetermined value, e.g., a design value corresponding to an integrated voltage divider application, wherein a bias resistor, e.g.,the bias resistor 104, is formed in the same manufacturing flow and integrated with the thermistor 102 on the same die, wherein the bias resistor, similar to the thermistor 102, is also independently tunable.

[0014] At the Fig. In the exemplary integrated thermistor-resistor configuration shown in FIG. 1, the bias resistor 104, having terminal regions 109A and 109B, is operable to be connected in series with the thermistor 102 via a common node 151 coupled to a pad, e.g., pad 106-2. Similar to the contact line arrangement previously set forth with respect to the thermistor 102, the bias resistor 104 may also be provided with two sets of contact lines 112A, 112B at terminal regions 109A and 109B, respectively. Furthermore, each contact line grouping 112A / 112B associated with the bias resistor 104 may be provided with a corresponding set of fuse links 113A / 113B, similar to the fuse link arrangement associated with the thermistor 102, for selectively coupling terminal regions 109A / 109B to corresponding pads, e.g., pads 106-1 and 106-2.Additionally, each set of contact lines 112A and 112B may be provided with different spacings between two adjacent contact lines, allowing for coarse or fine tuning operations subsequent to fabrication of a resistive body of bias resistor 104, e.g., in a manner similar to the trimming operations previously discussed with respect to thermistor 102. By selectively opening all but one of the fuse links 113A, the terminal region 109A having a corresponding resistive segment may be placed in an electrically conductive relationship with pad 106-1. Similarly, by selectively opening all but one of the fuse links 113B, the terminal region 109B having a corresponding resistive segment may be electrically connected to pad 106-2 as well as the terminal region 103A of thermistor 102 via a node 151.

[0015] Fig. Figure 2 illustrates an exemplary voltage divider 200 in a circuit diagram representation generally corresponding to the integrated thermistor-resistor arrangement of the Fig. 1, wherein a bias resistor (R Bias ) 204 and a thermistor (R TMP ) 202 are connected in series to a common node 209B connected between a reference voltage rail 209A, e.g., a V Bias -rail, and a second reference voltage rail 209C, e.g., ground. Fuse links or banks 208A and 208B are connected to respective terminals of R Bias 204 to enable resistor trimming operations as previously explained. Likewise, fuse links or banks 206A and 206B are connected to respective terminals of R TMP 202 to enable associated resistor trimming operations. In operation, an output voltage V TEMP as a fraction of V Bias, e.g. multiplied by the resistance ratio {R TMP / [R Bias + R TMP ]}, can be obtained.

[0016] In one implementation example, the thermistor 102 / 202 and a well resistor may be formed in an n-well region of a suitable semiconductor substrate, and a bias resistor 104 / 204 may be formed as a doped polysilicon resistor disposed in a region of the substrate isolated from the n-well region. Fig. 3A-3N illustrate cross-sectional views of a partially formed semiconductor device at various manufacturing stages for fabricating a thermistor coupled to a bias resistor in an integrated process flow, according to some examples. Fig. 5A and Fig. 5B each represent a portion 500A and 500B, respectively, of a flowchart of a manufacturing process that summarizes various steps that roughly correspond to the Fig. 3A-3N. With joint reference to Fig. 3A-3N and 5A / 5B present an integrated process flow according to a representative implementation.

[0017] In Fig. 3A, a semiconductor device or integrated circuit (IC) 301 is shown at an early stage of manufacturing, wherein a p-type substrate portion 302 and a lightly doped p-type single crystal silicon layer 304 (e.g., epitaxially grown or formed) over the p-type substrate portion 302 may form part of a die formed in a semiconductor process wafer (e.g., a silicon wafer). For purposes herein, the p-type substrate portion 302 and the p-type single crystal silicon layer 304 may be cumulatively treated as a substrate 306, wherein a thermistor region 308 and a reference or bias resistor region 310 may be formed to enable the fabrication of two separate resistive components, e.g., a resistor. B. a high-TCR component or a low / zero-TCR component, can be provided without reducing (or reactivating) the activation or performance of respective dopants during different thermal processes.

[0018] In Fig. 3B and at block 502 of method 500A / 500B, a manufacturing stage is set forth wherein a deep n-well (DNWELL) 309, sometimes referred to as a thermistor body 309, is formed in the thermistor region 308 of the single crystal layer 304. Depending on the process flow, the DNWELL 309 may be formed before or after an active area definition process (e.g., referred to as a MOAT process in some manufacturing facilities) configured to pattern an active area of ​​the die, which may include defining contact posts, stripes, or bumps with varying spacing therebetween for tuning a thermistor body, as will be detailed further below. In the Fig. In the example shown in Figure 3B, DNWELL patterning and implantation are performed before MOAT patterning and formation associated with field isolation regions. In one implementation example, DNWELL 309 can be doped with phosphorus or arsenic. For example, phosphorus can be doped with a dose of approximately 2.0×10 12 / cm 2 (implantation energy of about 2 MeV) and arsenic with a dose of about 3.0×10 12 / cm 2(Implantation energy of about 160 keV) to achieve a junction depth of about 2.5 µm in the single crystal layer 304. In some additional examples, an annealing step may be performed (not specifically shown in the figures) to drive and / or activate the dopants, which may occur prior to forming dielectric isolation regions, e.g., by shallow trench isolation (STI) or local oxidation of silicon (LOCOS) in some examples.In some additional, alternative, and / or optional examples, shallow p-well (SPWELL) regions may be formed to isolate multiple DNWELL regions that may be provided to support a multi-component / segment thermistor structure (not specifically shown in the cross-sectional views), where the SPWELL regions are formed using any known or previously unknown shallow p-well formation processes, as shown in block 504, which may be optionally provided. Additional details regarding the formation of multi-segmented thermistors according to some examples can be found in U.S. Patent Application Publication No. 2020 / 0119132, which is hereby incorporated by reference in its entirety for all purposes.

[0019] It is understood, however, that SPWELL-based insulation may optionally be provided in some process flows, even in a single-segment thermistor application, although it may involve an additional masking step, potentially increasing production costs. Regardless of whether a multi-segment or single-segment thermistor application is implemented, if SPWELL insulation is provided, the DNWELL annealing process is implemented prior to SPWELL formation, which annealing process may be performed at about 1150°C for about 4 to 5 hours or similar. One skilled in the art will recognize, upon reference to this, that a DNWELL region, e.g.,DNWELL 309 with suitable dopants, can be suitably annealed to provide suitable junction profile(s) for supporting a resistive body operable as a thermistor with a target resistance value that can be tuned according to the present examples.

[0020] In Fig. 3C and at block 506, a manufacturing stage is set forth in which the semiconductor device 301 is patterned for definition of an active area (e.g., a MOAT structure), wherein suitable contact posts or bumps may be formed at respective resistive header regions 317A, 317B associated with the thermistor body formed in the DNWELL 309. As illustrated, a first set of contact posts (appearing as rectangular stripes or bumps in a top view), e.g., contact posts 311-1 to 311-3, may be formed in a header region 317A, wherein the contact posts may be provided with a close spacing, or a first pitch, therebetween (as illustrated, e.g., by a thermistor fine tuning line (TFL) 1 and TFL 2). In a similar manner, a second set of contact posts, e.g., B.Contact posts 319-1 to 319-3 may be formed in the header region 317B to have further spacing therebetween, or a second pitch (as illustrated, for example, by the thermistor coarse tuning line (TCL) 1 and TCL 2). It should be understood that different pitch sizes may be provided within a single header region and / or between the two header regions, which may be configured to effect multiple combinations of fine tuning and / or coarse tuning resistor segments in predetermined increments of a thermistor resistance value during fabrication of the semiconductor device 301. Further, the contact posts 319-1 to 319-3 and 311-1 to 311-3 may be formed in the header regions 317A and 317B, respectively.317B by an additional n-type dopant in an implantation process that can be selectively blocked to integrate the fabrication of a poly-based bias resistor in the same flow, as explained below.

[0021] A field dielectric layer 312 (e.g., an STI layer) may be formed over the single crystal layer 304 of the substrate 306, as shown in Fig. 3D and at block 506. In an exemplary arrangement, the field dielectric layer 312 may include a field oxide extending into the substrate 306. In some arrangements, the STI / dielectric layer 312 may be formed as part of a MOAT definition process prior to a DNWELL implantation, as previously discussed. Regardless of whether the MOAT isolation is formed before or after DNWELL formation, the field dielectric layer 312 may be polished or planarized using, for example, a chemical mechanical polishing (CMP) process (not specifically shown in the figures depicting cross-sectional views). Thereafter, a polysilicon layer 314 of appropriate thickness is formed over the field dielectric layer 312, as shown in Fig. 3E and at block 508. In some arrangements, the polysilicon layer 314 may be made amorphous or left polycrystalline and may have a thickness of about 20 nm to 100 nm. A resistance-setting p-type implant 315 may be performed (block 508), e.g., as a blanket implant to avoid additional patterning, to form an implanted resistor body operable as a bias resistor in subsequent process steps. In one implementation example where a low TCR / zero TCR resistor is desired, the dopant species of the blanket implant 315 may be boron (B) at a dose of 1×10 15 / cm 2 up to 1×10 16 / cm 2 to achieve a dopant density of 1×10 20 / cm 3 up to 4×10 20 / cm 3It will be appreciated that various dopant doses and / or concentrations may be provided depending on the desired target resistance values, taking into account the die area available for forming a bias resistor integrated with a thermistor while minimizing the impact on the overall die area. Furthermore, providing a net doping density that is p-type may, in some examples, advantageously provide better control of the sheet resistance in the bias resistor body than an n-type net doping density. Additional details regarding forming a polysilicon-based low TCR / zero TCR bias resistor according to some examples may be found in U.S. Patent No.No. 8,927,385 and the pending TI patent application entitled “ADVANCED POLY RESISTOR AND CMOS TRANSISTOR” (TI Docket No. T100579US01), having application serial number 17 / 714,990 (filed April 6, 2022), each of which is incorporated herein by reference in its entirety for all purposes.

[0022] In some additional and / or alternative arrangements, the polysilicon layer 314 may be doped in situ rather than using a separate implantation process, e.g., the blanket implantation 315 as previously discussed. In-situ doping may be implemented as a technique in which a suitable dopant species is introduced into a polysilicon layer at the same time the polysilicon layer is deposited. For example, in-situ doping may be implemented using a suitable chemical Si precursor, e.g., silane (SiH4), and a boron-containing precursor, e.g., diborane (B2H6), together with CVD reactant gases used in polysilicon deposition.In still further arrangements, the polysilicon layer 314 may be doped via diffusion doping at appropriate temperatures, wherein a heavily doped glass may be grown or deposited to serve as the source of boron that can diffuse into the polysilicon material to achieve an appropriate resistance value.

[0023] In Fig. 3F and at block 510, the polysilicon layer 314 may be patterned in a manufacturing stage (e.g., involving photolithography and etching, not specifically shown in the figures) to form a bias resistor body 316 with appropriate dimensions over the bias resistor region 310 of the semiconductor device 301. As will be explained further below, in additional and / or alternative arrangements, the doped bias resistor body 316 may be patterned to form an overlying structure disposed over the STI portion that electrically isolates the underlying DNWELL region 309, e.g., B. the doped bias resistor body 316 has a shape and / or area that does not block the thermistor head regions 317A and 317B and follows applicable minimum geometry design rules associated therewith.

[0024] In some arrangements, the contact posts 311-1 to 311-3 and 319-1 to 319-3 formed in the head regions 317A and 317B, respectively, may be implanted with an additional n-type dopant, as previously noted. For example, an implantation process 324 described in Fig. 3G and set forth at block 512, may cause the respective contact posts 311-1 to 311-3 and 319-1 to 319-3 to be adjusted to act as n +Contact posts (e.g., in some implementations, in a process referred to as NSD implantation), where the contact posts have higher n-type dopant concentrations than the surrounding resistor body formed in the n-well. The p-doped bias resistor body 316 may be blocked by a patterned photoresist 318 of a suitable thickness (e.g., functioning as an implantation block) formed prior to the implantation process. It will be appreciated that NSD implantation blocking is effective in preventing the n-type dopants from interfering with the properties of the bias resistor body 316 (e.g., by counteracting the p-type dopants therein), so that the integration of a bias resistor with appropriate properties can be enabled in the same flow used to fabricate a thermistor with a different set of properties, e.g.,of the thermistor manufactured in DNWELL 309.

[0025] After implanting the contact posts of the respective head regions 317A / 317B, a dopant activation anneal process may be effected, as set forth in block 514 (not specifically shown in the cross-sectional views of the manufacturing stages). In an exemplary arrangement, the dopant activation anneal process may include a rapid thermal anneal (RTA) process at approximately 1000°C for approximately 10 to 15 seconds, which allows the dopants in the thermistor contact posts as well as the poly-based bias resistor body 316 to be activated with minimal risk of significantly altering respective diffusion profiles. Subsequently, a silicide blocking layer (SBL or SiBLK layer) 325 may be formed over the semiconductor device 301, as shown in Fig. 3H. In an exemplary arrangement, the SiBLK layer 325 may be etched to form a patterned SiBLK structure 328 for defining a plurality of contact holes at respective terminal regions or header regions 331A and 331B of the poly-based bias resistor 316, which remain exposed for subsequent silicide formation while the main bias resistor body is blocked by silicide formation, as set forth at blocks 516 and 518 and in manufacturing stages in Fig. 3I and Fig. 3J. As illustrated, an exemplary SiBLK structure 328 may be patterned to extend over the header regions 331A / 331B and corresponding vertical edges / walls of the bias resistor 316 and onto at least a portion of the field dielectric layer 312. In some additional and / or alternative examples, the semiconductor device 301 may be fabricated such that the SiBLK layer 325 may not need to be formed over the thermistor region 308 due to the coverage provided by the field dielectric layer 312. In some examples, the SiBLK layer 325 may comprise a multi-layer structure including an oxide layer and a layer containing nitride, carbide, SiCN, or other suitable material (not specifically shown in the figures).An exemplary oxide layer of the SiBLK layer 325 may be grown or deposited and may have a thickness of 1 nm to 100 nm. An exemplary nitride, carbide, or SiCN layer of the SiBLK layer 325 may be deposited by a (bis(tertiary-butylamino)silane) (BTBAS) process, e.g., at 550°C, or in a plasma-enhanced chemical vapor deposition (PECVD) process, e.g., at 350°C to 400°C, and with a thickness of 5 nm to 40 nm.

[0026] For example, the patterned SiBLK structure 328 is configured to expose two contact holes 327-1, 327-2 in the header region 331A and three contact holes 321-1 to 321-3 in the header region 331B of the bias resistor body 316, as shown in Fig. 3I. It should be understood that the plurality of contact holes / stripes formed in the respective header regions 331A and 331B of the bias resistor body 316 may have different spacings to enable various combinations of fine and coarse tuning operations, similar to the thermistor contact posts 319-1 to 319-3 and 311-1 to 311-3, as previously described. As illustrated, the contact holes 327-1, 327-2 are spaced at a first pitch (e.g., as illustrated by bias resistor fine tuning line (BRFL) 1) more closely than contact holes 321-1 to 321-3 disposed in the header region 331B and having further spacings therebetween, e.g., B. have a second pitch (as illustrated by bias resistor coarse tuning line (BRCL) 1 and BRCL 2).

[0027] After forming and patterning the SiBLK structure 328, a silicide loop may be performed, forming metal silicide regions on the exposed semiconductor regions of the contact holes of the polysilicon bias resistor body 316 and the contact posts of the thermistor body including the DNWELL 309. Silicides 330-1 and 330-2 are illustrative of silicided the exposed semiconductor regions of the polysilicon bias resistor body 316 to effect low-resistance connections to an overlying metal layer in a subsequent metallization stage. Similarly, silicides 322-1 and 322-2 are illustrative of silicided the exposed silicon posts of the thermistor body 309 to effect low-resistance connections to the overlying metal layer. In a representative implementation, a silicide loop may involve a deposition of a metal (e.g.including nickel, cobalt, titanium, tungsten, molybdenum, platinum, palladium, tantalum, etc.), annealing to form a silicide (e.g., using heat, ionic energy, laser energy, etc.), followed by removal of unreacted metal and further annealing to form a low-resistivity phase of the silicide material.

[0028] After silicided the contact holes and contact posts, a pre-metal dielectric (PMD) stack 332 may be formed over the semiconductor device 301, which may include one or more layers and / or liners, e.g., using known or previously unknown processes, materials, and compositions, as set forth at block 520 and in the manufacturing stage of Fig. 3K. In one implementation example, a PMD liner 332A comprising SiN may be conformally formed over the SiBLK structure 328, over which a PMD oxide layer 332B may then be deposited, after which the entire PMD stack 332 may be planarized to a suitable thickness using CMP. A suitable contact etch process (not specifically shown in this figure) may be effected to open a plurality of contact vias corresponding to the contact posts associated with the thermistor body 309 and the contact holes associated with the bias resistor body 316 (block 522).Thereafter, the semiconductor device 301 may be subjected to a contact lining and plugging process to fill the contact vias with suitable metal compositions, liners, or posts, which may be formed with a patterned metal layer formed over the PMD stack 332 in a metallization process subsequent to the opening of pads, and metal-based fuse inserts (in . Fig. 3A-3N not specifically shown) with respect to the thermistor body 309 and the bias resistor body 316. Depending on an implementation, the patterned metal layer may include a plurality of interconnect lines for enabling electrical connectivity between the respective resistor heads of the thermistor body 309, the bias resistor body 316, and the pad terminals formed as part of the semiconductor device 301 via respective fuse links associated therewith.

[0029] For example, a Fig. 3L illustrates a process in which contact vias 350-1, 350-2, and contact vias 353-1 through 353-3 are formed with respect to the header regions 331A and 331B, respectively, of the bias resistor body 316 (e.g., using a silicide-stopping etch process). Similarly, contact vias 360-1 through 360-3 and contact vias 363-1 through 363-3 are formed with respect to the header regions 317A and 317B, respectively, of the thermistor body 309 (e.g., using a silicide-stopping etch process).

[0030] A contact via a metallization step, which is Fig. 3M and set forth at block 524 illustrates a process in which contact vias may be metallized using a Ti / TiN liner followed by a tungsten (W) filler, although other metallurgies may be implemented in additional and / or alternative examples. As illustrated, metallized contact conductors 351-1, 351-2 are formed in contact vias 350-1 and 350-2, and metallized contact conductors 352-1 through 352-3 are formed in contact vias 353-1 through 353-3 associated with the bias resistor body 316. Similarly, metallized contact conductors 361-1 to 361-3 are formed in contact vias 360-1 to 360-3, and metallized contact conductors 362-1 to 362-3 are formed in contact vias 363-1 to 363-3 associated with the thermistor body 309. A polishing process (e.g.,a CMP process) may be implemented to remove excess metal formed or left remaining on the planarized surface of the PMD stack 332 (block 524).

[0031] A first metallization stage of the backend-of-line (BEOL) flow may include depositing, patterning, and etching a metallic material (e.g., aluminum, copper, etc.) to form a metal interconnect layer that interconnects the bias resistor 316, the thermistor body 309, and the die pads (and any optional ESD protection devices, if provided) via respective metal fuse links, which may be configured for tuning (block 526), ​​as previously set forth. Furthermore, respective fuse code settings may be obtained to achieve appropriate resistance values ​​with respect to the bias resistor and / or thermistor, as set forth below. As in Fig. 3N, reference numerals 353-1 and 353-2 and reference numerals 355-1 to 355-3 refer to metal traces for interconnecting the head regions 331A and 331B, respectively, of the bias resistor 316. Similarly, reference numerals 365-1 to 365-3 and reference numerals 364-1 to 364-3 refer to metal traces for interconnecting the head regions 317A and 317B, respectively, of the thermistor body 309.

[0032] With further reference to Fig. 5B, but without corresponding cross-sectional views, additional steps are provided in the fabrication of the semiconductor device 301. For example, in step 528, a semiconductor process wafer including the semiconductor substrate 306 may be coupled to test equipment for resistance measurements, after which an appropriate set of fuse links may be laser trimmed based on a fuse code determination, as set forth below. Thereafter, each die or IC including the integrated thermistor and bias resistor is singulated (e.g., cut or diced) from the semiconductor wafer. Thereafter, some or all of the ICs (e.g., those that pass additional / optional testing) may be packaged.Encapsulation typically places a wrapper around (or encapsulates) the IC and further provides an external interface, typically a number of conductive pins fixed relative to pads on the die. Conductors such as wire bonds, contact pads, or balls, etc., are formed between the IC pads and the encapsulation pins. Encapsulated ICs with acceptable test results are then determined for sale and shipment to a customer.

[0033] Fig. 4A and Fig. 4B illustrate a generalized potentiometer scheme for tuning a thermistor and / or a bias resistor based on respective fuse codes to achieve appropriate resistance characteristics according to some examples, wherein reference numeral 400A of Fig. 4A generally refers to a resistive component 402 having a resistive body formed as part of an integrated semiconductor structure, e.g., device 301 described previously, and reference numeral 400B of Fig. 4B generally refers to an example circuit diagram corresponding to resistive component 400A. The example resistive component 402 is provided with a first header region 406A having a plurality of closely spaced contacts 404A for enabling fine tuning increments of appropriate resistance segments, e.g., each having a first unit resistance value. Similarly, a second header region 406B is provided with a plurality of widely spaced contacts 404B for enabling coarse tuning increments of appropriate resistance value, e.g., each having a second unit resistance value. With respect to each header region of resistive component 402, only one of the contacts is connected to the corresponding pad based on an appropriate security code, which may be determined subsequent to forming the semiconductor structure including resistive component 402.Accordingly, various permutations and / or combinations of resistor lengths between the two header regions 406A and 406B may be achieved, as illustrated, for example, by lengths 403-1 to 403-3. In general, if the first and second header regions of a resistive component have N and M contacts, respectively, a total of [N × M] resistor lengths may be available to tune the final resistance value of the resistive component. Furthermore, a resistor length combination resulting in the longest effective inter-header channel length exhibits the highest resistance value, whereas a resistor length combination with the shortest effective inter-header channel length exhibits the lowest resistance value. For example, unity resistance values ​​(R FX ) of approximately 50 Ω and unit resistance values ​​(R CX) of approximately 300 Ω to effect fine-tuning or coarse-tuning adjustments, with a main channel resistance value (R HAUPT ) may be doped or otherwise engineered to have a nominal resistance of approximately 9 kΩ with respect to the resistive component 402 disposed between pads 450A and 450B, as shown in Fig. 4B illustrates.

[0034] In one implementation example of the previously presented binary ladder potentiometer architecture, the unit resistors can be provided as identical structures located at the respective head regions to ensure good matching and predictability of the properties. By using fuses to determine which branches are opened and which branches remain shorted, the resistance value can be adjusted between the two end cases, as previously presented. In some examples, multiple metal laser fuse links can be laid out in the metal layer, and a post-metallization process can be implemented to program a specific fuse pattern (e.g., a fuse code) to achieve a target resistance value based on appropriate trimming.For example, after a protective overcoat (PO) deposition, a structure can be etched to open the probe pads and expose the fuses. The resistance value can be measured using a probe, which can be configured to allow temperature correction, e.g., with respect to thermistor tuning. Using the measured resistance value, a trimming algorithm can be implemented to determine which fuses should be opened (e.g., according to the fuse code) to achieve the desired resistance target. After the resistance measurement, an oxide film can be deposited to cover the pads and unselected fuses, and a laser trimming tool can be used to expose the selected fuses, damaging the oxide layer and locally melting the exposed metal.A wet slag etch can then be performed to chemically remove any metal that may remain where the fuses are to be opened. A final PO-SiON layer can be deposited and etched to open the pads while leaving the fuses covered.

[0035] Fig. 6 illustrates a cross-sectional view of a semiconductor IC device 600 in which an integrated thermistor and a bias resistor are vertically oriented relative to each other (e.g., in a stacked arrangement), according to another example of the present disclosure. It is understood that a vertically oriented voltage divider may be formed in a previously set forth process flow, wherein patterning of a doped polysilicon layer, which in Fig.3F, may be modified to form a bias resistor body 652 disposed over the STI portion that isolates the thermistor body in the DNWELL 309. Similarly, the patterning of the SiBLK structure 654 overlying the bias resistor body 652, as well as remaining processing steps, may also be modified in a corresponding manner, mutatis mutandis, e.g., to form silicided contacts in resistor head regions 696A / 696B, respectively, in accordance with the preceding description.

[0036] Based on the foregoing, it will be appreciated that examples of the present disclosure provide an integrated thermistor and a bias reference resistor on a single die, thereby eliminating the need to acquire two discrete components, possibly from different manufacturers, for a product application. Because the voltage divider circuit according to the present examples is formed as an integrated component rather than two separate devices, circuit board space—and cost—can be minimized, which may enable product miniaturization in an application, e.g., in a sensor application. Die size savings may be particularly significant in a vertically oriented thermistor-bias resistor configuration.Furthermore, while conventional bias reference transistors are manufactured in process flows that require more stringent process controls to achieve a required precision, which hinders integration of the device in an IC with other components that are typically manufactured in less stringent flows (and relatively simpler flows with only a small number of mask layers), such as thermistor flows, present examples provide an integrated process flow that can advantageously accommodate the fabrication of a low / zero TCR component, e.g., a bias resistor, in a flow that includes the thermistor flow, in which the bias resistor can be fine-tuned to meet the specifications of a particular application.Therefore, while exemplary arrangements set forth herein are expected to provide a combination of various tangible improvements, no particular result is a requirement unless explicitly recited in a particular claim.

[0037] Although various examples of the present disclosure have been described above, it should be understood that they have been presented merely as examples and not by way of limitation. Numerous changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Accordingly, the meaning and scope of the present disclosure should not be limited by any of the previously described examples. Instead, the scope of the disclosure should be defined in accordance with the claims appended hereto and their equivalents.

[0038] For example, in this disclosure and the following claims, unless otherwise stated and / or specified to the contrary, any one or more of the layers set forth herein may be formed in any number of suitable ways, such as spin-on techniques, sputtering techniques (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD), etc. As another example, silicon nitride may be a silicon-rich silicon nitride or an oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the dielectric constant of the materials is substantially different from that of high-purity silicon nitride.

[0039] Furthermore, in at least some additional or alternative implementations, the functions / acts described in the blocks may occur out of the order shown in the flowcharts. For example, two blocks shown in succession may actually execute substantially concurrently, depending on the functionality / acts involved, or the blocks may sometimes execute in the reverse order. Furthermore, the functionality of a given block of the flowcharts and / or block diagrams may be separated into multiple blocks and / or the functionality of two or more blocks of the flowcharts and / or block diagrams may be at least partially integrated. Furthermore, some blocks in the flowcharts may optionally be omitted.Although some of the diagrams include arrows along communication paths to indicate a primary direction of communication, it is further understood that communication may occur in the opposite direction relative to the arrows depicted. Finally, other blocks may be added / inserted between the blocks illustrated.

[0040] It should therefore be clearly understood that the order or sequence of acts, steps, functions, components, or blocks illustrated in any of the flowcharts and / or block diagrams depicted in the drawings of figures of the present disclosure may be modified, altered, substituted, adapted, or otherwise rearranged within a particular flowchart or block diagram, including removal or omission of a particular act, step, function, component, or block.In addition, the acts, steps, functions, components, or blocks illustrated in a particular flowchart may be intermixed with, or otherwise rearranged or arranged with, the acts, steps, functions, components, or blocks illustrated in another flowchart to effect additional variations, modifications, and configurations with respect to one or more processes for purposes of practicing the teachings of the present disclosure.

[0041] At least some portions of the foregoing description may include some directional terminology, such as, for example, "upper," "lower," "top," "bottom," "left," "right," "front," "back," "vertical," "horizontal," etc., that may be used with reference to the orientation of some of the figures or illustrative elements thereof being described. Because components of some examples may be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. Likewise, references to features labeled "first," "second," etc., do not indicate any particular order, importance, or the like, and such references may be interchanged mutatis mutandis depending on the context, implementation, etc.Furthermore, the features of examples described here may be combined with each other unless specifically stated otherwise.

[0042] Although various implementations have been shown and described in detail, the claims are not limited to any specific implementation or example. Nothing in the above detailed description should be read to imply that any particular component, element, step, act, or function is essential such that it must be included within the scope of the claims. When phrases such as "at least one of A and B," or phrases of similar meaning, are mentioned or described, such phrase should be understood to mean "only A, only B, or both A and B." A reference to an element in the singular is not intended to mean "one and only one" unless explicitly stated, but rather "one or more."All structural and functional equivalents to the elements of the above-described implementations known to one of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims appended below. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 8,927,385

[0021] US 17 / 714,990

[0021]

Claims

[1] Electronic device comprising: a substrate including an n-well region; a thermistor formed in the n-well region; and a bias resistor connected in series with the thermistor, the bias resistor being formed in a region of the substrate that is isolated from the n-well region. [2] The electronic device of claim 1, wherein the thermistor comprises a well resistor in the n-well region with a dopant species comprising phosphorus and / or arsenic. [3] The electronic device of claim 1, wherein the bias resistor comprises a boron-doped polysilicon structure disposed over a field oxide extending into the substrate. [4] The electronic device of claim 1, further comprising a first plurality of fuses for tuning the thermistor and a second plurality of fuses for tuning the bias resistor. [5] The electronic device of claim 4, wherein the first plurality of fuses for tuning the thermistor comprises a first subset of fuses spaced at a first pitch and coupled to a first terminal of the thermistor, and a second subset of fuses spaced at a second pitch greater than the first pitch and coupled to a second terminal of the thermistor. [6] The electronic device of claim 4, wherein the second plurality of fuses for tuning the bias resistor comprises a first subset of fuses spaced at a first pitch and coupled to a first terminal of the bias resistor, and a second subset of fuses spaced at a second pitch greater than the first pitch and coupled to a second terminal of the bias resistor. [7] The electronic device of claim 1, wherein the thermistor has a positive temperature coefficient. [8] The electronic device of claim 1, wherein the thermistor has a negative temperature coefficient. [9] The electronic device of claim 1, wherein the n-well region extends into an epitaxial layer of the substrate. [10] The electronic device of claim 1, wherein the bias resistor and the thermistor are arranged relative to each other in a stack with a dielectric layer formed therebetween. [11] A method of manufacturing an electronic device, comprising: Forming a voltage divider over a semiconductor substrate, which includes: Forming a thermistor in an n-well region extending into the semiconductor substrate; Forming a bias resistor over a region of the semiconductor substrate that is isolated in conductivity from the n-well region; and Connecting the thermistor and the bias resistor in series between a first reference voltage rail of the electronic device and a second reference voltage rail of the electronic device. [12] The method of claim 11, wherein the thermistor comprises a well resistor in the n-well region with a dopant species comprising phosphorus and / or arsenic. [13] The method of claim 11, wherein the bias resistor comprises a boron-doped polysilicon structure disposed over a field oxide extending into the semiconductor substrate. [14] The method of claim 11, further comprising forming a first plurality of fuses over the semiconductor substrate for tuning the thermistor and a second plurality of fuses for tuning the bias resistor.

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