BUS MEASUREMENTS FOR CALCULATION AND DISPLAY OF TIMING CHARACTERISTICS OF BUS PROTOCOLS IN TEST AND MEASURING INSTRUMENTS

Abstract

Systems and procedures implement the measurement of operating signal timing parameters of electrical signals transmitted via an electrical bus through a device under test in a test and measurement instrument. A bus timing characteristic analyzer identifies nominal signal timing parameters for the acquired electrical signals. The nominal signal timing parameters are defined by the bus protocol and the timing criteria for the electrical signals. The analyzer measures the operating signal timing parameters for each acquired electrical signal and compares them to the nominal signal timing parameters to determine whether the operating signal timing parameters meet the timing criteria.The analyzer then displays a visual indication on the test and measurement instrument for each of the electrical signals, showing whether the operating signal timing parameters for the electrical signal meet the timing criteria.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This disclosure claims priority under 35 USC § 119 to Indian Provisional Patent Application No. 202321057202, entitled “BUS MEASUREMENT TO CALCULATE AND DISPLAY THE REPORT FOR TIMING CHARACTERISTICS OF ANY BUS PROTOCOL IN OSCILLOSCOPE,” filed August 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. FIELD OF TECHNOLOGY

[0002] The present disclosure relates generally to the detection and decoding of electrical signals transmitted over an electrical bus with a test and measurement instrument, and more particularly to a test and measurement instrument that determines whether the detected electrical signals to be decoded satisfy required timing characteristics defined by a bus protocol of the electrical bus. BACKGROUND

[0003] In test and measurement instruments, such as oscilloscopes, protocol decoding is the process of translating or decoding electrical signals transmitted over a serial electrical bus from a device under test (DUT). Protocol decoding translates these electrical signals into corresponding bit sequences as defined in a bus protocol of the electrical bus. This functionality of test and measurement instruments allows developers to verify the design and operation of the DUT against the decoded messages, or frames, transmitted over the electrical bus. Many different types of serial buses are in use today, with each serial bus having an associated bus protocol defined by a corresponding standard.Each bus protocol includes a protocol layer that specifies coding techniques, definitions for different frames and packets, specific bit patterns, and error handling for the electrical signals transmitted over the electrical bus.

[0004] In protocol decoding, a DUT under test is coupled to an electrical bus, and a test and measurement instrument acquires the electrical signals transmitted to and from the DUT over the electrical bus. As part of this process, a user configures a protocol decoder within the instrument, including selecting the type of electrical bus under test and establishing thresholds and other related settings defined for the selected bus through a protocol decoder bus configuration menu. The protocol decoder within the instrument then translates or decodes the acquired electrical signals to generate corresponding frames formed by these electrical signals according to the bus protocol.Decoding involves identifying frame information such as the start and end of a frame, as well as verifying the values ​​of various packets transmitted as part of the frame according to the bus protocol for the electrical bus. The protocol decoder identifies errors in the decoded packets and displays the decoded packets along with a display of the detected errors for user review. Errors can include, for example, packets with incorrect values ​​(i.e., bit sequences) and error checking, including cyclic redundancy check (CRC) or parity checking, for the decoded packets.

[0005] The design of the protocol decoder involves setting thresholds used during the decoding of electrical signals to decode "1" and "0" bits in the bit sequence, or bit stream, transmitted over the electrical bus. The protocol decoder uses these thresholds, along with information from the bus protocol for the electrical bus over which the electrical signals are transmitted, to decode the signals. For example, the protocol decoder uses information about the frame format defined for the bus protocol to detect the beginning and end of frames and to recognize different frame types such as address frames and data frames.

[0006] The signal timing characteristics of the electrical signals transmitted over the electrical bus are also defined by the bus protocol. More specifically, the signal timing characteristics are defined by nominal signal timing parameters specified for the bus protocol. Examples of nominal signal timing parameters include parameters for the rise and fall times for the rising and falling edges of the electrical signals, respectively, parameters for the start condition setup and hold time, data setup and hold time parameters, a stop condition setup time parameter, a buffer time parameter that defines a minimum time between a stop and start condition on the electrical bus, and so on, depending on the protocol of the specific electrical bus in use.The electrical signals transmitted over an electrical bus must conform to the timing characteristics defined by the associated nominal signal timing parameters to ensure proper operation of the electrical bus. If the electrical signals do not conform to these nominal signal timing parameters, it may result in erroneous information being transmitted over the electrical bus. Test and measurement instruments require improved techniques to ensure that acquired electrical signals to be decoded by a protocol decoder meet the required timing characteristics defined by the corresponding bus protocol as part of decoding the acquired electrical signals. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a test and measurement system having a test and measurement instrument including a bus timing characteristics analyzer for analyzing timing characteristics of electrical signals transmitted over an electrical bus in accordance with embodiments of the disclosure. Fig. Figure 2 is a signal timing diagram illustrating a set of nominal signal timing parameters associated with data and clock signals of an inter-integrated circuit (I2C) electrical bus. Fig. Figure 3 is a signal timing diagram illustrating the data and clock signals of an I2C bus and showing an address frame and a data frame transmitted on the bus according to the I2C bus protocol. Fig. Figure 4 is a signal timing diagram showing the data and clock signals acquired by the instrument and the decoded data and address frames as generated by a protocol decoder of the test and measurement instrument. Fig. Figure 5 is a flowchart of a process performed by the bus timing characteristics analyzer of Fig. 1 is performed to analyze the timing characteristics of data and clock signals transmitted over an I2C bus in accordance with embodiments of the disclosure. Fig. 6 shows an exemplary display of training provided on a user interface by the bus timing characteristics analyzer of Fig. 1 for training by a user of the bus timing characteristics analyzer in accordance with embodiments of the disclosure. Fig. 7 is a bus configuration display generated by the bus timing characteristics analyzer of Fig. 1 displayed on a user interface of the test and measurement instrument in accordance with embodiments of the disclosure. Fig. 8 shows a display of the configuration of the bus timing results presented by the bus timing characteristics analyzer on the user interface of the test and measurement instrument in accordance with embodiments of the disclosure. Fig. 9 shows a display of the bus timing results presented by the bus timing characteristics analyzer on the user interface of the test and measurement instrument in accordance with embodiments of the disclosure. Fig. 10 shows another example of a display of bus timing results that also includes time domain representations of the collected electrical data in accordance with embodiments of the disclosure. DETAILED DESCRIPTION

[0007] Embodiments of the disclosure relate to methods for analyzing timing characteristics of electrical signals transmitted from a device under test (DUT) over an electrical bus and in a test and measurement instrument for testing the DUT, as well as systems for implementing these methods in accordance with embodiments of the disclosure.

[0008] According to embodiments of the disclosure, a bus timing characteristics analyzer of a test and measurement instrument determines whether the timing characteristics of electrical signals transmitted over an electrical bus meet the required timing criteria or characteristics for those electrical signals as defined by a bus protocol of the electrical bus. The bus timing characteristics analyzer is configured to be responsive to user inputs for a desired type of electrical bus being used and, in response to the user inputs, loads or retrieves nominal signal timing parameters for the electrical signals of the desired bus. The nominal signal timing parameters are defined by the bus protocol and specify timing criteria for the electrical signals.The test and measurement instrument acquires the electrical signals transmitted over the bus to and from the DUT, and the bus timing characteristics analyzer measures the operating signal timing parameters for the acquired electrical signals. The bus timing characteristics analyzer then compares the operating signal timing parameters with the nominal signal timing parameters to determine whether the operating signal timing parameters meet the defined timing criteria. The bus timing characteristics analyzer then displays a visual indication on the test and measurement instrument. that displays the results of the comparison. The visual indication shows the user whether the operating signal timing parameters for the electrical signal meet the timing criteria. The bus timing characteristics analyzer also displays indicators on a test and measurement instrument user interface that allow the user to navigate through the comparison results for each of the signal timing parameters. This navigation allows the user to more closely investigate the occurrence of specific errors in the timing characteristics of the electrical signals during the DUT test.

[0009] Fig. 1 shows a test and measurement system 100 with a test and measurement instrument 102 including a bus timing characteristics analyzer 104 that determines whether the timing characteristics of electrical signals ES communicated over an electrical bus EB meet the required timing criteria or characteristics for those electrical signals defined by a bus protocol of the electrical bus. The electrical signals ES are transmitted over the electrical bus EB from one or more devices 106 connected to the electrical bus, one of which is a device under test (DUT). The test and measurement instrument 102 captures the electrical signals ES transmitted from the DUT over the power bus over a specified period of time to generate a "capture" or "captured waveform" for the electrical signals.The bus timing characteristics analyzer 104 analyzes the acquired waveforms to determine whether the electrical signals ES transmitted over the electrical bus EB satisfy the required timing characteristics for those electrical signals as defined by the bus protocol of the electrical bus. In the embodiment of FIG. Fig. 1, the electrical bus EB is an I2C bus (I2C = Inter-integrated Circuit) with three devices 106 coupled to the I2C bus in the form of a bus controller 108 and two bus target devices or targets 110, 112. The bus controller 108 can be, for example, a microcontroller and the bus targets 110 and 112 can be an electrically erasable programmable read-only memory (EEPROM) or a real-time clock module.

[0010] The instrument 102 includes one or more processors 114, which may be configured to execute instructions from a memory 116 and to perform any methods and / or associated steps corresponding to such instructions. A user interface 118 is connected to the one or more processors 114 and may include, for example, a keyboard, a mouse, a touchscreen, an output display, a file storage, and / or other controls that may be used by a user to interact with the instrument 102. In some embodiments, the user interface 118 may be connected to or controlled by a remote interface (not shown) so that a user can control the operation of the instrument 102 at a remote location physically removed from the instrument. A display portion of the user interface 118 may be a digital screen, such as aAn LCD, LED, or other monitor for displaying waveforms, measurements, and other data to a user. In some embodiments, a main output display of the user interface 118 may also be located remotely from the instrument 102.

[0011] The instrument 102 also includes one or more measurement units 120 that perform the functions of measuring parameters and other characteristics of the signals of the DUT being measured or tested by the instrument 102. Typical measurements include measuring voltage, current, and power of signals in the time domain, as well as measuring characteristics of the signals in the frequency domain. The measurement units 120 represent all measurements typically performed on test and measurement instruments, and the bus timing characteristics analyzer 104 can be integrated into or coupled to such measurement units 120. The test and measurement instrument 102 is coupled via cables 122a, 122b and probes 124a, 124b to detect or sense the electrical signals ES transmitted over the I2C bus. This coupling to the electrical signals ES is represented by a dashed line for each of the probes 124a, 124b.

[0012] If the electrical bus EB is an I2C bus, as in the embodiment of Fig. 1, the electrical signals ES correspond to a serial data signal SDA and a serial clock signal SCL. The embodiments of the disclosure relate to an I2C bus by way of example, and the embodiments of the disclosure are not limited to test devices connected to an I2C bus. The electrical bus EB may be any type of electrical bus, including a variety of different types. The electrical bus EB may be any electrical bus where the characteristics of the electrical signals are clearly defined according to a bus protocol in a bus specification. In some embodiments of the disclosure, the electrical bus EB is one of the following: I2C bus, I3C or feedback bus ("SenseWire" bus), RS-232 bus, USB bus (Universal Serial Bus), embedded USB bus (eUSB), SPI bus (Serial Peripheral Interface), embedded SPI bus (eSPI), and SENT bus (i.e., SAE J2716).

[0013] When operating the bus timing characteristics analyzer 104, a user first provides inputs via the user interface 118 of the instrument 102 to configure the bus timing characteristics analyzer for testing the DUT. The DUT corresponds to one of the devices under test 106 and is thus one of the bus controllers 108, the bus target 110, or the bus target 112 in the embodiment of Fig. 1. These user inputs include identifying the type of electrical bus EB used by the DUT. In response to the user inputs, the bus timing characteristics analyzer 104 is configured to analyze certain timing characteristics of the electrical signals ES transmitted over the identified electrical bus EB. The electrical bus EB is the I2C bus in the embodiment of Fig. 1. In this example, user inputs identify the I2C bus, and the bus timing characteristics analyzer 104 retrieves corresponding nominal signal timing parameters for the I2C bus from memory 116, which define the signal timing characteristics for the bus. These nominal signal timing parameters may alternatively be stored in another memory (not shown), such as a memory of the bus timing characteristics analyzer 104 or in a memory external to the instrument 102.

[0014] In some embodiments, the nominal signal timing parameters for the I2C bus include a rise time parameter tRise for rising edges of the SDA and SCL signals, a fall time parameter tFall for falling edges of the SDA and SCL signals, and a clock period tFreq that defines a clock frequency f SCLof the SCL signal. Each of the nominal signal timing parameters tRise, tFall, tFreq has a range of acceptable values, where the range is defined by corresponding minimum and maximum values ​​for the signal timing parameter so that the SDA, SCL signals comply with the bus protocol specifications of the I2C bus. Accordingly, in some embodiments, the nominal signal timing parameters for the I2C bus include a maximum rise time tRisemax and a minimum rise time tRisemin for rising edges of the SDA, SCL signals, a maximum fall time tFallmax and a minimum fall time tFallmin for falling edges of the SDA, SCL signals, and a maximum clock period tFreqmax and a minimum clock period tFreqmin for the SCL signal.

[0015] In addition to these nominal signal timing parameters, additional or alternative nominal signal timing parameters may be used by the bus timing characteristics analyzer 104 in some embodiments of the disclosure. Additional nominal signal timing parameters that may be used by the bus timing characteristics analyzer 104 include, for example, setup and hold times for the SDA signal, along with setup and hold times for start and stop conditions, as defined in the bus protocol specifications for the I2C bus. Fig. Figure 2 is a signal timing diagram showing a number of nominal signal timing parameters associated with the SDA and SCL signals. In the example signal timing diagram of Fig. 2, the I2C signal timing parameters tRise and tFall are defined as t r and t f and the clock period tFreq is not explicitly shown. Fig. 2 also shows additional nominal signal timing parameters that may be used by the bus timing characteristics analyzer 104 in further embodiments of the disclosure. These additional signal timing parameters include a hold start condition time tHD;STA, a minimum low clock period tLOW, a minimum high clock period tHIGH, a data hold time tHD;DAT, a setup start condition time tSU;DAT, a setup start condition time tSU;STA, a hold start condition time tHD;STA, a setup stop condition time tSU;STO, and a bus-free time tBUF. Each of these additional signal timing parameters is defined in the bus protocol for the I2C bus and is understood by those skilled in the art, so they will not be described in detail here.

[0016] Before describing the operation of the bus timing characteristics analyzer 104 in more detail, the operation of a protocol decoder PD of the instrument 102 will first be briefly explained. Normally, a user would use the bus timing characteristics analyzer 104 in combination with the protocol decoder PD of the instrument 102. The protocol decoder PD is coupled to the measurement units 120 ( Fig. 1) to receive the capture of the SDA and SCL signals from the measurement units 120. The protocol decoder PD then translates or decodes the bit sequences in the captures of the SDA and SCL signals transmitted over the I2C bus into frames as defined by the I2C bus protocol. A designer uses the protocol decoder to verify the design and operation of the DUT under test by examining the decoded frames transmitted to and from the DUT over the I2C bus.

[0017] Fig. Figure 3 is a signal timing diagram illustrating the SDA and SCL signals, showing an address frame and a data frame transmitted on the I2C bus according to the bus protocol. The protocol decoder PD decodes the bit sequences transmitted by the SDA signal using the SCL signal to generate corresponding decoded data. Fig. Figure 4 is a signal timing diagram generated by the protocol decoder PD. It shows the SCL and SDA signals acquired by instrument 102 in the upper part of the figure and the decoded data generated by the protocol decoder for bit sequences of the SDA signal in the lower part of the figure. The correct values ​​for the address frames A and data frames D to be transmitted are known during DUT testing, so the protocol decoder PD is able to detect errors in the decoded values ​​for the address and data frames. The protocol decoder can flag or display detected errors in the decoded data so that they can be reviewed by the user.

[0018] The protocol decoder PD does not perform any analysis of the timing characteristics of the SDA and SCL signals transmitted over the I2C bus. Therefore, if errors in the decoded data are caused by timing characteristics of the SDA and SCL signals that do not meet the specifications set by the nominal signal timing parameters of the I2C bus, the protocol decoder PD is unable to identify such errors. The bus timing characteristics analyzer 104 according to embodiments of the disclosure enables the identification of these types of errors resulting from errors in the timing characteristics of the SDA and SCL signals. The overall operation of the bus timing characteristics analyzer 104 will now be described with reference to the flowchart of Fig. 5 described in more detail.

[0019] Fig. 5 is a flowchart of a process 500 performed by the bus timing characteristics analyzer 104 for analyzing the timing characteristics of the SDA and SDL signals in accordance with embodiments of the disclosure. Before the bus timing characteristics analyzer 104 begins executing the process 500, a user inputs a timing characteristic value via the user interface 118 ( Fig. 1) of the instrument 102 to select a "Protocol Utility" option in a configuration menu displayed by the user interface. After selecting the protocol utility, the user enters inputs to identify the type of electrical bus EB used, and the bus timing characteristics analyzer 104 then performs an analysis of the timing characteristics of the electrical signals ES transmitted on the electrical bus EB. The design of the bus timing characteristics analyzer 104 is described below with reference to the Fig. described in more detail.

[0020] Once the user provides input to select the I2C bus, the bus timing characteristics analyzer 104 begins executing the process 500 in operation 502 and loads or retrieves nominal signal timing parameters for the I2C bus (i.e., the selected bus). As described above, in some embodiments, the nominal signal timing parameters include a rise time tRise for rising edges of the SDA and SCL signals, a fall time tFall for falling edges of the SDA and SCL signals, and a clock frequency f CLor a clock period tFreq for the SCL signal. The nominal signal timing parameters may be specified in terms of a maximum and a minimum around a nominal value and may therefore, in some embodiments, include a maximum rise time tRisemax, a minimum rise time tRisemin, a maximum fall time tFallmax, a minimum fall time tFallmin, a maximum clock period tFreqmax, and a minimum clock period tFreqmin for the SCL signal.

[0021] After retrieving the parameters tRisemax, tRisemin, tFallmax, tFallmin, tFreqmax, and tFreqmin in operation 502, the process 500 proceeds to operation 504, and rising and falling edges in the current acquisition or the acquired waveform of the SDA and SCL signals acquired by the instrument 102 are detected. The bus timing characteristics analyzer 104 may detect these edges, or the edge detection may be performed by other components in the instrument 102, such as the measurement units 120.Whether performed by the bus timing characteristics analyzer 104 or another component in the instrument 102, once rising and falling edges have been detected in the current acquisition or acquired waveform in operation 504, the process 500 proceeds to operation 506 and initializes a set of operating variables used in calculating operating signal timing parameters for the current acquisition of the SDA and SCL signals. The operating variables include a current edge index EDGE, a total edge count EDGECNT, a rise time tRise, a fall time tFall, and a frequency tFreq associated with detected rising and falling edges in the current acquisition and the frequency of the SCL signal for each unit interval (UI) of the SCL signal.EDGE, tRise, tFall, and tFreq are each initialized to zero, and the total edge count EDGECNT is set to the total number of detected edges in the acquisition at operation 506.

[0022] Starting at operation 506, process 500 proceeds to operation 508 and determines whether a currently detected edge in the capture, as defined by the value of the edge index EDGE, is less than the total edge count EDGECNT. If the determination in operation 508 is true, process 500 proceeds to operation 510 and measures or calculates the rise time tRise of the detected rising edge, which corresponds to the current value of the edge index EDGE. In operation 510, process 500 also measures or calculates the fall time tFall of the detected falling edge, which corresponds to the current value of the edge index EDGE. From operation 510, process 500 proceeds to operation 512 and calculates or measures the clock period tFreq or the clock frequency f CLfor a current unit interval UI of the SCL signal. Process 500 then proceeds from operation 512 to operation 514 and calculates and stores values ​​for the rise time tRise, the fall time tFall, and the frequency tFreq associated with the current value of the edge index EDGE in a measurement vector MV for the current acquisition.

[0023] The process 500 then proceeds from operation 514 to operation 516 and determines whether each of the rise time tRise, the fall time tFall, and the frequency tFreq associated with the current value of the edge index EDGE meets the timing characteristics or timing criteria defined by the corresponding nominal signal timing parameter retrieved in operation 502. Thus, in operation 516, the process 500 determines whether the currently measured or calculated rise time tRise is greater than the minimum rise time tRisemin and less than the maximum rise time tRisemax, as required by the I2C bus protocol for rising edges of the SDA, SCL signals. Similarly, in operation 516, process 500 determines whether the currently measured or calculated fall time tFall is greater than the minimum fall time tFallmin and less than the maximum fall time tFallmax as required by the I2C bus protocol for falling edges of the SDA, SCL signals.Finally, in operation 516, the process 500 also determines whether the currently measured or calculated clock period tFR is greater than the minimum clock frequency tFreqmin and less than the maximum clock frequency tFreqmax as required by the I2C bus protocol for the SCL signal.

[0024] If one or more of the determinations in operation 516 are negative, the process 500 proceeds to operation 518 and generates a separate error vector FV for each error detected in operation 516. Thus, in operation 518, the process 500 generates an error vector FV-R for the rising edge that indicates whether the rise time tRise for the current rising edge corresponding to the current value of the edge index EDGE meets the timing criteria defined by the corresponding nominal timing parameters (i.e., whether tRisemin <tRise<tRisemax). Ein Bestanden- oder Durchgefallen-Wert wird in Operation 518 in dem Anstiegsflanken-Fehlervektor FV-R gespeichert, um anzuzeigen, ob die Anstiegszeit tRise für die aktuelle Anstiegsflanke die Timing-Kriterien bestanden oder nicht bestanden hat. Der Prozess 500 erzeugt in Operation 518 auch einen Ausfallvektor für die fallende Flanke FV-F und einen Ausfallvektor für die Taktfrequenz FV-CF in Operation 518.In operation 518, a pass or fail value is stored in each of the falling edge FV-F and clock frequency FV-CF error vectors to indicate whether the falling edge fall time tFall and clock frequency fsCL and clock period tFreq, which correspond to the value of the current edge index EDGE, passed or failed the corresponding timing criteria.

[0025] From operation 518, process 500 proceeds to operation 520 and increments the current edge index value EDGE. The process then returns to operation 508 and determines whether the current edge index value EDGE is less than the total edge count EDGECNT. Furthermore, process 500 also proceeds directly to operation 520 if all determinations in operation 516 are positive, meaning no error was detected for any of the analyzed signal timing parameters tRise, tFall, or tFreq. Each of the rising edge (FV-R), falling edge (FV-F), and clock frequency (FV-CF) error vectors first stores a pass value for tRise, tFall, and tFreq corresponding to the current edge index EDGE.Thus, if all determinations in operation 516 are positive, the process 500 immediately proceeds to operation 520 and the current edge index EDGE is incremented, with all initial values ​​for tRise, tFall and tFreq corresponding to the current edge index EDGE remaining at the initially set pass values ​​in each of the vectors FV-R, FV-F, FV-CF.

[0026] The process 500 continues executing operations 508-520 until the determination in operation 508 is negative, indicating that the timing characteristics of all detected edges in the current acquisition were measured and determined to have met or failed the corresponding timing criteria. If the determination in operation 508 is negative, the process 500 proceeds to operation 522 and displays, via the user interface 118 ( Fig. 1) whether each of the measured operating signal timing parameters tRise, tFall, tFreq passed or failed the timing criteria for the I2C bus as defined by the corresponding nominal signal timing parameters tRisemin, tRisemax, tFallmin, tFallmax, tFreqmin and tFreqmax.

[0027] The measured operating signal timing parameters tRise, tFall, tFreq are considered not met if at least one rising or falling edge or the clock frequency for at least one unit interval UI does not meet the timing criteria as defined by the corresponding nominal signal timing parameters. At operation 522, the process 500 displays a "Pass" indication for a measured signal timing parameter tRise, tFall, tFreq if all edges or the frequency or all unit intervals UI for the SDA, SCL signals meet the associated timing criteria. Conversely, at operation 522, the process 500 displays a "Fail" indication for the measured signal timing parameter tRise, tFall, tFreq if a failure is detected.If a fault is detected for a measured signal timing parameter tRise, tFall, tFreq, the process 500 also uses the associated fault vector FV-R, FV-F, FV-CF in operation 522 to allow a user to navigate through the fault vector and examine each instance of a fault for the corresponding signal SDA, SCL. The operation of the bus timing characteristics analyzer 104 in executing operation 522 to present pass and fail indications and allow the user to navigate through the faults and examine them in more detail is described further below with reference to FIG. Fig. described in more detail. After operation 522, process 500 proceeds to operation 524 and ends.

[0028] Fig. 6 shows an example of a configuration display 600 presented on the user interface 118 by the bus timing characteristics analyzer 104 to enable configuration by a user of the bus timing characteristics analyzer 104 according to embodiments of the disclosure. In the configuration display 600, a "Protocol Utility" option is added to an existing configuration menu, and the user selects this option to configure the bus timing characteristics analyzer 104 to perform an analysis of the timing characteristics of electrical signals generated by a DUT. The existing configuration menu presented in the configuration display 600 provides several signal analysis options that the instrument 102 can perform on the acquired waveforms.These analysis options are selected via additional tabs at the top of the configuration display 600 and include a WBG-DPT tab for selecting wide bandgap double pulse tests of a DUT, a DPM tab for selecting digital power management tests of a DUT, an IMDA tab for selecting inverter motor drive analysis tests of a DUT, a Power tab for selecting power tests of a DUT, and a Jitter tab for selecting jitter analyses of a DUT.

[0029] The user selects the protocol utility via a Standard tab displayed in the upper left corner of the configuration display 600. The user selects the "Standard" tab and then the "Protocol Utility" option, which is displayed in the lower left part of the configuration display 600 as one of several different types of bus measurements that the instrument 102 can perform on electrical signals of a DUT. The "Standard" tab is indicated by a thicker line and the "Protocol" tab by a dashed line in Fig. 6 to indicate that these two tabs have been selected by a user. The user then selects a bus source via a source field displayed in the middle left part of the configuration display 600 to define the type of bus to be analyzed, e.g., an I2C bus. The "Source" field is in Fig. 6 shown as bus 1.

[0030] After selecting the "Source" field, a user can then configure parameters for the selected bus type, which is the source of the electrical signals to be analyzed. Selecting the Source field causes a bus configuration display 700 to be displayed, as shown in Fig. 7, which is displayed by the user interface 118 of the instrument 102. The configuration display 700 includes a display field with which the user may display or not display the output of the bus timing characteristic analyzer 104 on the user interface 118. A "Label" field allows the user to assign a desired label to the bus to be analyzed. The type of bus to be analyzed is set in a bus type field and is shown in the example of Fig. 7 is represented as an I2C bus. As already mentioned, different bus types can be analyzed, and the user selects the appropriate bus using the "Bus Type" field.

[0031] The user then selects the appropriate CH channels on the instrument for the corresponding electrical signals of the selected bus type. The I2C bus includes the SDA and SCL signals, as described above. In the example of Fig. 6, one of the SDA and SCL signals is connected to a first channel CH1 of the instrument 104 and the other of the SDA and SCL signals is connected to a second channel CH2 of the instrument. A threshold field in the display 700 is used to set a corresponding threshold voltage for the SDA, SCL signals connected to the first and second channels CH1, CH2 of the instrument 102. An R / W bit field in the display 700 provides the user with the ability to include a read / write R / W bit in the decoded addresses on the I2C bus. A display format field allows the user to select the desired format for displaying the SDA and SCL signals, i.e., whether the signals are displayed as decoded frames on the bus (i.e., "bus" as in Fig. 7) or as time-varying voltage levels for these signals. If the "Bus" format is selected, each value is displayed for each decoded frame, as shown for the I2C bus below in Fig. 4. A display format field allows the user to select the desired format for displaying the values ​​of the decoded frames, e.g., hexadecimal (hex), binary, decimal, although other format options may also be available.

[0032] Fig. 8 shows a configuration display of the bus timing results 800, which allows the user to configure the desired results of the analysis of the bus timing characteristics analyzer 104 to be displayed for user review. More specifically, the configuration display 800 includes a navigation source field in the lower left portion of the display, which allows the user to select the desired timing characteristic or criteria to be displayed for user review. The "Source" field is in the example of Fig. 8 Bus 1, where Bus 1 corresponds to the I2C bus. The "Navigation Source" field accordingly offers the user the option to select one of the desired timing parameters to be analyzed by the Bus Timing Characteristics Analyzer 104.

[0033] As described above, in embodiments, these timing parameters include a frequency of the clock signal SCL, a rise time for rising edges of the SCL signal, a fall time for falling edges of the SCL signal, and rise and fall times for rising and falling edges of the data signal SDA. These various timing parameters are displayed in drop-down subfields available for the Navigation Source field in the configuration display 800 of Fig. 8 are available. The rising edges of the SCL signal are selected by a thicker line for this subfield. A field for the measurement navigation type is also part of the configuration display 800 and allows the user to determine whether all occurrences of the selected timing parameter or only occurrences where errors occurred should be reviewed. This selection is made via an "All Occurrences" subfield and an "Error" subfield of the "Measurement Navigation Type" field. For example, if the rise time of the rising edges of the SCL signal is as in the example of Fig. 8 is selected, allows the selection of the subfield “All occurrences” as in the example of Fig. 8 allows the user to navigate through the Rise Time parameter and review the rise time calculated for all rising edges of the SCL signal in the current acquisition being analyzed by the Bus Timing Characteristics Analyzer 104.

[0034] Fig. 9 shows a bus timing result display 900 via the user interface 118 of the instrument 104 by the bus timing characteristic analyzer 104 to allow the user to review the results of the timing characteristic analysis for the analyzed timing parameters. In the example of Fig. 9, the bus timing result configuration display 800 for the I2C bus shows the previously discussed measured or operational timing parameters, namely the rise and fall time parameters for the rising and falling edges of the SDA and SCL signals, along with the frequency of the SCL signal. These operational signal timing parameters are referred to in the configuration display 900 as follows: the rise time for rising edges of the SCL signal is referred to as the clock rise time trCL; the fall time for falling edges of the SCL signal is referred to as the clock fall time tfCL; the rise time for rising edges of the SDA signal is referred to as the data rise time trDA; the fall time for falling edges of the SDA signal is referred to as the data fall time tfDA; and the frequency of the SCL signal is referred to as a clock frequency fsCL.

[0035] The bus timing results display 900 also includes a value field for each of the timing parameters trCL, tfCL, trDA, tfDA, and fsCL, which displays the value for the timing parameter. A status field for each timing parameter indicates whether the timing parameter passed or failed the analysis by the bus timing characteristics analyzer 104. A user can then use the navigation buttons 902, 904 to navigate through a selected signal timing parameter to review instances of a desired parameter. The user navigation button 904 is in Fig. 9 by a thicker line for that button as selected. In some embodiments where there are no violations for a particular signal timing parameter, navigation for that parameter is disabled. In the example of Fig. 9, for example, no navigation is provided through the instances of the parameters trDA, tfCL, and fsCL, since these parameters passed the analysis, as indicated by the corresponding status fields. Each of the parameters trCL and trDA can then be navigated using buttons 902 and 904, since these parameters failed the analysis, as indicated by the corresponding status fields. The Min' and Max' buttons in the bus timing results display 900 allow the user to determine minimum and maximum values ​​for a selected timing parameter.

[0036] In some embodiments, the bus timing characteristics analyzer 104 performs additional analysis of each of the analyzed signal timing parameters. In embodiments, the bus timing characteristics analyzer 104 calculates, for example, a mean value, a minimum value, a maximum value, and a standard deviation for each of the signal timing parameters tfCL, trCL, tfCL, trDA, and tfDA. Furthermore, in embodiments, navigation through a selected signal timing parameter using buttons 902, 904 may also be presented by the user interface 118 in a time-domain representation of the corresponding signal SDA, SCL to allow the user to view instances of the signal timing parameter being analyzed in the time-domain representation of the corresponding SDA, SCL signal. Fig. 10 shows another example of a bus timing result display 1000 that uses the bus timing result display 900 from Fig. 9 in the upper right corner, along with time-domain representations of the SDA and SCL signals and decoded frames in the left part of the frame. In this embodiment, a specific instance of a timing parameter error displayed in the bus timing result display 900 is also identified or marked by a dashed box 1000 in the time-domain representations of the SDA and SCL signals.

[0037] In some embodiments, the nominal signal timing parameters for the I2C bus include parameters for a standard mode and a fast mode of operation. For the standard mode, the nominal signal timing parameters may include a rise time parameter tRise of 1000 nanoseconds (ns) for rising edges of the SDA and SCL signals, a fall time parameter tFall of 300 ns for falling edges of the SDA and SCL signals, a clock frequency tFreq of less than or equal to 100 kHz, a minimum low clock period tLOW of 4.7 microseconds (µs) and a minimum high clock period tHIGH of 4.0 µs.For fast mode, the nominal signal timing parameters may include a rise time parameter tRise of 20 ns to 300 ns for rising edges of the SDA and SCL signals, a fall time parameter tFall of 20 ns to 300 ns for falling edges of the SDA and SCL signals, a clock frequency tFreq of less than or equal to 400 kHz, and a minimum low clock period tLOW of 1.3 µs and a minimum high clock period tHIGH of 0.6 µs.

[0038] Aspects of the disclosure may operate on specially designed hardware, firmware, digital signal processors, or on a specially programmed general-purpose computer with a processor that operates according to programmed instructions. As used herein, the terms "controller" or "processor" are intended to encompass microprocessors, microcomputers, application-specific integrated circuits (ASICs), and special-purpose hardware controllers. One or more aspects of the disclosure may be embodied in computer-usable data and computer-executable instructions, such as one or more program modules executed by one or more computers (including supervisory modules) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc.that perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. The computer-executable instructions may be stored on a non-transitory, computer-readable medium such as a hard disk, an optical disk, a removable storage medium, solid-state memory, random access memory (RAM), etc. As will be apparent to one skilled in the art, the functionality of the program modules may be arbitrarily combined or distributed in various aspects. Furthermore, the functionality may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, FPGAs, and the like.Certain data structures may be used to more effectively implement one or more aspects of the disclosure, and such data structures are contemplated as part of the computer-executable instructions and computer-usable data described herein.

[0039] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or a combination thereof. The disclosed aspects may also be implemented in the form of instructions stored on one or more non-transferable computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as a computer program product. Computer-readable media, as described herein, is any media accessible by a computer. Computer-readable media may include, for example, but is not limited to, computer storage media and communications media.

[0040] Computer storage media is any media that can be used to store computer-readable information. Examples of computer storage media include RAM, ROM, EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory or other storage technologies, CD-ROM (Compact Disc Read-Only Memory), DVD (Digital Video Disc) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media employed in any technology. Computer storage media excludes signals as such and transient forms of signal transmission.

[0041] Communication media refers to any medium that can be used to transmit computer-readable information. Examples of communication media include coaxial cable, fiber optic cable, air, or any other medium suitable for transmitting electrical, optical, radio frequency (RF), infrared, acoustic, or other signals. EXAMPLES

[0042] Examples of the technologies disclosed herein are listed below. An embodiment of the technologies may include one or more, and any combination, of the examples described below.

[0043] Example 1 is a test and measurement instrument comprising one or more processors configured to control sensing of a plurality of electrical signals transmitted over an electrical bus according to a bus protocol by a device under test; and a bus timing characteristics analyzer configured to identify nominal signal timing parameters for the sensed plurality of electrical signals, wherein the nominal signal timing parameters are defined by the bus protocol and define timing criteria for the plurality of electrical signals; measuring operating signal timing parameters for each of the sensed plurality of electrical signals; comparing the operating signal timing parameters to the nominal signal timing parameters for each of the sensed plurality of electrical signals to determine whether the operating signal timing parameters meet the timing criteria;and displaying a visual indication on the test and measurement instrument for each of the plurality of electrical signals indicating whether the operating signal timing parameters for the electrical signal meet the timing criteria;

[0044] Example 2 is the test and measurement instrument of Example 1, wherein the bus timing characteristics analyzer is further configured to, to measure the operating signal timing parameters for each of the detected plurality of electrical signals, detect edges in each of the detected plurality of electrical signals; determine whether each edge is a rising edge or a falling edge; and measure the operating signal timing parameters for each of the detected plurality of electrical signals using the rising and falling edges of the electrical signal.

[0045] Example 3 is the test and measurement instrument of Example 1 or Example 2, wherein the sensed plurality of electrical signals includes at least one data signal, and wherein the operating signal timing parameters for the at least one data signal include a rise time measured for each rising edge and a fall time measured for each falling edge of the at least one data signal.

[0046] Example 4 is the test and measurement instrument of any one of examples 1 to 3, wherein the nominal signal timing parameters comprise a nominal rise time signal timing parameter and a nominal fall time signal timing parameter, and wherein the bus timing characteristics analyzer is further configured to, for the at least one data signal, compare the measured rise time for each rising edge to the nominal rise time signal timing parameter; and, for the at least one data signal, compare the measured fall time for each falling edge to the nominal fall time signal timing parameter.

[0047] Example 5 is the test and measurement instrument of any one of Examples 1 to 4, wherein the nominal rise time signal timing parameter comprises a range around a nominal value, the range being defined by a minimum and a maximum allowable value for the nominal rise time signal timing parameter, and wherein the nominal fall time signal timing parameter comprises a range around a nominal value, the range being defined by a minimum and a maximum allowable value for the nominal fall time signal timing parameter, and wherein the bus timing characteristics analyzer is further configured to determine whether the measured rise time for each rising edge of the at least one data signal has a value within the range of the nominal rise time signal timing parameter;and determine whether the measured fall time for each falling edge of the at least one data signal has a value within the range of the nominal fall time signal timing parameter;

[0048] Example 6 is the test and measurement instrument of any one of Examples 1 to 5, wherein the nominal signal timing parameters further comprise a setup time tSU and a hold time tHD for the at least one data signal.

[0049] Example 7 is the test and measurement instrument of any one of examples 1 to 6, wherein the sensed plurality of electrical signals further includes a clock signal, and wherein the nominal signal timing parameters for the clock signal include a nominal clock frequency, a nominal rise time signal timing parameter, and a nominal fall time signal timing parameter.

[0050] Example 8 is the test and measurement instrument of any one of examples 1 to 7, wherein the visual indication for each of the plurality of electrical signals indicates a pass condition when all operating signal timing parameters meet the timing criteria for the electrical signal, and indicates a fail condition when one or more of the operating signal timing parameters do not meet the timing criteria.

[0051] Example 9 is the test and measurement instrument of any one of Examples 1 to 8, wherein the electrical bus is one of the following: an inter-integrated circuit (I2C) bus, an I3C or feedback bus, an RS-232 bus, a universal serial bus (USB), an embedded USB (eUSB) bus, a serial peripheral interface (SPI) bus, an embedded SPI (eSPI) bus, and a SENT bus.

[0052] Example 10 is the test and measurement instrument of any one of Examples 1 to 9, wherein the test and measurement instrument may include an oscilloscope.

[0053] Example 11 is a test and measurement system comprising a number of electronic devices; an electrical bus interconnecting the electronic devices, wherein one of the electronic devices is a device under test (DUT), and the electrical bus carries electrical signals having nominal signal timing parameters defined by a bus protocol of the electrical bus, the nominal signal timing parameters determining timing criteria for the electrical signals; and a test and measurement instrument including one or more processors configured to control acquisition of the electrical signals.and a bus timing characteristics analyzer configured to: identify nominal signal timing parameters for the sensed electrical signals, wherein the nominal signal timing parameters are defined by the bus protocol and define timing criteria for the electrical signals; measure operating signal timing parameters for each of the sensed electrical signals; compare the operating signal timing parameters to the nominal signal timing parameters for each of the sensed electrical signals to determine whether the operating signal timing parameters meet the timing criteria; and display a visual indication for each of the electrical signals on the test and measurement instrument indicating whether the operating signal timing parameters for the electrical signal meet the timing criteria.

[0054] Example 12 is the test and measurement system of Example 11, wherein the electrical bus is one of the following: an inter-integrated circuit (I2C) bus, an I3C or feedback bus, an RS-232 bus, a universal serial bus (USB), an embedded USB (eUSB) bus, a serial peripheral interface (SPI) bus, an embedded SPI (eSPI) bus, and a SENT bus.

[0055] Example 13 is the test and measurement system of Example 11 or Example 12, wherein the test and measurement instrument may further include a memory and the nominal signal timing parameters are stored in the memory.

[0056] Example 14 is the test and measurement system of any one of Examples 11 to 13, wherein the test and measurement instrument may include an oscilloscope.

[0057] Example 15 is the test and measurement system of any one of Examples 11 to 14, wherein the sensed electrical signals comprise a clock signal and a data signal, wherein the nominal signal timing parameters comprise rise time and fall time signal timing parameters for rising and falling edges of the clock and data signals, and further comprise a frequency signal timing parameter for the clock signal.

[0058] Example 16 is the test and measurement system of any one of Examples 11 to 15, wherein the test and measurement instrument may further include a protocol decoder configured to translate bit sequences upon acquisition of electrical signals into frames according to the bus protocol of the electrical bus.

[0059] Example 17 is a method for measuring operating signal timing parameters of electrical signals transmitted over an electrical bus, the method comprising retrieving, by a test and measurement instrument, nominal signal timing parameters for the electrical signals, the nominal signal timing parameters being defined by a bus protocol of the electrical bus and defining timing criteria for the electrical signals; sensing the electrical signals in the test and measurement instrument; sensing edges in the sensed electrical signals in the test and measurement instrument; measuring, in the test and measurement instrument, operating signal timing parameters associated with the sensed edges of the sensed electrical signals; comparing, in the test and measurement instrument, the operating signal timing parameters to the nominal signal timing parameters to determine whether the operating signal timing parameters meet the timing criteria.Storing the results of the comparison in the test and measurement instrument; and displaying a pass or fail indication for each of the electrical signals on the test and measurement instrument based on the stored results of the comparison.

[0060] Example 18 is the method of Example 17, wherein the electrical bus is an I2C bus and the electrical signals include a clock signal and a data signal.

[0061] Example 19 is the method of Example 17 or Example 18, wherein the nominal signal timing parameters include a rise time tRise for each rising edge of the clock and data signals, a fall time tFall for each falling edge of the clock and data signals, a clock frequency tFreq of the clock signal, a hold start condition time tHD;STA, a minimum low clock period tLOW, a minimum high clock period tHIGH, a data hold time tHD;DAT, a setup start condition time tSU;DAT, a setup start condition time tSU;STA, a hold start condition time tHD;STA, a setup stop condition time tSU;STO, and a bus-free time tBUF.

[0062] Example 20 is the method of any of Examples 17-19, wherein the nominal signal timing parameters include a maximum value and a minimum value for each nominal signal timing parameter.

[0063] The previously described versions of the disclosed subject matter have many advantages that have either been described or are obvious to a person of ordinary skill. However, these advantages or features are not required in all versions of the disclosed devices, systems, or methods.

[0064] Furthermore, this written description refers to specific features. It is understood that the disclosure in this specification encompasses all possible combinations of these particular features. Where a particular feature is disclosed in connection with a particular aspect or example, that feature may, where possible, also be used in connection with other aspects and examples.

[0065] Although this application refers to a method comprising two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context precludes such possibilities.

[0066] Although specific examples of the invention have been shown and described for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 202321057202

[0001]

Claims

[1] A test and measuring instrument that includes: one or more processors configured to control acquisition of a plurality of electrical signals transmitted over an electrical bus according to a bus protocol by a device under test; and a bus timing characteristics analyzer configured to perform the following: Identifying nominal signal timing parameters for the sensed plurality of electrical signals, wherein the nominal signal timing parameters are defined by the bus protocol and define timing criteria for the plurality of electrical signals; Measuring operating signal timing parameters for each of the acquired plurality of electrical signals; Comparing the operating signal timing parameters with the nominal signal timing parameters for each of the detected plurality of electrical signals to determine whether the operating signal timing parameters meet the timing criteria; and Displaying a visual indication for each of the plurality of electrical signals on the test and measurement instrument indicating whether the operating signal timing parameters for the electrical signal meet the timing criteria. [2] The test and measurement instrument of claim 1, wherein the bus timing characteristics analyzer is further configured to measure the operating signal timing parameters for each of the acquired plurality of electrical signals to perform the following: Detecting edges in each of the acquired electrical signals; Determine whether each edge is a rising or falling edge; and Measuring the operating signal timing parameters for each of the acquired plurality of electrical signals using the rising and falling edges of the electrical signal. [3] The test and measurement instrument of claim 2, wherein the sensed plurality of electrical signals comprises at least one data signal, and wherein the operating signal timing parameters for the at least one data signal include a rise time measured for each rising edge and a fall time measured for each falling edge of the at least one data signal. [4] The test and measurement instrument of claim 3, wherein the nominal signal timing parameters comprise a nominal rise time signal timing parameter and a nominal fall time signal timing parameter, and wherein the bus timing characteristics analyzer is further configured to perform the following: Comparing the measured rise time for each rising edge with the nominal rise time signal timing parameter for the at least one data signal; and Comparing the measured fall time for each falling edge with the nominal fall time signal timing parameter for the at least one data signal. [5] The test and measurement instrument of claim 4, wherein the nominal rise time signal timing parameter includes a range around a nominal value, the range being defined by a minimum and a maximum allowable value for the nominal rise time signal timing parameter, and wherein the nominal fall time signal timing parameter includes a range around a nominal value, the range being defined by a minimum and a maximum allowable value for the nominal fall time signal timing parameter, and wherein the bus timing characteristics analyzer is further configured to perform the following: Determining whether the measured rise time for each rising edge of the at least one data signal has a value within the range of the nominal rise time signal timing parameter; and Determining whether the measured fall time for each falling edge of the at least one data signal has a value within the range of the nominal fall time signal timing parameter. [6] The test and measurement instrument of claim 5, wherein the nominal signal timing parameters further comprise a setup time tSU and a hold time tHD for the at least one data signal. [7] The test and measurement instrument of any one of claims 1 to 6, wherein the sensed plurality of electrical signals further includes a clock signal, and wherein the nominal signal timing parameters for the clock signal comprise a nominal clock frequency, a nominal rise time signal timing parameter, and a nominal fall time signal timing parameter. [8] The test and measurement instrument of any one of claims 1 to 7, wherein the visual indication for each of the plurality of electrical signals indicates a pass condition when all operating signal timing parameters satisfy the timing criteria for the electrical signal, and indicates a fail condition when one or more of the operating signal timing parameters do not satisfy the timing criteria. [9] The test and measurement instrument according to any one of claims 1 to 8, wherein the electrical bus is one of the following: an I2C (inter-integrated circuit) bus, an I3C or "feedback" bus, an RS-232 bus, a USB (universal serial bus), an embedded USB (eUSB) bus, an SPI (serial peripheral interface) bus, an embedded SPI (eSPI) bus, and a SENT bus. [10] The test and measurement instrument according to any one of claims 1 to 9, wherein the test and measurement instrument comprises an oscilloscope. [11] A test and measurement system comprising: a series of electronic devices; an electrical bus interconnecting the electronic devices, wherein one of the electronic devices is a device under test (DUT), and the electrical bus carries electrical signals having nominal signal timing parameters defined by a bus protocol of the electrical bus, the nominal signal timing parameters defining timing criteria for the electrical signals; and a test and measuring instrument comprising: one or more processors configured to control the acquisition of the electrical signals; and a bus timing characteristics analyzer configured to perform the following: Identifying nominal signal timing parameters for the acquired electrical signals, wherein the nominal signal timing parameters are defined by the bus protocol and specify timing criteria for the electrical signals; Measuring operating signal timing parameters for each of the acquired electrical signals; Comparing the operating signal timing parameters with the nominal signal timing parameters for each of the acquired electrical signals to determine whether the operating signal timing parameters meet the timing criteria; and Displaying a visual indication for each of the electrical signals on the test and measurement instrument that indicates whether the operating signal timing parameters for the electrical signal meet the timing criteria. [12] The test and measurement system of claim 11, wherein the electrical bus is one of the following: an I2C (inter-integrated circuit) bus, an I3C or "feedback" bus, an RS-232 bus, a USB (universal serial bus), an embedded USB (eUSB) bus, a SPI (serial peripheral interface) bus, an embedded SPI (eSPI) bus, and a SENT bus. [13] The test and measurement system of claim 11 or 12, wherein the test and measurement instrument further comprises a memory, and wherein the nominal signal timing parameters are stored in the memory. [14] The test and measurement system according to any one of claims 11 to 13, wherein the test and measurement instrument comprises an oscilloscope. [15] The test and measurement system of any one of claims 11 to 14, wherein the sensed electrical signals comprise a clock signal and a data signal, wherein the nominal signal timing parameters comprise rise time and fall time signal timing parameters for rising and falling edges of the clock and data signals, and further comprise a frequency signal timing parameter for the clock signal. [16] The test and measurement system of any one of claims 11 to 15, wherein the test and measurement instrument further comprises a protocol decoder configured to translate bit sequences upon detection of electrical signals into frames according to the bus protocol of the electrical bus. [17] A method for measuring operating signal timing parameters of electrical signals transmitted over an electrical bus, the method comprising: Retrieving nominal signal timing parameters for the electrical signals by a test and measurement instrument, wherein the nominal signal timing parameters are defined by a bus protocol of the electrical bus and define timing criteria for the electrical signals; Capturing the electrical signals in the test and measuring instrument; Detecting edges in the acquired electrical signals in the test and measuring instrument; Measuring operating signal timing parameters associated with the sensed edges of the sensed electrical signals in the test and measurement instrument; Comparing the operating signal timing parameters with the nominal signal timing parameters in the test and measurement instrument to determine whether the operating signal timing parameters meet the timing criteria; Saving the results of the comparison in the test and measuring instrument and Display, on the test and measuring instrument, a pass or fail indication for each of the electrical signals based on the stored results of the comparison. [18] The method of claim 17, wherein the electrical bus is an I2C bus and the electrical signals comprise a clock signal and a data signal. [19] The method of claim 18, wherein the nominal signal timing parameters comprise: a rise time tRise for each rising edge of clock and data signals, a fall time tFall for each falling edge of the clock and data signals, a clock frequency tFreq of the clock signal, a hold start condition time tHD;STA, a minimum low clock period tLOW, a minimum high clock period tHIGH, a data hold time tHD;DAT, a setup start condition time tSU;DAT, a setup start condition time tSU;STA, a hold start condition time tHD;STA, a setup stop condition time tSU;STO and a bus-free time tBUF. [20] The method of any one of claims 17 to 19, wherein the nominal signal timing parameters comprise a maximum value and a minimum value for each nominal signal timing parameter.

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