DATA STORAGE DEVICE AND METHOD FOR MITIGATING READ DISTURBANCES IN POWER SAVING MODES

Abstract

A data storage device may verify data integrity on a wordline in a memory each time the data storage device exits power-saving mode. Frequent exits from power-saving mode result in the wordline being read many times, which may lead to a read disturb problem. To mitigate this problem, in one embodiment disclosed herein, a different wordline is used to verify data integrity each time out of a plurality of times the data storage device exits a power-saving mode. Using different wordlines for the data integrity check may reduce the likelihood of a read disturb error. Other embodiments are disclosed.

Description

BACKGROUND

[0001] Some data storage devices are configured to support a power-saving mode. Generally, power-saving mode refers to an operating state of the data storage device that reduces power consumption when it is not performing a task. Power-saving mode can improve energy efficiency and meet a host's performance specifications (e.g., to extend the host's battery life). During the transition between active and power-saving modes, the data storage device can execute procedures to ensure data integrity in the data storage device's memory. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a block diagram of a data storage device of one embodiment. Fig. 1B is a block diagram illustrating a storage module of one embodiment. Fig. Figure 1C is a block diagram illustrating a hierarchical storage system of one embodiment. Fig. Figure 2A is a block diagram showing components of the controller of the Fig. 1A according to one embodiment. Fig. Figure 2B is a block diagram showing components of the Fig. 1A according to one embodiment. Fig. 3 is a block diagram of a host and a data storage device of one embodiment. Fig. 4 is a flowchart of an embodiment method for estimating the bit error rate (BER) when exiting a power saving mode. Fig. 5 is a flowchart of a method of one embodiment for a BER estimating read trigger. Fig. 6 is a diagram illustrating exiting a power saving mode of one embodiment. Fig. 7 is a diagram illustrating exiting a power saving mode of one embodiment. Fig. 8 is a diagram illustrating an embodiment in which relocation is triggered due to a high BER detection. Fig. 9 is a table illustrating occurrences of a read interference problem of one embodiment. Fig. 10 is a flowchart of an embodiment method for mitigating read disturbances during a power saving mode. DETAILED DESCRIPTION

[0002] The following embodiments generally relate to a data storage device and method for mitigating read disturbances in power-saving mode. In one embodiment, a data storage device is provided that includes a memory and one or more processors.The processor(s) are configured, individually or in combination, to: receive a command from a host to exit a power saving mode; and in response to receiving the command from the host to exit the power saving mode: randomly select a word line from a set of word lines in the memory designated for an active read scan; perform a bit error rate (BER) check on the randomly selected word line and its neighboring word lines; determine whether a BER error exists on the randomly selected word line or its neighboring word lines; and in response to determining that a BER error exists on the randomly selected word line or its neighboring word lines, perform a BER estimation scan (BES) of the memory.

[0003] In another embodiment, a method is provided that is performed in a data storage device having a memory. The method comprises: each time in a plurality of times that the data storage device transitions from a power saving mode to an active mode: selecting a wordline in the memory, wherein in response to each of the plurality of times a different wordline is selected; determining whether a number of errors in the selected wordline is above a threshold; and in response to determining that the number of errors in the selected wordline is above the threshold, relocating data in the selected wordline to a different wordline in the memory.

[0004] In another embodiment, a data storage device is provided, comprising: a memory; and means for checking data integrity on a different word line in the memory each of a plurality of times that the data storage device exits a power saving mode, wherein checking data integrity on different word lines reduces a likelihood of a read disturb error.

[0005] Other embodiments are possible, and each of the embodiments may be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the accompanying drawings. Embodiments

[0006] The following embodiments relate to a data storage device (DSD). As used herein, a "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Details of example DSDs are provided below.

[0007] Examples of data storage devices suitable for use in implementing aspects of these embodiments are described in Fig. 1A to 1C. Note that this is purely exemplary, and other implementations may be used. Fig. 1A is a block diagram illustrating the data storage device 100 according to one embodiment. Referring to Fig. 1A, the data storage device 100 in this example includes a controller 102 coupled to a non-volatile memory, which may be constructed from one or more non-volatile memory dies 104. As used herein, the term "die" refers to the collection of non-volatile memory cells and associated circuitry for managing the physical operation of these non-volatile memory cells formed on a single semiconductor substrate. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory die 104. Additionally, the phrase "in communication with" or "coupled with" could mean directly in communication / coupled with or indirectly in communication / coupled with via one or more components that may or may not be shown or described herein.Communication / coupling can be wired or wireless.

[0008] The controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random access memory (ReRAM), phase change memory (PCM), or magnetoresistive random access memory (MRAM) controller)) may include one or more components, individually or in combination, configured to perform certain features, including, but not limited to, the functions described herein and illustrated in the flowcharts. For example, the controller 102 may, as shown in Fig. 2A, one or more processors 138, individually or in combination, configured to perform functions such as, but not limited to, the functions described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-volatile memories 139 within the controller 102 and / or external to the controller 102 (e.g., in the random access memory (RAM) 116 or in the read-only memory (ROM) 118). As another example, the one or more components may include circuit logic, such as, but not limited to, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller.

[0009] In one embodiment, non-volatile memory controller 102 is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device, using any suitable operating system. Non-volatile memory controller 102 may have various functionalities in addition to the specific functionality described herein. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory is operating properly, map defective non-volatile memory cells, and allocate spare cells to replace future defective cells.A portion of the spare cells can be used to hold firmware (and / or other metadata used for housekeeping and tracking) to run the non-volatile memory controller and implement other features. During operation, when a host needs to read or write data to non-volatile memory, it can communicate with the non-volatile memory controller. If the host provides a logical address to read / write data to, the non-volatile memory controller can translate the logical address received from the host into a physical address in the non-volatile memory.The non-volatile memory's memory controller can also perform various memory management functions, including, but not limited to, wear leveling (spreading out writes to avoid wearing out certain memory blocks that would otherwise be repeatedly written to) and garbage collection (after a block is full, only the valid data pages are moved to a new block so that the full block can be erased and reused).

[0010] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state memory cells (e.g., flash memory cells) and may be one-time programmable, multi-time programmable, or multi-time programmable. The memory cells may also be single-level cells (SLC), multiple-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or use other memory cell-level technologies now known or later developed. In addition, the memory cells may be fabricated in a two-dimensional or three-dimensional manner.

[0011] The interface between the controller 102 and the non-volatile memory die 104 may be any suitable flash interface, such as a toggle mode 200, 400, or 800. In one embodiment, the data storage device 100 may be a card-based system, such as a Secure Digital (SD) card or a micro Secure Digital (micro SD) card. In an alternative embodiment, the data storage device 100 may be part of an embedded data storage device.

[0012] Although in the Fig. 1A, the data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104, the subject matter described herein is not limited to a single memory channel. For example, in some architectures (such as those shown in Fig. 1B and Fig. 1C), depending on controller capabilities, two, four, eight, or more memory channels may be present between the controller and the memory device. In any of the embodiments described herein, more than a single channel may be present between the controller and the memory die, even if a single channel is shown in the drawings.

[0013] Fig. 1B illustrates a storage module 200 including a plurality of non-volatile data storage devices 100. As such, the storage module 200 may include a storage controller 202 connected to a host and to the data storage device 204 including a plurality of data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interface Express (PCIe) interface, a Double Data Rate (DDR) interface, or a Serial Attached Small Scale Computing (SAS / SCSI) interface.The storage module 200, in one embodiment, may be a solid state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), such as found in a server PC or in portable computing devices such as laptop computers and tablet computers.

[0014] Fig. 1C is a block diagram illustrating a hierarchical storage system. A hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a respective data storage device 204. Host systems 252 may access storage within the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) interface or a Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the Fig. The system illustrated in Figure 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as might be found in a data center or other location where mass storage is required.

[0015] With further reference to Fig. 2A, the controller 102 in this example also includes a front-end module 108 that interfaces with a host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in the RAM 116 and controls the internal bus arbitration of the controller 102. A module may include one or more processors or components, as discussed above. The ROM 118 may store the system boot code. Although in Fig. 2A as being disposed separately from the controller 102, in other embodiments, either or both of the RAM 116 and ROM 118 may be disposed within the controller 102. In still other embodiments, portions of the RAM 116 and the ROM 118 may be located both within the controller 102 and external to the controller 102.

[0016] The front-end module 108 includes a host interface 120 and a physical layer (PHY) interface 122, which provide the electrical interface with the host or the next-level storage controller. The choice of host interface 120 type may depend on the type of storage used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serially Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. The host interface 120 typically supports the transfer of data, control signals, and clock signals.

[0017] The backend module 110 includes an error correction code (ECC) engine 124, which encodes the data bytes received from the host and decodes and error-corrects the data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, for transmission to the non-volatile memory die 104. A RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of corrupted data. RAID parity can be used as an additional level of integrity protection for the data written to the storage device 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides the command sequences for the non-volatile memory die 104 and receives status information from the non-volatile memory die 104.In one embodiment, the memory interface 130 may be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. The controller 102, in this example, also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the back-end module 110.

[0018] The data storage device 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may be connected to the controller 102. In alternative embodiments, one or more of the physical layer interface 122, the RAID module 128, the media management layer 138, and the buffer management / bus controller 114 are optional components that are not required in the controller 102.

[0019] Fig. 2B is a block diagram illustrating components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes the non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 further includes a data cache 156 that temporarily stores data. The peripheral circuitry 141 in this example includes a state machine 152 that provides status information to the controller 102.Peripheral circuitry 141 may also include one or more components configured, individually or in combination, to perform particular functions, including, but not limited to, the functions described herein and illustrated in the flowcharts. For example, memory die 104, as shown in FIG. Fig. 2B, one or more processors 168, individually or in combination, configured to execute computer-readable program code stored in one or more non-volatile memories 169, in the memory array 142, or external to the memory die 104. As another example, the one or more components may include circuit logic, such as, but not limited to, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller.

[0020] In addition to or instead of the one or more processors 138 (or general components) in the controller 102 and the one or more processors 168 (or general components) in the memory die 104, the data storage device 100 may include another set of one or more processors (or general components). In general, one or more processors (or general components) in the data storage device 100, regardless of location and number, may be configured individually or in combination to perform various functions, including, but not limited to, the functions described herein and illustrated in the flowcharts. For example, the one or more processors (or components) may be located in the controller 102, in the memory device 104, and / or elsewhere in the data storage device 100.Furthermore, different functions may be performed using different processors (or components) or combinations of processors (or components). Furthermore, means for performing a function may be implemented with a controller having one or more components (e.g., processors or the other components described above).

[0021] Referring again to Fig. 2A, the flash control layer 132 (referred to herein as the flash translation layer (FTL)) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm in firmware, is responsible for the internal operations of memory management and translates writes from the host into writes to memory 104. The FTL may be needed because memory 104 may have a limited lifetime, may only be written in multiples of pages, and / or may not be written to unless erased as a block. The FTL is aware of these potential limitations of memory 104, which may not be visible to the host. Accordingly, the FTL attempts to translate the writes from the host into writes to memory 104.

[0022] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table or a data structure) and an allocated cache memory. In this way, the FTL translates logical block addresses ("LBAs") from the host into physical addresses in memory 104. The FTL may include other features, such as, but not limited to, power-off recovery (so that the FTL's data structures can be restored in the event of a sudden power loss) and wear leveling (so that wear is even across memory blocks to prevent certain blocks from experiencing excessive wear, which would result in a greater likelihood of failure).

[0023] Referring again to the drawings, Fig. 3 is a block diagram of a host 300 and the data storage device 100 of one embodiment. The host 300 may take any suitable form, including, but not limited to, a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a surveillance system, etc. The host 300 in this embodiment (herein, a computing device) includes one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in the one or more memories 340 directs the one or more processors 330 to perform the actions described herein that are performed by the host 300. Thus, actions performed by the host 300 are sometimes referred to herein as being performed by an application (computer-readable program code) executing on the host 300.For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0024] The data storage device 100 may be configured to support a power saving mode (LPM). Generally, the power saving mode refers to an operating state of the data storage device 100 intended to reduce power consumption when it is not performing a task. The power saving mode may improve energy efficiency and meet the performance specifications of the host 300 (e.g., to extend the battery life of the host 300). In some embodiments, the data storage device 100 may operate in an active mode (P0 / P1 / P2) or in a power saving mode (PS3 / PS4 / PS5). When the data storage device 100 transitions from one power mode to another (e.g., from power mode A to power mode B), this is referred to as exiting mode A and entering mode B.During entry and exit from a power mode, the controller 102 of the data storage device 100 may perform specific procedures to ensure data integrity in the memory 104. There are situations where the host 300 may actively utilize the power saving mode to conserve power by frequently switching between active and power saving modes. However, the memory 104 of the data storage device 100 may only support limited read disturbances / endurance.

[0025] Read noise issues can occur when transitioning between power modes. During a read operation, a voltage is applied to a memory cell (e.g., a specific word line in NAND memory) to measure the stored charge and determine the data value. During repeated read operations, neighboring cells (word lines) can be affected by the voltage applied during the read operation. The word lines (WL+1 and WL-1) closest to the read word line (WL) are most affected by this problem, and this phenomenon is called read noise.

[0026] Due to current technological advances in the personal computing industry, there is often a need to operate a data storage device with the lowest possible power consumption. Currently, there is no specific standard or JEDEC specification that prescribes a fixed number of times a data storage device should enter power-saving mode. Without an established industry standard or restriction on transitioning to power-saving mode, it is expected that a significant number of power-saving mode requests will arise, and that data storage devices will need to handle them accordingly.

[0027] During the transition from power save mode to active mode (LPM to active), the controller 102 in the data storage device 100 lacks information about the duration of the power save mode. This timing uncertainty in the prompts causes the system to check for potential reliability issues during the power save mode. To address these reliability concerns, the controller 102 may perform an initial read operation, referred to as a bit error rate (BER) estimation read, to assess the impact on the reliability of the memory 104. Because the BER estimation read helps optimize read levels, this may be a common requirement for data storage devices. A "first-read problem" may occur because the bit error rate may depend on the time between the last access to a memory block and a subsequent read operation.When blocks are in the first read state, a read decode error may occur if there is a long delay between reads or power-on and power-off.

[0028] The inventors made two important observations while analyzing data storage devices that failed due to read failures in customer environments. First, the host 300 requested approximately 5 to 7 million transitions to power-saving mode within a short period of time. Second, the power-saving frequency for each power-saving mode (average time) is calculated to be ≈0.2 seconds per power-saving mode.

[0029] Referring again to the drawings, Fig. 4 is a flowchart 400 of a method of one embodiment for estimating the bit error rate (BER) when exiting a power saving mode. As in Fig. 4, in response to a power save mode (LPM) exit request N (action 410), controller 102 performs a read operation with BER estimation on word line (WL) 31 (actions 420 and 430). This is followed by an LPM exit request for N+1 (action 440). As shown in the graphic in Fig. As shown in Figure 4, requesting a BER estimation on WL31 when exiting the power saving mode results in a read disturbance on the neighboring word lines WL30 and WL32.

[0030] Given the high transition frequency, controller 102 can only manage a single read operation for each power-saving mode before returning to power-saving mode. Controller 102 always returns to power-saving mode on the first read. Given the significant volume of power-saving mode transitions, approximately 5 to 7 million power-saving mode transitions can result in a corresponding number of read operations. The read operations with BER estimation are typically limited to a specific block and a specific wordline within the block. This, in turn, increases the likelihood of read disturbances occurring on the adjacent wordline.

[0031] To investigate the effects of read disturbances, the inventors conducted an experiment that found that performing approximately 150,000 consecutive read operations on a word line is sufficient to trigger read disturbances on neighboring word lines. However, the data also shows that the host entered power-saving mode approximately 5 to 7 million times, which can further exacerbate the read disturbance problem. The bit error rate profile across the word lines showed that the word lines were affected by the read disturbance problem caused by consecutive read operations during power-saving mode transitions. Power-saving mode LPM transitions can be as high as ≈10 million, while the need to perform read operations with BER estimation to achieve an optimal read operation level remains unchanged.Nevertheless, it may be necessary to mitigate the risk of read disturbance problems caused during power-saving mode transitions. The following embodiments provide versioning solutions to this problem.

[0032] One embodiment utilizes an "always-on timer" (an "AON timer"). An AON timer is a type of timer in electronic devices that operates independently of the main system or processor. AON timers operate even when the device is in a power-saving mode or in a sleep mode. AON timers ensure precise timing and perform specific functions at specified intervals, even when the main system is inactive. In this embodiment, an AON timer (e.g., in controller 102) accumulates the duration (e.g., drive duration in each power state) of each power-saving mode (PS3 / PS4 / PS5) and decides whether the read operation with BER estimation is necessary. A time threshold (e.g., "X hours") can be set, and only when the cumulative time in the power saving mode exceeds this threshold does the controller 102 perform a read with BER estimation to optimize the read levels.

[0033] Referring again to the drawings, Fig. 5 is a flowchart 500 of a method of one embodiment for triggering a read operation with BER estimation. As in Fig. 5, after starting the method (action 510), the controller 102 performs an initialization process in which the low power mode (LPM) transitions to the active state (action 520). Next, the controller 102 checks the always-on timer (AON) timer value (action 530) and determines whether the AON timer value is greater than or equal to the BER scan time threshold (action 540). If the AON timer value is not greater than or equal to the BER scan time threshold, the controller 102 proceeds with the regular initialization process (action 550), and the method ends (action 560). However, if the AON timer value is greater than or equal to the BER scan time threshold, the controller 102 initiates a BER estimation read operation (action 570) and determines whether the BER scan was successful (action 580). If the BER scan was successful, the controller 102 proceeds with the regular initialization process (action 550) and the method ends (action 560).However, if the BER scan was unsuccessful, the controller 102 triggers a BER estimation scan (BES) and, if necessary, another relocation is performed (action 590), after which the procedure ends (action 560).

[0034] As this example demonstrates, using an AON timer-based approach offers the advantage of managing the frequency of read triggers for BER estimation during power-save mode transitions, preventing unnecessary BER estimations and ensuring that these estimations occur only at necessary intervals (e.g., every six hours of cumulative time in power-save mode (taking all LPM states into account)). This strategy effectively addresses the risk of read disturbances while maintaining the reliability specifications of the data storage device.For example, in a situation where there are a total of 5.4 million power-saving mode transitions and 414 hours of operation, using this embodiment with a time threshold of six hours (based on an estimated three-year data storage device lifetime) may result in approximately 70 BER-estimated reads, compared to approximately 5.4 million BER-estimated reads when this embodiment is not used. This significant reduction in BER-estimated reads reduces the risk of read disturbance.

[0035] Another embodiment uses an active read scan (ARS) to scan memory 104 and minimize reliability risks. ARS is a read scrub algorithm designed to verify the quality of the data stored in each physical block of memory 104 and relocate it to a new location before it becomes unreadable. ARS can be used to address phenomena such as program crashes and read crashes, which tend to compromise the integrity of the data stored in memory 104 and can lead to high BER events, correctable error-correcting code (CECC) events, or uncorrectable error-correcting code (UECC) events that impact system performance and the defective parts per million (DPPM) of the product. ARS can be a periodic operation performed by controller 102.For example, the controller 102 may perform ARS every 24 hours on a set of word lines (e.g., about 20 word lines) that are scanned during a BER test.

[0036] In this embodiment, controller 102 uses these ARS wordlines as part of the BER test during a transition to power-saving mode. Controller 102 can add the neighboring wordlines to the scan list so that any read disturb phenomena can be identified by the controller's ARS scan algorithm. Currently, the wordline for BER estimation in power-saving mode is fixed to a single wordline within a block. Instead of a fixed wordline, in this embodiment, controller 102 can randomly select "X" (e.g., 20) wordlines from the list of ARS wordlines, and the BER test can be performed on the random wordline. In this way, read disturb can be distributed across a set of wordlines within a block, rather than concentrating on just one wordline.In addition, these wordline sets are already part of the ARS scan, and in the event of a read fault, these wordlines are scanned and the block is relocated.

[0037] In summary, this embodiment reduces the risk of read disturbances by distributing the read operations across multiple wordlines and providing protection to these wordlines using ARS and a neighboring wordline scan algorithm. This embodiment will now be described in connection with Fig. 6 to 8 further illustrates this.

[0038] Fig. Figure 6 is a diagram illustrating exiting a power-saving mode using an approach where each power-saving transition is forwarded as a read operation with BER estimation to a fixed wordline (here, WL31). Consecutive read operations may cause read disturbances on the adjacent wordlines (here, WL30 and WL32). Fig. Figure 7 is a diagram illustrating exiting a power saving mode using the approach of this embodiment. As in Fig. As shown in Figure 8, in this embodiment, the controller 102 randomly selects a wordline among the ARS wordlines (e.g., 20 wordlines) to perform the BER estimation read operation. This reduces the read disturbance impact of a single wordline. If the BER on the neighboring wordlines is high due to consecutive transitions to power-saving mode, the ARS scan will detect this (the neighboring wordlines are already part of the ARS wordlines) and relocate the block. Fig. Figure 9 is a table illustrating the prevalence of a dyslexia problem.

[0039] Fig. 10 is a flowchart 1000 of a method of one embodiment for mitigating read disturbances during a power saving mode. As in Fig.10, upon exiting power management mode (LPM) (action 1010), controller 102 retrieves a list of ARS wordlines (action 1020). Next, controller 102 randomly selects (purely randomly or pseudorandomly) any ARS wordline based on firmware randomization logic for BER checking (action 1030). Controller 102 then initiates BER checking of the randomly selected ARS wordline plus its neighboring wordlines (action 1040). (Other types of error checking may be used instead of, or in addition to, a BER check.) Next, controller 102 determines whether a BER error exists on any of the ARS wordlines or neighboring wordlines (action 1050). If no BER error is detected, controller 102 proceeds with regular initialization (action 1060).However, if a BER error is detected, the controller 102 initiates a (BER) estimation scan (BES) and performs further relocation if necessary (action 1070).

[0040] Several advantages are associated with these embodiments. For example, a data storage device may undergo millions of power-save transitions, which can cause read disturbances. This can occur in situations where the host attempts to conserve power by frequently switching between active mode and power-save mode. Given the uncertainty of whether the data storage device will remain in power-save mode during the transition from power-save to active mode, the embodiments presented herein can be used to aid in optimizing read operation levels to mitigate any reliability issues caused during the power-save state. Optimizing the read operation level can also be accomplished by performing a BER-estimated read on one of the blocks.During consecutive power-save transitions, each power-save transition may result in a read operation with BER estimation, and performing consecutive reads on a block may result in read-disturbance phenomena in the block. Furthermore, as mentioned above, up to 10 million power-save transitions may be possible, and a significant number of data storage devices may exhibit signs of read-disturbance. These embodiments can be used to address this issue by effectively mitigating the problem of read-disturbance during the power-save transition.

[0041] Furthermore, the data storage device of these embodiments can support more transitions to power-saving mode throughout the lifetime of the data storage device without compromising reliability. As data storage devices move more aggressively toward power-saving schemes, these embodiments can be used to prepare data storage devices for future use cases. Additionally, these embodiments can provide future implementation flexibility by allowing the BER check times to continue to be configured within the firmware / system handling. Depending on future storage health, users can reduce / increase the frequency and flexibly change the timing.Additionally, limited reads for BER estimation in the power-save path can improve power-save exit latency, allowing the storage device to be ready for host operations faster than before. For example, assuming a 1-terabyte drive capacity with eight memory dies, each with 48 timestamp read levels, the storage device can be approximately 30 ms faster each time it exits power-save mode. This results in a more robust storage device capable of supporting a high number of power-save transitions. Regarding timestamp updating, CVD tracking is a system solution that manages read level offsets to minimize read errors and prevent LDPC decode throughput from becoming the bottleneck for read performance.Periodic timestamp updating is the process of keeping timestamp parameters (read operation levels) updated, especially after a power cycle or a transition to low power mode.

[0042] Finally, as mentioned above, any suitable type of memory may be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0043] The memory devices may be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching memory element, such as an anti-fuse, phase-change material, etc., and optionally a steering element, such as a diode, etc. Further, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements including a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric material for charge storage.

[0044] Multiple storage elements may be configured to be connected in series or such that each element is individually accessible. As a non-limiting example, flash memory devices in a NAND (NAND memory) configuration typically include storage elements connected in series. A NAND memory array may be configured such that the array is composed of multiple memory chains, in which a chain is composed of multiple storage elements that share a single bit line and are accessed as a group. Alternatively, storage elements may be configured such that each element is individually accessible, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be configured otherwise.

[0045] The semiconductor memory elements arranged in and / or above a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0046] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, memory elements in a two-dimensional memory structure are arranged in a plane (e.g., a plane in the xz direction) that extends substantially parallel to a major surface of a substrate supporting the memory elements. The substrate may be a wafer over or in which the layer of memory elements is formed, or it may be a carrier substrate that is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0047] The memory elements may be arranged in an ordered array, such as in a plurality of rows and / or columns, at the individual memory device level. However, the memory elements may be arranged in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0048] A three-dimensional memory array is arranged such that memory elements occupy multiple levels or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, with the y direction being substantially perpendicular and the x and z directions being substantially parallel to the main surface of the substrate).

[0049] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As a further non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements in each column. The columns may be arranged in a two-dimensional configuration, e.g., in an xz-plane, resulting in a three-dimensional array of memory elements with elements on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions may also form a three-dimensional memory array.

[0050] As a non-limiting example, the memory elements in a three-dimensional NAND memory array may be coupled together to form a NAND chain within a single horizontal (e.g., xz) memory device plane. Alternatively, the memory elements may be coupled together to form a vertical NAND chain spanning multiple horizontal memory device planes. Other three-dimensional configurations may be contemplated, with some NAND chains including memory elements in a single memory plane, while other chains including memory elements spanning multiple memory planes. Three-dimensional memory arrays may also be configured in a NOR configuration and a ReRAM configuration.

[0051] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also include one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers forming the individual memory device levels of the array are typically formed on top of the layers of the underlying memory device levels of the array. However, layers may be shared by adjacent memory device levels of a monolithic three-dimensional memory array or may include intermediate layers between memory device levels.

[0052] Then, in turn, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, non-monolithic stacked memories can be constructed by forming memory planes on separate substrates and then stacking the memory planes on top of each other. The substrates can be thinned or removed from the memory device planes before stacking, but because the memory device planes are initially formed over separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked-chip memory device.

[0053] Dedicated circuitry is typically required for the operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may include circuitry used to control and drive memory elements to perform functions such as programming and reading. This dedicated circuitry may be located on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory write / read operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0054] Those skilled in the art will recognize that this invention is not limited to the described two-dimensional and three-dimensional structures, but covers all relevant memory structures within the spirit and scope of the invention as described herein and as understood by those skilled in the art.

[0055] It is intended that the foregoing detailed description be construed as an illustration of selected forms the invention may take, rather than as a definition of the invention. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it is to be understood that each aspect of each of the embodiments described herein may be used alone or in combination with one another.

Claims

[1] Data storage device, comprising: a memory; and one or more processors, individually or in combination, configured to: Receiving a command from a host to exit a power saving mode; and in response to receiving the command from the host to exit power saving mode: randomly selecting a word line from a set of word lines in the memory designated for an active read scan; Performing a bit error rate (BER) test on the randomly selected word line and its neighboring word lines; Determining whether a BER error exists on the randomly selected word line or its neighboring word lines; and in response to determining that a BER error exists on the randomly selected wordline or its neighboring wordlines, performing a BER estimation scan (BES) of the memory. [2] The data storage device of claim 1, wherein a different word line is randomly selected from the set of word lines each time the power saving mode exit command is received. [3] The data storage device of claim 1, wherein the one or more processors, individually or in combination, are further configured to: in response to determining that a BER error exists on the randomly selected word line or its neighboring word lines, relocating the block containing the randomly selected word line or its neighboring word lines. [4] The data storage device of claim 1, wherein the one or more processors, individually or in combination, are further configured to: in response to determining that there is no BER error on the randomly selected wordline or its neighboring wordlines, performing an initialization process. [5] The data storage device of claim 1, wherein the one or more processors, individually or in combination, are further configured to: Determining the set of word lines in the memory designated for the active read scan. [6] A data storage device according to claim 1, wherein the memory comprises a three-dimensional memory. [7] In a data storage device comprising a memory, a method comprising: each time in a plurality of times that the data storage device transitions from a power saving mode to an active mode: selecting a word line in the memory, wherein a different word line is selected in response to each of the plurality of times; Determining whether a number of errors in the selected word line is above a threshold; and in response to determining that the number of errors in the selected word line is above the threshold, shifting data in the selected word line to another word line in the memory. [8] The method of claim 7, wherein data in a block containing the selected word line is shifted to another block. [9] The method of claim 7, wherein a bit error rate (BER) test is used to determine whether the number of errors in the selected word line is above the threshold. [10] The method of claim 7, wherein the word line is selected from a subset of word lines that is considered to be relatively more error-prone than other word lines in the memory. [11] The method of claim 10, further comprising: Determine which word lines in the memory are included in the subset of word lines. [12] The method of claim 7, further comprising: Determining whether a number of defects in adjacent word lines of the selected word line is above the threshold; and in response to determining that the number of errors in the adjacent wordlines of the selected wordline is above the threshold, shifting data in the adjacent wordlines to other wordlines in the memory. [13] The method of claim 12, further comprising: Using an exclusive-or handling process to restore data in the adjacent word lines. [14] The method of claim 7, further comprising: Correct error(s) in the selected word line. [15] The method of claim 7, further comprising: Using an active read scan (ARS) to detect one or more errors on the selected wordline. [16] The method of claim 7, wherein a random process is used to select the word line. [17] The method of claim 7, further comprising: in response to determining that the number of errors in the selected word line is above the threshold, performing a bit error rate (BER) estimation scan (BES) of the memory. [18] The method of claim 7, further comprising: in response to determining that the number of errors in the selected word line is not above the threshold, performing an initialization process. [19] The method of claim 7, wherein the memory comprises a three-dimensional memory. [20] Data storage device comprising: a memory; and Means for checking data integrity on a different word line in the memory each of a plurality of times that the data storage device exits a power saving mode, wherein checking data integrity on different word lines reduces a likelihood of a read disturb error.

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