Performance module

Abstract

The invention relates to a power module (1), wherein the power module (1) has a carrier (2), the carrier (2) having an insulating layer (3) and a structured metallization (4) on a top surface of the insulating layer (3), wherein at least one planar bidirectional GaN transistor (9) is arranged on a first structure of the metallization (4), the GaN transistor having a silicon substrate (12), the bidirectional GaN transistor (9) having a first terminal (16) and a second terminal (17) as well as gate terminals (G1, G2), the first terminal (16) being electrically connected to a second structure (7) and the second terminal (17) being electrically connected to a third structure (8) of the metallization (4), the first, second and third structures (6-8) being electrically isolated from each other, and wherein at least one component is arranged between the first structure (6) and the second structure (7) and between the first structure (6) and the third structure (8).by means of which the first structure (6) is set to a defined potential.

Description

[0001] The invention relates to a power module with at least one planar bidirectional GaN transistor.

[0002] Bidirectional lateral GaN semiconductors offer significant advantages for some power electronic topologies. One topology where such a bidirectional switch can be advantageously used is the 3-level T-type topology. This topology also offers many advantages for applications as traction inverters, as motor losses can be significantly reduced. The high-side and low-side switches have almost identical requirements compared to a 2-level topology. However, the middle switch must be able to block voltage in both directions, which is why it is often implemented using two separate switches. The problem with this is that when using two MOSFETs, even with the same chip area, the conduction losses are doubled, which is why an additional switch must be connected in parallel to achieve the same conduction losses.For this reason, even with conventional GaN-FETs, four times the chip area is required if one wants to be able to block the voltage in both directions.

[0003] There is currently significant development activity aimed at compensating for precisely this negative effect of a four times larger chip area. This is expected to be achieved with bidirectional GaN switches. Various approaches exist, with the common-drain approach currently being the most popular and promising.

[0004] One embodiment of the common-drain is described in US 8,604,512 B2. The advantage of this approach is that the drift zone (the region where the majority of the two-dimensional electron gas (2DEG) forms) is shared. This allows for a smaller chip area, since the voltage gap must be maintained in this region, and this gap significantly impacts the area. However, all these approaches to a bidirectional lateral GaN switch suffer from the problem that, currently, a non-insulating silicon substrate is often used for cost reasons. If this substrate is not connected to a potential, effects such as threshold voltage shifts or dynamic increases in R can occur. DSon result.

[0005] For this reason, an approach was described in US 8,604,512 B2, US 2023 / 0282638A1, and US 2014 / 0374766A1A4 for applying a suitable voltage potential to the substrate within the semiconductor. A suitable voltage potential here means that the substrate should always be applied to the lower of the two terminals S1 / D2 and S2 / D1. The aim is to generate the same behavior as in a normal GaN HEMT, where the substrate is connected to the source. Various clamping circuits can be used for this purpose. For example, additional monolithically integrated switches or monolithically integrated diodes / resistors can be used to control the substrate.

[0006] Such a solution with monolithically integrated diodes is known, for example, from US 2022 / 0 416 777 A1.

[0007] The problem with this strategy is that additional chip area must be allocated on each semiconductor for this substrate potential control. This has a negative impact on the chip area.

[0008] Furthermore, this circuit is required for each switch in a parallel configuration, and these switches can negatively affect each other if the substrates are connected. This is the case, for example, when the switch and its substrate are mounted on a metallized substrate. Such a substrate could be, for example, a DCB or IMS substrate.

[0009] Furthermore, due to the poor conductivity of the substrate, a Schottky diode cannot be used between the substrate and the S / D or D / S terminals in such a setup to reduce losses during conduction in the third quadrant when off. This is particularly relevant for hard-switching applications with a high switching frequency (switches are only operated in this region during the turn-on delay of the delay, but due to the high voltage drop of the GaN FETs in this region, the losses are still significant at high switching frequencies).

[0010] The invention is based on the technical problem of creating a power module with at least one planar bidirectional GaN transistor, in which the problems described above are reduced.

[0011] The solution to the technical problem is achieved by a power module with the features of claim 1. Further advantageous embodiments of the invention are set out in the dependent claims.

[0012] The power module comprises a substrate, which includes an insulating layer and a structured metallization on the top surface of the insulating layer. The insulating layer is, for example, a ceramic. The substrate can be, for example, a DCB or IMS substrate. At least one planar bidirectional GaN transistor is mounted on a first metallization structure. The GaN transistor has a silicon substrate. Furthermore, the bidirectional GaN transistor has a first terminal, a second terminal, and two gate terminals. Depending on the current direction, the first and second terminals are the source terminal and the drain terminal, respectively. The first terminal is electrically connected to a second metallization structure, and the second terminal is electrically connected to a third metallization structure. This electrical connection can be made, for example, by means of bond wires.The first, second, and third structures are electrically isolated, with at least one component positioned between the first and second structures and between the first and third structures. This component sets the first structure to a defined potential, thereby also setting the silicon substrate to a defined potential. In essence, the substrate potential control is removed from the GaN transistor and replaced by an external substrate potential control, so the GaN transistor does not lose any chip area. A further advantage is that the heat generated by the components has no direct impact on the GaN transistor.

[0013] In one embodiment, the power module comprises two parallel-connected bidirectional GaN transistors whose silicon substrates are electrically connected. The external substrate potential control only needs to be simple.

[0014] In one embodiment, a first transistor and a second transistor are arranged on the first structure, the first transistor being connected to the second structure and the second transistor to the third structure. Preferably, the power module is configured such that the first transistor is switched on when the voltage potential at the first terminal is lower than at the second terminal, and the second transistor is switched on when the voltage potential at the first terminal is higher than at the second terminal.

[0015] In another embodiment, a driver circuit for the first and second transistors is monolithically integrated into the transistors, making the circuit quite compact.

[0016] In another embodiment, the first transistor and the second transistor are designed as GaN transistors.

[0017] In another embodiment, a Schottky diode is arranged in parallel to the first transistor and in parallel to the second transistor.

[0018] In an alternative embodiment, the components are not designed as transistors, but as a parallel circuit of a resistor and a diode, preferably a Schottky diode. The advantage is that no active control is required, although due to the resistor, the potentials of the first and second, or the first and third, structures are not completely equal.

[0019] In another embodiment, a further metallization is applied to the underside of the insulation layer, by means of which the power module can be connected to a heat sink, for example.

[0020] The invention is explained in more detail below with reference to preferred embodiments. The figures show: Fig. 1 a schematic representation of a power module in a first embodiment, Fig. 2 a schematic representation of a power module in a second embodiment and Fig. 3 a schematic representation of a 3-LT type inverter (state of the art).

[0021] In the Fig. Figure 3 shows a 3-level T-type inverter 100, which has three high-side switches S 1U and three low-side switches S 2U exhibits. Between a neutral point N and the center taps between high-side switches S 1U and low-side switch S 2U Each pair consists of two MOSFETs connected in opposite directions. 3U , S 4U arranged. These middle MOSFETs S 3U , S 4U are now to be replaced by at least one bidirectional planar GaN transistor.

[0022] In the Fig. Figure 1 shows a power module 1, which has a carrier 2 with an insulating layer 3 and a structured metallization 4 on the top side and another metallization 5 on the bottom side. The structured metallization 4 has a first structure 6, a second structure 7, and a third structure 8. The structured metallization 4 may have further structures. A planar bidirectional GaN transistor 9 is arranged on the first structure 6. The bidirectional GaN transistor 9 has a GaN layer 10, a buffer layer 11, and a silicon substrate 12, the silicon substrate 12 being electrically connected to the first structure 6 via a bonding layer 13 (e.g., as a solder or sintered layer). An AlGaN layer is deposited on the GaN layer 10, on which two P-GaN layers 15 are arranged side by side, each with a metallization.This forms a first gate contact G1 and a second gate contact G2. Furthermore, the GaN transistor 9 has a first terminal 16 and a second terminal 17, which function as either source or drain contacts depending on the current direction. The first terminal 16 is connected, for example, to the second structure 7 via a bond wire 18, and the second terminal 17 is connected, for example, to the third structure 8 via a bond wire 19. A first transistor 20 and a second transistor 21, configured, for example, as MOSFETs with intrinsic diodes, are also arranged on the first structure 6. The source terminal S3 of the first transistor 20 is connected to the first structure 6 via a bond wire 22. Similarly, the source terminal S4 of the second transistor 21 is connected to the first structure 6 via a bond wire 23.The drain terminal D3 of the first transistor 20 is connected to the second structure 7 via a bond wire 24 and the drain terminal D4 of the second transistor 21 is connected to the third structure 8 via a bond wire 25.

[0023] Depending on the current direction of the GaN transistor 9, the transistor 20 or 21 assigned to the respective source contact is switched on. That is, if the first terminal 16 operates as source contact S1, the first transistor 20 is switched on, so that source contact S1 is connected via the second structure 7 and the first transistor 20 to the first structure 6 and, via that, to the silicon substrate 12. Conversely, the first transistor 20 is switched off and the second transistor 21 is switched on when the second terminal 17 operates as source contact S2. Thus, the silicon substrate 12 is always connected to the lowest potential of the GaN transistor 9. Fig. Figure 1 above shows the corresponding equivalent circuit diagram.

[0024] In the Fig. Figure 2 shows an alternative embodiment of a power module 1. The only difference is that transistors 20 and 21 are made of Fig. 1 are replaced by a parallel circuit consisting of a resistor 26 and a diode 27. No active substrate control takes place here, but the substrate potential is fixed via the resistors 26 and can no longer float. Reference symbol list 1 power module 2 carriers 3 Insulation layer 4 structured metallization 5 further metallization 6 first structure 7 second structure 8 third structure 9 GaN transistor 10 GaN layers 11 Buffer layer 12 Silicon substrate 13. Compound layer 14 AlGaN layer 15 R-GaN layer 16 first connection 17 second connection 18 Bond wire 19 Bond wire 20 first transistor 21 second transistor 22 Bond wire 23 Bond wire 24 Bond wire 25 Bond wire 26 Resistance 27 Diode 100 3-Level-T-Type Inverters G1 first gate contact G2 second gate contact N Neutral point S1 Source Contact S2 Source Contact S 1U High-side switch S 2U Low-side switch

Claims

[1] Power module (1), wherein the power module (1) comprises a carrier (2), the carrier (2) comprising an insulating layer (3) and a structured metallization (4) on a top surface of the insulating layer (3), wherein at least one planar bidirectional GaN transistor (9) comprising a silicon substrate (12) is arranged on a first structure (6) of the metallization (4), the bidirectional GaN transistor (9) comprising a first terminal (16) and a second terminal (17) as well as gate terminals (G1, G2), wherein the first terminal (16) is electrically connected to a second structure (7) and the second terminal (17) is electrically connected to a third structure (8) of the metallization (4), wherein the first, second and third structures (6-8) are electrically isolated from each other, and wherein at least one component is arranged between the first structure (6) and the second structure (7) and between the first structure (6) and the third structure (8).by means of which the first structure (6) is set to a defined potential. [2] Power module (1) according to claim 1, characterized by , that the power module (1) has at least two parallel-connected bidirectional GaN transistors (9) whose silicon substrates (12) are electrically connected. [3] Power module (1) according to claim 1 or 2. characterized by , that on the first structure (6) a first transistor (20) and a second transistor (21) is arranged, wherein the first transistor (20) is connected to the second structure (7) and the second transistor (21) is connected to the third structure (8). [4] Power module (1) according to claim 3, characterized by, that the power module (1) is designed such that the first transistor (20) is switched on when the voltage potential at the first terminal (16) is lower than at the second terminal (17) and the second transistor (21) is switched on when the voltage potential at the first terminal (16) is higher than at the second terminal (17). [5] Power module (1) according to claim 3 or 4, characterized by , that a driver circuit of the first and second transistors (20, 21) is monolithically integrated into the transistors (20, 21). [6] Power module (1) according to any one of claims 3 to 5, characterized by , that the first transistor (20) and the second transistor (21) are designed as GaN transistors. [7] Power module (1) according to any one of claims 3 to 6, characterized by , that a Schottky diode is arranged in parallel to the first transistor (20) and in parallel to the second transistor (21). [8] Power module (1) according to claim 1 or 2, characterized by , that the components are designed as a parallel circuit of a resistor (26) and a diode (27). [9] Performance module (1) according to any of the preceding claims, characterized by , that a further metallization (5) is applied to the underside of the insulating layer (3).

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