Semiconductor devices with double silicon lens

Abstract

A semiconductor device comprises a silicon substrate having first and second opposite sides and having first and second regions. The semiconductor device further comprises a first silicon lens formed in the first region and along a first surface of the silicon substrate on the first side thereof. The semiconductor device further comprises a second silicon lens formed in the first region and along a second surface of the silicon substrate on the second side thereof. The semiconductor device further comprises a photonic die disposed in the first region and on the second side of the silicon substrate.

Description

background

[0001] Electrical signal transmission and processing is a technology for signal transmission and processing. Optical signal transmission and processing has been used in an increasing number of applications in recent years, particularly due to the use of optical fiber-based signal transmission applications.

[0002] Optical signal transmission and processing are typically combined with electrical signal transmission and processing to provide fully integrated applications. For example, optical fibers can be used for long-distance signal transmission, and electrical signals can be used for short-distance signal transmission, processing, and control. Accordingly, devices integrating optical and electrical components are designed to convert between optical and electrical signals, as well as to process optical and electrical signals. Packages can thus include both optical (photonic) dies with optical devices and electronic dies with electronic devices. Short description of the drawings

[0003] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 shows a multi-chip system with multiple locations according to some embodiments. Fig. 2 shows an exemplary arrangement of components of a location of the multi-chip system of Fig. 1 according to some embodiments. Fig. 3 shows a sectional view of part of the site of Fig. 1 according to some embodiments. Fig. 4 shows a detailed sectional view of the Fig. 3 shown portion of the site according to some embodiments. Fig. Figure 5 shows a sectional view of a silicon-based lens used in the Fig. 3, according to some embodiments. Fig. 6 shows an exemplary flow diagram of a method for producing the Fig. 3, according to some embodiments. Fig. 7 shows an exemplary flow diagram of a method for producing the Fig. 5, according to some embodiments. The Fig. 8 to 20 show respective sectional views of a portion of a semiconductor package during various stages of manufacture, which is produced by the method of Fig. 6 and Fig. 7, according to some embodiments. Detailed description

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] The present disclosure provides various embodiments of a three-dimensional (3D) package including an optical and an electrical device that may be electrically coupled to each other, and the method of forming the same. In certain embodiments, a System on Integrated Chip (SoIC) may offer advantages such as smaller pitch (e.g., a relatively higher bond density), shorter line delay in SoIC bonding, or hybrid laser microlens integration and fiber-to-photonic integrated circuit (PIC) assembly in an SoIC system, for example, to reduce photonic packaging resources. The SoIC structure may include or integrate individual systems, such as photonic or optical integrated circuits (ICs), radio-frequency integrated circuits (RFICs), power ICs, analog ICs, mixed-mode ICs, etc.An optical grating coupler (GC) (e.g., for a maximum wavelength of approximately 1310 nm) is provided or used to emit a beam mode-matched with a single-mode fiber with a spot diameter of approximately 9.2 µm, but the spot diameter can also have other dimensions or be configured with other dimensions, larger or smaller than 9.2 µm. In some cases, a grating can emit approximately 63% (e.g., 2 dB) of the input power in each of the uplink and downlink directions. The beam emitted in the downlink direction can expand as it propagates through the substrate (e.g., a silicon material or other types of substrate materials).

[0007] In some configurations, a silicon lens (e.g., a silicon microlens) may be placed or formed on a front side of a chip (or a front side of a substrate) to collimate a divergent beam from the optical GC. These silicon-based lenses can serve as an optical input / output for an optical device. For example, the silicon-based lens with configurable dimensions or profiles can collimate a received optical source and create a focal point for the optical source at a guided-mode resonant component (e.g., a GC) for the optical device. Therefore, the optical device can have significantly higher coupling efficiency. Furthermore, if the focal point is adjusted directly at the grating coupler, a beam size of the optical source can be optimized (e.g., minimized), which in turn can reduce the size of the grating coupler.Accordingly, the area occupied by the optical device can be reduced, advantageously leaving more space for integrating more high-performance devices (e.g., electrical devices) into the package. In some cases, a collimated beam from an external source with the correct diameter can be emitted onto or coupled into the lens and focused into a spot (e.g., with a spot diameter of approximately 9.2 µm) on the GC.

[0008] However, in a single-lens configuration, the GC cannot be placed or positioned at the focal point of the lens for beam collimation. In scenarios where the GC is not positioned at the focal point of the lens (or in cases where the lenses are provided in or on the substrate), coupling efficiency may be reduced or a relatively larger beam size may be generated. Additionally, the radius of curvature of the lens may not be easily controlled, e.g., with a circular lens, and process variation may be greater than with a planar routing. In various embodiments, the package disclosed herein embeds or otherwise includes a silicon-based (e.g., silicon, silicon nitride) doublet lens optically coupled to the optical device.The dual silicon lenses may be formed on different (opposite) sides of the substrate to improve process variation, including radius of curvature variation, compared to a silicon-based single lens, e.g., for light diffraction, to accommodate or reduce a light incidence angle error when using the dual silicon lenses. The package of the technical solution discussed here may, for example, include a first silicon lens formed along a first surface on a first side of a substrate (e.g., a silicon substrate) and a second silicon lens formed along a second surface on a second side of the substrate, thereby forming a dual lens on different sides of the substrate.By integrating or forming the double silicon lens, the directionality of the SoIC structure and the coupling efficiency can be improved, and the fiber light loss can be reduced while maintaining the beam size.

[0009] Fig. 1 shows a multi-chip system 100 according to various embodiments. The multi-chip system 100 is, for example, a high-performance computing (HPC) system, and includes a plurality of sites 102, each of which may be a separate computing system. Each of the sites 102 may, for example, be configured as a (e.g., three-dimensional (3D)) semiconductor package formed on a common package substrate. The Fig. 1 has twenty locations 102, but it should be understood that the system 100 may have any number of locations 102, which is also within the scope of the present disclosure.

[0010] The sites 102 are interconnected by an optical path connection 104 so that the separate computing systems of the sites 102 can communicate with each other. The optical path connection 104 can, for example, be a closed loop (or ring) connecting all sites 102 of the multi-chip system 100. This allows each site 102 to communicate with one of the other sites 102 via the optical path connection 104. In one embodiment, the optical path connection 104 includes a plurality of waveguides, with each waveguide connecting two of the sites 102 peer-to-peer. In some embodiments, the optical path connection 104 is a photonic silicon interconnect, but other types of optical path connections may be used.

[0011] In Fig. 2, an exemplary layout or other arrangement of components (e.g., dies, devices, etc.) at each location 102 is shown according to various embodiments. As a non-limiting example, Fig. 2, each site 102 may include a processor die 106, memory die 108, an electronic die (an implementation of the electrical device) 110, and a photonic die (an implementation of the optical device) 112. The optical path interconnect 104 extends below or above one or more components of each site 102, depending on the arrangements, but extends at least below the photonic die 112 of each site 102. The sites 102 are interconnected by an electrical path interconnect (which is shown in Fig. 1 or Fig. 2 is not shown but will be described later).

[0012] The processor die 106 may be a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or the like. The memory dies may be volatile memories, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), or the like. In the illustrated embodiment, each location 102 includes one processor die 106 and four memory dies 108, but it should be understood that each location 102 may include more or fewer memory dies 108 or more processor dies 106.

[0013] The photonic die 112 can transmit, receive, convert, modulate, demodulate, or otherwise process optical signals. For example, the photonic die 112 can convert electrical signals from the processor die 106 into optical signals and can convert optical signals into electrical signals. The photonic die 112 can transmit these optical signals via the optical path connection 104 ( Fig. 1) with one or more other photonic dies. According to various embodiments of the present disclosure, the photonic die 112 may receive the optical signals from a silicon-based lens embedded on the corresponding site 102 and may transmit and / or receive the optical signals via one or more waveguides of the optical path interconnect 104. As will be explained in more detail later, the silicon-based lens may be optically coupled to the optical path interconnect 104 by edge or grating coupling (e.g., via a grating coupler). These optical signals received via the silicon-based lens may include a probe signal configured to probe the corresponding photonic die 112, the optical path interconnect 104, etc.; and / or a carrier signal (e.g., a laser carrier signal).Accordingly, the photonic die 112 is responsible for the input / output (I / O) of optical signals to / from the optical path interconnect 104. In some embodiments, the optical path interconnect 104, or at least a portion thereof, may be integrated into the photonic die 112.

[0014] In various embodiments, the photonic die 112 may be a photonic integrated circuit (PIC), and the electronic die 110 (sometimes referred to as an electrical die) includes electronic circuitry required to connect the processor die 106 to the photonic die 112. The electronic die 110 may include, for example, controllers, transimpedance amplifiers, and the like. The electronic die 110 controls high-frequency signal transmission of the photonic die 112 according to (digital or analog) electrical signals received from the processor die 106. The electronic die 110 may be an electronic integrated circuit (EIC). The processor die 106, the memory dies 108, and the electronic die 110 are, in the non-limiting example of Fig. 2 as separate dies, it should be understood that locations 102 could each be a system-on-chip (SoC) or a system-on-integrated-circuit (SoIC) device / package. This allows processing, storage, and / or electronic control functionality to be integrated on the same die or substrate.

[0015] Fig. 3 shows a sectional view of a portion of one of the locations 102 according to various embodiments. For example, the Fig. 3 shows an electronic die 110 attached to or otherwise stacked over an optical die 112, with these two stacked dies being arranged over a package substrate 302. The sectional view of the site 102 of Fig. 3 is simplified as a schematic representation, but further details of position 102 are given in Fig. 4 and will be discussed with reference thereto. It should also be understood that above the package substrate 302, the site 102 may include one of several other dies attached thereto, for example, one or more memory dies 108, one or more processor dies 106, etc., which is also within the scope of the present disclosure.

[0016] The electronic die 110 is formed over a substrate 304. The substrate 304 may be a semiconductor substrate, such as a bulk semiconductor substrate or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 304 may be a wafer, such as a silicon wafer. Other substrates, such as a multilayer or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 304 may include: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In one embodiment, the substrate 304 is a silicon wafer, e.g., a 12-inch silicon wafer.In some embodiments, the substrate 304 may be formed with a thickness of, for example, about 300 µm to about 1000 µm or more than 1000 µm, depending on the configuration.

[0017] In some embodiments, as illustrated, the substrate 304 may be referred to as a substrate having a front side or surface 305A, sometimes referred to as a second side (or, depending on the arrangement, a first side), and a back side or surface 305B, sometimes referred to as a first side (or, depending on the arrangement, a second side). In general, the electronic die 110 includes a plurality of device elements or structures (e.g., transistors) formed along the front side 305A; and a plurality of conductive features (sometimes referred to as front-side interconnect structures) formed over these device structures on the front side 305A.However, it should be understood that the electronic die 110 may include a plurality of additional conductive features (sometimes referred to as backside interconnect structures) formed on the backside 305B, which is also within the scope of the present disclosure.

[0018] Additionally, the substrate 304 includes a plurality of lateral regions, including a first region 304B and a second region 304A. In some arrangements, the first and second regions may be reversed. In some embodiments, the electronic die 110 may be formed in the second region 304A, while a silicon-based lens 306a (e.g., sometimes referred to as a first silicon lens) is formed in the first region 304B and on the backside 305B of the substrate 304. In particular, the silicon-based lens 306a may be aligned (e.g., vertically) with a light source / supply 310 that provides photonic energy (e.g., light) 311 to the photonic die 112, with a dielectric layer 308 (e.g., silicon oxide, silicon nitride, a combination thereof, or the like) disposed therebetween.The light source / supply 310 may, for example, comprise an optical fiber that transmits photonic energy. The dielectric layer 308 may be formed with a thickness of, for example, about 0 µm to about 50 µm or more than 8 µm, depending on the configuration. In addition to forming the silicon-based lens 306a, a second silicon-based lens 306b is formed on the front side 305A of the substrate 304. In some implementations, the silicon-based lens 306a and / or the silicon-based lens 306b may occasionally be referred to as silicon-based lens(es) 306. The silicon-based lens 306a may be aligned (e.g., vertically) with the silicon-based lens 306b. In some cases, the silicon-based lens 306a may be spaced apart from the silicon-based lens 306b (e.g.,vertically) shifted (or laterally displaced).

[0019] This creates an optical transmission path that extends from the light source / supply 310 to the silicon-based lenses 306. As will be explained later in Fig. 4, such an optical transmission path does not include any conductive (e.g., metallic) structural element, thereby significantly limiting interference by conductive structural elements. The dimensions and profile of the silicon-based lens 306 (e.g., the silicon-based lens 306a and / or the silicon-based lens 306b), e.g., a radius of curvature, a thickness, a diameter, an angle, etc., may be configured according to properties (e.g., a range of wavelengths) of the light source 311. The silicon-based lens 306b may be formed from similar materials as the silicon-based lens 306a. The silicon-based lens 306b may be formed in a similar manner or using a similar method (e.g., at least one suitable etching method) as the silicon-based lens 306a, as described, among other things, with reference to at least one of the Fig. 5 to 20. As a result, when an overlying light source 311 is received by the silicon-based lens 306a, the silicon-based lens 306a can collimate the light source 311 through the substrate 304, the silicon-based lens 306b, and the dielectric layer 308 to a focal point approximately at a position of the light source / supply 310. By using the silicon-based lens 306a and the silicon-based lens 306b, for example, the variation in the radius of curvature can be improved over using a single silicon-based lens.

[0020] In various configurations, the silicon-based lenses 306 may be formed from at least one suitable material, such as silicon or silicon nitride, etc. The silicon-based lenses 306 may be formed from a similar material to or a different material than the substrate 304. In some cases, the silicon-based lenses 306 may be formed on the substrate 304 using at least one suitable etching process. For example, the silicon-based lens 306a may be formed by etching various portions of the backside 305B of the substrate 304 (e.g., directly). The silicon-based lens 306b may be formed by etching various portions of the frontside 305A of the substrate 304. The process for forming the silicon-based lenses 306 is described, for example, with reference to the Fig. 5 to 20. In some other cases, the silicon-based lenses 306 may be formed using at least one deposition technique. For example, the silicon-based lens 306a may be formed by depositing a material (e.g., silicon) on the surface of the backside 305B of the substrate 304. The silicon-based lens 306b may be formed by depositing a material (e.g., silicon) on the surface of the frontside 305A of the substrate 304.

[0021] The dimensions of at least one of the silicon-based lenses 306 may be configured or structured to compensate for the potential displacement (or offset) of a fiber (e.g., the optical fiber or an optical source). For example, a diameter of at least one of the silicon-based lenses 306 may be, for example, about 10 µm to about 500 µm (but not limited thereto). The maximum diameter of at least one of the silicon-based lenses 306 may be, for example, more than 100 µm. A thickness (e.g., a height) of at least one of the silicon-based lenses 306 may be, for example, about 1 µm to 50 µm, wherein the maximum thickness of the silicon-based lenses 306 may be, for example, more than 5 µm. For example, a first radius of curvature (R1) of the silicon-based lens 306a and / or a second radius of curvature (R2) of the silicon-based lens 306b may be about 100 µm to about 500 µm.For example, a first radius of curvature of the silicon-based lens 306a and / or a second radius of curvature of the silicon-based lens 306b may be greater than 290 µm. One or more parameters (e.g., diameter, thickness, or radius of curvature) of the silicon-based lens 306a may be similar to or different from those of the silicon-based lens 306b. For example, the diameter of the silicon-based lens 306a may be similar to or different from the diameter of the silicon-based lens 306b. A thickness (e.g., a height) of the silicon-based lens 306a may be similar to or different from the thickness of the silicon-based lens 306b. The radius of curvature of the silicon-based lens 306a may be similar to or different from the radius of curvature of the silicon-based lens 306b.

[0022] In some cases, the silicon-based lens 306a may be aligned with the silicon-based lens 306b (e.g., vertically). In some other cases, the silicon-based lens 306a may be offset from the silicon-based lens 306b (e.g., vertically) by a distance (d). The (e.g., vertical) offset distance between the silicon-based lens 306a and the silicon-based lens 306b may be, for example, about 0 µm to about 100 µm or about 0 µm to about -100 µm. An angle of the optical fiber may be configured to be, for example, 5° to 15° according to the position of at least one of the silicon-based lenses 306 (but not limited thereto). The angle of the optical fiber is, for example, Fig. 3 and with reference thereto as an angle at which an optical fiber (e.g., associated with the light source / supply 310) is aligned or positioned with respect to the silicon-based lens 306a, the surface of the substrate 304, or other components of the site 102. The structural elements of at least one of the silicon-based lenses 306 are illustrated and described, for example, at least with reference to Fig. 5 described.

[0023] The site 102 also includes a plurality of (first) conductive connectors 312 and a plurality of (second) conductive connectors 314. The first conductive connectors 312 may electrically and / or physically couple various dies (e.g., the stacked electronic die 110 and optical die 112) to the package substrate 302, and the second conductive connectors 314 may electrically and / or physically couple the package substrate 302 to one or more other devices / packages. For example, the package substrate 302 may be coupled to at least the photonic die 112 via one or more of the first conductive connectors 312. The package substrate 302 may be coupled to one or more other devices / packages via one or more of the second conductive connectors 314.

[0024] Now with reference to Fig. 4, the electronic die 110, which is arranged in the second region 304A and on the second side 305A of the substrate 304, comprises a plurality of device elements 402 formed along the front surface of the substrate 304. The device elements may be partially or completely covered by a dielectric layer 404. Over the dielectric layer 404 (when the location 102 of Fig. 2), a plurality of conductive features 406 are formed in a dielectric layer 408. The dielectric layers 404 and 408 may be formed of the same material or of different materials selected from the group consisting of silicon oxide, silicon nitride, a low-k dielectric material, or combinations thereof. The conductive features 406 may include lines and vias and may be formed using a damascene process, e.g., a dual damascene process, a single damascene process, or the like. The conductive features 406 may be arranged in multiple layers or levels, sometimes referred to as metallization layers. In general, the metallization layers arranged closest to or farthest from the device elements 402 may be referred to as Mo (the bottommost metallization layer) and Mo (the bottommost metallization layer), respectively.Mx (the topmost metallization layer). A plurality of pads (not shown) may be formed over the Mx layer to electrically connect the conductive features 406 therein to conductive features of the photonic die 112.

[0025] The photonic die 112 may be formed on a semiconductor-on-insulator (SOI) substrate, which includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a BOX (buried oxide) layer, a silicon oxide layer, or the like. The insulating layer is provided on a semiconductor material, typically a silicon or glass substrate. As shown in Fig. 4, layers 412 and 414 may represent this underlying semiconductor material and the BOX layer, respectively.

[0026] Additionally, the photonic die 112 may include a plurality of device elements 416 (e.g., photodiodes) and a plurality of waveguides 418 formed in the overlying semiconductor material (not shown). The front side (or face) of this overlying semiconductor material is patterned to form the waveguide 418. Patterning the overlying semiconductor material may be accomplished using suitable photolithography and etching techniques. In particular, openings are etched in the overlying semiconductor material, and remaining portions of the overlying semiconductor material may form the waveguide 418. The BOX layer 414 may act as an etch stop layer for the etching process.

[0027] The waveguide 418 may be arranged on the front side 305A (e.g., the second side) of the substrate 304. The waveguide 418 may include one or more grating couplers 420 formed in upper portions of the waveguide 418. Through the grating coupler 420, the waveguide 418 may transmit light to or receive light from the upper-lying light source or optical signal source (e.g., through the silicon-based lens 306a and the silicon-based lens 306b). The grating coupler 420 may be formed using suitable photolithography and etching techniques. In one embodiment, the grating coupler 420 is formed after the waveguide 418 is defined. The grating coupler 420 may be formed from silicon-based materials. The dimension of the grating coupler 420 may include a thickness, for example, B. is larger than 200 nm and is approximately 100 nm to 1000 nm. For example, a photoresist can be deposited on the front side of the higher-lying semiconductor material (e.g.on the waveguide 418 and in recesses that define it). The photoresist can be patterned with openings corresponding to the grating coupler 420. One or more etching processes can be performed using the patterned photoresist as an etch mask. In particular, the front side of the overlying semiconductor material can be etched to create recesses in the waveguide 418, thereby defining the grating coupler 420. The etching processes can be anisotropic wet or dry etching processes.

[0028] The photonic die 112 also includes a dielectric layer 422 formed over the device elements 416 and the waveguide 418. The dielectric layer 422 may also be formed in the recesses defining the waveguide 418 and the grating coupler 420. The dielectric layer 422 may be formed from silicon oxide, silicon nitride, a combination thereof, or the like by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on dielectric, or the like, or a combination thereof. After formation, the dielectric layer 422 may be planarized, for example, with chemical mechanical polishing (CMP) or by machining, to avoid transferring the structure of the waveguide 418 to the dielectric layer 422. In one embodiment, the dielectric layer 422 is an oxide, such as silicon oxide.Due to the difference in the refractive indices of the materials of waveguide 418 and dielectric layer 422, waveguide 418 exhibits strong internal reflections, so that light is confined within waveguide 418, which depends on the wavelength of the light and the refractive indices of the respective materials. In one embodiment, the refractive index of the material of waveguide 418 is higher than that of the material of dielectric layer 422.

[0029] Over the dielectric layer 422 (which is shown in Fig. 2), a plurality of conductive features 424 are formed in a dielectric layer 426. The dielectric layers 422 and 426 may be formed of the same material or of different materials selected from the group consisting of silicon oxide, silicon nitride, a low-k dielectric material, and combinations thereof. The refractive index of the material of the waveguide 418 is higher than that of the material of the dielectric layer 426. The conductive features 424 may include lines and vias and may be formed using a damascene process, e.g., a dual damascene process, a single damascene process, or the like. The conductive features 424 may be arranged in multiple layers or levels, sometimes referred to as metallization layers.In general, the metallization layers located closest to or farthest from the device elements 416 may be referred to as Mo (the bottommost metallization layer) and Mx (the topmost metallization layer), respectively. A plurality of pads (not shown) may be formed over the Mx layer to electrically connect the conductive features 424 therein to the conductive features 406 of the electronic die 110, i.e., the electronic die 110 is bonded or otherwise attached to the photonic die 112.

[0030] In some embodiments, the bond between the electronic die 110 and the photonic die 112 may not include a bump structure, but may be bumpless. However, in some other embodiments, the bond between the electronic die 110 and the photonic die 112 may be realized by a number of bump structures. The bond may, for example, be a hybrid bond, a fused bond, a direct bond, a dielectric bond, a metal bond, solder bonds (e.g., microbumps), or the like.

[0031] As a non-limiting example, the electronic die 110 is bonded to the photonic die 112 by hybrid bonding. In these embodiments, covalent bonds are formed with oxide layers, such as the dielectric layer 408 of the electronic die 110 and the dielectric layer 426 of the photonic die 112. Prior to bonding, a surface treatment may be performed on the electronic die 110. Then, a pre-bonding process may be performed in which respective pads or conductive features of the electronic die 110 and the photonic die 112 are aligned. The electronic die 110 and the photonic die 112 are pressed against each other to form weak bonds. After the pre-bonding process, the electronic die 110 and the photonic die 112 are annealed to strengthen the weak bonds.During annealing, OH bonds in the top surface of the dielectric layers break, creating strong Si-O-Si bonds between the electronic die 110 and the photonic die 112, thereby strengthening the bonds.

[0032] As in Fig. As shown in Figure 4, an optical transmission path extends from the grating coupler 420 of the photonic die 112 to the silicon-based lenses 306, which include the silicon-based lens 306b (e.g., the second silicon lens) and the silicon-based lens 306a (e.g., the first silicon lens). In these cases, the silicon-based lens 306b may be disposed between the silicon-based lens 306a and the grating coupler 420. In other arrangements, the silicon-based lens 306a may be disposed between the silicon-based lens 306b and the grating coupler 420. In various embodiments, this optical transmission path does not include any of the conductive features 406 or the conductive features 424. In other words, there are no components formed from a conductive material along this optical transmission path, which can significantly limit the interference caused by the conductive features.

[0033] The photonic die 112 further includes a plurality of vias 428 extending through the dielectric layer 422, the BOX layer 414, and the underlying semiconductor material 412. The vias 428 may be formed by filling a plurality of openings extending through the dielectric layer 422, the BOX layer 414, and the underlying semiconductor material 412 with a conductive material. The conductive material is deposited in the openings, for example, by electrochemical plating (ECP) or electroless plating. The conductive material may be a metallic material that is a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, or alloys thereof. To remove excess conductive material along a surface (e.g.,A planarization process, such as CMP or machine grinding, may be performed on the underlying semiconductor material 412 (a backside). In various embodiments, the vias 428 may electrically couple the conductive features 424 of the photonic die 112, which are electrically coupled to the conductive features 406 of the electronic die 110, to the conductive connectors 312.

[0034] Above the back surface of the underlying semiconductor material 412, the site 102 further includes conductive pads 430, some of which may electrically contact the vias 428. The conductive pads 430 may be aluminum pads or aluminum-copper pads, but other metal pads may also be used.

[0035] A passivation layer 432 may be formed over the back surface of the underlying semiconductor material 412 to cover the conductive pads 430. The passivation layer 432 may be formed from a dielectric material, such as silicon oxide, silicon nitride, or the like, or combinations thereof. Openings are formed through the passivation layer 432 to expose (e.g., central) portions of the conductive pads 430.

[0036] Underbump metallization (UBM) 434 may be formed on the conductive pads 430 and the passivation layer 432. The UBM 434 may be formed by forming a conductive protective layer on the passivation layer 432 and in the openings, for example, by electroplating. The conductive layer may be formed from copper, a copper alloy, silver, gold, aluminum, nickel, or the like, or combinations thereof. The conductive layer may be patterned to form the UBM 434.

[0037] The conductive interconnects 312 are formed on the UBM 434 and are arranged, for example, on a first side of the photonic die 112 opposite a second side of the photonic die 112 facing the substrate 304. The conductive interconnects 312 may be BGA (ball grid array) interconnects, solder balls, metal pillars, C4 (controlled collapse chip connection) bumps, microbumps, ENEPIG (electroless nickel electroless palladium immersion gold) bumps, or the like. The conductive interconnects 312 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof.In some embodiments, the conductive interconnects 312 are formed by first forming a layer of solder using such commonly used techniques as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After the layer of solder is formed on the structure, a reflow process may be performed to form the material into the desired bump shapes. In another embodiment, the conductive interconnects 312 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed over the conductive interconnects 312.The metallic capping layer may contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be formed using a plating process.

[0038] In some embodiments, site 102 further includes one or more anti-reflection coating (ARC) layers 450 formed on the front side 305A and / or the back side 305B of substrate 304. ARC layer 450 may be formed over silicon-based lens 306a. In some cases, ARC layer 450 may be formed under (or, depending on the configuration, over) silicon-based lens 306b. ARC layer 450 may be implemented as a multilayer of anti-reflection materials, such as silicon, silicon nitride, silicon oxide, titanium, titanium nitride, aluminum, aluminum oxide, silicon oxynitride, combinations thereof, or the like. The ARC layer 450 may, for example, comprise a first silicon oxide (e.g., having a thickness of 1000 Å), a first silicon nitride (e.g., having a thickness of about 500 Å), a second silicon oxide (e.g.,with a thickness of approximately 2400 Å) and a second silicon nitride (e.g., with a thickness of approximately 2200 Å) stacked on top of one another. In this embodiment, the ARC layer 450 (or any of its anti-reflective materials) may be deposited using a deposition process such as CVD, PVD, or the like. However, any suitable materials and methods of formation may be used.

[0039] Fig. 5 shows an enlarged view of a silicon-based lens 306 (e.g., the silicon-based lens 306a and / or the silicon-based lens 306b) according to various embodiments. Fig. Although Figure 5 shows the silicon-based lens 306a as an example, one or more parameters, such as dimensions, radius of curvature, thickness, etc., of the silicon-based lens 306a may be similarly used for the silicon-based lens 306b. As in the example of Fig. 5, the silicon-based lens 306a (or the silicon-based lens 306b) has a hemispherical profile, sometimes referred to as a plano-convex profile, with one spherical surface projecting away from the back surface 305B and one flat surface substantially aligned with the back surface 305B. However, it should be understood that the silicon-based lens 306a or the silicon-based lens 306b may also have one of several other profiles, such as a biconvex profile, a converging meniscus profile, a positively achromatic profile, etc., as long as the silicon-based lens 306a and the silicon-based lens 306b have a focal point at the grating coupler 420 ( Fig. 4), which is also within the scope of the present disclosure. By forming the silicon-based lens 306a and the silicon-based lens 306b, the two silicon lenses can collectively provide a focal point at the grating coupler 420.

[0040] Additionally, various dimensions of the silicon-based lens 306a (or the silicon-based lens 306b) may be configured to collimate the optical source 311 and cause it to be focused at the grating coupler 420. For example, the silicon-based lens 306a has a thickness e defined as a maximum height from the flat surface to the spherical surface; an angle θ defined as an angle between a tangent line at one end of the spherical surface and a tangent line at one end of the flat surface; a radius of curvature R of the spherical surface; and a diameter d of the silicon-based lens 306a. As a non-limiting example, the thickness e may be about 1 µm to about 50 µm, the angle θ (e.g., the angle of the optical fiber) may be about 5° to about 15°, the radius of curvature R may be about 100 µm to about 500 µm, and the diameter d may be about 10 µm to about 500 µm.In some embodiments, the diameter d may be at least 100 µm to compensate for an offset of the optical source (e.g., an optical fiber). In some embodiments, the angle θ may be configured in the aforementioned range to optimize a coupling efficiency of the silicon-based lens 306a. In some embodiments, the radius R may be configured to be about 290 µm or larger to also optimize the coupling efficiency of the silicon-based lens 306a. In some embodiments, the radius R may be about 100 µm to about 500 µm.

[0041] Fig. 6 shows a flow diagram of an exemplary method 600 for forming at least a portion of a semiconductor package according to some embodiments. It should be noted that the method 600 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the order of operations of the method 600 of Fig. 6 can be changed, further operations before, during and after the procedure 600 of Fig. 6 may be provided and some other operations may only be described briefly here.

[0042] A semiconductor package manufactured by method 600 may include at least one electronic die and one photonic die operatively and physically coupled to each other, as well as a silicon-based lens operatively (e.g., optically) coupled to the photonic die. For example, the semiconductor package may include a portion of site 102, as set forth above. Therefore, operations of method 600 will be discussed in connection with the components described with reference to Fig. 3 to 5 have been described.

[0043] The method 600 begins with an operation 602 for forming a first silicon lens (e.g., 306a) along a first surface on a first side (e.g., 305B, sometimes referred to as a first-side surface) of the substrate (e.g., 304). The silicon-based lens 306a is formed, for example, on a backside surface (e.g., 305B) of the substrate 304. Furthermore, the silicon-based lens 306a is formed in a first region (e.g., 304B) of the substrate 304. In some embodiments, the silicon-based lens 306a is formed with a plano-convex profile using multiple photolithography and etching processes, which will be described later with reference to Fig. 7 is explained in more detail.

[0044] The method 600 then proceeds with an operation 604 for forming a second silicon lens (e.g., 306b) along a second surface on a second side (e.g., 305A, sometimes referred to as a second-side surface) of the substrate (e.g., 304). The silicon-based lens 306b is formed, for example, on a front surface (e.g., 305A) of the substrate 304. The front surface is the side of the substrate 304 opposite the back surface. Furthermore, the silicon-based lens 306b is formed in the first region (e.g., 304B) of the substrate 304. In some embodiments, the silicon-based lens 306b is formed similarly to the silicon-based lens 306a with a plano-convex profile using multiple photolithography and etching processes, which will be described later with reference to Fig. 7 is explained in more detail.

[0045] The method 600 then proceeds with an operation 606 to form an electronic die over the second surface (side) (e.g., 305A) of the substrate (e.g., 304). The electronic die may be formed in a second region (e.g., 304A) of the substrate, wherein the second region is laterally adjacent to the first region of the substrate. For example, an electronic die (e.g., 110) having a plurality of electrical device elements (e.g., 402) and conductive features (e.g., 406) may be formed over the front surface (e.g., 305A) of the substrate (e.g., 304). Additionally, the electronic die 110 may be formed in a second region (e.g., 304A) of the substrate 304 in which no silicon-based lenses 306 are to be formed. In some embodiments, the first region of the substrate may be referred to as a part of the electronic die 110.

[0046] The method 600 then proceeds with an operation 608 for attaching a photonic die to the electronic die on the second side (e.g., 305A) of the substrate. For example, before, simultaneously with, or after forming the electronic die 110 (and the silicon-based lenses 306) on the substrate 304, a photonic die (e.g., 112) is formed over the front surface (e.g., 305A) of the substrate (e.g., an SOI substrate with the underlying semiconductor material 412, the BOX layer 414, and an overlying semiconductor material). In some embodiments, the photonic die 112 includes a plurality of optical device elements (e.g., 416), a plurality of waveguides (e.g., 418) with at least one grating coupler (e.g., 420), and a plurality of conductive features (e.g., 424). The grating coupler (e.g., 420) may be vertically aligned to at least one of the silicon-based lenses (e.g., 306a or 306b), as described, for example, with reference to Fig. 3 and / or Fig. 4 has been explained.

[0047] Continuing with the same example, after forming the photonic die 112 and the electronic die 110, the two dies may be attached to each other using various bonding techniques, such as hybrid bonding, fusion bonding, direct bonding, dielectric bonding, metal bonding, solder joints (e.g., microbumps), or the like. In some embodiments, the electronic die 110 may be bonded to the photonic die 112 with the conductive features 406 (of the electronic die 110) facing the conductive features 424 (of the photonic die 112). In other words, the electronic die 110 may be bonded to the photonic die 112 with their respective front-side surfaces facing each other, thereby forming the silicon-based lens 306a on an (opposite) back-side surface (e.g.,305B) of the substrate 304 on which the electronic die 110 is formed, and the silicon-based lens 306b is arranged on a (same) front surface (e.g., 305A) of the substrate 304 on which the electronic die 110 is formed.

[0048] In some embodiments, the electronic die and the photonic die may be attached to a package substrate. For example, after bonding the photonic die 112 and the electronic die 110 together, these bonded dies may be attached to a package substrate (e.g., 302). In some embodiments, the bonded dies 112 and 110 may be attached to the package substrate 302 using a plurality of bump structures (e.g., 312). Furthermore, the bump structures 312 may be formed on a front side (opposite side) of the substrate on which the photonic die 112 is formed.

[0049] As set forth above, operation 602 (or operation 604) includes multiple process steps / operations for forming the silicon-based lens (e.g., 306a or 306b). Fig. 7 shows a flowchart including these operations. In some embodiments, operations of method 700 may be associated with cross-sectional views of a portion of an exemplary semiconductor package 800 including an embedded silicon-based lens at various manufacturing stages, each of which is shown in the Fig. 8 to 20 are shown.

[0050] The method 700 begins with an operation 702 to form a first mask over the first (back) side / surface of the silicon substrate. The method 700 then proceeds with an operation 704 to etch the substrate (from the back) using the first mask. The method 700 then proceeds with an operation 706 to laterally reduce the mask (e.g., the first mask) to form a second mask. The method 700 then proceeds with an operation 708 to etch the silicon substrate (from the back) using the reduced mask. In various embodiments, operation 706 and / or 708 may be repeated a certain number of times until a desired stair profile is formed on the back of the first substrate. After forming the stair profile, the method 700 proceeds with an operation 710 to round the stair profile to form the silicon-based lens.

[0051] According to Operation 702 of Fig. 7 shows Fig. 8 shows a cross-sectional view and a top view of the semiconductor package 800 according to various embodiments, wherein a backside of the substrate 304 (e.g., the backside 305B) is covered by a mask (e.g., a hard mask) 802 (e.g., a first mask at this stage / in this operation). It is understood that the substrate 304 of Fig. 8 (and the following figures) is shown upside down, and thus the mask 802 is formed on the substrate 304, e.g., along the first surface or side of the silicon substrate. Furthermore, based on the method 600, one or more electronic dies may be formed before or after performing the method 700 (for forming the silicon-based lens).

[0052] The mask 802 may include or be formed from silicon nitride, photoresist, or other materials. The mask 802 may be formed in an elliptical, circular, or other shape suitable for etching the silicon substrate 304. In some embodiments, the mask 802 may be formed as a single structure (e.g., as one piece). In some other embodiments, the mask 802 may include multiple pieces (not shown) arranged over other pieces along a corresponding surface of the substrate 304. The mask 802 may be formed or positioned on a corresponding surface in or around the first region (e.g., 304B) of the silicon substrate. The silicon-based lens 306a may be referred to as a first silicon lens, and the silicon-based lens 306b may be referred to as a second silicon lens.The corresponding area of the substrate 304 depends on whether the operations or processes are used to form the first or second lens. For example, the mask 802 may be formed on the first side 305B of the silicon substrate to form the first silicon lens, or it may be formed on the second side 305A of the silicon substrate to form the second silicon lens.

[0053] After forming the mask 802, and according to an operation 704 of Fig. 7, shows Fig. 8 illustrates, according to some embodiments, a first etching process 804 performed on a surface (e.g., the back surface or the front surface) of the substrate 304 using the mask 802. The first etching process 804 may be a wet etching process (based on etchants such as NH4OH, HNO3, or combinations thereof) or a dry etching process (based on etchants such as NF3, F2, Cl2, or combinations thereof). The amount of the substrate 304 etched away with the etching process 804 may be controlled by the duration of the etching process 804. Based on the structures of the mask 802, the surface may, for example, have a donut shape (when viewed from above), in which the donut is depicted as a recessed portion relative to a remaining portion covered by the mask 802. In particular, the remaining portion and the recessed portion may form a step that may be Fig. 8 is labeled 805.

[0054] According to an operation 706 of Fig. 7 shows Fig. 9 shows a cross-sectional view and a top view of the semiconductor package 800, in which, according to various embodiments, the mask 802 (e.g., the first mask) is reduced in size, e.g., resulting in a second mask having a diameter smaller than that of the first mask. In order to reduce the mask 802 (e.g., to remove a portion of the mask 802) without reducing other structures of the semiconductor package 800, at least one suitable etching process may be used, such as, for example, plasma etching. The etching process may be used to uniformly recess or reduce the size of the mask 802. As shown, the mask 802 has Fig. 9 has a relatively smaller diameter than the mask 802 of Fig. 8 (e.g., prior to the lateral reduction of the mask 802). The mask 802 (e.g., its diameter) is reduced laterally, for example, to expose further portions (e.g., a portion 900) of the surface of the substrate 304. The portions of the surface exposed by the lateral reduction of the mask 802 may, for example, form a donut shape.

[0055] According to an operation 708 of Fig. 7 shows Fig. 10 shows a cross-sectional view and a top view of the semiconductor package 800, in which, according to various embodiments, a second etching process 806 is performed on the surface of the substrate 304 using the (e.g., reduced-size) mask 802. The second etching process 806 may be a wet etching process (based on etchants such as NH4OH, HNO3, or combinations thereof) or a dry etching process (based on etchants such as NF3, F2, Cl2, or combinations thereof). The second etching process 806 may be similar to the first etching process 804. In various embodiments, the operation 708 may be similar to the operation 704 of Fig. 7. For example, the amount of substrate 304 that is etched away with the etching process 806 can be controlled by the duration of the etching process 806. As in Fig. 10, based on the structures of the (e.g., laterally reduced) mask 802, the surface (e.g., the back surface for forming the first silicon lens) may have a different donut shape (when viewed from above), in which the donut is depicted as a recessed portion relative to a remaining portion covered by the mask 802. In particular, the remaining portion and the recessed portion may form a further step, e.g., 807, wherein the step 805 is disposed below and encloses the step 807, as shown in Fig. 10 is shown.

[0056] By repeating operations 706 and 708 once, a further step 809 can be formed on the corresponding surface (e.g., on the back surface for the first silicon lens or on the front surface for the second silicon lens) with a still further etching process 808 using a further reduced-size mask 802, which is shown in sectional views and plan views of Fig. 11 or Fig. 12. The step 809 is similarly formed so that it is disposed above and enclosed by the preceding steps, e.g., 807 and 805.

[0057] After repeating operations 706 and 708 one or more times, a corresponding number of steps, which may form a staircase profile, is located on the corresponding surface of the substrate 304. For example, a further step 811 may be formed on the corresponding surface (e.g., on the back surface for the first silicon lens or on the front surface for the second silicon lens) with a yet further etching process 810 using a further reduced-size mask 802, which is shown in cross-sectional and top views of Fig. 13 respectively Fig. 14. The step 811 is similarly formed so that it is disposed above and enclosed by the preceding steps, e.g., 809, 807, and 805.

[0058] Fig. 15 shows a cross-sectional view of the semiconductor package 800 in which the mask 802 is removed after a desired step profile has been formed. In some embodiments, the hard masks may be removed with a phosphoric acid solution at an elevated temperature (e.g., about 170°C), plasma etching, wet cleaning, or other methods suitable for removing the remaining mask 802. In some embodiments, the etching processes performed on the substrate (e.g., 304) may define or set the thickness (e.g., depth or height) and / or diameter of the first and second silicon lenses. For example, relatively more etching processes (e.g., forming more steps) may result in a relatively thicker or wider silicon lens, which may depend on the duration of the individual etching processes or the configuration of the mask 802.

[0059] According to Operation 710 of Fig. 7 shows Fig. 16 shows a cross-sectional view and a top view of the semiconductor package 800 in which, according to various embodiments, an etching process 812 is performed to round the steps of the staircase profile. The etching process 812 may be a wet etching process. In some embodiments, in the etching process 812, ammonia solution and / or nitric acid solution may be applied over the corresponding surface to round the staircase profile. For example, the etching process 812 may include etching protruding parts of the staircase profile significantly earlier than the steps (e.g., 805, 807, 809, or 811). As a result, these protruding parts may be rounded (or smoothed) to form a spherical surface protruding away from the corresponding surface, resulting in a silicon-based lens (e.g., 306a or 306b) with a plano-convex profile.

[0060] According to Operation 604 of Fig. 6, the operations of method 700 may be Fig. 7 may be repeated to form another silicon lens along the other (opposite) side of the silicon substrate. For example, after forming one of the silicon lenses, the silicon substrate (which is, for example, fixed to a carrier substrate during the manufacturing process) may be flipped to expose the other side of the silicon substrate. After flipping the silicon substrate, operations of method 700 may be performed to form the another silicon lens. The first silicon lens (e.g., 306a) may be formed before or after the second silicon lens (e.g., 306b). The operations of method 700, such as those that Fig. 8 to 16 may be used to form the first silicon lens (e.g., 306a), but in some cases, they may be used similarly to form the second silicon lens (e.g., 306b). In these cases, the second silicon lens may be formed on the front or second side (e.g., 305A) of the substrate 304, and the first silicon lens may be formed on the back or first side (e.g., 305B) of the substrate 304.

[0061] As in Fig. 17, and according to operations 602 and 604 of Fig. 6, the first silicon lens (e.g., 306a) and the second silicon lens (e.g., 306b) may be formed along the corresponding surface on a respective side of the silicon substrate in the first region (e.g., 304B). For example, the silicon-based lens 306a may be formed along the first surface on the first side 305B of the substrate 304. The silicon-based lens 306b may be formed along the second surface on the second side 305A of the substrate 304. The first side 305B is opposite the second side 305A of the substrate 304. The silicon-based lenses 306 (e.g., 306a and 306b) are formed in the first region 304B. The silicon-based lenses 306 may, for example, form a double-convex lens.

[0062] According to operation 606, Fig. 18 shows a cross-sectional view of the semiconductor package 800 in which an electronic die and a dielectric layer are formed according to various embodiments. The electronic die may, for example, be formed in the second region (e.g., 304B) of the silicon substrate after the first silicon lens (e.g., 306a) and the second silicon lens (e.g., 306b) have been formed. The second region is laterally adjacent to the first region (e.g., 304B) of the silicon substrate in which the first and second silicon lenses are formed. For example, an electronic die (e.g., 110) having a plurality of electrical device elements (e.g., 402) and conductive features (e.g., 406) may be formed over the front surface (e.g., 305A) of the substrate (e.g., 304). Additionally, the electronic die 110 may be formed in a second region (e.g., 304A) of the substrate 304 in which no silicon-based lenses 306 are formed.

[0063] After forming the electronic die, a dielectric layer (e.g., 308) may be formed, arranged, or deposited along the front side (e.g., 305A) of the silicon substrate and the surface of the electronic die (e.g., 110). As shown in Fig. 18, the dielectric layer (e.g., 308) may be formed or deposited, for example, along a surface (e.g., the second surface) of the front side (e.g., the second side) of the silicon substrate and the electronic die. The deposited dielectric layer may have a specified thickness (e.g., target thickness). For example, the dielectric layer may have a thickness that is, for example, greater than 8 µm and in a range from 0 µm to 50 µm. In some cases, at least one suitable etching technique may be used to thin the dielectric layer (e.g., 308) or to remove a portion thereof.

[0064] According to operation 608, Fig. 19 is a cross-sectional view of semiconductor package 800 in which a photonic die is formed according to various embodiments. As shown, a photonic die (e.g., 112) is formed over a front surface (e.g., 305A) of a substrate (e.g., an SOI substrate including underlying semiconductor material 412, BOX layer 414, and an overlying semiconductor material) or along the front surface of a dielectric layer (e.g., 308). The front surface of the dielectric layer is opposite the back surface of the dielectric layer facing the substrate (e.g., 304). As set forth herein, the photonic die 112 includes, for example, a plurality of optical device elements (e.g., 416), a plurality of waveguides (e.g., 418) with at least one grating coupler (e.g., 420), and a plurality of conductive structural elements (e.g., 424). The grating coupler (e.g., 420) may be vertically aligned with at least one of the silicon-based lenses (e.g., 422).B. 306a and 306b) as described with reference to . Fig. 3 and / or Fig. 4. The conductive structural elements (e.g., 424) can be arranged above the grating coupler (e.g., 420), but not in the optical transmission path.

[0065] The photonic die 112 can be attached to the electronic die 110. The two dies can be attached to each other using various bonding techniques, such as hybrid bonding, fusion bonding, direct bonding, dielectric bonding, metal bonding, solder connections (e.g., microbumps), or the like. In some embodiments, the electronic die 110 can be bonded to the photonic die 112, for example, with the conductive features.

[0066] Fig. 20 is a cross-sectional view of semiconductor package 800 in which one or more conductive interconnects (e.g., 312) are formed, according to various embodiments. Conductive interconnects 312 may be formed, for example, on a front surface of the substrate (e.g., 304) on which photonic die 112 is formed. As shown, the one or more conductive interconnects 312 are formed on a first side of photonic die 112 (e.g., facing away from substrate 304) opposite a second side of photonic die 112 facing substrate 304. In some embodiments, conductive interconnects 312 may be formed by first forming a layer of solder using such commonly used techniques as evaporation, electroplating, printing, solder transfer, ball placement, or the like.After the layer of solder has been formed on the structure, a reflow process may be performed to form the material into the desired bump shapes. In another embodiment, the conductive interconnects 312 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and may have substantially vertical sidewalls.

[0067] The conductive connectors 312 may enable or provide a connection between the photonic die 112 and the package substrate (e.g., 302). For example, after forming the conductive connectors 312, the semiconductor package 800 may be turned over and attached to the package substrate (e.g., 302), as described with reference to Fig. 3 and / or Fig. 4. By turning the semiconductor package 800 at this stage, the back side (e.g., 305B) of the silicon substrate may face up, and the front side (e.g., 305A) of the silicon substrate may face down, as shown, for example, in the Fig. 3 and Fig. 4. Other structures, not limited to the structures described herein, may be formed, connected, or implemented in conjunction with the semiconductor package 800.

[0068] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a silicon substrate having first and second opposite sides and having first and second regions. The semiconductor device includes a first silicon lens formed in the first region and along a first surface of the silicon substrate on the first side thereof. The semiconductor device includes a second silicon lens formed in the first region and along a second surface of the silicon substrate on the second side thereof. The semiconductor device includes a photonic die disposed in the first region and on the second side of the silicon substrate.

[0069] In another aspect of the present disclosure, a semiconductor package is disclosed. The semiconductor package includes a substrate disposed over a package substrate. The semiconductor package includes a grating coupler disposed over the substrate. The semiconductor package includes a plurality of first conductive features disposed over the grating coupler. The semiconductor package includes an electronic die disposed over the plurality of first conductive features and including a plurality of second conductive features. The semiconductor package includes a first silicon lens formed along a first surface of a silicon substrate. The semiconductor package includes a second silicon lens formed along a second surface of the silicon substrate, the second surface opposite the first surface.The electronic die is formed along the second surface of the silicon substrate.

[0070] In yet another aspect of the present disclosure, a method of manufacturing a semiconductor package is disclosed. The method includes forming a first silicon lens along a first surface on a first side of a silicon substrate and in a first region on the first side. The method includes forming a second silicon lens along a second surface on a second, opposite side of the silicon substrate and in the first region on the second side. The method includes forming an electronic die on the second side and in a second region laterally adjacent to the first region. The method includes attaching a photonic die to the electronic die on the second side, wherein the photonic die includes a grating coupler vertically aligned with at least one of the first and second silicon lenses.

[0071] As used herein, the terms "about" and "approximately" generally mean ±10% of the stated value. For example, "about 0.5" would encompass 0.45 to 0.55, "about 10" would encompass 9 to 11, and "about 1000" would encompass 900 to 1100.

[0072] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

[1] Semiconductor device comprising: a silicon substrate having first and second opposite sides and first and second regions; a first silicon lens formed in the first region and along a first surface of the silicon substrate on the first side thereof; a second silicon lens formed in the first region and along a second surface of the silicon substrate on its second side; and a photonic die disposed in the first region and on the second side of the silicon substrate. [2] The semiconductor device of claim 1, further comprising a waveguide disposed on the second side of the silicon substrate and including a grating coupler. [3] The semiconductor device of claim 2, wherein the grating coupler is configured to allow the waveguide to receive light through both the first and second silicon lenses. [4] A semiconductor device according to claim 2 or 3, wherein the first and second silicon lenses are arranged to collectively provide a focal point at the grating coupler. [5] A semiconductor device according to any preceding claim, further comprising an electronic die disposed in the second region and on the second side of the silicon substrate. [6] A semiconductor device according to any one of the preceding claims, wherein the photonic die comprises a plurality of conductive structural elements. [7] The semiconductor device according to claim 6, wherein an optical transmission path extending from the first silicon lens through the second silicon lens to a grating coupler of the photonic die does not include the plurality of conductive structural elements. [8] A semiconductor device according to any preceding claim, further comprising a plurality of conductive connectors disposed on a first side of the photonic die opposite a second side thereof facing the silicon substrate. [9] The semiconductor device of claim 8, further comprising a package substrate coupled to the photonic die via at least the plurality of conductive connectors. [10] A semiconductor device according to any one of the preceding claims, wherein the first silicon lens has a first radius of curvature and the second silicon lens has a second radius of curvature, the first radius of curvature being equal to the second radius of curvature. [11] A semiconductor device according to any one of the preceding claims, wherein the first silicon lens has a first radius of curvature and the second silicon lens has a second radius of curvature, the first radius of curvature being different from the second radius of curvature. [12] A semiconductor device according to any one of the preceding claims, wherein the first silicon lens has a first thickness and the second silicon lens has a second thickness, the first thickness being equal to the second thickness. [13] A semiconductor device according to any one of the preceding claims, wherein the first silicon lens has a first thickness and the second silicon lens has a second thickness, the first thickness being different from the second thickness. [14] Semiconductor package with: a substrate disposed over a package substrate; a grating coupler arranged above the substrate; a plurality of first conductive structural elements arranged above the grating coupler; an electronic die disposed over the plurality of first conductive features and including a plurality of second conductive features; a first silicon lens formed along a first surface of a silicon substrate; and a second silicon lens formed along a second surface of the silicon substrate, the second surface opposite the first surface, the electronic die formed along the second surface of the silicon substrate. [15] The semiconductor package of claim 14, wherein the first and / or second silicon lens is / are aligned vertically to the grating coupler. [16] The semiconductor package of claim 14 or 15, wherein the first and second silicon lenses are laterally offset from each other by a distance, the distance being about 0 µm to about 100 µm. [17] A semiconductor package according to any one of claims 14 to 16, wherein the first and second silicon lenses are arranged to collectively provide a focal point at the grating coupler. [18] A semiconductor package according to any one of claims 14 to 17, wherein the first and second silicon lenses each have a hemispherical profile. [19] A method of manufacturing a semiconductor package, comprising: Forming a first silicon lens along a first surface on a first side of a silicon substrate and in a first region on the first side; Forming a second silicon lens along a second surface on a second, opposite side of the silicon substrate and in the first region on the second side; Forming an electronic die on the second side and in a second region laterally adjacent to the first region; and Attaching a photonic die to the electronic die on the second side, the photonic die comprising a grating coupler vertically aligned with the first and / or second silicon lens. [20] The method of claim 19, wherein the step of forming the first silicon lens and the step of forming the second silicon lens each further comprise: (a) forming a mask over the corresponding area of the silicon substrate; (b) etching the silicon substrate using the mask; (c) lateral reduction of the mask; (d) etching the silicon substrate using the reduced mask; (e) repeating steps (c) and (d) to form a stair profile; and (f) Rounding the stair profile.

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