Semiconductor device with field plate structure

Abstract

A semiconductor device comprises a substrate (100), an insulating layer (120), and a field-plate structure (200). The substrate (100) has a background doping of a first conductivity type and a first doped region (170) of a second conductivity type that is complementary to the first conductivity type. The insulating layer (120) is formed on a major surface (101) of the substrate (100). The field-plate structure (200) is formed on the insulating layer (120) between the first doped region (170) and a boundary structure (190), wherein the field-plate structure (200) has a high-resistance and / or semi-insulating junction (259) with at least one non-floating conductive structure (140).

Description

TECHNICAL AREA

[0001] This disclosure relates to semiconductor devices with a field-plate structure. Examples of this disclosure relate to high-voltage integrated circuits (HVICs) with embedded high-voltage devices and power semiconductor devices with lateral termination structures. BACKGROUND

[0002] Semiconductor chips for power semiconductor devices with vertical load current flow include lateral termination structures to reduce the electric field towards the lateral edge of the semiconductor chip. Integrated high-voltage circuits in CMOS (complementary metal oxide semiconductor) technology often include a low-side part operating in a low-voltage domain, a high-side part operating in a high-voltage domain, and an embedded high-voltage component for signal exchange between the high-side and low-side components. The embedded high-voltage component includes a voltage transition region to reduce the electric field in the lateral direction. Both the lateral termination structures in power semiconductor devices and the voltage transition regions in integrated high-voltage circuits define the breakdown voltage of the semiconductor device.Field plate structures often shape the electric field in the lateral termination structures and voltage transition areas to avoid critical field peaks.

[0003] There is a constant need to improve the long-term stability of component parameters in semiconductor devices with field plate structures. SUMMARY

[0004] A semiconductor device comprises a substrate, an insulating layer, and a field-plate structure. The substrate has a background doping of a first conductivity type and includes a first doped region of a second conductivity type that is complementary to the first. The insulating layer is formed on a major surface of the substrate. The field-plate structure is formed on the insulating layer between the first doped region and a boundary structure. The field-plate structure features a high-resistance and / or semi-insulating connection with at least one non-floating conductive structure. The high-resistance and / or semi-insulating connection allows for the slow transport of charge carriers to and / or from the field-plate structure.The charge in the field plate structure can slowly adapt to charges that accumulate and dissipate over time in passivation layers and / or a molding material formed over the field plate structure. This can lead to a slowly varying breakdown voltage of the semiconductor device in the absence of the high-resistance and / or semi-insulating junction. Combining the field plate structure with the charge shielding layer improves shielding on long timescales, while the combination has little effect on short timescales such as switching events.

[0005] The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference symbols refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various examples shown may be combined, provided they are not mutually exclusive. Fig. Figure 1 is a schematic vertical cross-sectional view of a section of a semiconductor device with a field plate structure and a high-resistance and / or semi-insulating connection of the field plate structure according to one embodiment. Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D includes vertical cross-sectional views of sections of three semiconductor devices with a field plate structure and various high-resistance and / or semi-insulating connections of the field plate structure according to embodiments. Fig. Figure 3 is a schematic vertical cross-sectional view of a section of a semiconductor device with a charge shielding layer in direct contact with a contact structure for a first doped region and an edge structure according to one embodiment. Fig. 4A, Fig. 4B and Fig. Figure 4C includes vertical cross-sectional views of sections of three semiconductor devices with a charge shielding layer in direct contact with various field plate structures according to embodiments. Fig. Figure 5 is a schematic vertical cross-sectional view of a section of a semiconductor device with a field plate structure formed over a voltage junction structure, according to one embodiment. Fig. 6A, Fig. 6B and Fig. Figure 6C includes vertical cross-sectional views of sections of three semiconductor devices with a field plate structure formed over various voltage transition structures, according to embodiments. Fig. Figure 7 is a schematic horizontal cross-sectional view of a semiconductor device with a voltage junction structure formed along a lateral outer surface of a semiconductor chip, according to an embodiment relating to power semiconductor devices. Fig. Figure 8 is a schematic horizontal cross-sectional view of a semiconductor device with a high-voltage device comprising an embedded voltage junction structure, according to an embodiment relating to HVICs. Fig. Figure 9 is a schematic horizontal cross-sectional view of a semiconductor device with a voltage junction structure and a field plate structure with two ring sections formed along a lateral outer surface of a semiconductor chip, according to an embodiment relating to power semiconductor devices. Fig. Figure 10 is a schematic horizontal cross-sectional view of a semiconductor device with a high-voltage device comprising an embedded voltage junction structure and a field plate structure with two ring sections, according to an embodiment relating to HVICs. Fig. Figure 11 is a schematic vertical cross-sectional view of a section of a semiconductor device with a field plate structure formed over a variation of a lateral doping region and with a charge shielding layer connected to contact structures on both sides of the voltage transition region, according to one embodiment. Fig. Figure 12 is a schematic vertical cross-sectional view of a section of a semiconductor device with a field plate structure having a plurality of laterally separated field rings, according to one embodiment. Fig. Figure 13 is a schematic vertical cross-sectional view of a section of a semiconductor device having a silicon-on-insulator (SOI) configuration and a field plate structure having a plurality of laterally separated field rings, according to one embodiment. Fig. Figure 14 is a schematic vertical cross-sectional view of a section of a semiconductor device with a SOL configuration and a field plate structure having a plurality of laterally separated field rings with tile sections in another metallization layer, according to one embodiment. Fig. Figure 15 is a diagram showing the leakage current as a function of the reverse voltage for various field-effect transistors to discuss the effects of the embodiments. Fig. Figure 16 is a diagram showing the breakdown voltage as a function of the charge density in a passivation layer for various field-effect transistors to discuss effects of the embodiments. Fig. Figure 17 is a diagram showing the drain current of a field-effect transistor as a function of a drain voltage for various field-effect transistors to discuss the effects of the embodiments. Fig. Figure 18 is a timing diagram showing the voltage response of various field-effect transistors to discuss the effects of the embodiments. Fig. Figure 19 is a schematic block diagram of a gate driver circuit with BJTs and MOSFETs for routing differential data signals from a high-side part to a low-side part and from the low-side part to the high-side part according to one embodiment. DETAILED DESCRIPTION

[0007] The terms "have," "contain," "comprise," and the like are open-ended and indicate the presence of certain structures, elements, or features, but do not exclude the presence of additional elements or features. The articles "a," "an," and "the" include both the plural and the singular unless the context clearly indicates otherwise.

[0008] The terms "signal-linked" and "electrically coupled" encompass a permanent, low-resistance ohmic connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material, but do not preclude the presence of other passive and / or active elements in the signal path between the "signal-linked" or "electrically coupled" elements. For example, these other elements may include resistors, ohmic conductors, capacitors and / or inductors, transistors, semiconductor diodes, Schottky diodes, transformers, optocouplers, and others.

[0009] The term "power semiconductor device" refers to semiconductor devices with a high-voltage blocking capability of at least 30 V, for example 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV or more, and with a nominal forward or forward current of at least 200 mA, for example 1 A, 10 A or more.

[0010] The term “vertical power semiconductor device” refers to power semiconductor devices with a vertical load current flow between a first load electrode on one front side of a semiconductor chip and a second load electrode on the opposite side, where the thickness of the semiconductor chip in the vertical direction is typically less than the horizontal extent of the semiconductor chip.

[0011] An ohmic contact describes a non-rectifying electrical junction between two conductors, e.g., between a semiconductor material and a metal. The ohmic contact exhibits a linear or nearly linear current-voltage (IV) curve in the first and third quadrants of the IV diagram, as described by Ohm's law.

[0012] Ranges specified for physical dimensions include the limit values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least".

[0013] The term "on" should not be interpreted as meaning only "directly on". Rather, if one element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) can be positioned between the two elements (e.g., another layer can be positioned between a layer and a substrate if the layer is "on" the substrate).

[0014] Two adjacent doped regions in a semiconductor layer form a semiconductor junction. Two adjacent doped regions of the same conductivity type but with different dopant concentrations form a unipolar junction, e.g., an n / n+ or p / p+ junction along an interface between the two doped regions. At the unipolar junction, a dopant concentration profile orthogonal to the junction may exhibit a step or inflection point where the dopant concentration profile changes from concave to convex or vice versa. Two adjacent doped regions with complementary conductivities form a pn junction.

[0015] The figures represent relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" signifies a doping concentration lower than that of an "n" doped area, while an "n+" doped area has a higher doping concentration than an "n" doped area. Doped areas with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped areas can have the same or different absolute doping concentrations.

[0016] The examples described herein provide a semiconductor device that may comprise a substrate, an insulator layer, and a field-plate structure. The substrate has a background doping of a first conductivity type and includes a first doped region of a second conductivity type that is complementary to the first conductivity type. The insulator layer is formed on a major surface of the substrate. The field-plate structure is formed on the insulator layer between the first doped region and a boundary structure, wherein the field-plate structure has a high-resistance and / or semi-insulating connection with at least one non-floating conductive structure.

[0017] The substrate can be a semiconducting substrate in which the doped regions of a power semiconductor device are formed, e.g., a single-crystal silicon substrate. Alternatively, the substrate can be the semiconducting base substrate of a semiconductor-on-insulator (SOI) device. A primary surface on a front side of the substrate and an opposite back surface are formed in parallel horizontal planes. A normal to the primary surface defines a vertical direction orthogonal to the primary surface. The first conductivity type can be n-type and the second conductivity type p-type. Alternatively, the first conductivity type can be p-type and the second conductivity type n-type.

[0018] The first doped region can extend from the main surface into the substrate and can form a pn junction with a substrate base section, where the substrate base section contains only the background doping. The boundary structure can include a second doped region extending from the main surface into the substrate. The first and second doped regions can have the same conductivity type or complementary conductivity types.

[0019] For SOl devices, e.g., HVICs, the first and second doped regions can have the same conductivity type, and an internal termination can be formed in the substrate between the first and second doped regions. In at least one lateral direction, the second doped region can be formed at a relatively large distance from a lateral outer surface of the substrate, and further semiconductor elements can be formed between the second doped region and the lateral outer surface.

[0020] For a vertical current-flow, lateral edge-terminated power semiconductor device, the second doped region can form a channel-stopper region extending along or adjacent to the lateral outer surface of the substrate. The channel-stopper region is configured to suppress charge carrier flow to / from the lateral outer surface of the substrate and can have the same conductivity type and a higher doping concentration than the substrate base section. In the absence of a channel-stopper region, the lateral outer surface can form the edge structure.

[0021] The insulating layer can be a homogeneous layer or a stack of layers with two or more sublayers of different material composition and / or structure. The insulating layer can comprise silicon oxide, e.g., thermally grown silicon oxide and / or deposited silicon oxide, a layer of silicon nitride and / or silicon oxynitride, and / or a silicate glass. The insulating layer can be formed directly on the main surface.

[0022] The field plate structure can be formed directly on the insulating layer. Alternatively, a semiconductor layer, one or more metallization layers, and a corresponding number of interlayer dielectrics can be formed between the insulating layer and the field plate structure in a vertical direction orthogonal to the main surface. The field plate structure can comprise one or more laterally separated field plate sections of the same material composition. The field plate sections can be equidistant. Each field plate section can be a homogeneous structure or can comprise two or more horizontal sublayers of different material composition and / or internal structure. Each field plate section can comprise heavily doped polycrystalline silicon, an elemental metal, a metal alloy, and / or a metal compound.

[0023] At least one, a majority, or all of the field plate sections have a high-resistance and / or semi-insulating connection with one, two, or more non-floating conductive structures. The non-floating conductive structure can be a conductive structure that exhibits a non-floating potential when the semiconductor device is in operation and an active semiconductor element, a passive voltage divider, or an external device via a component terminal applies a potential to the non-floating conductive structure. Each of the non-floating conductive structures can include a contact structure that forms an ohmic contact with a doped region in the substrate and / or a doped device region in a semiconductor layer formed on the insulating layer.Alternatively, the non-floating conductive structure can be an auxiliary conductor or include an auxiliary conductor that receives a potential from an active semiconductor element, a passive voltage divider, or via a component terminal from an external device.

[0024] During operation, charge carriers can accumulate over a long period in passivation layers and / or in a molded material formed over the main surface of the substrate and / or the field plate structure. The amount of accumulated charge can change over time. Without a high-resistance and / or semiconducting connection, the fluctuating charge can alter characteristic parameters of the semiconductor device, such as breakdown voltage and / or leakage current, over time.

[0025] The high-resistance and / or semi-insulating junction enables charge carrier transport to the field plate structure sufficient to allow for the slow self-adjustment of a mirror-image charge that builds up in the field plate structure over time. For this purpose, the high-resistance and / or semi-insulating junction allows significantly better transport of electrons and / or holes than a silicon oxide layer, a silicon nitride layer, a polyimide layer, or a conventional molding material. The high-resistance and / or semi-insulating junction allows significantly less transport of electrons and / or holes than a metal layer, so that a leakage current to / from the first doped region through the high-resistance and / or semi-insulating junction is smaller than or of the same order of magnitude as parallel leakage paths.The charge carrier build-up is several orders of magnitude slower than the switching time of the semiconductor device.

[0026] In combination with the charge shielding layer, a mirror-image charge in the field plate structure largely compensates for the accumulated charges in the passivation layer and / or the molding material at all times, thus reducing the effect of the accumulated charge on the device properties. Furthermore, the electrical separation of the field plate sections from the non-floating conductive structure and other conductive structures is still sufficiently strong that the field plate sections can be considered electrically floated when the semiconductor device operates as intended.

[0027] According to one embodiment, the non-floating conductive structure can comprise a contact structure, wherein the contact structure forms an ohmic contact with one of the first doped regions and a second doped region, wherein the second doped region can be part of the edge structure.

[0028] According to another embodiment, the non-floating conductive structure can comprise a contact structure, wherein the contact structure forms an ohmic contact with a doped device area of ​​a semiconductor layer formed on the insulating layer.

[0029] According to one embodiment, the high-resistance and / or semi-insulating connection can comprise a charge shielding layer in direct contact with the field plate structure and the non-floating conductive structure.

[0030] The charge shielding layer is high-resistance and / or semi-insulating. In addition to the charge shielding layer, the high-resistance and / or semi-insulating connection may include one or more low-resistance sections electrically connected in series between the charge shielding layer and the non-floating conductive structure. The low-resistance sections may comprise a metallic structure, such as a metal conductor.

[0031] The conductivity of the charge shielding layer can be a function of the electric field to which the charge shielding layer is exposed, or it can be independent of the electric field. For example, the material of the charge shielding layer can have a resistivity greater than 1 Ωcm, for example, greater than 10 4The resistivity is measured in Ωcm at a temperature of 25 degrees Celsius and can be metallic or semiconducting. The resistivity can increase with increasing temperature (metallic) or decrease (semiconductor). The charge shielding layer can be a homogeneous layer or a stack of layers consisting of two or more sublayers with different material compositions and / or structures. The charge shielding layer can include or consist of a layer of high-purity semiconductor material, such as amorphous silicon (a-Si), diamond-like carbon (DLC), or silicon-rich silicon nitride (SiSiN) with a higher silicon content than stoichiometric Si3N4.The charge shielding layer can be a one-piece structure that allows a comparatively slow charge carrier transport between the field plate sections and at least one of the first doped regions, the second doped region in the boundary structure and the auxiliary conductor on a very small scale, which may be lower than or on the same order of magnitude as other leakage currents to or from the first doped region.

[0032] According to one embodiment, the charge shielding layer (250) can be formed directly on the field plate structure (200).

[0033] According to one embodiment, the semiconductor device may further comprise an insulating passivation layer formed on the charge shielding layer.

[0034] The passivation layer is formed from one or more insulator materials and may, for example, include an organic insulator such as a polyimide. The passivation layer may be formed directly on the charge shielding layer or it may be separated from the charge shielding layer, for example, by a barrier layer. The passivation layer material may tend to generate, absorb, and / or release ions. A form material may embed the semiconductor chip. The form material may tend to generate, absorb, and / or release ions when the semiconductor device operates under ambient conditions.

[0035] According to one embodiment, the semiconductor device can include a separating layer that separates the charge shielding layer and the passivation layer.

[0036] The separating layer can be a homogeneous layer or can comprise two or more sublayers of different materials, e.g., a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer. The separating layer can form a diffusion barrier that prevents moisture and / or ions from diffusing from the passivation layer and the mold material into the charge shielding layer and beyond. The separating layer increases the distance between the metal field plate sections and the passivation layer and reduces the electric field in sections of the passivation layer, particularly near the top edges of the field plate sections.

[0037] According to one embodiment, the field plate structure can include a metal section and the charge shielding layer can be formed directly on the metal section.

[0038] The field plate structure can comprise two or more laterally separated field plate sections, with each field plate section encompassing a portion of the metal section. The metal section and other metal contact structures of the semiconductor device can be formed from the same deposited metal layer. The charge shielding layer can be structured together with a subsequently deposited passivation layer.

[0039] According to one embodiment, the field plate structure can include a polysilicon section formed from doped polycrystalline silicon, and the charge shielding layer can be formed directly on the polysilicon section.

[0040] The field plate structure can comprise two or more laterally separated field plate sections, with each section containing a portion of the polysilicon section. Compared to metal field plate sections, polycrystalline field plate sections can be structured with higher precision. Each part of the polycrystalline section can have a uniform width, a uniform vertical extent, and a uniform doping concentration. Deposition and structuring of a polycrystalline silicon layer to form the polycrystalline field plate sections adds only a small amount of additional effort to the manufacturing process.

[0041] According to one embodiment, the field plate structure can comprise a polycrystalline section formed at a distance from the main surface and a metal section formed in direct contact with the polycrystalline section on one side of the polycrystalline section opposite the substrate, wherein the charge shielding layer is formed directly on the metal section.

[0042] The field-plate structure can comprise two or more laterally separated field-plate sections, each field-plate section containing a portion of the metal section and a portion of the polysilicon section. The polycrystalline portions can be formed from laterally separated sections of a planar polycrystalline layer. A second interlayer dielectric can be formed on top of the laterally separated sections of the planar polycrystalline layer. Openings in the second interlayer dielectric can expose the separated portions of the polycrystalline section. A deposited metal fills the openings. A layer formed from the deposited metal is structured to form laterally separated portions of the metal section.The charge shielding layer can cover the area of ​​the metal section above the second interlayer dielectric and can therefore be patterned together with the passivation layer without an additional lithography process. Since the charge shielding layer is deposited only after the metal layers and interlayer dielectrics have been deposited and patterned, the process control for the charge shielding layer is simplified.

[0043] According to one embodiment, the semiconductor device may further comprise a voltage junction structure formed in the substrate between the first doped region and the edge structure, wherein the voltage junction structure is configured to reduce a maximum electric field in the substrate when a voltage is present between the first doped region and the edge structure.

[0044] The voltage junction structure reduces the maximum electric field strength that occurs in a section of the substrate between the first doped region and the boundary structure, for example, when a voltage is applied between the first and second doped regions, or between the first doped region and a backside electrode formed on the back side of the substrate opposite the main surface. The voltage junction structure can smooth the curvature of a depletion zone (charge space zone) that develops along the pn junction between the substrate base section and the first doped region.

[0045] The voltage junction structure can be a single-piece structure in lateral contact with the first doped region. Such a single-piece structure can form a junction termination region with a lower maximum dopant concentration than the first doped region. For vertical high-voltage semiconductor devices, the junction termination region is part of the lateral edge termination of the semiconductor device and resembles a junction termination extension (JTE) of the first doped region.

[0046] Alternatively, the one-piece structure can be a variation of a lateral doping region in which the dopant concentration decreases laterally with increasing distance from the first doped region. For vertical power semiconductor devices, the variation of a lateral doping region is part of the lateral edge termination of the semiconductor device and is similar to a variation of a lateral doping VLD of the first doped region.

[0047] Alternatively, or in combination with a transition termination region or a variation of a lateral doping region, the voltage transition structure can include one, two, or more protective regions of the second conductivity type, separated laterally from each other, the first doped region, and the boundary structure. Each of at least some or all of the protective regions can be formed in the vertical projection of one of the field plate sections, with the protective region and the corresponding field plate section being capacitively coupled.

[0048] According to one embodiment, the stress junction structure can laterally surround the first doped region.

[0049] For a vertical power semiconductor device, the voltage junction structure can be formed in an edge termination region that laterally separates the first doped region from the lateral outer surface of the substrate in all lateral directions. For a SOI device, the voltage junction structure can be formed in a device junction region that laterally separates a low-side portion of the SOI device from a high-side portion, where both the low-side and high-side portions contain digital and / or analog circuitry, and the reference potentials of the high-side and low-side portions differ from each other by more than 60 V during operation, e.g., more than 600 V.

[0050] According to one embodiment, the field plate structure can laterally surround the first doped region. For a vertical power semiconductor device, the field plate sections of the field plate structure can be formed in the edge termination region that laterally separates the first doped region from the lateral outer surface of the substrate in all lateral directions. For an SOI device, the field plate sections are formed in the device transition region.

[0051] According to one embodiment, the edge structure can include a lateral outer surface of the substrate. The semiconductor device can be a vertical power semiconductor device, such as a high-voltage (HV) semiconductor diode, a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), or a MOSFET (metal-oxide semiconductor field-effect transistor) in the usual sense, including insulated-gate field-effect transistors (IGFETs) with polysilicon gate electrodes, such as a silicon MOSFET or a silicon carbide (SiC) MOSFET, or an insulated-gate bipolar transistor (IGBT). If the semiconductor device is an HV semiconductor diode, the first doped region forms an anode region. If the semiconductor device is a MOSFET or IGBT, the first doped region forms the body region for the transistor cells, the body region separating the transistor cell source regions from a common drain / drift structure.The insulating layer can be formed directly on the main surface of the substrate and forms an intermediate dielectric layer that vertically separates the substrate from a first metallization layer in which the field plate structure can be formed.

[0052] According to another embodiment, the semiconductor device can further comprise a semiconductor layer formed on the insulating layer and a first interlayer dielectric formed on the semiconductor layer, wherein the field plate structure is formed above the first interlayer dielectric.

[0053] The field plate structure can be formed directly on the first interlayer dielectric. Alternatively, further metallization layers and interlayer dielectrics can be formed between the field plate structure and the first interlayer dielectric. The edge structure can include a second doped region of the second conductivity type. Digital and / or analog circuits can be formed in at least one lateral direction between the lateral outer surface and an outer edge of the field plate structure. The semiconductor device is a high-voltage integrated circuit (HVIC), e.g., a power factor correction controller or a gate driver circuit.

[0054] According to one embodiment, the semiconductor device can further comprise a first metallization structure formed directly on the first interlayer dielectric and a second interlayer dielectric formed directly on the first metallization structure, wherein the field plate structure can comprise a first section formed from a section of the first metallization structure and a second section formed on the second interlayer dielectric. The field plate structure can be formed in a second metallization layer.

[0055] According to one embodiment, the field plate structure can comprise a plurality of laterally separated field plate sections, and the first metallization layer can comprise a plurality of laterally separated tile sections, each tile section being electrically connected to at least one of the field plate sections. The tile sections can increase the horizontal area covered by the field plate structure and can improve the shielding effect of the field plate structure.

[0056] According to one embodiment, the tile sections can be formed in gaps between the field plate sections. Each tile section can extend over at least 50% of the gap between the two adjacent metal field plate sections. For example, each tile section can extend completely over the gap between the two adjacent field plate sections of the tile section, with a lateral width of the tile section being greater than the lateral distance between the two adjacent field plate sections on either side of the gap. Any vertical line intersecting the main surface between the first doped area and the edge structure can intersect a tile section and / or one of the field plate sections.

[0057] Fig. Figure 1 shows a semiconductor chip with a substrate 100 made of single-crystal silicon. A main surface 101 on a front side of the substrate 100 and an opposite back surface 102 are formed in parallel horizontal planes. A normal to the main surface defines a vertical direction orthogonal to the main surface 101.

[0058] Substrate 100 has a background doping of a first conductivity type. A first doped region 170 of a second conductivity type, complementary to the first conductivity type, extends from the main surface 101 into substrate 100. A substrate base section 109 of substrate 100 contains only the background doping. The first doped region 170 and the substrate base section 109 form a pn junction 179.

[0059] An insulating layer 120 is formed directly on the main surface 101. The insulating layer 120 comprises silicon oxide, e.g., thermally grown silicon oxide and / or deposited silicon oxide, a layer of silicon nitride, a layer of silicon oxynitride, and / or a layer of silicate glass.

[0060] An edge structure 190 is formed at a lateral distance from the first doped region 170. The edge structure 190 can be or comprise a lateral outer surface of the semiconductor chip, a doped region extending from the main surface 101 into the substrate 100, an insulating trench structure extending from the main surface 101 into the substrate 100, a conductive structure formed on the insulating layer 120, a conductive structure formed on the main surface 101 of the substrate 100, or a conductive structure extending from the main surface 101 into the substrate 100.

[0061] A field plate structure 200 is formed on the insulator layer 120 between the first doped region 170 and the edge structure 190. The field plate structure 200 comprises laterally separated field plate sections 205 of the same material composition. Each field plate section 205 is a homogeneous structure made of highly doped polycrystalline silicon, an elemental metal, a metal alloy, and / or a metal compound.

[0062] A high-resistance and / or semi-insulating connection 259 structurally connects the field plate structure 200 to a non-floating conductive structure 140, which is formed directly on the main surface 101 or at a distance from the main surface 101. The high-resistance and / or semi-insulating connection 259 may comprise one or more low-resistance sections that are electrically connected in series with one or more high-resistance and / or semi-insulating sections.

[0063] During operation, charge carriers can accumulate in layers above the field plate structure 200 over a long period of time. The amount of accumulated charge can vary over time. The high-resistance and / or semi-insulating junction 259 allows the charge on the field plate structure 200 to follow the constantly changing charge in the layers above the field plate structure 200 and continuously reflect the amount of charge accumulated there, so that characteristic parameters of the semiconductor device, such as breakdown voltage and / or leakage current, remain stable over time. On the other hand, the charge transport through the high-resistance and / or semi-insulating junction 259 is slow enough to have no significant influence on the switching behavior.

[0064] In Fig. 2A includes the edge structure 190 and a second doped region 195 extending from the main surface 101 into the substrate 100. The second doped region 195 exhibits the second conductivity type. The second doped region 195 and the substrate base section 109 form another pn junction. The field plate structure 200 forms part of a voltage junction structure 180 located between the first doped region 170 and the second doped region 195. The voltage junction structure 180 forms an in-device termination between a low-side region and a high-side region of a high-voltage integrated circuit (HVIC).In at least one lateral direction, a distance d1 between an inner edge of the second doped region 195, which is aligned to the first doped region 170, and a lateral outer surface 103 of the substrate 100 can be comparatively large, and further semiconductor elements can be formed between the inner edge of the second doped region 195 and the lateral outer surface 103.

[0065] The non-floating conductive structure 140 comprises a first contact structure 290, which forms an ohmic contact with the first doped region 170, and a second contact structure 290, which forms an ohmic contact with the second doped region 195. The high-resistance and / or semi-insulating connection 259 structurally connects the field plate structure 200 to the contact structures 290.

[0066] In Fig. 2B includes the edge structure 190 and a second doped region 195 that extends along the lateral outer surface 103 of the substrate 100 from the main surface 101 into the substrate 100. The second doped region 195 exhibits the first conductivity type. The second doped region 195 and the substrate base section 195 form a unipolar junction. The field-plate structure 200 forms part of a voltage junction structure 180 that is formed between the first doped region 170 and the second doped region 195. The voltage junction structure 180 forms an edge termination between a functional part of the semiconductor chip and the lateral outer surface 103. No other semiconductor elements are formed between the outer edge of the second doped region 195 and the lateral outer surface 103.

[0067] The second doped region 195 forms a channel stopper region 198, which suppresses a charge carrier flow to / from the lateral outer surface 103 of the substrate 100, and can have the same conductivity type and a higher doping level than the substrate base section 109.

[0068] The non-floating conductive structure 140 comprises a first contact structure 290, which forms an ohmic contact with the first doped region 170, and a second contact structure 290, which forms an ohmic contact with the second doped region 195. The high-resistance and / or semi-insulating connection 259 structurally connects the field plate structure 200 to the contact structures 290.

[0069] In Fig. 2C forms the lateral outer surface 103 and the edge structure 190. In addition to a field plate structure 200 with two laterally separated field plate sections 205, the voltage transition structure 180 comprises protection zones 185 of the second conductivity type. The protection zones 185 are laterally separated from each other. Each protection zone 185 can be formed directly beneath a field plate section 205, with the insulating layer 120 separating the protection zones 185 from the field plate sections 205. Each protection zone 185 is capacitively coupled to a corresponding field plate section 205.

[0070] The non-floating conductive structure 140 comprises a contact structure 290 that forms an ohmic contact with the first doped region 170. The high-resistance and / or semi-insulating connection 259 structurally connects the field plate structure 200 to the contact structures 290.

[0071] In Fig. 2D includes the boundary structure 190, a first doped region 170, and a second doped region 195, extending from the main surface 101 into the substrate 100. Similar to in Fig. 2A forms a field plate structure 200 as part of a voltage junction structure 180, which is formed between the first doped region 170 and the second doped region 195. The voltage junction structure 180 forms an internal termination between a low-side region and a high-side region of an HVIC. A semiconductor layer 130 is formed on the insulating layer 120. A first interlayer dielectric 210 is formed on the semiconductor layer 130. A field plate structure 200 is formed on the first interlayer dielectric 210 between the first doped region 170 and the second doped region 195.

[0072] The non-floating conductive structure 140 comprises a contact structure 290, which forms an ohmic contact with a doped device area 137 in the semiconductor layer 130. A further doped device area 138 is formed in the semiconductor layer 130. The doped device areas 137 and 138 can be the anode and cathode regions of a high-voltage semiconductor diode, the source and drain regions of a MOSFET or JFET, or the emitter and collector regions of a BJT or IGBT. The high-resistance and / or semi-insulating connection 259 structurally connects the field plate structure 200 to the contact structure 290.

[0073] The non-floating conductive structure 140 comprises a contact structure 290, which forms an ohmic contact with the first doped region 170. The high-resistance and / or semi-insulating connection 259 structurally connects the field plate structure 200 to the contact structure 290.

[0074] Fig. Figure 3 shows a metal contact structure 290 extending from the front face into the first doped region 170. A charge shielding layer 250 is formed directly on the field plate structure 200 and on sections of the insulator layer 120 between the field plate sections 205.

[0075] The material of the charge shielding layer 250 has a specific resistance of more than 1 Ωcm, for example more than 10 4 The resistance is measured in Ωcm at a temperature of 25 degrees Celsius and is metallic or semiconducting in nature, with the specific resistance increasing with increasing temperature as for metals or decreasing as for semiconductors. The charge shielding layer 250 is a silicon-rich silicon nitride SiSiN with a higher silicon content than stoichiometric Si3N4.

[0076] Fig. 4A, Fig. 4B and Fig. Figure 4A shows a passivation layer 270 formed on the charge shielding layer 250. The passivation layer 270 fills the gaps between the field plate sections 205 and can have a planar surface on the front side.

[0077] The passivation layer 270 contains one or more fully insulating (not semi-insulating) insulating materials, e.g., a silicate glass or an organic insulating material such as a polyimide. The passivation layer 270 can be formed directly on the charge-shielding layer 250 or can be separated from the charge-shielding layer 250, e.g., by a separating or barrier layer. The material of the passivation layer 270 may be prone to generating, absorbing, and / or releasing ions. The material of the passivation layer 270 has a higher resistivity than the material of the charge-shielding layer 250. At a temperature of 25 degrees Celsius, the resistivity of the material of the passivation layer 270 is at least one order of magnitude higher than the resistivity of the material of the charge-shielding layer 250.

[0078] A molding material 280 is formed on the passivation layer 270 and partially encapsulates the semiconductor chip. The molding material 280 may include a fusible organic resin, such as epoxy resin, non-fusible inorganic fillers, catalysts to accelerate the curing reaction, a mold release material that allows the organic resin to exit a mold, pigments, flame retardants, adhesion promoters, ion traps, and / or stress relief agents. The molding material may tend to generate, absorb, and / or release ions when the semiconductor device operates under ambient conditions.

[0079] In Fig. In 4A, the field plate structure 200 comprises only one metal section 206, which forms the field plate sections 205. The metal section 206 forms the laterally separated field plate sections 205 directly on the insulating layer 120. The charge shielding layer 250 is formed directly on the metal section 206.

[0080] In Fig. In 4B, the field plate structure 200 comprises only a single polysilicon section 207 formed from doped polycrystalline silicon. The polysilicon section 207 forms the laterally separated field plate sections 205 directly on the insulating layer 120. The charge shielding layer 250 is formed directly on the polysilicon section 207. Unlike helical field plate structures, the charge conduction properties of the shielding structure, which comprises the polysilicon section 207 and the charge shielding layer 250, are adjusted via the thickness and specific conductivity of the charge shielding layer. The etching process, which defines the field plate structure 200 from a deposited polysilicon layer and / or a sacrificial oxide process, can round the top edges of the polysilicon field plate sections 205 to reduce the maximum electric field.

[0081] In Fig. 4C comprises the field plate structure 200, a polycrystalline section 207 with laterally separated sections formed directly on the insulating layer 120. A first interlayer dielectric 210 covers the polysilicon section 207 and fills the gaps between the laterally separated sections of the polysilicon section 207. A metal section 206 with laterally separated sections is formed on the first interlayer dielectric 210. A via of each laterally separated section of the metal section 206 extends through the first interlayer dielectric 210 to a section of the polysilicon section 207. The charge shielding layer 250 is formed directly on the metal section 206. Each field plate section 205 comprises a section of the metal section 206, which includes a via, and a section of the polysilicon section 207.Since the charge shielding layer 250 is formed after the uppermost metal layer, the charge shielding layer 250 can be structured together with the passivation layer 270.

[0082] Fig. Figure 5 shows a voltage junction structure 180 formed in the substrate 100 between the first doped region 170 and the edge structure 190. The voltage junction structure 180 reduces the maximum electric field in the substrate 100 when a voltage is present between the first doped region 170 and the edge structure 190.

[0083] The voltage transition structure 180 can form part of an internal termination between a low-side part and a high-side part of an HVIC or part of a lateral edge termination of a power semiconductor device.

[0084] The voltage transition structure 180 comprises one or more differently defined doped regions of the conductivity type of the first doped region 170, e.g. a JTE region, a VLD region and / or protection regions.

[0085] Fig. Figure 6A shows a section of an HVIC with a first doped region 170 formed in a first voltage domain region and a second doped region 195 in a second voltage domain region of a substrate 100. The first voltage domain region is a first of the low-side and high-side regions. The second voltage domain region is the second of the low-side region of the high-side region. In at least one lateral direction, a distance d1 between the inner edge of the second doped region 195 and a lateral outer surface 103 of the substrate 100 is large enough to allow logic circuits and / or analog circuits to be formed between the inner edge of the second doped region 195 and the lateral outer surface 103. An insulating layer 120 is formed on a primary surface 101 at a front face of the substrate 100. Metal contact structures 290 formed on the insulator layer 120 include vias.The vias extend through the insulating layer 120 and form ohmic contacts with the first doped region 170 and the second doped region 195. A field plate structure 200 with laterally separated field plate sections 205 is formed on the insulating layer 120 between the contact structures 290. A charge shielding layer 250 allows moderate charge carrier transport between the field plate sections 205 and the contact structures 290.

[0086] A transition termination region 181 with a lower maximum dopant concentration than the first doped region 170 extends vertically from the main surface 101 into the substrate 100 and laterally from the first doped region 170 to the second doped region 195, extending beyond the outermost field plate section 205 that is closest to the second doped region 195. The vertical extent of the transition termination region 181 is constant over a large part of its lateral extent.

[0087] Fig. Figure 6B shows a section of a power semiconductor device with a first doped region 170 formed in a central area of ​​a substrate 100. A second doped region 195, formed in a peripheral area of ​​the substrate 100 in direct contact with a lateral outer surface 103 of the substrate 100, forms a channel stopper region 198. An insulator layer 120 is formed on a major surface 101 at a front face of the substrate 100. Metal contact structures 290 formed on the insulator layer 120 include vias. The vias extend through the insulator layer 120 and form ohmic contacts with the first doped region 170 and the second doped region 195. A field plate structure 200 with laterally separated field plate sections 205 is formed on the insulator layer 120 between the contact structures 290.

[0088] A variation of a lateral doping region 182 extends vertically from the main surface 101 into the substrate 100 and laterally from the first doped region 170 to the second doped region 195, extending beyond the outermost field plate section 205 that is closest to the second doped region 195. The vertical extent of the variation of the lateral doping region 182 and the dopant concentration within the variation of the lateral doping region 182 decrease laterally with increasing distance from the first doped region 170.

[0089] In Fig. 6C is not a metal contact structure formed between the outermost field plate section 205, which is closest to the lateral outer surface 103, and the lateral outer surface 103. A weakly doped substrate base section 195 may extend along the lateral outer surface 103 from the main surface 101 downwards to the back surface. Laterally separated protective regions 183 of the second conductivity type extend between the first doped region 170 and the lateral outer surface 103 of the substrate 100 from the main surface 101 into the substrate 100. Each protective region 183 is formed directly beneath one of the field plate sections 205. A vertical projection of a protective region 183 into the plane of the main surface 101 and a vertical projection of the associated field plate section 205 into the plane of the main surface 101 overlap each other.

[0090] Fig. Figure 7 shows a front face of a substrate 100 of a power semiconductor device with a p-type first doped region 170 formed in a central device region. The first doped region 170 can form an anode region of a high-voltage semiconductor diode or a body region of an n-channel MOSFET. The cathode region of the high-voltage semiconductor diode or the drain region of the n-channel MOSFET (not shown) is formed along the opposite back surface. In a peripheral device region surrounding the central device region, the lightly n-doped substrate base section 109 brings the back-side potential along the lateral outer surface 103 to the front face. In an edge termination region separating the central device region and the peripheral device region, a junction termination region 181 extends outward from the first doped region 170 to the lateral outer surface.

[0091] Fig. Figure 8 shows a front face of a substrate 100 of a high-voltage integrated circuit (HVIC) with a p-type first doped region 170, formed in a first stress domain region, and a second doped region 195, formed in a second stress domain region of the substrate layer of a SOl configuration. The first stress domain region is a first of both the low-side and high-side parts of the HVIC. The second stress domain region is the second of both the low-side and high-side parts of the HVIC. In an internal termination region separating the first and second stress domain regions, a transition termination region 181 extends from the first doped region 170 outward to the second doped region 195.

[0092] Fig. 9 complements the in Fig. 7 Power semiconductor device shown with a field plate structure comprising two annular field plate sections 205 formed in the edge termination area above the transition termination structure 181.

[0093] Fig. 10 complements the in Fig. 8 HVIC shown with a field plate structure comprising two ring-shaped field plate sections 205 formed in the component-internal termination area above the transition termination structure 181.

[0094] Fig. Figure 11 shows another example of a power semiconductor device with a first doped region 170 formed in a central region of a substrate 100, a second doped region 195 formed in a peripheral region of the substrate 100 in direct contact with a lateral outer surface 103 of the substrate 100, and a variation of a lateral doping region 182 extending laterally from the first doped region 170 to the second doped region 195. For example, the maximum vertical extent of the variation of the lateral doping region 182 and the vertical extent of the first doped region may be equal. Similarly, the maximum dopant concentration in the variation of the lateral doping region 182 and the dopant concentration in the first doped region 170 may also be equal.

[0095] In Fig. 12 An n-doped surface layer 108, formed directly beneath the main surface 101, extends from the variation of the lateral doping area 182 to the lateral surface 103. A metal termination 295 is formed between the field plate structure 200 and the lateral outer surface 103 on the insulator layer 120.

[0096] Fig. 13 and Fig. Figure 14 shows SOI devices. A substrate 100 comprises a single-crystal silicon layer that forms the basis of an SOI chip. An insulating layer 120 is formed on the main surface 101 at one front face of the substrate 100. A semiconductor layer 130 is formed on the front face of the insulating layer 130. A first metallization structure 220 is formed directly on the first interlayer dielectric 210. A second interlayer dielectric 230 is formed directly on the first metallization structure 220.

[0097] At least one section of a field plate structure 200 with laterally separated field plate sections 205 is formed on the second interlayer dielectric 230.

[0098] A first contact structure 290 comprises a section of the first metallization structure 220, a via extending from the first metallization structure 220 through the first interlayer dielectric 210 to a doped device area 137 in the semiconductor layer 130, a metal pad formed on the second interlayer dielectric 230, and a via extending from the metal pad through the second interlayer dielectric 230 to the first metallization structure 220.

[0099] A charge shielding layer 250 is formed directly on the field plate sections 205, the section of the contact structure 290 formed on the second interlayer dielectric 230, and sections of the second interlayer dielectric 230 between the field plate sections 205. A separating layer 275 is formed directly on the charge shielding layer 250 and separates the charge shielding layer 250 from a passivation layer 270 formed on the separating layer 275.

[0100] The separating layer 275 comprises a silicon oxide layer 276 formed directly on the charge-shielding layer 250 and a silicon nitride layer 277 formed directly on the silicon oxide layer. The separating layer 275 may contain silicon oxynitride at least along the interface between the silicon oxide layer 276 and the silicon nitride layer 277. The separating layer 275 forms a diffusion barrier that prevents ions from diffusing from the passivation layer 270 and the molding material into the charge-shielding layer and beyond. By increasing the distance between the metal field plate sections 205 and the passivation layer 270, the separating layer 275 contributes to reducing the electric field in the passivation layer 270.

[0101] In Fig. 13 the field plate structure 200 is completely formed on the second interlayer dielectric 230.

[0102] In Fig. 14 Each field plate section 205 further comprises a tile section 225 formed from a section of the first metallization structure 220 and a via extending from the section formed on the second interlayer dielectric 230 through the second interlayer dielectric 230 to the tile section 225. Each tile section 225 extends completely across a gap between the two sections of adjacent field plate sections 205 formed from the second interlayer dielectric 230.

[0103] Fig.Figure 19 shows a semiconductor device 500 configured as a gate driver circuit. The gate driver circuit comprises a high-side part 620 configured to drive a gate of a high-side switch 922 of a half-bridge, and a low-side part 610 configured to drive a gate of a low-side switch 921 of the half-bridge. The semiconductor-on-insulator device 500 includes a high-side power supply circuit 621 to provide a positive power supply voltage VB for the high-side part 620 (high-side supply potential VB), with a bootstrap diode 360 ​​charging a bootstrap capacitor from an external supply voltage VCC. The positive power supply voltage VB for the high-side part 620 is referenced to a high-side reference potential VS, which corresponds to the potential of the switching node of a half-bridge 920.

[0104] A high-side desaturation detection circuit 622 is connected to the supply potential VA of the half-bridge 920, detects desaturation of the high-side switch 922 of the half-bridge 920, and outputs a high-side desaturation signal indicating whether a desaturation condition exists. A high-side receiver circuit 623 receives a differential gate control signal from two field-effect transistors, e.g., n-channel MOSFETs 381, as described above, and outputs an asymmetric high-side gate control signal. A logic circuit 624 in the high-side part 620 receives the high-side desaturation signal and the high-side gate control signal. The logic circuit 624 in the high-side section 620 outputs a second gate driver signal GOut2 in response to the high-side gate control signal, provided that the high-side desaturation signal does not specify a desaturation condition. A high-side driver stage 625 can drive the second gate driver signal GOut2.

[0105] The logic circuit 624 in the high-side section also outputs a differential high-side data signal. Two PNP BJTs 382, ​​as described above, transmit the differential high-side data signal from the high-side section 620 to a low-side receiver circuit 613 in the low-side section 610.

[0106] The low-side section 610 of the gate driver circuit includes a low-side power supply circuit 611 to provide a positive power supply voltage VDD for the low-side section 610. The positive power supply voltage VDD for the low-side section 610 is referenced to the first reference potential VSS.

[0107] A low-side desaturation detection circuit 612 is connected to the output node of the half-bridge 920, detects desaturation of the low-side switch 921, and outputs a low-side desaturation signal indicating whether a desaturation condition exists. A low-side receiver circuit 613 receives a differential low-side data signal from the PNP BJTs 382 and outputs an asymmetric low-side data signal. A logic circuit 614 in the low-side section 610 receives the low-side data signal, the low-side desaturation signal, and a low-side gate control signal from an external source such as a processor 990. The logic circuit 614 in the low-side section 610 outputs a first gate driver signal GOut1 in response to the low-side gate control signal, provided that neither the low-side desaturation signal nor the low-side data signal specifies a desaturation condition. A low-side driver stage 615 drives the first gate driver signal GOut1.

[0108] The logic circuit 614 in the low-side section 610 also outputs a differential gate control signal. The two n-channel MOSFETs 381 transmit the differential gate control signal from the low-side section 610 to the high-side section 620. An inductive load 930 is electrically connected between the switching nodes of two half-bridges 920.

[0109] The n-channel MOSFETs 381 and pnp-BJTs 382, ​​which have any of the configurations of the present embodiments, improve the signal transmission between the low-side part 610 and the high-side part 620, reduce the leakage current between the high-side part 620 and the low-side part 610, can be made more compact, and can reduce the switching time and therefore improve the performance of the half-bridge 920 by allowing higher switching frequencies.

[0110] Although specific examples have been illustrated and described here, the person skilled in the art will recognize that a multitude of alternative and / or equivalent implementations can replace the specific examples shown and described without altering the scope of protection of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

[0111] It should be noted that the semiconductor device, including its preferred embodiments, as set forth in this document, can be used alone or in combination with the other semiconductor devices disclosed herein. Furthermore, the features set forth in the context of a semiconductor device are also applicable to a corresponding method and vice versa. Moreover, all aspects of the methods and semiconductor devices set forth in this document can be combined as desired. In particular, the features of the claims can be combined with one another in any manner.

[0112] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. A person skilled in the art will be able to implement various arrangements which, although not explicitly described or shown here, embody the principles of the invention and are included in its meaning and scope of protection. Furthermore, all examples and embodiments set forth in this document are expressly intended primarily for illustrative purposes only, to assist the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein that provide principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof.

Claims

[1] Semiconductor device comprising: a substrate (100) with a background doping of a first conductivity type and comprising a first doped region (170) of a second conductivity type that is complementary to the first conductivity type; an insulating layer (120) formed on a main surface (101) of the substrate (100); and a field plate structure (200) formed on the insulator layer (120) between the first doped region (170) and an edge structure (190), wherein the field plate structure (200) has a high-resistance and / or semi-insulating connection (259) with at least one non-floating conductive structure (140). [2] Semiconductor device according to claim 1, wherein the non-floating conductive structure (140) comprises a contact structure (290), wherein the contact structure (290) forms an ohmic contact with a first doped region (170) and a second doped region (195), wherein the second doped region (195) forms part of the edge structure (190). [3] Semiconductor device according to claim 1, wherein the non-floating conductive structure comprises a contact structure (290), wherein the contact structure (290) forms an ohmic contact with a first doped device area (137) and / or a second doped device area (138) of a semiconductor layer (130) formed on the insulating layer (120). [4] Semiconductor device according to one of the preceding claims, wherein the high-resistance and / or semi-insulating connection (259) comprises a charge shielding layer in direct contact with the field plate structure (200) and the non-floating contact structure (140). [5] Semiconductor device according to claim 4, wherein the charge shielding layer (250) is formed directly on the field plate structure (200). [6] Semiconductor device according to claim 4, further comprising: an insulating passivation layer (270) formed on the charge shielding layer (250). [7] Semiconductor device according to claim 6, further comprising: a separating layer (275) that separates the charge shielding layer (250) and the passivation layer (270). [8] Semiconductor device according to any one of claims 4 to 7, wherein the field plate structure (200) comprises a metal section (206) and wherein the charge shielding layer (250) is formed directly on the metal section (206). [9] Semiconductor device according to any one of claims 4 to 7, wherein the field plate structure (200) comprises a polysilicon section (207) formed from doped polycrystalline silicon, and wherein the charge shielding layer (250) is formed directly on the polysilicon section (207). [10] Semiconductor device according to any one of claims 4 to 7, wherein the field plate structure (200) comprises a polycrystalline section (207) formed at a distance from the main surface (101) and a metal section (206) formed in direct contact with the polycrystalline section (207) on one side of the polycrystalline section (207) opposite the substrate (100), and wherein the charge shielding layer (250) is formed directly on the metal section (206). [11] Semiconductor device according to any one of the preceding claims, further comprising: a voltage junction structure (180) formed in the substrate (100) between the first doped region (170) and the edge structure (190), wherein the voltage junction structure (180) is configured to reduce a maximum electric field in the substrate (100) when a voltage is present between the first doped region (170) and the edge structure (190). [12] Semiconductor device according to the preceding claim, wherein the voltage junction structure (180) laterally surrounds the first doped region (170). [13] Semiconductor device according to one of the preceding claims, wherein the field plate structure (200) laterally surrounds the first doped region (170). [14] Semiconductor device according to one of the preceding claims, wherein the edge structure (190) comprises a lateral outer surface (103) of the substrate (100). [15] Semiconductor device according to any one of claims 1 to 13, further comprising: a semiconductor layer (130) formed on the insulating layer (120) and a first interlayer dielectric (210) formed on the semiconductor layer (130), wherein the field plate structure (200) is formed on the first interlayer dielectric (210). [16] Semiconductor device according to any one of the preceding claims, further comprising: a first metallization structure (220) formed directly on the first interlayer dielectric (210) and a second interlayer dielectric (230) formed directly on the first metallization structure (220), wherein the field plate structure (200) comprises a first section formed from a field section of the first metallization structure (220) and a second section formed on the second interlayer dielectric (230). [17] Semiconductor device according to the preceding claim, wherein the field plate structure (200) comprises a plurality of laterally separated field plate sections (205), the first metallization layer (220) comprises a plurality of laterally separated tile sections (225) and each tile section (225) is electrically connected to at least one of the field plate sections (205). [18] Semiconductor device according to the preceding claim, wherein the tile sections (225) are formed in gaps between the field plate sections (205).

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