SEMICONDUCTOR HOUSING AND METHOD FOR MANUFACTURING A SEMICONDUCTOR HOUSING

Abstract

One aspect of the present disclosure relates to a semiconductor package (100, 300) comprising: a semiconductor chip, an encapsulant (130) made of a polymer material and encapsulating the semiconductor chip, a first leadframe portion (140, 140a) electrically connected to a first load electrode of the semiconductor chip, a second leadframe portion (140, 140b) electrically connected to a second load electrode of the semiconductor chip and separated from the first leadframe portion (140, 140a), wherein the first leadframe portion (140, 140a) and the second leadframe portion (140, 140b) are at least partially exposed from the encapsulant (130), and an inorganic barrier (172, 174) disposed on at least one surface portion of the encapsulant (130) along a shortest distance between the first leadframe portion (140, 140a) and the second leadframe portion (140, 140b) is arranged.Further aspects relate to methods for producing a semiconductor package.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor package and methods for manufacturing a semiconductor package. BACKGROUND

[0002] Molded semiconductor packages must meet specific requirements regarding the current creepage distance between exposed conductive parts, especially lead frames or terminals. The defined creepage distances between, for example, external contacts often limit package size shrinkage, which is often desirable.

[0003] A common way to extend the creepage distance without increasing the overall package footprint is by incorporating notches into the molded body or encapsulant of the package. This increases the creepage distance to meet relevant standards, such as IEC 60664-1. However, molded notches are subject to design constraints and result in additional tooling effort. SUMMARY

[0004] Therefore, it is an object of the present disclosure to provide an improved semiconductor package that addresses the challenges described above and to provide methods of manufacturing an improved semiconductor package that addresses the challenges described above.

[0005] This object is achieved by the appended independent claims. Specific embodiments emerge from the respective dependent claims.

[0006] One aspect, in particular a first aspect, of the present disclosure relates to a semiconductor package comprising: a semiconductor chip, an encapsulant made of a polymer material and encapsulating the semiconductor chip, a first lead frame part electrically connected to a first load electrode of the semiconductor chip, a second lead frame part electrically connected to a second load electrode of the semiconductor chip and separated from the first lead frame part, wherein the first lead frame part and the second lead frame part are at least partially exposed from the encapsulant, and an inorganic barrier arranged on at least a surface portion of the encapsulant along a shortest distance between the first lead frame part and the second lead frame part.

[0007] Advantageously, according to this aspect, creepage path length requirements can be handled without introducing notches into the encapsulant.

[0008] Furthermore, according to this aspect, scaling limitations resulting from the creepage distance requirements of standards such as, but not limited to, IEC 60664-1 can be overcome. Depending on the application voltage, the shortest distance between the first and second leadframe parts can be in the range of the gap distance; for 5 kV, this would be approximately 3 mm according to the IEC 60664-1 standard.

[0009] The above aspect further enables the design of semiconductor packages mainly independent of application voltages and thus enables the use of already existing packages, which is time and cost efficient in terms of releasing packages to the market.

[0010] According to one embodiment of the semiconductor package, the semiconductor package may further comprise a chip carrier, wherein the semiconductor chip is mounted on the chip carrier. The first leadframe part may be a first external electrical contact of the semiconductor package. The first external electrical contact may be electrically connected to the first load electrode of the semiconductor chip via the chip carrier. Furthermore, the second leadframe part may be a second external electrical contact of the semiconductor package. The second external electrical contact may be electrically connected to the second load electrode of the semiconductor chip via the chip carrier.

[0011] According to an alternative embodiment of the semiconductor package, the second leadframe part may comprise a die pad on which the semiconductor chip may be mounted. A backside of the die pad may be exposed by the encapsulant. Furthermore, the first leadframe part may be a first external electrical contact of the semiconductor package.

[0012] The semiconductor package may comprise one or more semiconductor chips.

[0013] Here, the semiconductor chips can be designed as power semiconductors, for example, such as power MOSFETs (metal oxide semiconductor field-effect transistors), IGBTs (insulated gate bipolar transistors), JFETs (junction field-effect transistors), power bipolar transistors, or power diodes. Additionally, the semiconductor chips can include control circuits, microprocessors, etc. The semiconductor chips can comprise a specific semiconductor material, such as Si, SiC, SiGe, GaAs, or GaN.

[0014] The terms "coupled" and "connected" may be used together with derivatives. It should be understood that these terms can be used to indicate that two elements cooperate or interact with each other, whether or not they are in direct physical or electrical contact; intermediate elements or layers may be provided. The term "electrically connected" can refer to an electrical connection made by mechanical contact under a specified contact force, by soldering, or inductively.

[0015] The encapsulant may comprise or be made of a polymer material, such as plastic. The polymer material may be considered an electrical insulator depending on a specific voltage range, a separation distance between the exposed first and second leadframe parts, and environmental conditions. The encapsulant may be manufactured by a molding process, such as injection molding or transfer molding.

[0016] Specifically, the encapsulant can be made from five classes of raw materials: organic resins that are meltable, such as epoxy resin; fillers that are non-melting inorganic materials; catalysts that accelerate the curing reaction; mold release materials that allow the naturally adhesive epoxy resin to exit the mold; and a pigment or dye. Other materials, such as flame retardants, coupling agents, ion traps, and stress relievers, may be added if desired.

[0017] Here, the term "exposed" means that a part or element of the semiconductor package is not completely covered or enclosed by the encapsulant. The term "uncovered" can also be used for the term "exposed."

[0018] The encapsulant may separate the second leadframe part from the first leadframe part. The encapsulant may be provided between the first and second leadframe parts.

[0019] The surface portion may be located on or at an outer surface of the encapsulant.

[0020] The surface portion may be encompassed or contained by a layer of the encapsulant having a thickness that extends substantially perpendicular to the outer surface of the encapsulant. The surface portion may extend along the outer surface of the encapsulant. The surface portion may extend substantially perpendicular to the outer surface of the encapsulant. The surface portion may extend from the outer surface of the encapsulant into the encapsulant. The surface portion may have a layered shape.

[0021] The surface portion may be or be comprised of an infinitesimally thick outer layer or an outer layer having a predetermined thickness of the encapsulant.

[0022] The inorganic barrier may be disposed on the outer surface of the encapsulant. Additionally or alternatively, the inorganic barrier may be housed in the surface portion of the encapsulant. The inorganic barrier may comprise parts or the entire outer surface of the encapsulant along the shortest distance between the first leadframe part and the second leadframe part.

[0023] According to one embodiment, the inorganic barrier may comprise or be an inorganic layer.

[0024] Advantageously, according to this embodiment, current leakage between the exposed leadframe parts can be effectively avoided. When designing the semiconductor package or evaluating the semiconductor package for a specific application, only the gap distance needs to be considered.

[0025] Herein, the term “layer” refers to a section whose thickness is much smaller compared to its extension in the length and / or width directions.

[0026] The inorganic layer may extend between the first leadframe part and the second leadframe part. It may extend continuously or intermittently. The inorganic layer may extend along the shortest distance between the first leadframe part and the second leadframe part. The inorganic layer may have a strip shape.

[0027] According to one embodiment, the inorganic layer can be made of glass and / or ceramic. It can comprise or consist of SiO.

[0028] By using glass and / or ceramic, it is possible to suppress surface charge currents and effectively prevent tracking between the first lead frame part and the second lead frame part.

[0029] According to one embodiment, the inorganic layer may be physically and / or chemically coupled to the encapsulant.

[0030] By physically and / or chemically coupling the inorganic layer with the encapsulant, the extension and position of the inorganic layer with respect to the first leadframe part and the second leadframe part can be effectively and precisely controlled.

[0031] For example, the inorganic layer may be physically and / or chemically coupled to the encapsulant by depositing a precursor material on the surface portion of the encapsulant and curing the precursor material, for example, by ultraviolet radiation or charged rays.

[0032] According to one embodiment, the inorganic barrier may comprise or be at least one inorganic insert element.

[0033] Advantageously, according to this embodiment, creepage distance requirements can be handled effectively.

[0034] The at least one inorganic insert element may be only one insert element or may comprise several insert elements.

[0035] The at least one inorganic insert element can be enclosed by or embedded in the encapsulant and exposed at the surface portion of the encapsulant between the first leadframe part and the second leadframe part. The at least one inorganic insert element can have a coplanar surface with the encapsulant. The at least one inorganic insert element can also protrude from the encapsulant. The at least one inorganic insert element can be arranged such that the at least one inorganic insert element can rise slightly above the outer surface of the encapsulant.

[0036] The at least one inorganic insert element can block the creepage path between the first leadframe part and the second leadframe part.

[0037] According to one embodiment, the at least one inorganic insert element is made of glass and / or ceramic.

[0038] Advantageously, these materials can provide very good insulation properties and effectively contribute to preventing surface tracking, i.e., creepage between the first leadframe part and the second leadframe part.

[0039] According to one embodiment, the at least one inorganic insert element may have a fastening structure.

[0040] Advantageously, according to this embodiment, the fastening structure can prevent slippage of the at least one inorganic insert element and ensure precise alignment of the at least one inorganic insert element before and / or during an encapsulation process forming the encapsulant.

[0041] The at least one inorganic insert element may have a polygonal shape. The at least one inorganic insert element may have a block shape.

[0042] The fastening structure may comprise one or more grooves.

[0043] Advantageously, according to this embodiment, the at least one inorganic insert element having one or more grooves may, apart from preventing slippage and ensuring accurate alignment, enable reducing the stray inductance of the semiconductor package, since the use of such an inorganic insert element or such inorganic insert elements may make it possible to design the leadframe parts within the encapsulant closer together.

[0044] According to one embodiment, the inorganic barrier may comprise either the inorganic layer or the at least one inorganic insert element or both the inorganic layer and the at least one inorganic insert element.

[0045] A further aspect, in particular a second aspect, of the present disclosure relates to a method for manufacturing a semiconductor package, the method comprising: providing a semiconductor chip, electrically connecting a first leadframe part to a first load electrode of the semiconductor chip, electrically connecting a second leadframe part to a second load electrode of the semiconductor chip, wherein the second leadframe part is separate from the first leadframe part, encapsulating the semiconductor chip and at least parts of the first leadframe part and the second leadframe part with a polymer material, and arranging an inorganic layer on at least one encapsulated surface portion of the semiconductor package along a shortest distance between the first leadframe part and the second leadframe part.

[0046] According to this aspect, a semiconductor package according to the embodiment of the first aspect, wherein the inorganic barrier comprises or is an inorganic layer, can be manufactured, which has the advantages described above.

[0047] The description, including additional features, embodiments and advantages, made with respect to the semiconductor package according to the first aspect or any of its embodiments may also be applicable to corresponding features of the method according to the above aspect and vice versa.

[0048] The encapsulation step may comprise the process of forming an encapsulant. The forming may include or be molding. The molding may include injection molding or transfer molding.

[0049] Here, the encapsulated surface portion refers to the surface portion of the encapsulant that encapsulates or encloses the above-mentioned parts or components after the encapsulation step.

[0050] According to one embodiment, disposing the inorganic layer may comprise depositing a precursor material and curing the precursor material.

[0051] The precursor material may comprise hydrogen silsesquioxane (HSQ).

[0052] The deposition and curing of this precursor material provides an effective layer or coating that prevents tracking without adjusting the mold tools or processes prior to applying the additional layer.

[0053] According to one embodiment, depositing the precursor material comprises spraying or dispensing the precursor material onto the encapsulated surface portion.

[0054] The precursor material can be precisely deposited by spraying or spreading. This precision can be achieved by masking. The precursor material can be deposited in small and narrow spaces or areas of the semiconductor package.

[0055] According to one embodiment, curing the precursor material comprises exposing the deposited precursor material to ultraviolet radiation or charged rays. The charged rays may, for example, be electron beams.

[0056] Curing the precursor material by exposing it to ultraviolet radiation or charged beams allows for precise shaping of the inorganic layer. The inorganic layer can be formed in small and narrow spaces or areas of the semiconductor package.

[0057] In another embodiment, a ceramic layer may be deposited. The deposition of the layer may be achieved by a process for depositing a thin ceramic layer over the encapsulated surface portion. A hydrogen silsesquioxane (HSQ) precursor, which may be dispensed in methyl isobutyl ketone (MBK), may be used. The precursor may be deposited in the designated area between the first leadframe part and the second leadframe part, either by spray coating or dispensing. Thereafter, the designated area for ceramic layer formation may be exposed to ultraviolet radiation or electron beam in such a way that the curing process can begin (with respect to the desired wavelength and energy). Any uncured residues may be washed away.

[0058] A further aspect, in particular a third aspect, of the present disclosure relates to a method for manufacturing a semiconductor package, the method comprising: providing a semiconductor chip, electrically connecting a first leadframe part to a first load electrode of the semiconductor chip, electrically connecting a second leadframe part to a second load electrode of the semiconductor chip, wherein the second leadframe part is separated from the first leadframe part, arranging at least one inorganic insert element along a shortest distance between the first leadframe part and the second leadframe part, and encapsulating the semiconductor chip and at least parts of the first leadframe part and the second leadframe part and the at least one inorganic insert element with a polymer material,wherein the at least one inorganic insert element is exposed in at least one encapsulated surface portion of the semiconductor package along the shortest distance between the first leadframe part and the second leadframe part.,

[0059] According to this aspect, a semiconductor package according to the embodiment of the first aspect, wherein the inorganic barrier comprises or is at least one inorganic insert element, can be manufactured, which has the advantages described above.

[0060] The description, including additional features, embodiments and advantages, made with respect to the semiconductor package according to the first aspect or any of its embodiments and with respect to the method according to the second aspect and any of its embodiments may also be applicable to corresponding features of the method according to the above aspect and vice versa.

[0061] According to one embodiment, the method further comprises providing a fastening structure on the at least one inorganic insert element prior to providing the at least one inorganic insert element.

[0062] According to one embodiment, providing the fastening structure may comprise providing one or more grooves on a surface of the at least one inorganic insert element.

[0063] In another embodiment, a ceramic block insert element may be placed between the first leadframe part and the second leadframe part prior to the encapsulating step, which may include molding. The placement may be such that, after the encapsulating step, the front surface of the block insert element may be exposed beyond the encapsulated surface portion, i.e., the surface portion of the encapsulant, thereby providing the intended creepage blocking. For alignment and fixation purposes during the encapsulating step, the shape of the ceramic block insert element may provide a sliding groove including a stop feature for precise adjustment.

[0064] One effect of this is that the use of such block insert elements can allow the leadframe parts to be designed closer together within the encapsulant. This can then reduce the stray inductance of the package.

[0065] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various illustrated examples may be combined, provided they are not mutually exclusive. Fig. Figure 1 is a schematic illustration of a conventional semiconductor package illustrating the introduction of a notch. Fig. 2 is a schematic illustration of an embodiment of a semiconductor package according to an aspect of the present disclosure. Fig. 3 illustrates a top view of an embodiment of a semiconductor package according to an aspect of the present disclosure. Fig. 4 illustrates a detailed view of an embodiment of a semiconductor package according to an aspect of the present disclosure. Fig. 5 illustrates an embodiment of the semiconductor package according to an aspect of the present disclosure. Fig. Figure 6 illustrates the molecular structure of hydrogen silsesquioxane (HSQ). Fig. 7 is a schematic illustration of an embodiment of a semiconductor package according to an aspect of the present disclosure. Fig. Figure 8 illustrates a detailed view of the inorganic insert elements of Fig. 7. Fig. 9 illustrates a method according to one aspect of the present disclosure. Fig. 10 illustrates a method according to one aspect of the present disclosure. DETAILED DESCRIPTION

[0067] Fig. 1 is a schematic illustration of a conventional semiconductor package 200 illustrating the introduction of a notch.

[0068] Fig. 1 shows that a notch 170 is provided in the encapsulant 130 between the contacts 140. The contacts 140 are separated by a distance CL with respect to the gap. The notch 170 is formed such that the creepage distance CR, or the creepage distance CR along the surface of the encapsulant 130 from the left contact 140 to the right contact 140, is greater than the distance CL with respect to creepage. This attempts to ensure that the creepage distance is too long for the leakage current to creep to the other contact. However, forming a notch 170 may impose design constraints and require additional tooling effort.

[0069] Fig. 2 is a schematic illustration of an embodiment of a semiconductor package 100 according to an aspect of the present disclosure.

[0070] Fig. Figure 2 schematically shows the provision of an inorganic layer 172 between the contacts 140 (left contact 140a, right contact 140b). The contacts 140a and 140b are separated by a distance CL with respect to the gap. The inorganic layer 172 is arranged on the surface of the encapsulant 130 such that it extends from the contact 140a to the contact 140b or vice versa. The extension length of the inorganic layer 172 between the contacts 140a and 140b is equal to the distance CL.

[0071] Thus, the distance CR along the surface of the encapsulant 130 from the left contact 140a to the right contact 140b can be kept equal to the distance CL with respect to creep.

[0072] Fig. 3 illustrates a top view of an embodiment of a semiconductor package 100 according to an aspect of the present disclosure.

[0073] The semiconductor package 100 comprises a chip carrier 110, a semiconductor chip 120, an encapsulant 130 and two lead frame parts forming two external contacts 140, wherein at least one of the external contacts 140 comprises at least one wing 150.

[0074] The chip carrier 110 comprises a first side 111 and a second, opposite side, with the semiconductor chip 120 arranged on the first side 111 and encapsulated by the encapsulant 130. The at least two external contacts 140 are electrically and mechanically connected to the first side 111 of the chip carrier 110 and are arranged side by side in such a way that they protrude laterally from the encapsulant 130, e.g., from a first lateral side 131. Additionally, the at least two external contacts 140 are made of a suitable metal or alloy.

[0075] At least one of the external contacts 140 has at least one wing 150 disposed within the encapsulant 130 and opposite the other external contact 140. In Fig. In Figure 3, for ease of illustration, the wings 150 are demarcated from the rest of the external contacts 140 by dashed lines. The wing or wings 150 have one or more cutouts 160 filled with the encapsulation material of the encapsulant 130.

[0076] The external contacts 140 may each have a first side 141, an opposite second side, and lateral sides 143 that interconnect the first side 141 and the second side. The external contacts 140 may be arranged on the chip carrier 110 such that the second sides face the first side 111 of the chip carrier 110.

[0077] An inorganic barrier, embodied as an inorganic layer 172, is disposed on the outer surface of the encapsulant 130 between the external contacts 140 to prevent tracing. This inorganic layer 172 extends along the outer surface of the encapsulant 130 from the left external contact 140 to the right external contact 140, or vice versa.

[0078] Fig. 4 illustrates a perspective detailed view of an embodiment of a semiconductor package 100 according to one aspect of the present disclosure.

[0079] The Fig. 4 may be similar or identical to the semiconductor package 100 shown in Fig. 3 shown.

[0080] As in Fig. As shown in Figure 4, the chip carrier 110 may comprise a patterned conductive layer 110_1, with an external contact 140 disposed on this conductive layer 110_1 and electrically connected thereto, e.g., by means of one or more solder joints. The conductive layer 110_1 may, for example, be disposed on a ceramic layer 110_2.

[0081] The conductive layer 110_1 may have one or more gaps 610 in the region of the solder joint(s). In the region of the gaps 610, the conductive layer 110_1 is removed, exposing the underlying ceramic layer 110_2. The presence of such a gap 610 may, for example, simplify or optimize the fabrication of the solder joint between the external contact 140 and the conductive layer 110_1.

[0082] Fig. 4 also shows that, according to one example, an external contact 140 does not necessarily have to have a central portion in the area of the cutouts 160. Instead, the external contact 140 may consist only of the wings 150 in this area.

[0083] In addition, similar to Fig. 3, the encapsulant 130 is provided with an inorganic layer 172 from outside the encapsulant between the wing portions 150 of the external contacts 140 to prevent tracking between the contacts 140.

[0084] Fig. 5 illustrates an embodiment of a semiconductor package 300 according to an aspect of the present disclosure.

[0085] Fig. 5 shows a back view 301 and a front view 302 of the semiconductor package 300. The illustrated semiconductor package 300 may be a discrete package with an exposed pad for top or bottom cooling, e.g., a surface mount device (SMD) package.

[0086] The semiconductor package 300 includes a semiconductor chip and two leadframe portions 140a and 140b. The semiconductor chip and the leadframe portions 140a and 140b are enclosed by an encapsulant 130. The leadframe portion 140a includes a plurality of leads that protrude from the encapsulant and form external electrical contacts of the semiconductor package.

[0087] The leadframe portion 140b includes a die pad on which the semiconductor chip is mounted. A backside of the die pad 305 is exposed by the encapsulant 130.

[0088] Since tracking may occur between the contacts 140a and the exposed backside of the die pad 305, an inorganic barrier, such as an inorganic layer 172, is disposed on the surface of the encapsulant 130 between the contacts 140a and the backside of the die pad 305. The disposed barrier extends with respect to the projection plane of Fig. 5 along the width of the semiconductor package 300.

[0089] The barrier is positioned along the shortest path or distance between the exposed pad and the leakage points. The barrier does not need to extend to both sides of the enclosure if the pad does not span the entire width of the enclosure.

[0090] The barrier is further disposed substantially in the center of the surface of the encapsulant 130 between the contacts 140a and the exposed backside of the die pad 305.

[0091] Fig. Figure 6 illustrates the molecular structure of hydrogen silsesquioxane (HSQ), which may be used in disposing an inorganic layer on at least one surface portion of the encapsulant of a semiconductor package according to one aspect of the present disclosure. The symbol "R" refers to the molecular residue H (H: hydrogen).

[0092] HSQ can be deposited on the surface portion of the encapsulant, for example, by spray coating. The deposited HSQ film can then be cured by ultraviolet radiation or electron beams. This can form a rigid, electrically insulating, and anti-tracking SiO layer.

[0093] Fig. 7 is a schematic illustration of an embodiment of a semiconductor package 100 according to an aspect of the present disclosure. Fig. The illustration shown in Figure 7 is similar to that of Fig. 2, wherein the inorganic layer 172 of Fig. 2 by several (three in Fig. 7) inorganic insert elements 174 which are partially enclosed by the encapsulant 130 (in Fig. 7 by the dashed lines), and the remainder of the insert elements 174 protrude from the encapsulant 130 between the two lead frame parts or contacts 140a and 140b. For simplicity, the inorganic insert elements 174 in Fig. 7 have a cuboid block shape. They can have any polygonal shape.

[0094] The inorganic insert elements 174 can block tracking between the contacts 140a and 140b.

[0095] Fig. Figure 8 illustrates a detailed view of the inorganic insert elements 174 of Fig. 7. At least one surface of each of the insert elements 174 is provided with grooves 176 (thick vertical lines in Fig. 8). In Fig. 8, the insert elements 174 have three grooves. However, any number of grooves may be possible. These grooves provide a fastening structure that prevents slippage of the insert elements 174 and ensures precise alignment of the insert elements 174 before and / or during formation of the encapsulant 130.

[0096] Fig. 9 illustrates a method 1000 according to one aspect of the present disclosure.

[0097] Fig. 9 shows a method 1000 for manufacturing a semiconductor package 100 or 300. The method 1000 includes the following steps: In a step 1100, which may be a first step, a semiconductor chip is provided. In a next step 1200, which may be a second step, a first leadframe part 140, 140a is electrically connected to a first load electrode of the semiconductor chip. In a next step 1300, which may be a third step, a second leadframe part 140, 140b is electrically connected to a second load electrode of the semiconductor chip. The second leadframe part 140, 140b is separated from the first leadframe part 140, 140a. In a next step 1400, which may be a fourth step, the semiconductor chip and at least parts of the first leadframe part 140, 140a and the second leadframe part 140, 140b can be encapsulated with a polymer material.In a next step 1500, which may be a final step, an inorganic layer 172 may be arranged on at least one encapsulated surface portion of the semiconductor package 100, 300 along a shortest distance between the first leadframe part 140, 140a and the second leadframe part 140, 140b.

[0098] Fig. 10 illustrates a method 3000 according to one aspect of the present disclosure.

[0099] Fig. 10 shows a method 3000 for manufacturing a semiconductor package 100, 300. The method 3000 includes the following steps: In a step 3100, which may be a first step, a semiconductor chip is provided. In a next step 3200, which may be a second step, a first leadframe part 140, 140a is electrically connected to a first load electrode of the semiconductor chip. In a next step 3300, which may be a third step, a second leadframe part 140, 140b is electrically connected to a second load electrode of the semiconductor chip. The second leadframe part 140, 140b is separated from the first leadframe part 140, 140a. In a next step 3400, which may be a fourth step, at least one inorganic insert element 174 is arranged along a shortest distance between the first leadframe part 140, 140a and the second leadframe part 140, 140b.In a next step 3500, which may be a final step, the semiconductor chip and at least parts of the first leadframe part 140, 140a and the second leadframe part 140, 140b and the at least one inorganic insert element 174 are encapsulated with a polymer material. The at least one inorganic insert element 174 is exposed in at least one encapsulated surface portion of the semiconductor package 100, 300 along the shortest distance between the first leadframe part 140, 140a and the second leadframe part 140, 140b.

[0100] Finally, notches in the encapsulant, which impose design constraints and require additional tooling effort, are eliminated by instead incorporating an inorganic barrier (layer and / or insert element(s)) into the encapsulant to block the current path. Inorganic, particularly glass and / or ceramic, surfaces resist current creepage to a level that exceeds the defined CTI range (ceramics are characterized by their tracking in an inclined plane according to ASTM D2303). By incorporating the inorganic barrier, the distance between the leadframe parts of the semiconductor package can be reduced to a level that eliminates the need for notches.

[0101] Although specific examples have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

[0102] It should be noted that the methods and devices, including their preferred embodiments, as outlined in this document can be used alone or in combination with the other methods and devices disclosed in this document. Additionally, the features outlined in connection with one device are also applicable to a corresponding method, and vice versa. Furthermore, all aspects of the methods and devices outlined in this document can be combined in any desired manner. In particular, the features of the claims can be combined with one another in any desired manner.

[0103] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined in the present document are primarily intended to be expressly provided for illustrative purposes only to assist the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein that provide principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include their equivalents.

Claims

[1] Semiconductor package (100, 300), comprising: a semiconductor chip, an encapsulant (130) made of a polymer material and encapsulating the semiconductor chip, a first leadframe part (140, 140a) electrically connected to a first load electrode of the semiconductor chip, a second leadframe part (140, 140b) electrically connected to a second load electrode of the semiconductor chip and separated from the first leadframe part (140, 140a), wherein the first leadframe part (140, 140a) and the second leadframe part (140, 140b) are at least partially exposed from the encapsulating agent (130), and an inorganic barrier (172, 174) disposed on at least one surface portion of the encapsulant (130) along a shortest distance between the first leadframe part (140, 140a) and the second leadframe part (140, 140b). [2] The semiconductor package (100, 300) of claim 1, wherein the inorganic barrier (172, 174) comprises an inorganic layer (172). [3] Semiconductor package (100, 300) according to claim 2, wherein the inorganic layer (172) extends, in particular continuously or with interruptions, between the first leadframe part (140, 140a) and the second leadframe part (140, 140b). [4] Semiconductor package (100, 300) according to one of claims 2 to 3, wherein the inorganic layer (172) comprises SiO. [5] Semiconductor package (100, 300) according to one of claims 2 to 4, wherein the inorganic layer (172) is physically and / or chemically coupled to the encapsulant (130). [6] The semiconductor package (100, 300) of any one of claims 1 to 5, wherein the inorganic barrier (172, 174) comprises at least one inorganic insert element (174). [7] Semiconductor package (100) according to claim 6, wherein the at least one inorganic insert element (174) is enclosed by the encapsulant (130) and is exposed at the surface portion of the encapsulant (130) between the first leadframe part (140, 140a) and the second leadframe part (140, 140b), in particular wherein the at least one inorganic insert element (174) protrudes from the encapsulant (130). [8] Semiconductor package (100, 300) according to claim 6 or 7, wherein the at least one inorganic insert element (174) is made of glass and / or ceramic. [9] Semiconductor package (100, 300) according to one of claims 6 to 8, wherein the at least one inorganic insert element (174) has a fastening structure (176). [10] The semiconductor package (100, 300) of claim 9, wherein the mounting structure (176) comprises one or more grooves. [11] Semiconductor package (100) according to one of claims 1 to 10, wherein the semiconductor package (100) further comprises: a chip carrier (110), wherein the semiconductor chip (120) is mounted on the chip carrier (110), wherein the first leadframe part (140, 140a) is a first external electrical contact of the semiconductor package (100), in particular is electrically connected to the first load electrode of the semiconductor chip (120) via the chip carrier (110), and wherein the second leadframe part (140, 140b) is a second external electrical contact of the semiconductor package (100), in particular is electrically connected to the second load electrode of the semiconductor chip (120) via the chip carrier (110). [12] Semiconductor package (300) according to one of claims 1 to 10, wherein the second leadframe part (140, 140b) comprises a die pad on which the semiconductor chip is mounted, wherein a back side of the die pad (305) is exposed from the encapsulant (130), and wherein the first leadframe part (140, 140a) is a first external electrical contact of the semiconductor package (300). [13] A method (1000) for manufacturing a semiconductor package (100, 300), the method comprising: Providing (1100) a semiconductor chip, electrically connecting (1200) a first leadframe part (140, 140a) to a first load electrode of the semiconductor chip, electrically connecting (1300) a second leadframe part (140, 140b) to a second load electrode of the semiconductor chip, wherein the second leadframe part (140, 140b) is separated from the first leadframe part (140, 140a), Encapsulating (1400) the semiconductor chip and at least parts of the first leadframe part (140, 140a) and the second leadframe part (140, 140b) with a polymer material, and Arranging (1500) an inorganic layer (172) on at least one encapsulated surface portion of the semiconductor package (100, 300) along a shortest distance between the first leadframe part (140, 140a) and the second leadframe part (140, 140b). [14] The method (1000) of claim 13, wherein disposing the inorganic layer (172) comprises depositing a precursor material and curing the precursor material. [15] The method (1000) of claim 14, wherein the precursor material comprises hydrogen silsesquioxane, HSQ. [16] The method (1000) of claim 14 or 15, wherein depositing the precursor material comprises spraying or dispensing the precursor material onto the encapsulated surface portion. [17] The method (1000) of any one of claims 14 to 16, wherein curing the precursor material comprises exposing the deposited precursor material to ultraviolet radiation or charged beams, in particular electron beams. [18] A method (3000) for manufacturing a semiconductor package (100, 300), the method comprising: Providing (3100) a semiconductor chip, electrically connecting (3200) a first leadframe part (140, 140a) to a first load electrode of the semiconductor chip, electrically connecting (3300) a second leadframe part (140, 140b) to a second load electrode of the semiconductor chip, wherein the second leadframe part (140, 140b) is separated from the first leadframe part (140, 140a), Arranging (3400) at least one inorganic insert element (174) along a shortest distance between the first leadframe part (140, 140a) and the second leadframe part (140, 140b), and Encapsulating (3500) the semiconductor chip and at least parts of the first leadframe part (140, 140a) and the second leadframe part (140, 140b) and the at least one inorganic insert element (174) with a polymer material, wherein the at least one inorganic insert element (174) is exposed in at least one encapsulated surface portion of the semiconductor package (100, 300) along the shortest distance between the first leadframe part (140, 140a) and the second leadframe part (140, 140b). [19] The method (3000) of claim 18, wherein prior to providing the at least one inorganic insert element (174), the method further comprises providing an attachment structure (176) on the at least one inorganic insert element (174). [20] The method (3000) of claim 19, wherein providing the attachment structure (176) comprises providing one or more grooves on a surface of the at least one inorganic insert element (174).

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