Power semiconductor device and method for manufacturing a power semiconductor device

Abstract

In a power semiconductor device (1), a deep semiconductor region (105) is provided in addition to a barrier structure (15). The barrier structure (15) is spatially separated from a trench structure (14, 16) in an active region (1-2) and arranged in a transition region (1-23) between the active region (1-2) and an edge termination region (1-3) of the power semiconductor device (1).

Description

Technical FieldThis description relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device.BackgroundMany functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving an electric motor or an electric machine, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name just a few, have been used for various applications including, but not limited to, switches in power supplies and power converters.A power semiconductor device comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is conducted by means of an active region of the power semiconductor device. The active region is surrounded by an edge termination region that is terminated by an edge of the chip.In the case of a controllable power semiconductor device, e.g. a transistor, the load current path may be controlled by means of insulated electrodes commonly referred to as gate electrodes. For example, upon receiving a corresponding control signal, e.g. from a driver unit and via a control terminal of the device, the control electrodes may put the power semiconductor device in one of a forward conducting state and a blocking state.Further, some devices provide a reverse load current capability; i.e., the active region of the semiconductor body is further configured to conduct a reverse load current along a reverse load current path between the two load terminals of the device. For example, the RC (reverse conduction) IGBT is a representative of such devices. In an RC-IGBT, a single chip combines an IGBT structure and a diode structure.It is often a design goal to provide the power semiconductor device with specific characteristics, for example, with respect to the switching characteristics, e.g., the associated control of the rate of change of the load current (dI / dt) and / or the rate of change of the collector / emitter voltage (dV / dt). However, it has been observed that simulated, i.e., predicted dI / dt and dV / dt values may deviate significantly from the actual values of the manufactured device. In addition, it may be challenging to design the device with specific dI / dt and dV / dt ranges as well as other target characteristics such as low switching losses and / or low conduction losses.SUMMARYThe subject matter of the independent claims is presented. Features of embodiments are defined in the dependent claims.According to an embodiment, a power semiconductor device comprises: an active region surrounded by an edge termination region; a semiconductor body extending in both the active region and the edge termination region and comprising a semiconductor drift region of a first conductivity type in the active region; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal in the active region; in the active region and the edge termination region, a trench structure extending along a vertical direction from the first side to the second side, the trench structure comprising a plurality of control trenches, each control trench including a control trench electrode configured to control the forward load current; in the active region, a deep semiconductor region of the first conductivity type. The deep semiconductor region has a dopant concentration at least twice as high as the dopant concentration of the semiconductor drift region, a thickness within the range of 10% to 120% of the vertical extension of the trench structure, and is arranged to overlap with the control trenches at least partially, for example by at least 50% of the thickness of the deep semiconductor region, along the vertical direction. The device further comprises, spatially separated from the trench structure and arranged in a transition region between the active region and the edge termination region, a barrier structure extending along the vertical direction from the first side to the second side.The depth of the deep semiconductor region may be defined by the depth at which the dopant concentration has dropped to 1% of the peak concentration of the deep semiconductor region.According to another embodiment, a method of manufacturing a power semiconductor device comprises forming the following components: an active region surrounded by an edge termination region; a semiconductor body extending in both the active region and the edge termination region and comprising a semiconductor drift region of a first conductivity type in the active region; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal in the active region; in the active region and the edge termination region, a trench structure extending along a vertical direction from the first side to the second side, the trench structure comprising a plurality of control trenches, each control trench including a control trench electrode configured to control the forward load current; in the active region, a deep semiconductor region of the first conductivity type. The deep semiconductor region has a dopant concentration at least twice as high as the dopant concentration of the semiconductor drift region, a thickness within the range of 10% to 120% of the vertical extension of the trench structure, and is arranged to overlap with the control trenches at least partially, for example by at least 50% of the thickness of the deep semiconductor region, along the vertical direction. The method further comprises forming, spatially separated from the trench structure and arranged in a transition region between the active region and the edge termination region, a barrier structure extending along the vertical direction from the first side to the second side.According to embodiments described herein, the barrier structure may be configured to prevent holes accumulated under the deep semiconductor region, e.g. when the device is off, from being transferred from the active region to the edge termination region. This prevention of hole transfer may enable improved predicted control of the dI / dt characteristics of the power semiconductor device.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.Brief Description of the DrawingsThe parts in the figures are not necessarily to scale, emphasis instead being placed upon illustrating principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings, there are shown: FIG. 1 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 2 schematically and exemplarily shows a vertical cross section of a power semiconductor device according to one or more embodiments; FIG. 3 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to an example; FIG. 4(A) schematically and exemplarily illustrates both a horizontal projection and a portion of a vertical cross section of a power semiconductor device according to an example; FIG. 4(B) schematically and exemplarily illustrates both a horizontal projection and a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; FIG. 5 schematically and exemplarily illustrates three partial views of a power semiconductor device according to one or more embodiments; FIG. 6 schematically and exemplarily shows two partial views of a power semiconductor device according to one or more embodiments; FIG. 7 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 8 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 9 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 10 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 11 schematically and exemplarily illustrates three partial views of a power semiconductor device according to one or more embodiments; FIG. 12 schematically and exemplarily illustrates three partial views of a power semiconductor device relating to a method of manufacturing a power semiconductor device according to one or more embodiments; FIG. 13 schematically and exemplarily illustrates three partial views of a power semiconductor device relating to a method of manufacturing a power semiconductor device according to one or more embodiments; FIG. 14 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; FIG. 15 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; and FIG. 16 schematically and exemplarily illustrates a vertical cross-section of a power semiconductor device according to one or more embodiments.Detailed DescriptionIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.In this regard, directional terminology, such as "top," "bottom," "below," "front," "back," "back," "leading," "trailing," "over," etc., may be used with reference to the orientation of the described figures. Since portions of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided for illustration and is not intended to limit the invention. For example, features illustrated or described as part of one embodiment may be used in or in conjunction with other embodiments to yield yet another embodiment. It is intended that the present invention encompasses such modifications and variations. The examples are described using a specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or fabrication steps have been designated by the same reference numerals throughout the several drawings, unless otherwise indicated.The term "horizontal" as used in this specification intends to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may be, for example, the surface of a semiconductor wafer or a die or a chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.The term "vertical" as used in this specification intends to describe an orientation arranged substantially perpendicular to the horizontal surface, i.e. parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y.In this specification, n-doped is referred to as "first conductivity type", while p-doped is referred to as "second conductivity type". Alternatively, opposite doping relationships may be used such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.In the context of the present description, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe that there is a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, zones, sections or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or a metallization or an electrode and a section or part of a semiconductor device, wherein "low-ohmic" can mean that the properties of the respective contact are substantially not influenced by the ohmic resistance. Further, the term "in contact" in the context of the present description intends to describe that there is a direct physical connection between two elements of the respective semiconductor device; e.g., a transition between two elements in contact with each other may not include a further intermediate element or the like.Additionally, in the context of the present specification, unless otherwise indicated, the term "electrical isolation" is used in the context of its generally valid understanding and is thus intended to describe that two or more components are positioned separately from each other and that there is no ohmic connection connecting these components. However, components that are electrically isolated from each other may still be coupled to each other, for example mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (for example in the case of a transition). To give an example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, e.g. by means of an insulation, e.g. a dielectric.Specific embodiments described in this specification relate to, but are not limited to, a power semiconductor device that can be used within a power converter or power supply. Thus, in one embodiment, such a power semiconductor device may be configured to carry a load current to be supplied to a load and / or provided by a power source. For example, the power semiconductor device may comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell, a monolithically integrated transistor cell, e.g. a monolithically integrated IGBT or MOSFET cell and / or derivatives thereof. Such diode / transistor cells may be integrated within a single chip. A plurality of such cells may form a cell array disposed within an active region of the power semiconductor device.The term "blocking state" of the power semiconductor device may refer to conditions when the power semiconductor is in a state configured to block a load current flow while an external voltage is applied. In particular, the power semiconductor device may be configured to block a forward load current through the power semiconductor device while applying a forward voltage bias. In comparison, the power semiconductor device may be configured to conduct the forward load current in a "conducting state" of the power semiconductor device while applying a forward voltage bias voltage. A transition between the blocking state and the conductive state may be controlled by a control electrode or, in particular, a potential of the control electrode. The electrical characteristics can naturally only hold within a predetermined operating range of the external voltage and the current density within the power semiconductor device. The term "forward biased blocking state" may therefore refer to conditions in which the power semiconductor device is in the blocking state while a forward voltage bias is applied.The term "power semiconductor device" as used in this specification intends to describe a power semiconductor device on a single chip having high voltage blocking and / or high current carrying capacities. In other words, such a power semiconductor device is intended for high current, typically in the Ampere range, e.g. up to several tens or hundreds of Ampere, and / or high voltages, typically above 15 V, more typically 100 V and above, e.g. up to at least 400 V or even more, e.g. up to at least 3 kV or even up to 10 kV or more, depending on the respective application.For example, the term "power semiconductor device" as used in this specification is not directed to logic semiconductor devices used, e.g., to store data, calculate data, and / or other types of semiconductor-based data processing.For example, the power semiconductor device described below may be a single semiconductor chip having, e.g., a strip cell configuration (or a pin cell configuration) and may be configured to be employed as a power component in a low, medium and / or high voltage application.With reference to FIGS. 1, 2 and 15, aspects relating to a possible general configuration of the power semiconductor device 1 will be explained:The power semiconductor device 1, also referred to herein as "device 1", comprises, e.g., in a single chip, a semiconductor body 10 configured to conduct a load current in an active region 1- 2 between a first load terminal 11 on a first side 110 of the semiconductor body 10 and a second load terminal 12 on a second side 120 of the semiconductor body 10. The device 1 may be an IGBT (or a derivative thereof, such as an RC-IGBT). Accordingly, the first load terminal 11 may be an emitter terminal and the second load terminal 12 may be a collector terminal.As exemplarily illustrated in FIG. 1, the active region 1- 2 of the device 1 is surrounded by an edge termination region 1- 3. In the active region 1- 2, a trench structure (cf. FIG. 16, reference numerals 14, 16) may form a cell array, which is explained further below. The edge termination region 1- 3 is typically not used for load current conduction, as is known to the person skilled in the art. The edge termination region 1- 3 is terminated by the chip edge 1- 4.As exemplarily illustrated in FIG. 2, the first side 110 and the second side 120 may be arranged opposite to each other. For example, the first side 110 is a front side of the device 1 and the second side 120 is a back side of the device 1. The semiconductor body 10 may be sandwiched between the first load terminal 11 and the second load terminal 12 and may have a vertical extension d, e.g. in the range of 50 μm to 700 μm, depending e.g. on the designated maximum blocking voltage.The device 1 further comprises a drift region 100 of a first conductivity type within the semiconductor body 10. For example, the vertical extension of the drift region 100 affects the voltage blocking capabilities (e.g. the maximum blocking voltage) of the device 1.The device 1 further comprises a trench structure 14, 16 extending from the first side 110 into the semiconductor body 10 to the second side 120, e.g. along the vertical direction Z. The trench structure will be described in more detail below. The trench structure 14, 16 comprises at least one trench control electrode 141 (cf. FIGS. 3, 16 ) electrically insulated from the first load terminal 11 and configured to receive a control signal. To this end, the trench control electrode 141 may be electrically connected to a control terminal (not shown) of the device 1, according to an embodiment.As schematically illustrated in FIG. 2 and in more detail in FIG. 16, the semiconductor body 10 at the first side 110 further comprises a semiconductor body region 102 of the second conductivity type electrically connected to the first load terminal 11 and a semiconductor source region 101 of the first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is insulated from the drift region 100 by at least the semiconductor body region 102. The trench control electrode 141 of the trench structure may be configured to induce an inversion channel in the semiconductor body portion 102 when exposed to a corresponding ON control signal. This process may put the device 1 in the forward conducting state. The trench control electrode 141 may be further configured to, when exposed to a corresponding OFF control signal, turn off the inversion channel in the semiconductor body portion 102, which may put the device 1 in the forward blocking state.A doped region 108 of the semiconductor body 10 below the drift region 100 adjoining the second load terminal 12 on the second side 120 may be configured according to the designated characteristic of the device 1. For example, the doped region 108 may be an emitter region of the second conductivity type if the device 1 is to have an IGBT configuration. The emitter region is arranged in contact with the second load terminal 12.In addition, a field stop region (not shown) of the first conductivity type may be provided between the drift region 100 and the second load terminal 12, wherein the field stop region has a greater dopant concentration than the drift region 100.If the device 1 is to have a MOSFET configuration, the emitter region is omitted, so that the field stop region (or another highly doped region of the first conductivity type) would be adjacent to the second load terminal 12. If the device 1 is to have an RC-IGBT configuration, the emitter region may have sub-portions of the first conductivity type, as is known to those skilled in the art.FIG. 3 schematically and exemplarily illustrates a horizontal projection of the power semiconductor device 1 according to an example. A portion of an upper portion of the active region 1- 2 (lower part) near the first side 110 is illustrated, wherein the active region 1- 2 adjoins a transition region 1- 23 between the active region 1- 2 and the edge termination region 1- 3, which is also only partially shown. The chip edge 1-4 is not shown.According to the example of FIG. 3, the trench structure extending into both the active region 1- 2 and the edge termination region 1- 3 comprises a plurality of control trenches 14, wherein each control trench 14 includes a control trench electrode 141 (cf. FIG. 16 ) configured to control the forward load current. The trench structure further comprises a plurality of source trenches 16, each source trench 16 including a source trench electrode 161 electrically connected to the first load terminal 11.The control trenches 14 and the source trenches 16 laterally confine mesas, wherein the mesas comprise mesas 17 of the first type (cf. also FIG. 16 ). For example, each mesa 17 of the first type is laterally bounded by at least one of the control trenches 14. Further, each first type mesa 17 may include one or more of the first conductivity type semiconductor source regions 101 that is / are electrically connected to the first load terminal 11. Further, each first type mesa 17 may comprise a portion of the second conductivity type semiconductor body region 102, wherein the semiconductor body region 102 isolates the one or more semiconductor source regions 101 from a portion of a first conductivity type region, e.g., a portion of the drift region 100 within the first type mesa 17 or a portion of a deep semiconductor region 105, which will be explained in more detail below. The semiconductor body portion 102 is electrically connected to the first load terminal 11.The mesas 17 of the first type are electrically connected to the first load terminal 11, e.g. as illustrated in FIGS. 3 and 16, e.g. based on first contact plugs 111 penetrating an insulating layer 191 between the semiconductor body 10 and the first load terminal 11 (or a portion of a load terminal metallization 117 thereof) to establish contact with both the respective semiconductor source region 101 and the respective semiconductor body region 102 within the mesa 17 of the first type.Each of the control trenches 14 includes a control trench insulator 142 that isolates the control trench electrode 141 from the semiconductor body 10, as schematically illustrated in FIG. 16. Similarly, each of the source trenches 16 includes a source trench insulator 162 that isolates the source trench electrode 161 from the semiconductor body 10.For example, in the edge termination region 1- 3, the device 1 further comprises a control terminal metallization 130, e.g. a gate ring as illustrated in FIG. 3, electrically connected to a control terminal 13 (cf. FIG. 5(C) ). For example, third contact plugs 131 extend from the control terminal metallization 130 along the vertical direction Z to contact the control trench electrodes 141 of the control trenches 14 to establish an electrical connection between the control terminal metallization 130 and the control trench electrodes 141. For example, the control trench electrodes 141 receive the control signal via the control terminal metallization 130. The control signal may be generated as a voltage between the control terminal 13 and the first load terminal 11.The device 1 further comprises, electrically insulated and spatially separated from the control metallization 130, a load terminal metallization 117 electrically connected to (or forming part of) the first load terminal 11. The load terminal metallization 117 may extend into both the active region 1- 2 and the transition region 1- 23. For example, second contact plugs 112 extend from the load terminal metallization 117 along the vertical direction Z to contact the source trench electrodes 161 of the source trenches 16 to establish the electrical connection between the load terminal metallization 117 and the source trench electrodes 161.As indicated above, the device 1 further comprises a deep semiconductor region 105 of the first conductivity type in the active region 1- 2. The deep semiconductor region 105 has a dopant concentration that is at least twice as high as the dopant concentration of the semiconductor drift region 100. The deep semiconductor region 105 has a thickness dd (cf. FIG. 16 ) within the range from 10% to 120% or within the range from 10% to 80% of the vertical extent dt (cf. FIG. 16 ) of the trench structure. The deep semiconductor region 105 is arranged to overlap with the control trenches 14 at least partially, for example by at least 50% of the thickness of the deep semiconductor region 105, along the vertical direction Z, as exemplarily illustrated in FIG. 16. The deep semiconductor region 105 may be arranged in contact with the semiconductor body region 102 or may be spatially separated therefrom along the vertical direction Z. For example, each of the first type mesas 17 includes a portion of the deep semiconductor region 105 that extends continuously with the respective first type mesa 17, as exemplarily illustrated in FIGS. 3 and 16.For example, the dopant concentration of the deep semiconductor region 105 varies along the vertical direction E.G. the dopant concentration of the deep semiconductor 105 has a maximum at a vertical level overlapping with the vertical extension of the control trenches 14.The device 1 may further include a semiconductor well region 109 in the edge termination region 1- 3. For example, the semiconductor well region 109 is of the second conductivity type. The semiconductor well region 109 may be electrically connected to the first load terminal 11, e.g. also via a portion of the load terminal metallization 117. The semiconductor well region 109 is spatially separated from the deep semiconductor region 105.Based on the source trenches 16 and the control trenches 14, a cell array is formed in the active region 1- 2. Various trench mesa patterns may be formed. For example, the first type mesas 17 may be adjacent either by two of the control trenches 14 (as the second first type mesa 17 on the left side and the second first type mesa 17 on the right side of FIG. 3 (see mesas with reference number 171)) or by only one of the control trenches 14 and one of the source trenches 16 (as all remaining mesas 17 of the first type in FIG. 3 ). This aspect will be described in more detail below.The upper part of FIG. 4(A) is identical to FIG. 3, wherein the load terminal metallization 117 and the control terminal metallization 130 are not illustrated. As illustrated in the lower part of FIG. 4(A), which corresponds to the vertical cross-section at dashed line ( 1) in the upper part of FIG. 4(A), deep semiconductor region 105 in active region 1- 2 may be configured to accumulate holes (illustrated as +-characters) in the region at or below deep semiconductor region 105, for example, during a turn-off process. However, at the periphery of the active region 1- 2, the holes may transfer to the transition region 1- 23, i.e. to the well region 109 in the edge termination region 1- 3. Since the semiconductor body 10 in the edge termination region 1- 3 is electrically connected to the first load terminal 11, the holes may accordingly "disappear". Therefore, the hole accumulation functionality of the deep semiconductor region 105 to hold holes in the region at or below the deep semiconductor region 105 could be limited. This could be disadvantageous because the drain of holes can affect the increase in voltage on the control electrode 141 during turn-on and, accordingly, the dI / dt.According to embodiments described herein and with the exemplary illustrations in FIG. 4(B), the device 1 further comprises, spatially separated from the trench structure 14, 16 and arranged in the transition region 1- 23 between the active region 1- 2 and the edge termination region 1- 3, a barrier structure 15 extending along the vertical direction Z from the first side 110 to the second side 120.For example, the barrier structure 15 is configured to avoid the transmission of the holes from the active region 1- 2 to the edge termination region 1- 3, e.g. during a turn-off process of the device 1 (as illustrated by the lower part of FIG. 4(B) ).In an embodiment, the barrier structure 15 extends further along the vertical direction Z than the deep semiconductor region 105.The upper part of FIG. 4(B) substantially corresponds to the upper part of FIG. 4(A), with the addition of the barrier structure 15 which can imply changes in the configuration of the source trenches 16 and the control trenches 14 in the transition region 1- 23. When needed and how implemented, changes may depend on the configuration of the barrier structure 15, some examples of which are described further below. According to the example illustrated in FIG. 4(B), the barrier structure 15 is embodied as a cross trench and the control trenches 14 adjoin the barrier structure 15 both from the edge termination region 1- 3 and the active region 1- 2, whereas the source trenches 16 terminate spaced apart from the barrier structure 15.Before further variants of the barrier structure 15 are described, some further optional features of the device 1 are described below, which can be provided for each of the embodiments described herein, unless expressly stated otherwise.For example, the trench structure 14, 16 has a trench pattern according to which each trench of the trench structure 14, 16 is either a control trench 14 or a source trench 16. For example, a trench having a floating trench electrode is not provided. As explained above, the first type mesas 17 may be adjacent either through two of the control trenches 14 (as the second first type mesa 171 on the left side and the second first type mesa 171 on the right side of the top portion of FIG. 4(B), hereinafter referred to as GG mesas 171) or through only one of the control trenches 14 and one of the source trenches 16 (as all remaining mesas 17 of the first type of the top portion of FIG. 4(B), hereinafter referred to as GS mesas). For example, the ratio of GS mesas to GG mesas is greater than 1, 2, 4 or even greater than 8. Further, second type mesas (not illustrated) may be provided in the active area, wherein each second type mesa is laterally bounded by two of the source trenches 16. These mesas of the second type, referred to below as SS mesas, may or may not be electrically connected to the first load terminal 11. The example ratios of GS mesas to GG mesas may be provided regardless of whether or not SS mesas are present. According to an embodiment, the variation of the ratio of GS mesas to GG mesas contributes to adjusting the ratio of the current slope dI / dt vs. voltage slope dU / dt, e.g. for turning on the device when the barrier structure 15 is implemented.The device 1 may further include, on the first side 110, the control terminal 13 (see, e.g., FIG. 5(C) ) electrically connected to the control trench electrodes 141. The electrical connection between the control terminal 13 and the control trench electrodes 141 is established, e.g., via the third contact plugs 131 and the control terminal metallization 130 in the edge termination region 1- 3. The electrical connection between the first load terminal 11 and the source trench electrodes 161 is established in the active region 1- 2 (alternatively or additionally in the edge termination region 1- 3), e.g. via the second contact plugs 112 and the load terminal metallization 117.The semiconductor well region 109 is spatially separated from the deep semiconductor region 105, according to an embodiment.The device 1 described herein may be a bipolar power semiconductor device. For example, the device 1 has an IGBT configuration (or a derivative thereof, such as an RC-IGBT configuration).For example, as illustrated in the drawings, the cell array in the active region 1- 2 has a striped cell configuration formed by the trench structure 14, 16 and the corresponding mesas 17 of the first type. The barrier structure 15 may have a lateral extension (e.g. along the first lateral direction X) perpendicular to the lateral extension of these stripe cells (e.g. along the second lateral direction Y), i.e. perpendicular to the lateral extension of the control trenches 14 (e.g. along the second lateral direction Y).In the transition region 1- 23, the barrier structure 15 may fill portions of the first type mesas 17 formed by the trenches of the trench structure 14, 16 in the transition region 1- 23, as will be explained in more detail with reference to the drawings. For example, the barrier structure 15 surrounds the active region 1- 2 at least partially, e.g. such that at least the mesas 17 of the first type are not seamless adjacent to the transition region 1- 23 but are interrupted by the barrier structure 15, e.g. such that holes accumulated at or below the deep semiconductor region 105, e.g. during the turn-off and / or the subsequent turned-off state of the device 1, may not escape into the edge termination region 1- 3, as explained above.For example, the barrier structure 15 has a vertical extension db (cf. FIG. 4(B) ) within the range of 80% to 200% of the vertical extension dt (cf. FIG. 16 ) of the trench structure.In an embodiment, the barrier structure 15 has a vertical extension db so deep as to effectively prevent the hole current flow to the edge termination region 1- 3. This prevention may mean a hole current flow reduction by a factor of at least 10 3 or at least 10 6 compared to a configuration without the barrier structure.Further, the barrier structure 15 may have a width wb (see FIG. 4(B) ) within the range of 20% to 1000% of the width wt (see FIG. 16 ) of one of the control trenches 14.The barrier structure 15 may have an aspect ratio wb / db within the range of 5% to 300%, according to an embodiment.The barrier structure 15 can be potential-free (i.e. not electrically connected to a defined electrical potential). For example, the barrier structure 15 may alternatively be coupled to a defined electrical potential, e.g. to the electrical potential of the control trench electrodes 141 or to the electrical potential of the first load terminal 11. For this purpose, the barrier structure 15 can also comprise an electrically conductive material and / or a semiconducting material.Further, the barrier structure 15 may extend further along the vertical direction Z than the deep semiconductor region 105. For example, the barrier structure 15 extends up to twice as far along the vertical direction as compared to the trench structure 14, 16.Depending on the position of the deep semiconductor region 105, the barrier structure 15 may penetrate the deep semiconductor region 105 (see FIG. 4(B) ) or not (see FIG. 11(B) ). In both cases, the barrier structure 15 may be arranged in contact with the deep semiconductor region 105. Thus, according to an embodiment, the barrier structure 15 is arranged in contact with the deep semiconductor region 105.According to the embodiment of FIGS. 5(A) to 5(C), the barrier structure 15 is partially or completely based on a semiconductor of the first conductivity type having a dopant concentration that is at least twice as high as the dopant concentration of the drift region 100. For example, the barrier structure 15 is partly or completely based on a polycrystalline semiconductor material of the first conductivity type. For example, the barrier structure 15 is partly or completely based on a continuously doped crystalline silicon with the same dopant as in the deep semiconductor region 105. Exemplary method steps for making such versions of the barrier structure 15 are discussed below.Fig. 5(A) corresponds to Fig. 5(B). FIG. 5(C) illustrates a horizontal projection of the device 1, and FIG. 5(B) illustrates an enlarged view of the portion (1) indicated in FIG. 5(C). FIG. 5(B) illustrates a variant of the configuration of the edge termination region 1- 3 according to which a portion of the load terminal metallization 117 from which fourth contact plugs 114 extend along the vertical direction Z electrically connects to the semiconductor well region 109 of the semiconductor body 10. Spatially separated from the portion of the load terminal metallization 117 is the control terminal metallization 130 from which the third contact plugs 131 extend along the vertical direction Z to electrically connect to the control trench electrodes. Spatially separated from the control terminal metallization 130, in the active area 1- 2, another portion of the load terminal metallization 117 is arranged, from which the first contact plugs 111 extend along the vertical direction Z to electrically connect to the mesas 17 of the first type and from which the second contact plugs 112 extend along the vertical direction Z to electrically connect to the source trench electrodes 161, as already described with reference to FIG. 4(B). According to an embodiment, as illustrated, the control terminal metallization 130 may laterally overlap with the barrier structure 15. An inner portion of the load connection metallization 117 may also overlap laterally with the barrier structure 15. An outer load terminal metallization 125 may comprise the electrical potential of the second load terminal 12.According to the embodiment of FIGS. 6(A) and 6(B), the barrier structure 15 is partially or completely based on local broadenings of the trenches 14, 16 of the trench structure, as best illustrated in FIG. 6(A). For example, the trenches 14, 16 are locally widened in the transition region 1- 23 to obtain a complete oxidation of the trench insulators 142, 162 to fill the respective portions of the mesas 17 of the first type. The relevant description of FIG. 5(B) may apply equally to FIG. 6(B).According to the embodiment illustrated by way of example in FIG. 7, the barrier structure 15 is embodied as a barrier trench. For example, the barrier structure 15 may be configured as a cross trench and include a cross trench electrode (not illustrated). For example, the cross trench electrode is electrically connected, e.g., via one of the contact plugs 112, to the first load terminal 11 as the source trench electrodes 161. For example, the source trenches 16 arranged in the active region 1- 2 adjoin the barrier structure 15 in the transition region 1- 23. For example, in this variant, the source trenches 16 terminate at the barrier structure 15 and accordingly do not extend into the edge termination region 1- 3. For example, in the barrier structure 15, the source trench electrodes 161 adjoin the optionally provided and not illustrated cross trench electrode of the barrier structure 15.The description of FIG. 7 applies equally to FIG. 8, the difference being that, according to the embodiment exemplarily illustrated in FIG. 8, a fifth contact plug 115 is used to establish the electrical connection between the optionally provided and not illustrated cross trench electrode of the barrier structure 15 and the portion of the load terminal metallization 117 in the transition region 1- 23. In this variant, no separate / further electrical connection need be provided between the portion of the load terminal metallization 117 and the first load terminal 11, since this connection is established via the second contact plugs 112 in the active region 1- 2, the source trench electrodes 161 adjoining the optionally provided and not illustrated cross trench electrode of the barrier structure 15, and via the fifth contact plug 115.According to FIG. 9, the barrier structure 15 is again embodied as a barrier trench and also, as in FIG. 8, laterally overlaps with the section of the load connection metallization 117 in the transition region 1- 23. However, neither the source trenches 16 nor the control trenches 14 are adjacent to the barrier structure 15. The fifth contact plug 115 is used to establish the electrical connection between the optionally provided and not illustrated cross trench electrode of the barrier structure 15 and the portion of the load terminal metallization 117 in the transition region 1- 23. The portion of the load terminal metallization 117 in the transition region 1- 23 may be connected to the first load terminal 11 by other means.According to FIG. 10, the barrier structure 15 is again embodied as a barrier trench and laterally overlaps with the control terminal metallization 130 in the transition region 1- 23. Neither the source trenches 16 nor the control trenches 14 are adjacent to the barrier structure 15. Rather, the fifth contact plug 115 is used to establish the electrical connection between the optionally provided and not illustrated cross trench electrode of the barrier structure 15 and the control terminal metallization 130 in the transition region 1- 23. The upper portion of the load terminal metallization 117 is connected to the first load terminal 11.According to the embodiment illustrated by way of example in FIG. 11, the deep semiconductor region 105 terminates at the barrier structure 15. For example, in this case, the barrier structure 15 is partially or completely based on a semiconductor of the first conductivity type having a dopant concentration that is at least twice as high as the dopant concentration of the drift region 100. For example, the barrier structure 15 is partly or completely based on a polycrystalline semiconductor material of the first conductivity type. For example, the barrier structure 15 is partly or entirely based on a continuously doped crystalline silicon having the same or a higher dopant concentration as in the deep semiconductor region 105. Fig. 11(B) illustrates the vertical cross section taken along the dotted line (1) shown in Fig. 11(A). The barrier structure 15 may laterally overlap with the control terminal metallization 130, as best shown in FIG. 11(C). However, the barrier structure 15 is electrically insulated from the electrical potential of the control terminal metallization 130. For example, the barrier structure 15 is kept floating. For example, the barrier structure 15 surrounds the entire active region 1- 2.According to the embodiment of FIG. 14, no portion of the load terminal metallization 117 is provided in the edge termination region 1- 3. Rather, the load terminal metallization 117 is provided only in the active region 1- 2 and the transition region 1- 23. The deep semiconductor region 105 is penetrated by the barrier structure 15. Again, the barrier structure 15 may be partly or entirely based on a semiconductor of the first conductivity type having a dopant concentration at least twice as high as the dopant concentration of the semiconductor drift region 100. For example, the barrier structure 15 is partly or completely based on a polycrystalline semiconductor material of the first conductivity type. For example, the barrier structure 15 is partly or entirely based on a continuously doped crystalline silicon with the same or a higher dopant as in the deep semiconductor region 105.According to the embodiment of FIG. 15, a portion of the load terminal metallization 117 is provided in the edge termination region 1- 3 (and could accordingly be referred to as emitter ring) and extends into the transition region 1- 23. The deep semiconductor region 105 is penetrated by the barrier structure 15. Again, the barrier structure 15 may be partly or entirely based on a semiconductor of the first conductivity type having a dopant concentration at least twice as high as the dopant concentration of the semiconductor drift region 100. For example, the barrier structure 15 is partly or completely based on a polycrystalline semiconductor material of the first conductivity type. For example, the barrier structure 15 is partly or entirely based on a continuously doped crystalline silicon with the same or a higher dopant as in the deep semiconductor region 105. Optionally, the fifth contact plugs 115 may be provided to electrically connect the barrier structure 15 to the portion of the load terminal metallization 117.Herein, a method for manufacturing a power semiconductor device is also presented. For example, the method of manufacturing a power semiconductor device comprises forming the following components: an active region surrounded by an edge termination region; a semiconductor body extending in both the active region and the edge termination region and comprising a semiconductor drift region of a first conductivity type in the active region; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal in the active region; in the active region and the edge termination region, a trench structure extending along a vertical direction from the first side to the second side, the trench structure comprising a plurality of control trenches, each control trench including a control trench electrode configured to control the forward load current; in the active region, a deep semiconductor region of the first conductivity type. The deep semiconductor region has a dopant concentration at least twice as high as the dopant concentration of the semiconductor drift region, a thickness within the range of 10% to 120% of the vertical extension of the trench structure, and is arranged to overlap with the control trenches at least partially along the vertical direction. The method further comprises forming, spatially separated from the trench structure and arranged in a transition region between the active region and the edge termination region, a barrier structure extending along the vertical direction from the first side to the second side.Embodiments of the above-described method correspond to the embodiments of the above-described power semiconductor device 1.For example, forming the barrier structure 15 according to the preceding paragraph may comprise performing an implantation processing step, e.g. an angled double sidewall implantation.For example, such an angled double sidewall implant is schematically illustrated based on FIGS. 12(A)-(C). FIG. 12(A) illustrates a horizontal projection that includes two dashed lines (1) and (2), with corresponding vertical cross-sections illustrated in FIG. 12(B) (along line (1)) and in FIG. 12(C) (along line (2)).For example, the barrier structure 15 is formed by masked (e.g. angled) dual mode side wall implants (dual mode side wall implants) into the trenches 14 and 16 before the respective trench electrodes 141, 161 are formed. For example, only two small implantation regions at the right and left near the trench ends are subjected to such implantation as illustrated in FIG. 12(C). In order not to implant too deeply along the vertical direction, the "shadowing effect" of trench sidewalls may be used according to an embodiment. Furthermore, according to one embodiment, the angle of the angled double sidewall implantation may be selected such that the bottom of the trenches is not exposed to the implantation or is at most not exposed to the implantation.After the implantation, a diffusion processing step may be performed such that the implanted regions 150 in FIG. 12(C) converge to form the barrier structure 15. For example, even after diffusion, the barrier structure 15 does not extend deeper than the trenches 14, 16 according to an embodiment.The structure of FIGS. 13(A) to 13(C) illustrating a variant of the implantation processing step corresponds to the structure of FIGS. 12(A) to 12(C) except that the trenches 14, 16 are interrupted, for example, such that an uninterrupted accumulation layer is not formed on the trench sidewalls at or below the deep semiconductor region 105, which may provide an additional hole inclusion. Otherwise, the description with reference to FIGS. 12(A) to 12(C) applies equally.In the above, embodiments related to power semiconductor devices and respective manufacturing methods have been explained.For example, these power semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g. the semiconductor body and its regions / zones, e.g. regions etc., may be a monocrystalline Si region or a monocrystalline Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.However, it is to be understood that the semiconductor body and its regions / zones may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, without being limited thereto, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), Aluminium gallium indium nitride (AlGaInN) or Indiumgalliumarsenidphosphid (InGaAsP) and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The above-mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are mainly used at present.Spatially relative terms such as "below," "below," "lower," "above," "upper," and the like, are used to simplify the description to explain the positioning of an element relative to a second element. These terms are intended to encompass different orientations of the respective device in addition to orientations other than those depicted in the figures. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, portions, etc., and are also not intended to be limiting. Like terms may refer to like elements throughout the specification.

Claims

A power semiconductor device (1) comprising - an active area (1-2) surrounded by an edge termination area (1-3); - a semiconductor body (10) extending in both the active area (1-2) and the edge termination area (1-3) and comprising in the active area (1-2) a semiconductor drift area (100) of a first conductivity type; - a first load terminal (11) on a first side (110) of the semiconductor body (10); - a second load terminal (12) on a second side (120) of the semiconductor body (10) opposite the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12) in the active area (1-2); in the active region (1-2) and the edge termination region (1-3) a trench structure (14, 16) extending along a vertical direction (Z) from the first side (110) to the second side (120), the trench structure (14, 16) comprising a plurality of control trenches (14), each control trench (14) including a control trench electrode (141) configured to control the forward load current; - in the active region (1-2), a deep semiconductor region (105) of the first conductivity type, wherein the deep semiconductor region (105) ◯ has a dopant concentration at least twice as high as the dopant concentration of the semiconductor drift region (100), ◯ has a thickness within the range of 10% to 120% of the vertical extension (dt) of the trench structure (14, 16), and ◯ is arranged to overlap with the control trenches (14) at least partially along the vertical direction (Z); and - spatially separated from the trench structure (14, 16) and arranged in a transition region (1-23) between the active region (1-2) and the edge termination region (1-3), wherein a barrier structure (15) extends along the vertical direction (Z) from the first side (110) to the second side (120).The power semiconductor device (1) according to claim 1, wherein the trench structure (14, 16) comprises a plurality of source trenches (16), each source trench (16) including a source trench electrode (161) electrically connected to the first load terminal (11).The power semiconductor device (1) according to claim 2, wherein the trench structure (14, 16) has a trench pattern according to which each trench of the trench structure (14, 16) is either a control trench (14) or a source trench (16).The power semiconductor device (1) according to claim 2 or 3, further comprising, on the first side (110), a control terminal (13) electrically connected to the control trench electrodes (141), wherein - the electrical connection between the control terminal (13) and the control trench electrodes (141) is established in the edge termination region (1-3), - the electrical connection between the first load terminal (11) and the source trench electrodes (161) is established in the active region (1-2).The power semiconductor device (1) according to any one of the preceding claims, further comprising, arranged in the edge termination region (1-3), electrically connected to the first load terminal (11) and spatially separated from the barrier structure (15), a semiconductor well region (109).The power semiconductor device (1) according to any of the preceding claims, wherein the barrier structure (15) has a lateral extension perpendicular to the lateral extension of the control trenches (14).The power semiconductor device (1) according to any of the preceding claims, wherein the barrier structure (15) fills portions of mesas (17) formed by the trenches of the trench structure (14, 16).The power semiconductor device (1) according to any of the preceding claims, wherein the barrier structure (15) has a vertical extension (db) within the range of 80% to 120% of the vertical extension (dt) of the trench structure (14, 16).The power semiconductor device (1) according to any one of the preceding claims, wherein the barrier structure (15) has a width (wb) within the range of 20% to 200% of the width (wt) of one of the control trenches (14).The power semiconductor device (1) according to any one of the preceding claims, wherein the barrier structure (15) is either electrically floating or coupled to the electrical potential of the control trench electrodes (141) or the first load terminal (11).The power semiconductor device (1) according to any of the preceding claims, wherein the barrier structure (15) extends further along the vertical direction (Z) than the deep semiconductor region (105), e.g. at least 120%, and / or wherein the barrier structure (15) is arranged in contact with the deep semiconductor region (105).The power semiconductor device (1) according to any one of the preceding claims, wherein the barrier structure (15) penetrates the deep semiconductor region (105).The power semiconductor device (1) according to any one of the preceding claims, wherein the barrier structure (15) at least partially surrounds the active region (1-2).The power semiconductor device (1) according to any one of the preceding claims, wherein the barrier structure (15) is partially or completely based on a semiconductor of the first conductivity type having a dopant concentration that is at least twice as high as the dopant concentration of the semiconductor drift region (100).The power semiconductor device (1) according to any one of the preceding claims, wherein the barrier structure (15) is partly or entirely based on a polycrystalline semiconductor material of the first conductivity type.The power semiconductor device (1) according to any of the preceding claims, wherein the barrier structure (15) is partly or entirely based on a continuously doped crystalline silicon with the same dopant as in the deep semiconductor region (105).Power semiconductor device (1) according to one of the preceding claims, wherein the barrier structure (15) is partially or completely based on local widenings of the trenches of the trench structure (14, 16).The power semiconductor device (1) according to any of the preceding claims, wherein the trenches of the trench structure (14, 16) laterally delimit mesas (17), wherein the mesas (17) comprise mesas (17) of the first type, each of which is laterally delimited by at least one of the control trenches (14) and comprises - a portion of the deep semiconductor region (105), - one or more semiconductor source regions (101) of the first conductivity type, which are electrically connected to the first load terminal (11), and - a semiconductor body region (102) of a second conductivity type, wherein the semiconductor body region (102) isolates the one or more semiconductor source regions (101) from a portion of the drift region (100) within the mesa (17) of the first type or from the portion of the deep semiconductor region (105).Power semiconductor device (1) according to one of the preceding claims, wherein the barrier structure (15) is embodied as a barrier trench and / or comprises one or more barrier trenches.The power semiconductor device (1) according to any one of the preceding claims, wherein the power semiconductor device (1) has an IGBT configuration.A method for manufacturing a power semiconductor device (1) comprising forming the following components: - an active region (1-2) surrounded by an edge termination region (1-3); - a semiconductor body (10) extending in both the active region (1-2) and the edge termination region (1-3) and comprising in the active region (1-2) a semiconductor drift region (100) of a first conductivity type; - a first load terminal (11) on a first side (110) of the semiconductor body (10); - a second load terminal (12) on a second side (120) of the semiconductor body (10) opposite the first side (110), wherein the power semiconductor device (1) is configured to conduct in the active region (1-2) a forward load current between the first load terminal (11) and the second load terminal (12); in the active region (1-2) and the edge termination region (1-3) a trench structure (14, 16) extending along a vertical direction (Z) from the first side (110) to the second side (120), the trench structure (14, 16) comprising a plurality of control trenches (14), each control trench (14) including a control trench electrode (141) configured to control the forward load current; - in the active region (1-2), a deep semiconductor region (105) of the first conductivity type, wherein the deep semiconductor region (105) ◯ has a dopant concentration at least twice as high as the dopant concentration of the semiconductor drift region (100), ◯ has a thickness within the range of 10% to 120% of the vertical extension (dt) of the trench structure (14, 16), and ◯ is arranged to overlap with the control trenches (14) at least partially along the vertical direction (Z); and - spatially separated from the trench structure (14, 16) and arranged in a transition region (1-23) between the active region (1-2) and the edge termination region (1-3), wherein a barrier structure (15) extends along the vertical direction (Z) from the first side (110) to the second side (120).The method of claim 21, wherein forming the barrier structure (15) comprises performing an angled double sidewall implant.

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