SIC backside conditioning for improved ohmic contact formation

Abstract

A method for producing a SiC wafer comprising SiC on a surface of a semiconductor substrate is described. The method comprises conditioning a surface region of a SiC wafer substrate by an acid treatment, forming a metal contact layer on the conditioned surface, and annealing the substrate / metal contact stack to form an ohmic contact at the interface between the SiC and the metal contact layer. Furthermore, a SiC wafer is described that comprises a SiC semiconductor substrate and a metal contact layer on its backside surface, which is produced by the method described herein. The wafer comprises at least some composite particles or layers resulting from a reaction of SiO x C yand the acid used in conditioning the wafer substrate surface area at the interface between the SiC semiconductor substrate and the metal contact layer on its back surface.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to methods of manufacturing a silicon carbide (SiC) wafer, particularly those comprising a silicon carbide wafer substrate surface in contact with a metal contact layer on the SiC backside. BACKGROUND

[0002] Semiconductor devices based on silicon carbide (SiC) and similar semiconductor components are widely used in many microelectronic devices. These microelectronic devices with SiC semiconductor material are used in power applications, high-temperature applications, and high-frequency applications, among others. Many device types based on SiC material have the electrical current flowing through the base material toward the metallized backside (e.g., the drain of a MOSFET device or one of the electrodes of a diode).

[0003] MOSFETs or diodes based on SiC rely heavily on good electrical contact on the metallization side. Furthermore, suitable adhesion properties of the metallization to the SiC substrate are required, e.g., in the soldering processes applied to the devices. Thus, good ohmic contact and good adhesion properties at the interface between SiC and the metallization improve electrical and mechanical performance during use or reliability testing.

[0004] To realize an ohmic contact, it is known to use a silicidation reaction by depositing a contact metal on a SiC back surface of a substrate, followed by a thermal annealing process. The back side of the wafer is typically heated to approximately 980°C, e.g., by laser thermal annealing (LTA), resulting in a thin molten surface layer, and silicidation occurs at the interface between the SiC and the deposited metal. However, during LTA annealing, unreacted metal regions, called NiSi bumps when the deposited metal is Ni or NiSi, can form. This results in a highly uneven surface with significant roughness. The formation of these NiSi bumps depends on the condition of the SiC surface and the laser energy used for the silicidation reaction.

[0005] For example, the unevenness of the NiSi layer can lead to contact problems during the wafer test process (poor contact between the wafer backside and the test chuck). These NiSi irregularities could also lead to rough metal layers deposited by evaporation or sputtering after the LTA process, which are conformally deposited on the roughened NiSi surface, resulting in rough backside metallization that is prone to quality issues at the die attach stage, such as increased solder void formation.

[0006] Therefore, it is an object of the present application to overcome at least some of the above problems. In particular, one object is to improve the reliability issues while providing a good, e.g., ohmic, backside contact of a SiC wafer. SUMMARY

[0007] According to one embodiment, the method for manufacturing a SiC wafer comprising SiC on a surface of a semiconductor substrate may include conditioning a surface region of a SiC wafer substrate through a chemical process, for example, an acid treatment. Acid treatment in this regard means preparing the surface region of the SiC wafer substrate in such a way that the surface is cleaned of impurities (e.g., some impurities or any impurities) and conditioned for a subsequent annealing process. Thus, a properly conditioned surface may enhance the reactions taking place at the surface in a subsequent annealing process, enabling a subsequent annealing process in a controlled manner on a SiC surface with defined chemical properties.

[0008] According to this embodiment, a metal contact layer can be formed on the conditioned surface region. "Forming" means that the metal contact can be formed directly on the SiC surface region where the ohmic contact is to be prepared, or it can be formed over the SiC surface, while an intermittent layer or at least some intermittent surface particles can be sandwiched between the SiC surface region and the metal contact material.

[0009] After forming the metal contact layer, the method may further comprise annealing the substrate / metal contact stack to form an ohmic contact at the interface between the SiC and the metal contact layer. Due to the conditioning of the surface region of the SiC wafer prior to forming the metal contact layer, particles or contaminant layers, e.g., formed during the back grinding process and present on the SiC surface, may be at least partially removed from the surface region to be brought into contact with the metal contact material.In some examples, the particles or impurity layers present on the surface may be chemically treated by the acidic components used to condition the surface region of the SiC wafer substrate, while the SiC substrate itself is generally not significantly etched due to the very low etch rate for SiC of the acidic etch treatment at room temperature. Chemical treatment may involve breaking bonds within the particles present at the surface or may involve depositing acidic components on their surface, thereby changing the physical or chemical properties of the particles. In some examples, bonds within the particles or layers may be broken, and the physical or chemical properties may be changed by reaction with acidic components. This may create composite particles or layers.Examples of such composite particles or layers generated in situ during conditioning can be obtained from a reaction of SiO. x C y and the acid or acid components used. In some examples, the counterions of the acid component can bind to dangling or broken bonds of the particles at the surface region. Examples of physical properties that have been altered can be thermal conduction or heat capacity. Examples of chemical properties that have been altered can be surface polarity and contact angle.

[0010] According to another embodiment, the present description relates to a SiC wafer comprising a SiC semiconductor substrate and a metal contact layer on its back surface, which is produced by one of the aforementioned described methods. According to this embodiment, the SiC wafer may comprise at least some composite particles resulting from a reaction of SiO x C yand the acid or acid components used in conditioning the wafer substrate surface area at the interface between the SiC semiconductor substrate and the metal contact layer on its backside surface. In this case, the conditioning does not have to clean the surface area to be contacted of any particles and contaminants, but can change the physical and chemical properties of the particles bound to the surface of the SiC wafer, at least to some extent. As a result, the manufacturing process can result in a SiC wafer with improved, i.e., higher reliability, while providing good ohmic contact at the backside of the SiC wafer.

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The elements of the drawings are not necessarily to scale relative to one another; instead, emphasis is placed upon illustrating the principles of the invention. Like reference numerals designate correspondingly similar parts. The features of the various illustrated examples may be combined, provided they are not mutually exclusive. Examples are shown in the drawings and described in detail in the following description. Fig. 1 illustrates process steps of a method for forming a SiC wafer according to a first embodiment of the present description. Fig. 2 illustrates the fabrication of a SiC wafer according to the first embodiment. Fig. 3 illustrates the fabrication of a SiC wafer according to a second embodiment. Fig. Figure 4 shows a microscopic image of a SiC wafer without using a preconditioning step. Fig. 5 shows a microscopic image of a SiC wafer according to one embodiment. DETAILED DESCRIPTION

[0013] In the following detailed description, semiconductor devices are based on silicon carbide, a material with potential for high-temperature, high-frequency, and radiation-hardened applications. SiC is a wide-bandgap semiconductor material suitable for semiconductor devices with specific dielectric gate structures, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), or insulated-gate bipolar transistors (IGBTs). Any other semiconductor devices with a dielectric gate structure are included in the general concept of the present disclosure, even if not explicitly mentioned herein. Many device types based on SiC material have the electrical current flowing through the base material toward the metallized backside (e.g., the drain of a MOSFET device or one of the electrodes of a diode).A suitable metallization with good adhesion to SiC makes it possible to achieve good electrical contact, especially ohmic contact, during the annealing process after contact metal deposition.

[0014] The semiconductor devices can be fabricated from semiconductor substrates, with substrate shapes and sizes varying and including commonly used round wafers of various sizes, for example, with a diameter between 50 and 450 mm. Any other semiconductor substrate shapes and sizes can be used instead of the commonly used exemplary round wafers.

[0015] In accordance with the description herein, a semiconductor substrate can generally be any semiconductor substrate comprising a SiC body on its surface, for example, in the form of a SiC-based substrate or as an epitaxial layer on a substrate made of any material suitable for use as a semiconductor material for microelectronic devices. The SiC wafers or SiC substrates, as previously described, are generally thinned by backside grinding to realize thin SiC chips. This thinning improves the thermal and electrical performance of the product. Thinning can be performed either by mechanical processing, for example, using grinding wheels with different grid sizes to mechanically remove portions of the SiC layer while water-cooling the SiC backside, or by using a suitable dry etching process, e.g., a downstream plasma etching process.Due to the mechanical grinding process, an uneven and rough surface of the SiC chips with grinding grooves on their surface is obtained, whereas in the case of subsequent plasma etching, an irregular hill and valley topography is created. Typically, the depth of the grooves is in the range of a few tens of nm to a few hundred nm. This thinning of the SiC layer on the backside of the SiC chip can be included as a preliminary step in the process as described herein, while the starting wafer can be manufactured according to any other process, such as a cleaving process that produces SiC wafers with a defined thickness. However, even for the cleaving process, it is mandatory in most cases to use a defined grinding or polishing step after cleaving to achieve the desired target SiC thickness within the total thickness variation specified for the manufactured SiC chip technology.

[0016] According to a first embodiment of the method for forming a SiC wafer, the semiconductor substrate comprising silicon carbide on a surface thereof may start from a SiC wafer, which may be obtained by thinning or grinding or any other mechanical processing, or any combination thereof, as long as a wafer has a planar SiC surface on the backside thereof. How the SiC wafer is obtained is not important for the method described herein, and any conventional manufacturing method may be used for this preliminary step. The thin SiC wafer to be treated according to the method described herein is then treated by an acid treatment. The acid treatment of the SiC substrate surface is more of a conditioning of the surface area of ​​the SiC wafer substrate, particularly on the backside of the wafer, than a cleaning of the SiC substrate. This embodiment is described in the Fig. 1 and Fig. 2 in more detail. The step of forming a semiconductor substrate 10 is shown as step O in Fig. 1. This step is not mandatory, and the method as described herein may be applied using any SiC wafer produced or obtained from another manufacturing process. For example, the SiC substrate 10 may be prepared or thinned by grinding or polishing the surface region of the substrate. Alternatively, a conventional trench structure with a SiC surface may be provided. The freshly prepared surface region may be contaminated, for example, with native oxides or carbonaceous impurities, which may be deposited as layer 15 in Fig. 2. The layer 15 may be a continuous thin layer of a few nanometers. Sometimes the surface may be contaminated by specific particles in a random distribution on the SiC surface 10. As previously described, the SiC wafer surface after grinding (step O in Fig. 1) A significantly rough surface. The surface area is sprayed with deionized water in standard procedures to clean the SiC wafer surface on the backside of the SiC wafer. The deionized water sprayed onto the surface usually removes some of the particles, but at least some of the particles remain after the water rinsing step. In particular, the number of remaining particles is higher in the grinding grooves than in other parts of the surface area. The contaminants 15 in the grinding grooves and on the surface 10 can lead to defects in the metallization layer.

[0017] If electrical contact to SiC is achieved through Ni-based materials, e.g., by sputtering a thin NiSi layer on the backside of a SiC wafer, as is sometimes used in the fabrication of SiC semiconductor devices, a laser thermal annealing (LTA) process can be used to create an ohmic contact. The annealing process can trigger a reaction between SiC and the deposited NiSi (e.g., SiC + 2Ni → Ni2Si + C). To avoid thermal reactions on the wafer frontside during a furnace process, laser thermal annealing (LTA) can therefore be used as the preferred heating technique on the backside of the wafer. During the LTA process, the melting of a very thin NiSi layer can occur, leading to the so-called silicidation reaction and the increase in the ohmic behavior of the electrical contact.However, due to surface roughness, inhomogeneities, or defects on the SiC wafer surface, unreacted metal areas, called NiSi bumps, can be created in an uneven pattern on the backside of the wafer, which can lead to increased backside roughness. The formation of these NiSi bumps depends on the condition of the SiC surface and the laser energy. This can also lead to several other problems in subsequent steps during semiconductor device manufacturing. For example, contact problems, adhesion issues, or reliability issues (leaky backside metal layers), conductivity differences, and so on, can occur due to the presence of a high number of defects, such as NiSi bumps, and increased SiC and / or NiSi roughness. These NiSi irregularities could also lead to rough metal layers deposited by evaporation or sputtering after the LTA process.Barrier layers, for example, should be high-density and as smooth as possible. In any case, roughness in an underlying layer is detrimental to barrier layers, carrying the risk of reliability issues.

[0018] Therefore, according to the method described herein, the surface region of the semiconductor substrate 10 containing the impurity layer 15 on its surface is treated using an acidic agent (step A), thereby conditioning the surface region for the following steps and ensuring improved thermal laser annealing. The surface region of the SiC wafer substrate can be conditioned and / or cleaned by an acid treatment A. On the other hand, the particles adhering to the surface and not removed (e.g., completely removed) by this conditioning can have at least some physical or chemical properties altered. It has been shown that the formation of NiSi bumps due to the subsequent metal contact layer formation C and thermal annealing E can be at least reduced or even avoided by an acid treatment A of the surface.The subsequent annealing E thus leads to a more uniform metal contact layer 20, e.g., a NiSi layer, and thus to a smoother backside compared to the processes without acid conditioning (step A) before the formation of the metal contact layer (step C).

[0019] The conditioning step using an acid treatment of the SiC surface region during the fabrication of electrical contacts, particularly on the backside of SiC substrates, can improve the annealing process. In particular, a more uniform silicidation reaction can be obtained at the surface between SiC 10 and the metal contact 20, e.g., Ni or NiSi or any other contact metal, such as Co. Therefore, although most examples rely on nickel or NiSi metal contact layers 20, the present description is not limited to nickel as an ohmic contact-forming material. The description also includes any other material that could form an ohmic contact to SiC through an annealing process, particularly those capable of forming a silicide layer 30 and that would also form bump structures during the annealing processes.

[0020] After the formation of the intermediate silicide layer 30, the layer 20 can be completely converted into a metal silicide layer 35 (see step F in Fig. 3). In the Fig. 3, the first three steps are the same as with the aforementioned embodiment shown in Fig. 2. Step F is an optional step and describes another exemplary embodiment of a manufacturing method for a SiC wafer comprising a semiconductor substrate 10 with a silicide layer 35 (e.g., a silicide layer including the function of a metal layer).

[0021] It has been shown that acid treatment does not etch significant portions of the SiC substrate, but likely provides other effects on the contaminants present at the surface after the grinding step. It is believed that the particles and contaminants at the surface react with the acidic components, thereby reducing the number of defects and particle size at the surface of the SiC wafer substrate. Therefore, the acid treatment used in SiC conditioning may use the same acidic components as in other semiconductor device manufacturing processes, but has a different effect on the material due to the very low etch rate of SiC against acids at room temperature. Thus, conditioning using acids does not involve a significant etching process of the SiC substrate, but does have an effect on the particles adhering to the SiC surface.Examples of particles or layers known to be present on SiC surfaces are SiO. x C y -Particles or layer stacks of SiO x C y and SiO x , which are also known as native oxides. Therefore, some examples of the method described herein include the step of conditioning the back surface of the SiC wafer by reducing or removing SiO x C y Particles or layers from the surface region. In some examples, bonds within these particles or layers can be broken and the physical or chemical properties can be changed by reaction with the acidic components. This can create composite particles or layers. Examples of such composite particles or layers created in situ during conditioning result from a reaction of SiO x C yand the acid or acid components used. In some examples, the counterions of the acid component can bind to broken bonds of the particles or layers at the surface region. Thus, the physical and chemical properties of these adhered composite particles or layers are altered such that subsequent annealing does not result in significant bump formation. It is believed that some of the Si-O bonds are broken and saturated by the respective counterion of the acid or acids used for conditioning. This can increase the thermal conductivity of these modified particles so that the environment around the particle is not affected upon laser heating in the same way as at sites covered with native oxides. This may be due to different vibrational or strain energies of the newly formed bonds compared to the O-Si-O bonds.It is assumed that the lower local heat increase at the locations of particles or contaminants would thus reduce the risk of bump formation. Therefore, a more uniform metal contact layer, i.e., a reduced number of defects, can be obtained when a preconditioning step with acidic components is performed as described herein.

[0022] In some embodiments, the acid treatment of the wafer substrate surface area is performed by plasma chemical or wet chemical processing. Example plasma techniques include, for example, downstream plasma etching processes containing fluorine (e.g., fluorine-containing agents). Example wet chemical processes include, for example, single-wafer spin etching or batch bath processes containing, for example, HF and HNO3. During conditioning, the wafer may, but does not have to, be supported by a foil or glass carrier on the front side to protect these areas from the acid treatment in the plasma chamber or wet processing chamber. If wet chemical processing is used, the backside of the wafer may be conditioned, for example, by spin-coating the acidic components onto the backside of the wafer, for example, a rotating wafer.Conventional rotation speeds used for semiconductor wafer etching processes can be applied here (e.g., 100–2000 rpm). Depending on the chemicals used and the processing method, conditioning can be performed at a temperature suitable for reacting with the impurities on the SiC surface. In some examples, the temperature can be adjusted between room temperature and elevated temperature (approximately 20–70 °C).

[0023] As previously described, particles or contaminants present at the SiC surface may be at least partially removed from the surface region to be brought into contact with the metal contact material during the conditioning processing as described herein. In some examples, the particles present at the surface may be treated by the acidic components used for conditioning the surface region of the SiC wafer substrate. If the acid treatment comprises a wet etching treatment, exemplary acids may be selected from acids, e.g., those defined by Brønsted as components having the ability to form hydrogen ions (H +)—otherwise known as protons—to bases that “accept” them. This acid-base reaction may underlie the reactions that take place on the particles or the SiC surface during the conditioning reaction. Example acids and acid mixtures may be selected from nitric acid (HNO3), sulfuric acid (H2SO4), hydrofluoric acid (HF), and phosphoric acid (H3PO4), among similar acids known for silicon etching treatments in the semiconductor field. According to some examples, the wet etching treatment may be performed using a combination of one or more acids selected from the groups consisting of HNO3, H2SO4, HF, and H3PO4. Some of the acids may have a reducing property, while others may have a more oxidizing property. Therefore, in some examples, a mixture of reducing and oxidizing acids may be used.In another process variant, a conditioning mixture similar to those used for coarse etching of silicon semiconductors can be used. Such coarse etching mixtures can contain HF, HNO3, H2SO4, and water in various concentration combinations. Suitable rinsing exposure times can range from 5-30 seconds to several minutes, for example. Other exemplary conditioning chemicals can include combinations of HNO3 / HF, HNO3 / H2SO4 / HF / H3PO4, and mixtures with other acids.

[0024] Chemical treatment may involve breaking bonds within the particles or layers present at the surface or may involve depositing acidic components on their surface, thereby changing the physical or chemical properties of the particles or layers. In some examples, bonds within the particles or layers may be broken and the physical or chemical properties may be changed by reaction with acidic components. This may produce composite particles or layers. Examples of such composite particles produced during in situ conditioning may result from a reaction of SiO x C y and the acid or acid components used. For example, if hydrofluoric acid is used, the counterions of the acid component F -Therefore, the composite components present at the conditioned surface may contain O-Si-F bonds. These O-Si-F bonds can be analyzed using surface-sensitive attenuated total reflection infrared (ATR-IR) spectral signals from SiC wafer backside surfaces. ATR-IR spectral signals can thus detect, for example, vibrational modes of Si-C, Si-O-Si, and O-Si-F. Other vibrational modes can also be detected to confirm which type of composite particles have been formed. In addition, the ATR-IR technique also makes it possible to at least estimate or calculate the composition of the particles or layers formed at the interface of the SiC and the contact metal. With these ATR-IR probes of wafer backsides conditioned with a coarse or uniform spin etching process, molecular SiO xFY compounds can be detected on the SiC wafer backside surfaces. These composite compounds can be used as a method for detecting the conditioning or cleaning process used for SiC backside fabrication of semiconductor devices. Alternatively, angle-resolved XPS (AR-XPS) techniques could be used to detect specific composite particles or layers, as described herein.

[0025] In some embodiments, the wafer substrate can be treated while rotating on a rotary etching tool. The wafer is thereby rotated around its axis at a rotation speed of 100–2000 rpm, in particular approximately 800 rpm. During rotation, the acid treatment components are spin-coated onto the backside of the rotating wafer. The wafer may, but need not, be supported by a foil or glass carrier on the front side to cover it. The coated conditioning fluid, e.g., a mixture of different acids as described in one of the above embodiments (e.g., HNO3 / H2SO4 / HF), can remain on the rotating wafer surface for between approximately 5 and 60 seconds to react and is then washed away. The temperature of the conditioning fluid used can be between approximately room temperature (approximately 25°C) and, for example, 80°C.In particular, the temperature of the conditioning fluid can be between approximately 20-70 °C.

[0026] In some embodiments, the thus-conditioned surface can be immediately treated with a contact material. Exemplary contact materials include Ti, Co, Ni, and NiSi. Combinations of one or more contact metals can be used. In particular, the metal contact layer can comprise contact materials selected from one or more components comprising Ni, Ti, and any combination thereof, or combinations thereof with Si. In particular, those contact materials that undergo a silicidation reaction during heat treatment can be suitably used to create the ohmic contact at the interface between the SiC and the contact metal layers.

[0027] In some embodiments of the methods described herein, an annealing step is used to perform a silicidation reaction between SiC and the contact material deposited thereon. The annealing step may include a laser thermal annealing (LTA) process. The LTA process is used to form the ohmic contact. In some examples, a NiSi layer was formed on a pretreated SiC wafer surface in accordance with the method described herein. After annealing, the formed NiSi layer exhibited a much more uniform and smoother appearance with fewer NiSi bumps than without any conditioning steps. This can even be achieved for single LTA shots and for LTA processes with lower energies. Thus, an improved contact layer can be realized, resulting in better ohmic backside contact.Furthermore, a smoother backside metal layer stack with no or few bumps can be realized compared to unconditioned surfaces. This also leads to fewer problems for the following processes, such as wafer dicing, chip picking, chip attach, soldering processes, and so on. The conditioning step used for the SiC surface preparation in the methods described herein further enables a wider process window for the LTA. Electrical tests showed very good results, comparable to the standard process without a conditioning step. In contrast to the standard process, the LTA process window is wider. This means that even lower LTA energies, e.g., approximately 3.8 J / cm, can be used. 2 or less, in particular about 3.6 J / cm 2 , and showed good ohmic backside contacts, even though each surface area is irradiated only once.

[0028] According to another embodiment, the present description relates to a SiC wafer comprising a SiC semiconductor substrate and a metal contact layer on its backside surface, which is produced by one of the aforementioned described methods. According to this embodiment, the SiC wafer may comprise at least some composite particles or layers resulting from a reaction of SiOxCy and the acid or acid components used in conditioning the wafer substrate backside surface region at the interface between the SiC semiconductor substrate and the metal contact layer on its backside surface. In this case, the conditioning does not completely clean the surface area to be contacted of any particles and contaminant layers, but may change the physical and chemical properties of the particles bonded to the surface of the SiC wafer.As a result, the manufacturing process can result in an optimized annealed contact layer, especially in a SiC wafer, with improved reliability, while providing good ohmic contact at the backside of the SiC wafer. The absence or low density of defects (e.g., bumps such as NiSi bumps) between the SiC wafer surface and the contact metal layer can result in a smoother and more uniform backside, even after further processing, such as the application of a solder material (e.g., AuSn backsides for diffusion soldering, Ag backsides for soft soldering, several other backside stacks used for sintering, etc.). Since lower energies can be used during annealing, the process window can be increased.

[0029] According to another embodiment, the present description relates to a SiC wafer comprising a SiC semiconductor substrate and a metal contact layer on its backside surface, which is produced by one of the aforementioned described methods. According to this embodiment, the SiC wafer may comprise at least some composite particles resulting from a reaction of SiOxCy and the acid or acid components used in conditioning the wafer substrate surface area at the interface between the SiC semiconductor substrate and the metal contact layer on its backside surface. In this case, the conditioning does not completely clean the surface area to be contacted of any particles and contaminant layers, but may change the physical and chemical properties of the particles bound to the surface of the SiC wafer.As a result, the manufacturing process can result in a SiC wafer with improved, i.e. increased, reliability while providing good ohmic contact at the back of the SiC wafer.

[0030] In some embodiments, the method is applied to a wafer substrate that is a SiC substrate comprising a main surface on which semiconductor elements are formed and a back surface facing the main surface. Example semiconductor elements may be MOSFET devices or diodes based on SiC substrates. These semiconductor devices may be fabricated by thinning and / or grinding, with or without polishing, a surface of a SiC wafer substrate into SiC chips with a thickness ready for forming further device structures therein or thereon. After the thinning or grinding step, the substrate surface may include a cleaning or rinsing step with deionized water to remove most of the non-adhered particles from the SiC substrate surface. Thereafter, a conditioning step as previously described may be performed before a contact metal is formed on the SiC surface.Annealing, for example, by LTA, can result in good ohmic contact on the backside of the semiconductor device. After backside contact formation, soldering processes or integrated frontside structures can be processed to obtain a semiconductor device with good ohmic contact on the backside of the semiconductor wafer substrate used. SiC wafers comprising a SiC semiconductor substrate and a metal contact layer on their backside surface, produced by one of the methods including a step of conditioning the SiC surface with an acid treatment, exhibit, among other things, good electrical contacts, suitable adhesion properties of the metal contact to the SiC, and suitable properties with respect to pre-assembly and assembly processes.Furthermore, the smoother and more uniform backside contacts obtained by the methods described herein also enable thinner backside stacks and more reliable backside metal stacks in many semiconductor devices.

[0031] An example of a SiC wafer is now prepared according to the Fig. 4 and Fig. 5. The SiC wafer produced by any of the above-mentioned manufacturing methods may comprise at least some composite particles or layers resulting from a reaction of SiO x C yand the acid used in the conditioning of the wafer substrate surface area at the interface between the SiC semiconductor substrate and the metal contact layer on its backside surface. In this case, a coarse etching mixture comprising HF, H2SO4, and HNO3 in combination was used in the SiC substrate surface conditioning step. Ni was then deposited in admixture with Si on the conditioned surface before an annealing step was performed. After an annealing step to create an ohmic contact, a microscope image of the SiC backside was taken and is shown in Fig. 5. As can be seen, only a small number of black dots based on NiSi bumps with significant volume are present on the significantly smooth surface. In contrast, Fig. Figure 4 shows a microscopic image of another SiC wafer without the preconditioning step. The dark spots shown in this image extend mainly along the grinding grooves 40 on the SiC surface and show a high number of NiSi bumps on the SiC backside after the LTA process. The number of spots in the image shown in Fig. 5, the SiC wafer with conditioning before metal contact layer deposition and annealing shows only a few NiSi bumps 50.

[0032] The surface shows smoothed grinding grooves and smaller and less SiO x C yParticles from grinding residues compared to wafer surfaces not conditioned with an acid treatment. In some examples, defect densities (measured via particle counts) were reduced by at least 20%, in some examples by more than 40%, sometimes more than 45%. There was a high statistical correlation between the defect density after cleaning and the number of NiSi bumps 50 after LTA annealing of the contact metal layer. Overall, the surface was improved, meaning smoother, after LTA annealing and after further processing, such as brazing another metal, such as Ag or AuSn braze material, in SiC wafers conditioned by an acid treatment prior to metal contact layer deposition and annealing.

[0033] In some examples, the SiC wafer after annealing has a changed SiO / SiC ratio in the SiO x C yparticles or layers after conditioning compared to unconditioned SiC wafers. In particular, the SiO / SiC ratio can be increased by at least a factor of 2 compared to the SiO / SiC ratio in SiO x C y -particles after the grinding step. Further exemplary reductions in the SiO / SiC ratio can be by factors of at least 3, 5, 7, 10 or even higher. The ratio can be measured by ATR-IR analysis and can be calculated based on the absorption ratio of SiO x and SiC. If at the same time the SiO x - and SiC ratio changes, new strain or bending modes of SiO xFy compounds are detected in the ATR-IR spectrum. These results demonstrate that the conditioning process used could still be detected on the final SiC wafer product by applying state-of-the-art analytical techniques to the SiC backside of newly constructed devices with removed backside metal layers.

[0034] In accordance with the embodiment described above, it has been shown that the production of composite compounds, e.g., SiO x Fy compounds, during the conditioning step using an acid treatment, in particular a treatment using a mixture of acids comprising at least HF, can lead to a SiC wafer with improved properties. In particular, the conditioning leads to a significant reduction of SiO x C y -particles on the SiC surface, the generation of newly formed SiO xFy composite particles or layers and an overall smoother surface after LTA annealing. It is assumed that the laser energy absorbed by the particles present at the surface varies depending on their composition and thermal conductivity. The lower number of SiO x-Components at the surface apparently leads to a smaller temperature increase at the particle locations during LTA annealing. The higher ratio of composite particles containing Si-F bonds can thus lead to a smaller temperature increase at the particle locations upon laser irradiation of the surface. A smaller temperature increase appears to result in fewer NiSi bumps at the particle locations and thus to a smoother surface of the SiC wafer backside, including the metal contact layer. Furthermore, the subsequently prepared solder material layers are smoother overall due to the smaller number of NiSi bumps and the smoother surface. Thus, the conditioning step can be performed using a chemical conditioning process as described herein, e.g.an acid treatment, lead to improved SiC wafers with good ohmic backside contact, a smooth surface and good reliability after completion of the SiC wafers.

[0035] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of the specified elements or features but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and singular unless the context clearly indicates otherwise.

[0036] It is understood that the features of the various embodiments described herein may be combined with one another unless expressly stated otherwise. Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments and examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, this disclosure is intended to be limited only by the claims and their equivalents.

Claims

[1] Method for producing a SiC wafer comprising SiC on a surface of a semiconductor substrate, comprising: Conditioning a surface area of ​​a SiC wafer substrate by acid treatment; Formation of a metal contact layer on the conditioned surface area; and Annealing the substrate / metal contact stack to form an ohmic contact at the interface between the SiC and the metal contact layer. [2] Method according to claim 1, further comprising thinning and / or grinding a surface of the SiC wafer substrate. [3] Method according to one of claims 1 and 2, wherein the wafer substrate is a SiC substrate comprising a main surface on which semiconductor elements are formed and a back surface facing the main surface. [4] Method according to any one of claims 1 to 3, wherein the back surface of the SiC wafer is reduced or removed by SiOx C y -particles from the surface area are conditioned. [5] Method according to any of the preceding claims, wherein the acid treatment of the wafer substrate surface area is carried out by plasma-chemical or wet-chemical processing. [6] Method according to any of the preceding claims, wherein the acid treatment comprises a wet etching treatment using a combination of one or more acids selected from the groups consisting of HNO3, H2SO4, HF and H3PO4. [7] Method according to any of the preceding claims, wherein the wafer substrate is treated while it is rotated on a rotary etching tool. [8] Method according to claim 7, wherein the acid treatment components are rotationally coated onto the back of the rotating wafer. [9] Method according to any of the preceding claims, wherein the metal contact layer comprises contact materials selected from one or more components comprising Ni, Ti and Co. [10] Method according to any of the preceding claims, wherein the tempering step comprises a thermal laser tempering process. [11] SiC wafer comprising a SiC semiconductor substrate and a metal contact layer on its back surface, produced by one of the aforementioned described methods, wherein the SiC wafer comprises at least some composite particles or layers formed by a reaction of SiO x C y and the acid that is used in the conditioning of the wafer substrate surface area at the interface between the SiC semiconductor substrate and the metal contact layer on its back surface. [12] SiC wafer according to claim 11, having a SiO / SiC ratio in the SiO x C y-particles after conditioning, which is at least 2 times higher than the SiO / SiC ratio in SiO x C y -particles are reduced after the grinding step.

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