Power electronics for a pulse inverter and method for producing a power module for this power electronics

Abstract

The invention relates to power electronics for a pulse-controlled inverter, comprising at least one power module (1) with a semiconductor chip (3) which is soldered or sintered on its underside via a sintered or soldering layer (7) onto a substrate (9), wherein the semiconductor chip (3) has an electrical connection surface (17) on its upper side, to which a connection element (23), in particular a leadframe, is connected via a connection layer (25), in particular a sintered layer, and wherein, during power electronics operation, a mechanical stress is generated in the connection layer (25) due to the connection element (23) being larger than the thermal expansion coefficient of the semiconductor chip (3).To reduce the mechanical stress in the connecting layer (25), according to the invention the semiconductor chip (3) and the connection element (23) are integrated in a sandwich structure in which a layer system (27) comprising at least one compensating layer is applied to the upper side of the connection element (23), said compensating layer counteracting thermal expansion of the connection element (23), wherein the layer system (27) is a double-layer system in which a compensating semiconductor chip (29) which is identical in construction to the semiconductor chip (3) and has no electrical function, and a sintered layer (31) are provided as compensating layers, so that an identical double-layer structure is formed on both sides of the connection element (23).

Description

[0001] The invention relates to a power electronics system for a pulse-controlled inverter according to the preamble of claim 1 and to a method for producing a power module for such a power electronics system according to claim 6.

[0002] In power electronics for a pulse-controlled inverter, a semiconductor chip of a power module is soldered or sintered on its underside to an upper aluminum or copper layer of a substrate. The substrate can be constructed using a DAB (direct aluminum bonding) or a DCB (direct copper bonding) design as a three-layer structure consisting of a central ceramic layer coated on both sides with the upper aluminum or copper layer and a lower aluminum or copper layer. The substrate is bonded to a heat sink through which coolant flows to enable heat dissipation from the semiconductor chip.

[0003] In such a semiconductor chip, electrical top-side contacting is commonly achieved using a bonding process in which aluminum bonding wires are friction-welded to a top-side chip connection pad. The aluminum bonding wires are bonded, with their wire ends facing away from the chip connection pad, to a contact point that is electrically decoupled from the upper aluminum layer of the substrate. A leadframe (e.g., a stamped or bent copper sheet) is also bonded to the contact point as a flat electrical connection element. Direct bonding of the leadframe with a sintered layer in between would, however, lead to mechanical stresses in the sintered layer due to the connection element's higher thermal expansion coefficient than that of the semiconductor chip.Such mechanical stresses can in turn result in delamination of the connection element from the semiconductor chip.

[0004] The contacting between the electrical connection element (i.e. leadframe) and the semiconductor chip described above is complex in terms of manufacturing technology and can only be carried out using several joining processes.

[0005] A semiconductor assembly of this type is known from DE 10 2019 212 895 A1. Another semiconductor assembly is known from JP H09 - 36 186 A. A semiconductor structure for reducing thermal expansion errors in chip-scale packaging is known from US 2023 / 0 215 820 A1. The semiconductor structure comprises a first metal layer over a substrate, a dielectric region, and a polymer region. The first metal layer comprises a first device metal structure. The dielectric region is formed over the first metal layer. The polymer region is formed over the dielectric region. The dielectric region comprises one or more metal layers and an interlayer dielectric layer with dielectric material between each pair of two adjacent metal layers in the plurality of metal layers. Each of the metal layers comprises a dummy metal structure over the first device metal structure.

[0006] US 2022 / 0 367 740 A1 discloses an electrical device comprising a substrate comprising the following components: a printing layer, a neutral voltage buffer layer, and a voltage compensation layer. The voltage buffer layer and the voltage compensation layer can each be formed from aluminum nitride.

[0007] The object of the invention is to provide a power electronics system for a pulse-controlled inverter which, compared to the prior art, enables simple electrical top-side contacting of the semiconductor chip with an electrical connection element, i.e. with a leadframe.

[0008] The object is achieved by the features of claim 1 or 6. Preferred developments of the invention are disclosed in the subclaims.

[0009] The invention relates to power electronics for a pulse-controlled inverter comprising at least one power module with a semiconductor chip. The chip is soldered or sintered onto a substrate on its underside via a sintered or soldered layer. The semiconductor chip has an electrical connection surface on its upper side, to which a connection element, in particular a leadframe, is connected via a connecting layer, in particular a sintered layer. During power electronics operation, mechanical stresses arise in the connecting layer due to the connection element's greater thermal expansion coefficient than the semiconductor chip's.According to the invention, the following measures are taken to reduce the mechanical stresses in the connecting layer: The semiconductor chip and the connecting element are integrated into a sandwich structure, in which a layer system consisting of at least one compensating layer is applied to the top side of the connecting element. The compensating layer counteracts excessive thermal expansion of the connecting element, so that the mechanical stress in the connecting layer can be reduced.

[0010] According to the invention, the mechanical stress arising in the connecting layer is therefore reduced by the different thermal expansion coefficients, thus making it possible for the preferably planar, i.e. flat-profile, connecting element (leadframe) to be joined directly to the semiconductor chip.

[0011] Compared to the prior art solutions, the invention requires only one component and one process for contacting the semiconductor chip and for leading the load path out of the module. The mechanical stress resulting from this connection is reduced by applying one or more layers (i.e., the compensation layers) to the leadframe above the semiconductor, thus preventing delamination of the leadframe from the semiconductor chip.

[0012] In a technical implementation, the material of the compensating layer can have a low coefficient of thermal expansion of, in particular, 3 to 14 ppm / K.

[0013] According to the invention, the layer system applied to the top side of the connection element is a double-layer system in which a compensating semiconductor chip, structurally identical to the semiconductor chip but electrically non-functional, is provided as a first compensating layer, and a sintered layer is provided as a second compensating layer. In this case, identical double-layer structures are formed on both sides of the connection element. During the completion of the sandwich structure, the sintered layer can first be pre-applied to the compensating semiconductor chip. Subsequently, in a sintering process, the compensating semiconductor chip can be sintered onto the top side of the connection element with the sintered layer interposed.

[0014] According to the invention, a dummy semiconductor chip with pre-applied sintering paste is used, which is sintered directly onto the connection element (i.e., the leadframe) above the semiconductor chip. By using identical materials above and below the connection element (leadframe), a sandwich structure is created that maximally counteracts uneven expansion in the sandwich structure. The first embodiment described above is preferred over the embodiments described below because it allows chip material scrap from semiconductor production to be used for the compensation semiconductor chips, thus incurring no additional costs. Furthermore, the best possible sandwich stack is created with exactly the same thermal expansion coefficients on both sides of the connection element.

[0015] The sintered layer is preferably made of a metal paste, in particular a copper paste, in which metal particles are coated with a solvent, such as alcohol. During the sintering process, the solvent evaporates due to the action of heat, and atoms of the metal particles diffuse into the at least one joining partner, creating a cohesive bond.

[0016] The substrate can be constructed in a DAB (direct aluminum bonding) or DCB (direct copper bonding) design as a three-layer structure consisting of a central ceramic layer coated on both sides with an aluminum or copper layer. The substrate is bonded to a heat sink through which coolant flows to enable heat dissipation from the semiconductor chip.

[0017] In summary, the present invention offers the advantage of cost savings over prior art solutions by using only a single component to contact the load path and by utilizing chip material scrap from semiconductor production, which is already factored into the price of the semiconductors by the manufacturer. Furthermore, in the first embodiment, only one joining process is required to construct the sandwich structure, which saves additional costs.

[0018] An exemplary embodiment of the invention and comparative examples not covered by the invention are described below with reference to the attached figures. They show: Fig. 1 a view of a power electronics according to the embodiment; Fig. 2 to 4 in views according to the Fig. 1 Comparative examples not covered by the invention.

[0019] For a simpler understanding of the invention, reference is first made to the Fig. 4, which is not covered by the invention. In the Fig. 5 shows a power module 1 of a power electronics system for a pulse-controlled inverter. The power electronics, along with other components such as the control board, intermediate circuit capacitor, and EMC unit, form a component of the pulse-controlled inverter. In an actual (but not shown) application, the power electronics is constructed for three phases with three power modules 1 and a heat sink 2. Each of these three power modules 1 has, for example, a half-bridge consisting of two semiconductor chips 3, of which Fig. 4 only one semiconductor chip 3 is shown. The semiconductor chip 3 is encapsulated in a potting compound 5, which is Fig. 4 is merely indicated by an outline. Other components of the pulse-controlled inverter have been omitted from the figures for clarity.

[0020] In the Fig. 4, the semiconductor chip 3 is sintered on its underside via a sintered layer 7 onto an upper aluminum layer 13 of a substrate 9. The substrate 9 is bonded to the heat sink 2. Furthermore, the substrate 9 is an aluminum-based substrate produced using a DAB (direct aluminum bonding) process, which has a three-layer structure consisting of a middle ceramic layer 11 coated on both sides with the upper aluminum layer 13 and a lower aluminum layer 13. The two aluminum layers 13 are bonded directly to the middle ceramic layer 11 to create a high-performance, thermally efficient substrate 9 for the power module 1.

[0021] As from the Fig. As can be seen further in Figure 4, an electrical top contact is made via bonding with aluminum bonding wires, of which Fig. 4, only one aluminum bonding wire 15 is shown. This is configured with a significantly smaller cross-section compared to the large-area leadframe 23. The aluminum bonding wire 15 can be bonded to a top-side chip connection pad 17 by friction welding. Furthermore, the aluminum bonding wire 15, with its wire end 19 facing away from the chip connection pad 17, is bonded to a contact point 21 decoupled from the upper substrate aluminum layer 13. A leadframe as a flat electrical connection element 23 (for example, a stamped and / or bent copper sheet) is also bonded to the contact point 21.

[0022] On the other hand, a direct connection of the planar connection element 23 to the top-side chip connection surface 17 with the interposition of a sintered layer would lead to mechanical stresses in the sintered layer and to a risk of delamination of the connection element 23 from the semiconductor chip 3 due to the thermal expansion coefficient of the planar connection element 23 being significantly higher than the thermal expansion coefficient of the semiconductor chip 3.

[0023] A core of the invention is to provide measures that enable such a direct connection of the planar connection element 23 without the risk of premature delamination of the connection element 23 from the semiconductor chip 3. Accordingly, first of all, the Fig. 1, which schematically indicates a power electronics whose structure and function are essentially the same as in the Fig. 4 indicated power electronics. Therefore, reference is made to the previous description. In contrast to the Fig. 4 is in the Fig. 1, the flat connection element 23 (i.e., the leadframe) is connected as a bent and / or stamped copper sheet directly to the top-side chip connection surface 17 of the semiconductor chip 3 with the interposition of a sintered layer 25 acting as a connecting layer. To reduce the mechanical stresses in the connecting layer 25, the semiconductor chip 3 and the connection element 23 are integrated in a sandwich structure. In the sandwich structure, a layer system 27 is applied to the top side of the connection element 23, which counteracts excessive thermal expansion of the connection element 23.

[0024] The shift system 27 is in the Fig. 1 is designed as a double-layer system with two compensation layers, namely with a compensation semiconductor chip 29 and a sintered layer 31. The compensation semiconductor chip 29 is constructed identically to the semiconductor chip 3, but is electrically non-functional. For example, the compensation semiconductor chip 29 can be a semiconductor chip 3 that has been sorted out as chip material waste. In the manufacture of the Fig. In the sandwich structure shown in Figure 3, the sintered layer 31 is first pre-applied as a metal paste layer onto the compensating semiconductor chip 29. Subsequently, in a sintering process, the compensating semiconductor chip 29 is sintered onto the top side of the connecting element 23 with the sintered layer 31 interposed.

[0025] In the Fig. 1, the sandwich structure therefore has an identical double-layer structure on both sides of the connection element 23; that is, on the one hand, the semiconductor chip 3 with the sintered layer 7 on the underside of the connection element 23, and on the other hand, the compensating semiconductor chip 29 with the sintered layer 31 on the top side of the connection element.

[0026] In the Fig. 2 is in a view corresponding to the Fig. 1 shows a further comparative example not covered by the invention, in which the layer system 27 has exactly one compensating layer. The compensating layer is formed as a sintered layer 33 filled with filler, such as metal particles. Fig. Figure 3 is a comparative example not covered by the invention in a view corresponding to Fig. 1, in which the layer system 27 is also - as in the Fig.1 - has a double-layer structure, namely with a foil or sheet metal blank 35 and a sintered layer 37.

[0027] The sintered layers 7, 31, 33, 37 can each be made of a metal paste, in particular a copper paste, in which metal particles are coated with a solvent, such as alcohol. During the sintering process, the solvent is evaporated under the influence of heat, causing atoms of the metal particles to diffuse into the joining partners, creating a bond between the joining partners. List of reference symbols 1 power module 3 semiconductor chip 5 Casting compound 7 Sintered layer 9 Substrat 11 middle ceramic layer 13 aluminum layer 15 aluminum bonding wires 17 top chip connection area 19 Wire end 21 Contact point 23 flat connection element or leadframe 25 Connection layer 27 shift system 29 Compensation semiconductor chip 31 sintered layer 33 sintered layer 35 Foil or sheet metal cutting 37 Sinter view

Claims

[1] Power electronics for a pulse-controlled inverter, comprising at least one power module (1) with a semiconductor chip (3) which is soldered or sintered on its underside via a sintered or soldered layer (7) on a substrate (9), wherein the semiconductor chip (3) has an electrical connection surface (17) on its upper side, to which a connection element (23) is connected via a connecting layer (25), and wherein, during power electronics operation, a mechanical stress is generated in the connecting layer (25) due to the thermal expansion coefficient of the connection element (23) being greater than the thermal expansion coefficient of the semiconductor chip (3), wherein, in order to reduce the mechanical stress in the connecting layer (25), the semiconductor chip (3) and the connection element (23) are components of a sandwich structure in which a layer system (27) comprising at least one compensating layer is applied to the upper side of the connection element (23),which counteracts thermal expansion of the connecting element (23), , characterized by that the layer system (27) is a double-layer system in which a compensating semiconductor chip (29) which is identical in construction to the semiconductor chip (3) and has no electrical function, and a sintered layer (31) are provided as compensating layers, so that an identical double-layer structure is formed on both sides of the connection element (23). [2] Power electronics according to claim 1, characterized by that the material of the compensating layer has a low coefficient of thermal expansion of in particular 3 to 14 ppm / K. [3] Power electronics according to claim 1 or 2, characterized by that during the production of the sandwich structure, the sintered layer (31) can be pre-applied to the compensating semiconductor chip (29), and then, in a sintering process, the compensating semiconductor chip (29) can be sintered onto the top side of the connecting element (23) with the sintered layer (31) interposed. [4] Power electronics according to one of the preceding claims, characterized by that the sintered layer (7, 25, 31) is made of a metal paste, in particular copper paste, in which metal particles are coated with a solvent, for example alcohol, and that in particular in the sintering process the solvent evaporates due to the action of heat and atoms of the metal particles diffuse into the at least one joining partner to produce a material-locking connection. [5] Power electronics according to one of the preceding claims, characterized by that the substrate (9) is a copper or aluminum-based substrate, and / or that the substrate (9) has a three-layer structure comprising a middle ceramic layer (11) which has a metallization (13) on both sides, in particular an aluminum or copper layer. [6] Method for producing a power module for power electronics according to one of the preceding claims.

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