Semiconductor chip and method for manufacturing it

Abstract

The application relates to a semiconductor chip comprising a semiconductor body; an insulating layer on a first side of the semiconductor body; an inorganic passivation layer system on the insulating layer; wherein the inorganic passivation layer system has an outer lateral edge in an edge termination region arranged on a lateral edge of the semiconductor body, wherein, viewed in a vertical cross-section perpendicular to the lateral edge of the semiconductor body, at least one opening is provided in the insulating layer in the edge termination region.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor chip comprising a semiconductor body. BACKGROUND

[0002] In embodiments of this application, the semiconductor body is made of silicon carbide (SiC), which has a comparatively wide bandgap, e.g., compared to silicon. This can be of interest, for example, for power semiconductor devices in high-voltage and / or high-current applications. A device structure with a load terminal or terminals, such as a transistor structure with a source terminal and a drain terminal, can be formed within the semiconductor body. A metallization can be formed on the semiconductor body for wiring and contacting the device structure. SUMMARY

[0003] Examples of the present application are directed to an advantageous semiconductor chip.

[0004] In one embodiment, a semiconductor chip comprises a semiconductor body, an insulating layer on a first side of the semiconductor body, and an inorganic passivation layer system on the insulating layer. The inorganic passivation layer system has an outer lateral edge in an edge termination region located at a lateral edge of the semiconductor body. In a vertical cross-section perpendicular to the lateral edge of the semiconductor body, at least one opening may be provided in the insulating layer in the edge termination region.

[0005] The opening in the insulating layer, i.e., a structuring of the insulating layer, can, for example, provide a defined location to limit or slow inward crack propagation, such as by improving adhesion or by providing a defined crack release point. Such crack propagation from the edge termination region toward the active region could result, for example, from increased mechanical stress at the lateral edge of the chip and / or from oxidation processes. Considering, for example, a semiconductor body made of silicon carbide, SiC oxidation could be triggered or driven by moisture and electric fields in this region, with the oxidation potentially leading to delamination at interfaces and inducing inward-propagating cracks.However, such crack induction and propagation can also occur in Si technologies, for example due to geometric reasons (e.g., large chip area).

[0006] Further embodiments and features are provided in the claims and throughout the entire disclosure. The individual features are to be disclosed independently of any specific claim category; the disclosure relates to device and apparatus aspects, but also to process and use aspects. For example, if a chip is described that is manufactured in a specific way, this also constitutes a disclosure of that manufacturing process, and vice versa. In general terms, one approach of this application is to provide an insulating layer arranged on the semiconductor body with a structuring and / or mechanical interlocking in an edge termination region.

[0007] The edge termination region is located between the lateral edge of the semiconductor body and an active region of the chip. Within the active region, a device structure can be formed within the semiconductor body, for example, a transistor device structure. Generally, when discussing elements in terms of their relative position, these elements are located, for example, on the same side of the active region, i.e., at the same lateral edge of the semiconductor body ("outward" means, for example, closer to / toward the respective lateral edge, and "inward" means closer to / toward the active region). Similar structures can be located at the other lateral edges of the semiconductor body, for example, collectively enclosing the active region when viewed from a top view.

[0008] As viewed in the plane of section, the opening can completely intersect the insulating layer in a vertical direction; laterally, it is defined between sections of the insulating layer. Regarding its shape perpendicular to the plane of section, i.e., in a lateral direction parallel to the lateral edge of the chip, the opening can also be defined laterally within the insulating layer (be a "hole") or have a fairly elongated lateral extension, as detailed below. Generally, when referring to the "plane of section," this refers to a vertical cross-section perpendicular to the lateral edge of the semiconductor body.

[0009] The insulating layer can, for example, comprise one or multiple oxide layers. Specifically, it can comprise an undoped oxide layer, such as a TEOS layer, which in the exemplary embodiment is referred to as the "second oxide layer." Additionally, it can comprise a doped oxide layer, such as a BPSG layer, which in the exemplary embodiment is referred to as the "third oxide layer." Optionally, it can comprise an additional oxide layer, for example, beneath the second and third oxide layers, which in the exemplary embodiment is referred to as the "first oxide layer." The first oxide layer, if present, can, for example, be a gate oxide layer, with the same layer forming, for example, a gate dielectric in the active region.

[0010] For example, the third oxide layer can have a thickness of at least 0.2 µm, e.g., at least 0.4 µm, and / or at most 2 µm, e.g., at most 1.2 µm. The second oxide layer can have a thickness of at least 0.1 µm, e.g., at least 0.15 µm, and / or at most 0.8 µm, e.g., at most 0.6 µm. The first oxide layer, if present, can have a thickness of at least 30 nm, 50 nm, 70 nm, or 80 nm, with possible upper limits being, for example, at most 250 nm, 200 nm, or 150 nm.

[0011] In general, any type of semiconductor can be used for the semiconductor body, e.g., silicon (Si) or silicon carbide (SiC), with the semiconductor body being, for example, a SiC semiconductor body. Regardless of whether it is made of Si or SiC, the semiconductor body can comprise a semiconductor substrate, for example, in combination with one or more epitaxial semiconductor layers on it. The side of a top epitaxial layer facing away from the substrate can be the "first side" of the semiconductor body. Conversely, the side of the substrate facing away from the epitaxial layer(s) can be the "second side" of the semiconductor body.

[0012] The inorganic passivation layer system can, for example, comprise a silicon nitride layer. Optionally, it can additionally comprise a silicon oxide layer. The silicon nitride layer can be arranged below or on top of the silicon oxide layer. In one embodiment, the silicon oxide layer is arranged on top of a first silicon nitride layer, with a second silicon nitride layer arranged on top of the silicon oxide layer, wherein the silicon oxide layer is, for example, arranged directly on top of the first silicon nitride layer and / or the second silicon nitride layer is arranged directly on top of the silicon oxide layer. The first silicon nitride layer can, for example, be thinner than the silicon oxide layer and / or the second silicon nitride layer. Regardless of these geometric details, the silicon oxide layer can, for example, be an undoped silicon oxide layer, e.g., undoped silicon glass (USG).

[0013] Regardless of the subsequent layer stack or materials in detail, the bottommost layer of the inorganic passivation system can be a silicon nitride layer, e.g., the first silicon nitride layer in the terminology above. This bottommost layer, e.g., the silicon nitride layer, of the inorganic passivation system can be located, for example, in the edge region in an area where no metallization is applied to the insulating layer, directly on the insulating layer, or with an additional layer in between. In other words, an additional layer, e.g., an aluminum oxide layer, can be placed between the inorganic passivation system and the insulating layer. For example, only the aluminum oxide layer can be placed between the inorganic passivation system and the first face of the SiC semiconductor body. The additional layer can, for example, serve as an adhesion promoter and / or an etch stop layer.For example, it can have a thickness of no more than 30 nm, 20 nm, or 15 nm, with possible lower limits being, for example, 3 nm or 5 nm. In other words, an arrangement "on" can mean a certain distance, e.g., a relatively small distance of no more than 100 nm, 50 nm, 30 nm, 20 nm, or 15 nm, or an arrangement "directly on." In other words, arranged "on" can also mean arranged "over" or "above."

[0014] In one embodiment, the inorganic passivation layer system extends over and into the at least one opening in the insulating layer. In other words, the inorganic passivation layer system can extend further outward than the insulating layer. As viewed in the sectional plane, an outer lateral edge of the inorganic passivation layer system can be located on the semiconductor body, i.e., laterally between the outer lateral edge of the semiconductor body and an outer lateral edge of the insulating layer. Regardless of its precise lateral extension, the lateral undercut between the inorganic passivation layer system and the insulating layer can provide mechanical interlocking, e.g., reducing the risk of lift-off. The lateral undercut, i.e.,Lateral interlocking can be formed with respect to a lateral direction perpendicular to the lateral edge of the semiconductor body (“lateral inward direction”). Considering an inorganic passivation layer system comprising multiple layers (see above), at least one bottommost layer can extend into the opening (depending on the opening width, the layer or layers above it may also extend into the opening).

[0015] In general, the at least one opening can be a single opening in the insulating layer or it can comprise a plurality of openings, i.e., at least two openings, as viewed in the section plane. In one embodiment, the opening or openings comprise a first opening which, as viewed in the section plane, is defined laterally between a first section and a second section of the insulating layer. In this embodiment, the first section is located further outward than the second section and has a columnar shape. As seen in a vertical plan view, the first section having the columnar shape can have a round perimeter, e.g., elliptical or circular, but it can also have a polygonal perimeter, e.g., rectangular / square or hexagonal. Regardless of the shape in detail, the columnar first section, being located laterally outside, can reduce inward crack propagation, e.g.,thus providing a defined point for crack release and stress relief.

[0016] In one embodiment, the first section of the insulating layer has an average lateral extent of at most 50 µm, with further upper limits being, for example, at most 40 µm, 30 µm, 20 µm, or 10 µm. Possible lower limits can be at least 1 µm, 2 µm, or 3 µm. The average lateral extent can be taken as the mean of a minimum and a maximum lateral extent of the first section. These lateral extents can be taken, for example, along two lateral directions that form an angle with each other, e.g., along the first and / or the second lateral direction. With respect to a vertical position, the lateral extents can be taken at an upper surface of the insulating layer. In the case of a circular shape, the average lateral extent corresponds, for example, to the diameter of the circle.

[0017] In one embodiment, a plurality of first sections, each having, for example, a column-like shape, are arranged successively along a longitudinal direction parallel to the lateral edge of the semiconductor body. Each of these first sections may have a circumference and / or an averaged lateral extent, as discussed above. In addition to being arranged along the longitudinal direction, the first sections may generally have a lateral offset from one another perpendicular to the lateral edge (they are not necessarily arranged on a common straight line parallel to the lateral edge of the semiconductor body). Alternatively, however, the first sections may be arranged on a common straight line parallel to the lateral edge.

[0018] In one embodiment, the opening or openings comprise a second opening which, as viewed in the plane of section, is defined laterally between a second and a third section of the insulating layer. In this embodiment, the second section is located closer to the lateral edge of the semiconductor body and has an elongated lateral extension. This lateral extension has at least one longitudinal directional component that is parallel to the lateral edge (see above). The second section, which has an elongated lateral extension and defines an opening located laterally within it, can be combined with a first section or sections located laterally outside it (the second section, as viewed in the plane of section, defines an opening both laterally inside and laterally outside).Regardless of these details, the second section, which has the elongated extension, can, for example, stop crack propagation, e.g., before a crack extends inwards to an electric field reduction structure, see below.

[0019] In one embodiment, the second section, as seen in a vertical top view, has a wave-like extension. Along the longitudinal direction, the second section can extend both towards and away from the lateral edge of the semiconductor body, i.e., it can have a varying distance from the lateral edge. It can extend repeatedly towards and away from the lateral edge, for example, in a regular repeating pattern. In general, the varying distance of the second section from the lateral edge can be realized with any waveform, e.g., a rectangular or triangular (e.g., sawtooth) pattern. In one embodiment, however, the wave has a sinusoidal shape.

[0020] In one embodiment, the opening or openings, as viewed in the plane of section, comprise a third opening, which is provided as a hole embedded laterally in the insulating layer. In other words, the insulating layer defines the hole laterally in all lateral directions. Viewed from a vertical top view, the hole may, for example, have a circular perimeter, such as elliptical or circular, or a polygonal perimeter, such as a rectangular / square or hexagonal shape. Considering the lateral extent of the hole, it may, for example, have a minimum lateral extent that is no more than 50% smaller than its maximum lateral extent (the lateral extents each taken at a top surface of the insulating layer).

[0021] In one embodiment, the hole has an average lateral extent of at most 50 µm, with further upper limits being, for example, at most 40 µm, 30 µm, 20 µm, or 10 µm. Possible lower limits could be, for example, 1 µm, 2 µm, or 3 µm. The average lateral extent can be taken as the average of the smallest and largest lateral extents of the hole (the lateral extents taken at the upper surface of the insulating layer), which corresponds, for example, to a diameter in the case of a circular shape.

[0022] In one embodiment, a plurality of holes are arranged consecutively along the longitudinal direction parallel to the lateral edge of the semiconductor body. Each hole is laterally embedded in the insulating layer, with reference to the preceding paragraphs regarding possible details concerning the size, shape, or size ratio of each hole. In addition to being arranged consecutively along the longitudinal direction, the holes may be offset perpendicular to the lateral edge of the semiconductor body; alternatively, they may be arranged on a common straight line parallel to the lateral edge.

[0023] In a lateral direction inwards, i.e., from the lateral edge towards the active area, the hole can be located laterally inside the first opening(s) and / or second opening(s). Specifically, the first section(s) can be located laterally outside, and the hole(s) can be located laterally inside, for example, in combination with the second section (elongated lateral extension) located laterally between them. In other words, as viewed in the plane of section, a sequence from the lateral edge to the active area can be: first section, first opening, second section, second opening, third section, third opening (hole). The multitude of holes arranged consecutively in the longitudinal direction can be the innermost holes, i.e.,Openings in the insulating layer can be located in the edge termination area (outside the active area), or alternatively, an additional row with a large number of holes can be arranged laterally inside (but still in the edge termination area).

[0024] Regardless of these details, the hole(s) in the insulating layer can improve the adhesion of the inorganic passivation layer system, e.g., by providing mechanical interlocking and reducing the risk of lift-off. In other words, the structures laterally outside can reduce or stop inward crack propagation, while the hole(s) reduce or prevent lift-off. The inorganic passivation layer system may have an outer lateral edge on the third section, e.g., extending only over and into the hole(s), with the second and / or first section(s) of the insulating layer not covered by the inorganic passivation layer system. Nevertheless, the first and second sections may be defined sites for crack release (and thus stress relief) and / or crack stopping, for example, in the case of oxidation on the first side of the semiconductor body (e.g.,Silicon carbide oxidation).

[0025] Alternatively, the inorganic passivation layer system can extend over and into all openings, with an outer lateral edge of the inorganic passivation layer system located on the first side of the semiconductor body, e.g., further outward than the first section(s). In other words, all sections defined in the insulating layer by the opening(s) can be covered by the inorganic passivation layer system. As viewed in a cross-sectional plane, an outer lateral edge or end of the inorganic passivation layer system can be spaced at least 5 µm from an outermost section of the insulating layer (e.g., the first section), with further lower limits being, for example, at least 10 µm or 20 µm (upper limits depend, for example, on the chip size, with possible values ​​being, for example, 0.8 mm, 0.5 mm, or 0.3 mm).In detail, this distance in the section plane can be taken as a lateral distance between the outer lateral edge of the inorganic passivation layer system and an outer lateral end of the insulating layer, e.g. the outer lateral end of the first section.

[0026] Laterally between the at least one opening and the active region, e.g., as viewed in the section plane, an electric field reduction structure can be arranged within the semiconductor body, configured to lower or reduce an electric field inwards, i.e., towards the active region. The electric field can, for example, extend upwards from the back side to the first side at the lateral edge of the semiconductor body. The electric field reduction structure can, for example, have a doping concentration that decreases at least integrally towards the lateral edge of the semiconductor body, e.g., comprising a doping well in which a plurality of laterally offset doped rings are embedded (rings doped in reverse relative to the well).

[0027] In one embodiment, the opening or openings comprise an innermost opening which, as viewed in the plane of section, is located at least 20 µm outside an electric field reduction structure formed in the semiconductor body. In detail, the distance can be taken as the smallest lateral distance in the plane of section, i.e., between an inner lateral end of the innermost opening in a top surface of the insulating layer and an outer lateral end of the field reduction structure in the first side of the semiconductor body. For example, considering a field reduction structure comprising a doped well in which a plurality of reverse-doped rings are embedded, the distance can be taken from an outer lateral end of the well.Regardless of these details, further lower limits can be, for example, at least 30 µm, 40 µm or 50 µm (upper limits can be chosen depending on the chip size, with possible values ​​being, for example, 0.8 mm, 0.5 mm or 0.3 mm).

[0028] In one embodiment, an outer lateral edge of the inorganic passivation layer system is arranged on the semiconductor body, with the inorganic passivation layer system extending further outward than the insulating layer. The arrangement "on" is to be read as "over" or "across," see the description above for further details (for example, an aluminum oxide layer may be arranged between them). Notwithstanding these details, at least one opening may be provided in the semiconductor body, viewed in the vertical cross-section perpendicular to the lateral edge of the semiconductor body, the opening in the semiconductor body being, for example, arranged laterally within the outer lateral edge of the inorganic passivation layer system. In other words, the inorganic passivation layer system may extend over and into the opening in the semiconductor body, i.e.,a lateral undercut (lateral interlock) with the semiconductor body is formed. This can, for example, reduce the risk of the inorganic passivation layer system lifting off, e.g., by improving adhesion to the semiconductor body.

[0029] The hole in the semiconductor body, into which the inorganic passivation layer system extends, can be combined with the opening(s) in the insulating layer or be an alternative to them. This embodiment will also be disclosed independently of the insulating layer, which is provided with an opening(s); in detail, it will be disclosed as follows: Semiconductor chip comprising: a semiconductor body; an inorganic passivation layer system; wherein the inorganic passivation layer system has an outer lateral edge on a first side of the semiconductor body in an edge termination region (outside and active region at a lateral edge of the semiconductor body), and wherein, viewed in a vertical cross-section perpendicular to the lateral edge of the semiconductor body, an opening is provided in the semiconductor body laterally within the outer lateral edge of the inorganic passivation layer system, wherein the inorganic passivation layer system extends over and into the opening in the semiconductor body and forms a lateral undercut with the semiconductor body.

[0030] In one embodiment, the opening in the semiconductor body is a trench with an elongated lateral extension. The trench can have its elongated extension in a longitudinal direction parallel to the lateral edge of the semiconductor body. Viewed from a vertical top view, the trench can extend alongside the active region, e.g., circumferentially around the active region, for example, forming a closed line over its entire circumference. Regardless of these details, the trench can act as a trap for ions that might melt along interfaces, for example. In other words, in addition to mechanical interlocking, the opening or trench in the semiconductor body can reduce ion contamination.

[0031] When considering a field reduction structure formed within the semiconductor body (see above), the opening in the semiconductor body can, for example, be located laterally outside of it. When combined with the structured insulating layer, the opening in the semiconductor body can be located laterally outside an outermost section of the insulating layer, e.g., laterally outside the first section or sections.

[0032] In one embodiment, a method for manufacturing a semiconductor chip comprises: forming an insulating layer with an opening, wherein the opening is arranged laterally outside an active region in an edge termination region. Specifically, the opening or openings can be formed by etching a corresponding pattern into the previously deposited insulating layer. For further manufacturing details, reference is made to the above description and the entire disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The semiconductor chip and the manufacturing process are explained in more detail below using exemplary embodiments. The individual features may also be relevant in other combinations. Fig. Figure 1 shows a cross-sectional view of a semiconductor chip comprising a SiC semiconductor body, an insulating layer and an inorganic passivation layer system; Fig. Figure 2a shows a more detailed view of an insulating layer and an inorganic passivation layer system on a semiconductor body; Fig. 2b illustrates the insulating layer of Fig. 2a in an oblique view; Fig. Figure 2c shows the insulating layer in a vertical top view; Fig. Figure 3 shows a schematic cross-section of a device formed in an active region of the semiconductor chip; Fig. 4a illustrates another embodiment of a structured insulating layer in a vertical top view; Fig. Figure 4b shows an alternative embodiment in a vertical top view; Fig. Figure 5 shows a vertical cross-section through a semiconductor body with an opening into which the inorganic passivation layer system extends; Fig. Section 6 summarizes some of the manufacturing steps in a flowchart. DETAILED DESCRIPTION

[0034] Fig. Figure 1 shows a section of a semiconductor chip 1 in a vertical cross-section. The semiconductor chip 1 comprises a semiconductor body 10, which in the example shown is a silicon carbide (SiC) semiconductor body 11. An insulating layer 90 is arranged on a first side 10.1 of the semiconductor body 10. Furthermore, a metallization 30 is formed on the semiconductor body 10, which comprises a barrier layer system 130. A copper layer system 230 is arranged on the barrier layer system 130, which in the example shown comprises a sputter-deposited copper layer 231 and a bath-deposited copper layer system 235 with a first bath-deposited copper layer 235a and a second bath-deposited copper layer 235b.

[0035] In detail, the cross-sectional view of Fig. 1 at a lateral edge 1.1 of the chip 1, wherein an edge termination region 1b is located laterally between the lateral edge 1.1 of the chip 1 and a Fig. The active region 1a shown on the right is arranged in the active region 1a. Transistor device cells can be arranged in the active region 1a (see below for details). Furthermore, a load pad 31 can be formed in the metallization 30, for example, a source pad connected to a source terminal of the device or device cells. In the edge termination region 1b, a gate runner 32 and / or a source runner 33, each extending along the active region 1a, can be formed in the metallization 30.

[0036] An inorganic passivation layer system 45 is arranged on the metallization 30. The inorganic passivation layer system 45 shown comprises a first silicon nitride layer 45.1, an undoped silicon oxide layer 45.2 directly on the first silicon nitride layer 45.1, and a second silicon nitride layer 45.3 directly on the undoped silicon oxide layer 45.2.

[0037] Fig. Figure 2a shows a more detailed view of the inorganic passivation layer system 45, which is arranged on the insulating layer 90, i.e., in a vertical cross-section perpendicular to the lateral edge 10.i of the semiconductor body 10. In the edge termination region 1b, at least one opening 100 is provided in the insulating layer, with two openings 100 shown in the sectional view of Fig. 2a are visible and a further opening 100, which lies behind the drawing plane, is indicated in dashed lines.

[0038] In the Fig. In the example shown in Figure 2a, the inorganic passivation layer system 45 has its outer lateral edge 45.i on the semiconductor body 10, i.e., it extends further outwards than the insulating layer 90. Consequently, the inorganic passivation layer system 45 extends over and into each of the openings 100, forming a lateral undercut with the insulating layer 90 in each case.

[0039] In the Fig. In the sectional view shown in Figure 2a, the openings 100 comprise a first opening 101, which is defined laterally between a first section 90.1 and a second section 90.2 of the insulating layer 90. Furthermore, a second opening 102 is arranged laterally within the first opening 101, defined laterally between the second section 90.2 and a third section 90.3 of the insulating layer 90. In the sectional view of Fig. 2a the third section 90.3 extends continuously, with a third opening 103 arranged behind the drawing plane and enclosed laterally in this third section 90.3.

[0040] Fig. Figure 2b shows the insulating layer 90 in an oblique view and illustrates the extent and arrangement of sections 90.1-90.3 in a longitudinal direction 201 (perpendicular to the drawing plane of Fig. 2a). The longitudinal direction 201 is parallel to the lateral edge 10.i of the semiconductor body 10. A lateral inward direction 202 is perpendicular to the lateral edge 10.i of the semiconductor body 10 and points towards the active region (not shown here), and a vertical direction 200 is perpendicular to the longitudinal direction 201 and to the lateral inward direction 202 and points downwards.

[0041] The first section 90.1 has a column-like shape, e.g., essentially the same lateral extent in the longitudinal direction 201 and in the lateral inward direction 202. A plurality of first sections 90.1, each having a column-like shape, are arranged in a row along the longitudinal direction 201. The second section 90.2, as in Fig. As shown in Figure 2b, the third opening 103 has an elongated lateral extension in the longitudinal direction 201. It extends in a wave-like shape, i.e., in a sinusoidal shape in the example shown. Further inward, the third opening 103 is arranged, which is designed as a hole 203 embedded laterally in the third section 90.3. A plurality of holes 203 are arranged in series within this hole, i.e., consecutively along the longitudinal direction 201.

[0042] Fig. Figure 2c illustrates the structured insulating layer 90 in a vertical plan view. In the example shown, the first sections 90.1 have a circular shape, i.e., a circular circumference. The averaged lateral extent of each of the first sections 90.1, i.e., a diameter in the example shown, is approximately 3 µm. The second section 90.2 has a width of approximately 3 µm in the lateral inward direction 202, with a waveform amplitude of approximately 0.5 µm, such that the distance from the lateral edge 10.i of the semiconductor body 10 varies by approximately 1 µm. The distance between the second section 90.2 and the third section 90.3, i.e., the width of the second opening 102, is also approximately 3 µm, as is the diameter of the holes 203. Of course, other values ​​are also possible; see the description above for different intervals / ranges.

[0043] Fig. Figure 3 illustrates a possible device 200 and device structure 20 formed in the active area 1a of the chip 1, e.g. under the load pad 31 (see Fig. (1 for comparison). In the semiconductor 10, e.g., SiC semiconductor body 11, a load terminal 21 is formed on the first side 10.1, which in the example shown is a source region 22. On the vertically opposite second side 10.2, a drain region 27 is arranged, with a body region 23 arranged below the source region 22 and a drift region 24 arranged between the body region 23 and the drain region 27.

[0044] A gate region 25, comprising a gate electrode 25.1 and a gate dielectric 25.2 that capacitively couples the gate electrode 25.1 to the body region 23, is arranged in a trench 26. A voltage applied to the gate electrode 25.1 can control channel formation in the body region 23 and consequently a current flow between the source region 22 and the drain region 25. The device 200 can comprise a plurality of device cells 201 connected in parallel.

[0045] How Fig. 2c illustrates Fig. 4a a structured insulating layer 90 in a vertical plan view. In general, in this disclosure, the same reference numerals denote the same elements or elements with the same function, and reference is also made to the description of the other figures. As in the embodiment of Fig. 2c are first sections 90.1, which have a column-like shape, formed in the insulating layer 90. In contrast to the embodiment discussed above, the first sections 90.1, as in Fig. Figure 4a illustrates a polygonal perimeter, i.e. a hexagonal perimeter in the embodiment shown.

[0046] Fig. Figure 4b also shows a structured insulating layer 90 with a polygonal / hexagonal structure, wherein a plurality of third openings 103 / holes 203 with a corresponding polygonal / hexagonal shape are provided. The holes 203 are arranged in a row along the longitudinal direction 201, with a second row of holes 303 provided laterally within it. Of course, the embodiments of Fig. 4a and Fig. 4b can also be combined, with columns of a polygonal / hexagonal shape arranged laterally outside and holes of a polygonal / hexagonal shape arranged laterally inside.

[0047] Fig. Figure 5 illustrates a semiconductor body 10 with an insulating layer 90 and an inorganic passivation layer system 45 in a sectional view, which is illustrated with Fig. 2a is comparable. Additionally, an opening 15 is provided in the semiconductor body 10 laterally outside the insulating layer 90. In detail, the opening 15 is arranged laterally between the outer lateral edge 45.i of the inorganic passivation layer system 45 and an outer lateral edge 90.i of the insulating layer 90. The inorganic passivation layer system 45 extends over and into the opening 15, i.e., it forms a lateral undercut with the semiconductor body 10.

[0048] In the example shown, the opening 15 is a trench 16 etched into the semiconductor body 10. Perpendicular to the plane of the drawing, the trench 16 has an elongated extent, i.e., parallel to the longitudinal direction 201. An inner side wall 16.1 of the trench 16 is covered by an oxide layer 370, and the remaining trench is filled with the inorganic passivation layer system 45.

[0049] Fig. Figure 5 also illustrates an electric field reduction structure 360 ​​formed in the semiconductor body 10. It is arranged laterally within the trench 16 and also within the openings 100 provided in the insulating layer 90 (although they are in Fig. (2a is not shown, it could also be provided there).

[0050] Fig.Figure 6 illustrates some manufacturing steps in a flowchart. Forming the insulating layer with the opening can include depositing the insulating layer onto the semiconductor body. Subsequently, the opening is etched into the insulating layer, for example, after forming a corresponding mask on the insulating layer.

Claims

[1] Semiconductor chip, comprising a semiconductor body; an insulating layer on one side of the semiconductor body; an inorganic passivation layer system on the insulating layer; wherein the inorganic passivation layer system has an outer lateral edge in an edge termination region which is arranged at a lateral edge of the semiconductor body, wherein, in a vertical cross-section perpendicular to the lateral edge of the semiconductor body, at least one opening is provided in the insulating layer in the edge termination region. [2] Semiconductor chip according to claim 1, wherein the inorganic passivation layer system (45), viewed in the vertical cross-section, extends over and into the at least one opening and forms a lateral undercut with the insulating layer. [3] Semiconductor chip according to claim 1 or 2, wherein the at least one opening is or comprises a first opening which, viewed in the vertical cross-section, is defined laterally between a first section and a second section of the insulating layer, wherein the first section is arranged further outwards than the second section and has a column-like shape. [4] Semiconductor chip according to claim 3, wherein the first section has an average lateral extent of at most 50 µm and / or, viewed in a vertical plan view, has a round or polygonal shape. [5] Semiconductor chip according to claim 3 or 4, wherein a plurality of first sections, each having a column-like shape, are arranged successively along a longitudinal direction (201) which is parallel to the lateral edge of the semiconductor body (10). [6] Semiconductor chip according to one of the preceding claims, wherein the at least one opening is or comprises a second opening which, viewed in the vertical cross-section, is defined laterally between a second section and a third section of the insulating layer, wherein the second section is arranged further outwards than the third section and has an elongated lateral extension. [7] Semiconductor chip according to claim 6, wherein the second section, viewed in a vertical plan view, has a wave-like extension. [8] Semiconductor chip according to one of the preceding claims, wherein the at least one opening is or comprises a third opening which is provided as a hole embedded laterally in the insulating layer. [9] Semiconductor chip according to claim 8, wherein the hole has an average lateral extent of not more than 50 µm and / or, viewed in a vertical plan view, has a round or polygonal shape. [10] Semiconductor chip according to claim 8 or 9, wherein a plurality of holes, each embedded laterally in the insulating layer, are arranged successively along a longitudinal direction that is parallel to the lateral edge of the semiconductor body. [11] Semiconductor chip according to one of the preceding claims, wherein, viewed in the vertical cross-section, an innermost at least one opening in the insulating layer is arranged at least 20 µm outside an electric field reduction structure formed in the semiconductor body. [12] Semiconductor chip according to one of the preceding claims, wherein the outer lateral edge (45.i) of the inorganic passivation layer system is arranged on the semiconductor body, wherein, viewed in the vertical cross-section perpendicular to the lateral edge of the semiconductor body, an opening is provided in the semiconductor body laterally within the outer lateral edge of the inorganic passivation layer system, wherein the inorganic passivation layer system extends over and into the opening in the semiconductor body and forms a lateral undercut with the semiconductor body. [13] Semiconductor chip according to claim 12, wherein the opening in the semiconductor body is a trench with an elongated lateral extent. [14] Method for manufacturing the semiconductor chip according to any one of the preceding claims, comprising: - Forming the insulating layer with at least one opening. [15] The method of claim 14, comprising: - Deposition of the insulating layer; - Etching at least one opening in the insulating layer.

Images