Silicon carbide semiconductor component with a buffer layer and manufacturing method

Abstract

A silicon carbide, SiC, semiconductor component (100) is proposed. The SiC semiconductor component (100) has a buffer layer (102) of a first conductivity type. The SiC semiconductor component (100) further has a drift layer (104) of the first conductivity type arranged along a vertical direction (y) on the buffer layer (102). A vertical profile of a dopant concentration (c) of the buffer layer (102) has at least a first valley section (1021), a first plateau section (1023), and a first transition section (1022) extending from the first valley section (1021) to the first plateau section (1023). The dopant concentration (c) of each of the first valley section (1021) and the first plateau section (1023) varies by less than 20%. A vertical extension (vt1) of the first transition section (1022) ranges from 1% to 30% of a vertical extension (vv1) of the first valley section (1021).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a silicon carbide, SiC, semiconductor device, in particular a SiC semiconductor device with a buffer layer. BACKGROUND

[0002] The technological development of new generations of SiC semiconductor devices, e.g., insulated-gate field-effect transistors (IGFETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), aims to improve electrical device properties and reduce costs by shrinking device geometries. Exemplary semiconductor devices are known from the publications DE 10 2015 208 097 A1, JP 2017 - 19 679 A, ​​DE 10 2018 132 236 A1, and DE 11 2019 006 020 T5. Although costs can be reduced by shrinking device geometries, a variety of trade-offs and challenges must be met when increasing device functionalities per unit area. For example, increasing the voltage blocking capability, e.g.,Drain-to-source breakdown voltage or collector-to-emitter breakdown voltage, are challenging given reliability limitations caused, for example, by process-related stress in deposited layers, which may depend, for example, on doping level and / or thickness of deposited layers.

[0003] There is a need to improve the trade-off between voltage blocking capability and reliability of SiC semiconductor devices. SUMMARY

[0004] The invention is defined in the independent claims. Further developments are the subject of the dependent claims. One example of the present disclosure relates to a semiconductor device comprising a SiC semiconductor body. The SiC semiconductor device comprises a buffer layer of a first conductivity type. The SiC semiconductor device further comprises a drift layer of the first conductivity type arranged along a vertical direction on the buffer layer. A vertical profile of a dopant concentration of the buffer layer comprises at least a first valley portion, a first plateau portion, and a first transition portion extending from the first valley portion to the first plateau portion. The dopant concentration of each of the first valley portion and the first plateau portion varies by less than 20%.A vertical extension of the first transition section ranges from 1% to 30% of a vertical extension of the first valley section.

[0005] Another example of the present disclosure relates to a method for manufacturing a SiC semiconductor device. The method comprises forming a buffer layer of a first conductivity type. The method further comprises forming a drift layer of the first conductivity type arranged along a vertical direction on the buffer layer. A vertical profile of a dopant concentration of the buffer layer comprises at least a first valley portion, a first plateau portion, and a first transition portion from the first valley portion to the first plateau portion. The dopant concentration of each of the first valley portion and the first plateau portion varies by less than 20%. A vertical extent of the first transition portion ranges from 1% to 30% of a vertical extent of the first valley portion.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various illustrated examples may be combined, provided they are not mutually exclusive. Fig. 1A schematically and exemplarily illustrates a cross-sectional view of a SiC semiconductor device with a drift layer on a buffer layer. Fig. 1B is a graph schematically and exemplarily illustrating a profile of a dopant concentration along a vertical direction of a portion of the buffer layer of Fig. 1A. Fig. 2 and Fig. 3 are graphs illustrating further exemplary profiles of a dopant concentration along the vertical direction of a portion of the buffer layer of Fig. 1A. Fig. 4 is a schematic cross-sectional view showing a configuration example of a SiC semiconductor device having a drift layer on a buffer layer. Fig. 5 is an exemplary process diagram for manufacturing a SiC semiconductor device. DETAILED DESCRIPTION

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which semiconductor substrates may be processed. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features shown or described for one example may be used on or in conjunction with other examples to provide yet another example. It is intended that the present disclosure include such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for purposes of illustration only.Corresponding elements are designated by the same reference numerals in the various drawings unless otherwise indicated.

[0009] The terms "comprising," "containing," "include," "comprise," and the like are open-ended, and the terms indicate the presence of the specified structures, elements, or features, but do not preclude the presence of additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0010] The term "electrically connected" may describe a permanent low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrically coupled" may imply that one or more intermediate elements configured for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0011] When two elements A and B are combined using "or," this should be understood to reveal all possible combinations, i.e., only A, only B, and both A and B, unless explicitly or implicitly defined otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B." The same applies, mutatis mutandis, to combinations of more than two elements.

[0012] Ranges specified for physical dimensions include the limits. For example, a range for a parameter y from a to b is a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least."

[0013] The main components of a layer or structure made of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0014] The term "on" should not be interpreted to mean only "directly on." Rather, when an element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0015] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples given herein are expressly intended primarily for illustrative purposes only. to assist the reader in understanding the principles of revelation and the concepts contributed to All statements herein that list principles, aspects, and examples of Revelation, as well as specific examples thereof, are intended Equivalents thereof include.

[0016] A configuration example of a silicon carbide, SiC, semiconductor device includes a buffer layer of a first conductivity type.

[0017] The SiC semiconductor device further comprises a drift layer of the first conductivity type arranged along a vertical direction on the buffer layer.

[0018] A vertical profile of a dopant concentration of the buffer layer may include at least a first valley portion, a first plateau portion, and a first transition portion extending from the first valley portion to the first plateau portion. The dopant concentration of each of the first valley portion and the first plateau portion may vary by less than 20% or by less than 10%. A vertical extent of the first transition portion may range from 1% to 30%, or from 1% to 20%, or from 1% to 10% of a vertical extent of the first valley portion.

[0019] For example, p-type dopants in SiC may include Al, B, Be, Ga, or any combination thereof. For example, n-type dopants in SiC may include N, P, or any combination thereof. The first conductivity type may be n-type and the second conductivity type may be p-type, or alternatively, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0020] The SiC semiconductor device may, for example, be part of an integrated circuit or may be a discrete semiconductor device or a semiconductor module. The SiC semiconductor device may, for example, be or may comprise an insulated gate field-effect transistor (IGFET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET), or an insulated gate bipolar transistor (IGBT). The SiC semiconductor device may be a vertical semiconductor device with a load current flow between the first surface and a second surface opposite the first surface along a vertical direction. The vertical power semiconductor device may be configured to conduct currents of more than 1 A, or more than 10 A, or more than 30 A, or more than 50 A, or more than 75 A, or even more than 100 A, and may further be configured to conduct voltages between load electrodes, e.g.between the collector and emitter of an IGBT, or between the drain and source of a MOSFET, in the range of several hundred to several thousand volts, e.g., 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV, 12 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device. The SiC semiconductor device can be used, for example, in applications related to power transmission and distribution, automotive and transportation, renewable energy, consumer electronics, and other industrial applications.

[0021] The SiC semiconductor device may be based on a SiC semiconductor body made of a crystalline SiC material. The crystalline SiC material may, for example, have a hexagonal crystal lattice. For example, the semiconductor material may be 2H-SiC (2H polytype SiC), 6H-SiC, or 15R-SiC. According to one example, the semiconductor material is 4H polytype silicon carbide (4H-SiC). The SiC semiconductor body may comprise or consist of a semiconductor substrate having one or more semiconductor layers, e.g., epitaxially grown layers, thereon.

[0022] The drift layer may be arranged along the vertical direction between the buffer layer and a first surface of the SiC semiconductor body. The first surface may define a front surface or a top surface of the SiC semiconductor body. The buffer layer may be arranged along the vertical direction between the drift layer and a second surface of the SiC semiconductor body. The second surface may, for example, define a rear surface or a back surface of the SiC semiconductor body. The SiC semiconductor body may, for example, be attached to a lead frame via the second surface. For example, bond pads may be arranged over the first surface of the SiC semiconductor body, and bond wires may be bonded to the bond pads.

[0023] To achieve a desired current-carrying capacity, the SiC semiconductor component can be configured by a plurality of parallel-connected SiC semiconductor component cells. The parallel-connected SiC semiconductor component cells can, for example, be SiC semiconductor component cells formed in the shape of a strip or a strip segment. Of course, the SiC semiconductor component cells can also have any other shape, e.g., circular, elliptical, polygonal, such as hexagonal or octahedral. The semiconductor component cells can be arranged in a transistor cell region of the SiC semiconductor body. The transistor cell region can be a region in which an emitter region of an IGBT (or a source region of a MOSFET) and a collector region of an IGBT (or a drain region of a MOSFET) are arranged opposite each other along a vertical direction.In the transistor cell region, a load current can enter or leave the SiC semiconductor body of the semiconductor device, e.g., via contact plugs or contact lines on the top surface of the mesa. The semiconductor device may further include an edge termination region, which may include a termination structure. In a blocking mode or in a reverse-biased mode of the SiC semiconductor device, the blocking voltage between the transistor cell region and a field-free region drops laterally across the termination structure. The termination structure may have a higher or slightly lower voltage blocking capability than the transistor cell region. The termination structure may, for example, include a junction termination extension (JTE) with or without variation in lateral doping (VLD), one or more laterally separated guard rings, or any combination thereof.

[0024] Unlike dopant concentration profiles formed by a plurality of overlapping ion implantation peak profiles, the dopant concentration profiles described herein can be approximated by a rectangular or square waveform. The vertical dimensions of the transition region between the valley and plateau sections can be smaller than the vertical dimensions of the corresponding valley and plateau sections.

[0025] The buffer layer described in the examples herein has regions of tensile and compressive stress, which, due to the counteraction of different stress directions, lead to a reduction in intrinsic stress. This can counteract the sliding of crystal defects and improve the trade-off between voltage-blocking capability and reliability of SiC semiconductor devices.

[0026] For example, the vertical extent of the first transition section may range from 1% to 30% or from 1% to 20% or from 1% to 10% of a vertical extent of the first plateau section.

[0027] For example, the dopant concentration of the first plateau section can be set from 1 × 0 17 cm -3 up to 1 × 10 19 cm -3 or of 1 × 10 18 cm -3 up to 1 × 10 19 cm -3 are sufficient.

[0028] For example, a dopant concentration of the first valley section of 1 × 10 16 cm -3 up to 1 × 10 18 cm -3 or of 1 × 10 17 cm -3 up to 1 × 10 18 cm -3 are sufficient.

[0029] For example, the vertical extent of the first plateau section and the vertical extent of the first valley section may be the same or differ by less than 20%.

[0030] For example, the vertical extent of the first valley section can range from 100 nm to 2 µm or from 200 nm to 1.5 µm.

[0031] For example, the buffer layer may further comprise an end portion adjacent to the drift layer. A dopant concentration profile of the end portion may continuously decrease toward the drift layer. In the drift layer, the dopant concentration may be constant along the vertical direction or may be constant in vertical segments thereof.

[0032] For example, the buffer layer may further include a second plateau portion and a second transition portion extending from the second plateau portion to the first valley portion. In some examples, additional plateau and / or valley portions may be present or included in the buffer layer. For example, a vertical extent of the second plateau portion and a vertical extent of the first plateau may be the same or differ by less than 20%.

[0033] For example, the dopant concentration of the second plateau section may vary by less than 20%. The vertical extent of the second transition section may range from 1% to 30%, or from 1% to 20%, or from 1% to 10% of the vertical extent of the first valley section.

[0034] For example, an average dopant concentration of the second plateau section and an average dopant concentration of the first plateau section may be the same or differ by less than 20% or by less than 10%.

[0035] For example, an average dopant concentration of the second plateau section may be a factor of 1.5 to 30 greater than an average dopant concentration of the first plateau section.

[0036] For example, a vertical extent of the second plateau section and a vertical extent of the first valley section may be the same or differ by less than 20% or by less than 10%.

[0037] For example, the buffer layer may further comprise a second valley portion and a third transition portion extending from the first plateau portion to the second valley portion. A dopant concentration of the second valley portion may vary by less than 20% or by less than 10%. A vertical extent of the third transition portion may range from 1% to 30%, or from 1% to 20%, or from 1% to 10% of a vertical extent of the second valley portion.

[0038] For example, an average dopant concentration of the second valley section and an average dopant concentration of the first valley section may differ by less than 20% or by less than 10%.

[0039] For example, an average dopant concentration of the first valley section may be a factor of 1.5 to 30 greater than an average dopant concentration of the second valley section.

[0040] For example, the vertical profile of a dopant concentration of the first valley portion, the first plateau portion, and the first transition portion may be an in-situ dopant concentration profile. An in-situ dopant concentration profile may enable increased vertical extensions of the valley and / or plateau portions compared to dopant concentration profiles formed by one or more ion implantations of dopants. Likewise, an in-situ dopant concentration profile may enable reduced vertical extensions of the transition portion compared to dopant concentration profiles formed by one or more ion implantations of dopants.Since broadening of dopant concentration profiles by diffusion is small in terms of the thermal budget during device formation in SiC compared to silicon, the above properties are even more pronounced and SiC regions defined by in-situ dopant concentration profiles and SiC regions defined by ion implantation profiles are substantially different with regard to the profile of incorporated dopants in the structure.

[0041] The above exemplary profile properties or combinations thereof can be combined to reduce intrinsic stress in the buffer layer due to counteracting different stress directions, thereby also counteracting the sliding of crystal defects and improving the trade-off between voltage blocking capability and reliability of SiC semiconductor devices.

[0042] Details relating to the structure or function or technical benefits of features described above with respect to a semiconductor device, such as a FET or IGBT, apply equally to the exemplary Methods described below. Processing the SiC semiconductor body may include one or more of the following: one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0043] It should be understood that the disclosure of multiple steps, processes, operations, steps, or functions disclosed in the specification or the claims should not be construed as being in the specific order unless explicitly or implicitly indicated otherwise, e.g., by terms such as "thereafter," for example, for technical reasons. Therefore, the disclosure of multiple steps or functions does not limit them to a particular order unless such steps or functions are not interchangeable for technical reasons. Further, in some examples, a single step, function, process, operation, or step may comprise or be broken down into multiple sub-steps, functions, processes, operations, or steps, respectively. Such sub-steps may be included and be part of the disclosure. Disclosure of this single step is not expressly excluded.

[0044] An example of a method for manufacturing a silicon carbide, SiC, semiconductor device includes forming a buffer layer of a first conductivity type. The method further comprises forming a drift layer of the first conductivity type arranged along a vertical direction on the buffer layer. A vertical profile of a dopant concentration of the buffer layer may include at least a first valley portion, a first plateau portion, and a first transition portion from the first valley portion to the first plateau portion. The dopant concentration of each of the first valley portion and the first plateau portion may vary by less than 20% or by less than 10%. A vertical extent of the first transition portion may range from 1% to 30%, or from 1% to 20%, or from 1% to 10% of a vertical extent of the first valley portion.

[0045] For example, the vertical profile of a dopant concentration of the first valley section, the first plateau section, and the first transition section can be formed by in-situ doping. In-situ doping can, for example, enable the formation of rectangular or square-wave dopant concentration profiles by controlling the amount and temporal variation of the dopant gases added to the reactant gases.

[0046] For example, the buffer layer may be formed on a SiC substrate by an epitaxial layer deposition process. The drift layer may be formed on the buffer layer by an epitaxial layer deposition process. The dopant concentration profile of the buffer layer, including at least the first valley portion, the first plateau portion, and the first transition portion, may be adjusted or formed, for example, before forming the drift layer on the buffer layer. The buffer layer and the drift layer on the buffer layer may be formed, for example, without interrupting the epitaxial layer deposition process, i.e., after forming the buffer layer and before forming the drift layer, by ion implantation processes into the buffer layer.

[0047] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples given herein are expressly intended primarily for illustrative purposes only. to assist the reader in understanding the principles of revelation and the concepts contributed to All statements herein that list principles, aspects, and examples of the revelation, as well as specific examples thereof, are intended to include equivalents thereof.

[0048] A configuration example of a SiC semiconductor device 100 is shown in the schematic cross-sectional view of Fig. 1A. In the graph of Fig. 1B is an example of a profile of a dopant concentration c along a vertical direction of the SiC semiconductor device 100 of Fig. 1A.

[0049] With reference to Fig. 1A, the SiC semiconductor device comprises a buffer layer 102 of a first conductivity type. A drift layer 104 of the first conductivity type is formed on the buffer layer 102 along a vertical direction y. The buffer layer 102 may be formed on a SiC base substrate, which may be thinned or even removed, for example, during the fabrication of the SiC semiconductor device 100.

[0050] With reference to Fig. 1B, a vertical profile of a dopant concentration c of the buffer layer 102 includes a first valley portion 1021. The profile further includes a first plateau portion 1023. The profile further includes a first transition portion 1022 extending from the first valley portion 1021 to the first plateau portion 1023. The profile may be an in-situ dopant concentration profile. The dopant concentration c of the first valley portion 1021 varies by less than 20%. Likewise, the dopant concentration c of the first plateau portion 1023 varies by less than 20%. A vertical extent vt1 of the first transition section 1022 ranges from 1% to 30% of a vertical extent vv1 of the first valley section 1021 or ranges from 1% to 30% of a vertical extent vp1 of the first plateau section 1023.

[0051] Further examples of a dopant concentration along a vertical direction of the SiC semiconductor device 100 are shown in the graph of Fig. 2 shown.

[0052] The buffer layer 102, which is associated with each of the profiles c1, c2, further comprises an end portion 1024 adjacent to the drift layer 104. While both profiles c1, c2 continuously decrease toward the drift layer 104, a gradient of the profile c1 also decreases toward the drift layer 104. The drift layer 104 is illustrated by a constant dopant concentration.

[0053] The buffer layer 102, which is associated with each of the profiles c1, c2, further comprises a second plateau section 1026 and a second transition section 1025 extending from the second plateau section 1026 to the first valley section 1021. The dopant concentration of the second plateau section 1026 varies by less than 20%. A vertical extent vt2 of the second transition section 1025 ranges from 1% to 30% of the vertical extent vv1 of the first valley section 1021. An average dopant concentration of the second plateau section 1026 differs by less than 20%. Likewise, an average dopant concentration of the first plateau section 1023 differs by less than 20%.

[0054] In the buffer layer 102, which is assigned to each of the profiles c1, c2, a vertical extension vp2 of the second plateau section 1026 and a vertical extension vv1 of the first valley section 1021 differ by less than 20%.

[0055] The buffer layer 102 further includes a second valley portion 1028 and a third transition portion 1027. The third transition portion 1027 extends from the first plateau portion 1023 to the second valley portion 1028. A dopant concentration of the second valley portion 1028 varies by less than 20%. A vertical extent vt3 of the third transition portion 1027 ranges from 1% to 30% of a vertical extent vv2 of the second valley portion 1028.

[0056] Further examples of a dopant concentration along a vertical direction of the SiC semiconductor device 100 are shown in the graph of Fig. 3 shown.

[0057] In the end section 1024 adjacent to the drift layer 104, the dopant concentration profiles c3, c4 are similar to the dopant concentration profiles c1, c2 of Fig. 2. Unlike the exemplary dopant profiles c1, c2, which are shown in Fig. 2, an average dopant concentration of the second plateau section 1026 is a factor of 1.5 to 30 greater than an average dopant concentration of the first plateau section 1023. Likewise, an average dopant concentration of the first valley section 1021 is a factor of 1.5 to 30 greater than an average dopant concentration of the second valley section 1028.

[0058] The buffer layer 102 may be part of a SiC semiconductor device 100, as shown, for example, in the schematic cross-sectional view of Fig. 4 shown.

[0059] The SiC semiconductor device 100 includes the buffer layer 102, as described in the examples herein. The buffer layer 102 is formed on a SiC semiconductor base substrate 101. In some examples, the semiconductor base substrate 101 may be partially or completely removed. An active device layer 107 is formed over the drift layer 104. The active device layer 107 includes one or more doped regions for implementing a desired device functionality, e.g., transistor cell functionality. The semiconductor base substrate 101, the buffer layer 102, the drift layer 104, and the active device layer 107 are parts of a SiC semiconductor body 105 having a first surface 1051 and a second surface 1052.

[0060] A first load electrode L1 is arranged on the first surface of the SiC semiconductor body 105 and is electrically coupled to the active device layer, e.g., to a source region of a MOSFET or to an emitter region of an IGBT. The first load electrode L1 is part of a wiring region above the first surface 1051 of the SiC semiconductor body 105. A control electrode C is arranged on and / or below the first surface 1051 of the SiC semiconductor body. The control electrode C can be, for example, a gate electrode of a planar gate or a trench gate transistor. A second load electrode L2 is arranged on the second surface 1052 of the SiC semiconductor body 105 and is electrically coupled to the drift layer 104.

[0061] It should be understood that the disclosure of multiple steps, processes, operations, steps, or functions disclosed in the specification or the claims should not be construed as being in the specific order unless explicitly or implicitly indicated otherwise, e.g., by terms such as "thereafter," for example, for technical reasons. Therefore, the disclosure of multiple steps or functions does not limit them to any particular order unless such steps or functions are not interchangeable for technical reasons. Further, in some examples, a single step, function, process, operation, or step may include or be broken down into multiple sub-steps, functions, processes, operations, or steps, respectively.Such sub-steps may be included and form part of the disclosure of that single step unless they are expressly excluded.

[0062] An example of a method for manufacturing a semiconductor device is described with reference to the flowchart of Fig. 5 shown.

[0063] The process feature S110 comprises forming a buffer layer of a first conductivity type.

[0064] Process feature S120 includes forming a drift layer of the first conductivity type arranged along a vertical direction on the buffer layer, wherein a vertical profile of a dopant concentration of the buffer layer includes at least a first valley portion, a first plateau portion, and a first transition portion from the first valley portion to the first plateau portion, wherein the dopant concentration of each of the first valley portion or the first plateau portion varies by less than 20%, and a vertical extent of the first transition portion ranges from 1% to 30% of a vertical extent of the first valley portion.

[0065] Although specific examples have been shown and described herein, it will be understood by one of ordinary skill in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

[0066] It should be noted that the methods and devices, including their preferred embodiments, as set forth in this document can be used alone or in combination with the other methods and devices disclosed in this document. Furthermore, the features set forth in the context of a device are also applicable to a corresponding method, and vice versa. Furthermore, all aspects of the methods and devices set forth in this document can be combined in any desired manner. In particular, the features of the claims can be combined with one another in any desired manner.

[0067] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not expressly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments set forth herein are expressly intended primarily for illustrative purposes only to assist the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof.

Claims

[1] A silicon carbide, SiC, semiconductor device (100) comprising: a buffer layer (102) of a first conductivity type; a drift layer (104) of the first conductivity type arranged along a vertical direction (y) on the buffer layer (102), wherein a vertical profile of a dopant concentration (c) of the buffer layer (102) includes at least a first valley portion (1021), a first plateau portion (1023), and a first transition portion (1022) extending from the first valley portion (1021) to the first plateau portion (1023), wherein the dopant concentration (c) of each of the first valley portion (1021) or the first plateau portion (1023) varies by less than 20%, and a vertical extent (vt1) of the first transition portion (1022) ranges from 1% to 30% of a vertical extent (vv1) of the first valley portion (1021), wherein the buffer layer (102) further comprises an end portion (1024) adjacent to the drift layer (104), and a profile of a dopant concentration (c) of the end portion (102), starting from a dopant concentration (c) of the first valley section (1021) or below it, continuously decreases in the direction of the drift layer (104). [2] SiC semiconductor device (100) according to the preceding claim, wherein the vertical extent (vt1) of the first transition section (1022) ranges from 1% to 30% of a vertical extent (vp1) of the first plateau section (1023). [3] SiC semiconductor device (100) according to one of the preceding claims, wherein the dopant concentration (c) of the first plateau portion (1023) is 1 × 10 17 cm -3 up to 1 × 10 19 cm -3 suffices. [4] SiC semiconductor device (100) according to one of the preceding claims, wherein a dopant concentration of the first valley portion (1021) of 1 × 10 16 cm -3 up to 1 × 10 18 cm -3 suffices. [5] SiC semiconductor device (100) according to one of the three preceding claims, wherein the vertical extent (vp1) of the first plateau portion (1023) and the vertical extent (vv1) of the first valley portion (1022) differ by less than 20%. [6] The SiC semiconductor device (100) according to any one of the preceding claims, wherein the vertical extent (vv1) of the first valley portion (1021) ranges from 100 nm to 2 µm. [7] The SiC semiconductor device (100) according to any one of the preceding claims, wherein the buffer layer (102) further comprises a second plateau portion (1026) and a second transition portion (1025) extending from the second plateau portion (1026) to the first valley portion (1021). [8] SiC semiconductor device (100) according to the preceding claim, wherein the dopant concentration of the second plateau section (1026) varies by less than 20% and a vertical extent (vt2) of the second transition section (1025) ranges from 1% to 30% of the vertical extent (vv1) of the first valley section (1021). [9] The SiC semiconductor device (100) according to any one of the two preceding claims, wherein an average dopant concentration of the second plateau portion (1026) and an average dopant concentration of the first plateau portion (1023) differ by less than 20%. [10] The SiC semiconductor device (100) according to claim 7 or 8, wherein an average dopant concentration of the second plateau portion (1026) is greater by a factor of 1.5 to 30 than an average dopant concentration of the first plateau portion (1023). [11] SiC semiconductor device (100) according to one of the four preceding claims, wherein a vertical extent (vp2) of the second plateau portion (1026) and a vertical extent (vv1) of the first valley portion (1021) differ by less than 20%. [12] The SiC semiconductor device (100) according to any one of the preceding claims, wherein the buffer layer (102) further includes a second valley portion (1028) and a third transition portion (1027) extending from the first plateau portion (1023) to the second valley portion (1028), and a dopant concentration of the second valley portion (1028) varies by less than 20%, and wherein a vertical extent (vt3) of the third transition portion (1027) ranges from 1% to 30% of a vertical extent (vv2) of the second valley portion (1028). [13] The SiC semiconductor device (100) according to the preceding claim, wherein an average dopant concentration of the second valley portion (1028) and an average dopant concentration of the first valley portion (1021) differ by less than 20%. [14] The SiC semiconductor device (100) of claim 12, wherein an average dopant concentration of the first valley portion (1021) is greater than an average dopant concentration of the second valley portion (1028) by a factor of 1.5 to 30. [15] The SiC semiconductor device (100) according to any one of the preceding claims, wherein the vertical profile of a dopant concentration (c) of the first valley portion (1021), the first plateau portion (1023) and the first transition portion (1022) is an in-situ dopant concentration profile. [16] A method of manufacturing a silicon carbide, SiC, semiconductor device (100), the method comprising: Forming a buffer layer (102) of a first conductivity type; and Forming a drift layer (104) of the first conductivity type arranged along a vertical direction (y) on the buffer layer (102), wherein a vertical profile of a dopant concentration (c) of the buffer layer (102) includes at least a first valley section (1021), a first plateau section (1023) and a first transition section (1022) from the first valley section (1021) to the first plateau section (1023), wherein the dopant concentration (c) of each of the first valley section (1021) or the first plateau section (1023) varies by less than 20% and a vertical extension (vt1) of the first transition section (1022) ranges from 1% to 30% of a vertical extension (vv1) of the first valley section (1021), wherein the buffer layer (102) further comprises an end section (1024) adjacent to the drift layer (104), and a profile of a dopant concentration (c) of the end section (102), starting from a Dopant concentration (c) of the first valley section (1021) or below it, continuously decreases in the direction of the drift layer (104). [17] Method according to the preceding claim, wherein the vertical profile of a dopant concentration (c) of the first valley portion (1021), the first plateau portion (1023) and the first transition portion (1022) is formed by in-situ doping. [18] The method according to any one of the two preceding claims, wherein the buffer layer (102) is formed on a SiC substrate by an epitaxial layer deposition process and the drift layer (104) is formed on the buffer layer (102) by an epitaxial layer deposition process.

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