Power semiconductor device: Method for manufacturing a power semiconductor device

Abstract

A method for manufacturing a power semiconductor device (1) comprising: providing (20) a semiconductor body (10), wherein the semiconductor body (10) has a front face (110) with a substantially horizontal region over both an active region (1-1) and an edge termination region (1-3) of the semiconductor body (10); forming (20) on the front face (110) a first insulating layer (11) over both the active region (1-1) and the edge termination region (1-3); forming (20) on the first insulating layer (11) a first mask layer (12), wherein the first mask layer (12) at least partially covers the edge termination region (1-3) and exposes the active region (1-1); and removing (22) a portion of the first insulating layer (11) covering the active region (1-1).While the first mask layer (12) or a modified first mask layer (12) or another mask layer (13) covers the edge termination region (1-3), subjecting (24) the edge termination region (1-3) to a first implantation processing step to form one or more doped semiconductor regions (1-31) in the edge termination region (1-3).

Description

Technical field

[0001] This description relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. Some embodiments presented herein relate to the integration of a high-voltage termination structure with silicon oxide and a variable lateral doping (VLD) region. background

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on power semiconductor devices. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications, including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is conducted through an active region of the power semiconductor device. The active region is surrounded by an edge termination region, which is terminated by an edge of the chip.

[0004] High-voltage devices may therefore require a defined active region and an edge termination region, which must also be aligned with each other. In some implementations, an edge termination featuring a VLD (Variation of Lateral Doping) configuration is chosen for reliability reasons. Within the edge termination region, the surface of the semiconductor body may also exhibit a termination structure, e.g., based on thermal oxidation, due to a low density of interfacial charges and traps.

[0005] The present description proposes techniques relating to a cost-effective manufacturing process for an edge termination region of a power semiconductor device. SUMMARY

[0006] The subject matter of the independent claims is presented. Features of exemplary embodiments are defined in the dependent claims.

[0007] According to one embodiment, a method for manufacturing a power semiconductor device comprises: providing a semiconductor body, wherein the semiconductor body has a front face with a substantially horizontal area over both an active region and an edge termination region of the semiconductor body; forming, on the front face, a first insulating layer over both the active region and the edge termination region; forming, on the first insulating layer, a first mask layer, wherein the first mask layer at least partially covers the edge termination region and exposes the active region; and removing a portion of the first insulating layer covering the active region.While the first mask layer, or a modified first mask layer, or another mask layer covers the edge termination region, subjecting the edge termination region to a first implantation processing step to form one or more doped semiconductor regions in the edge termination region.

[0008] According to another embodiment, a power semiconductor device is presented, wherein the power semiconductor device was manufactured according to the method described in the preceding paragraph.

[0009] According to a further embodiment, a power semiconductor device comprises: a semiconductor body, wherein the semiconductor body has a front face with a substantially horizontal region over both an active region and an edge termination region of the semiconductor body; a first insulating layer over the edge termination region, wherein the first insulating layer is a thermally grown oxide in contact with the front face and has a thickness within the range of 50 nm to 500 nm; and below the front face in the edge termination region a variation-of-the-lateral doping (VLD) region.

[0010] According to yet another embodiment, a power semiconductor device comprises: a semiconductor body, wherein the semiconductor body has a front face with a substantially horizontal region over both an active region and an edge termination region of the semiconductor body; a first insulating layer over the edge termination region and in contact with the front face; and below the front face in the edge termination region, a doped semiconductor region, wherein the doped semiconductor region has a dopant concentration profile along a vertical direction, such that: the dopant concentration at the front face has a starting value N A_0 exhibits; the dopant concentration has a maximum value N A_MAX reached, which is greater than the starting value N A_0 at a first vertical distance Z MAX from the front side; the dopant concentration along the vertical direction after the first vertical distance ZMAX continuously decreases and the starting value N A_0 at a second vertical distance Z MED from the front again; and (N A_MAX -N A_0 ) / N A_MAX not greater than 1 / 3.

[0011] The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. Brief description of the drawings

[0012] The parts in the figures are not necessarily to scale; instead, the focus is on illustrating the principles of the invention. Furthermore, identical reference numerals in the figures denote corresponding parts. The drawings show: Fig. 1-3 schematically and by way of example, based on sections of vertical cross-sections of a power semiconductor device being manufactured, a method for manufacturing the power semiconductor device according to some embodiments; Fig. 4. A schematic and exemplary dopant concentration profile in a power semiconductor device according to one or more embodiments; and Fig. 5 schematically and by way of example a section of a vertical cross-section of a power semiconductor device according to one or more embodiments. Detailed description

[0013] The following detailed description refers to the accompanying drawings, which form a part thereof and in which specific embodiments in which the invention can be implemented are shown for illustrative purposes.

[0014] In this respect, directional terminology such as "above," "below," "under," "front," "back," "leading," "trailing," "over," etc., may be used with reference to the orientation of the described figures. Since parts of embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention. The following detailed description is therefore not to be understood as limiting, and the scope of protection of the present invention is defined by the accompanying claims.

[0015] Various embodiments will now be described in detail, one or more examples of which are illustrated in the figures. Each example is provided for illustrative purposes and is not intended to limit the invention. For instance, features illustrated or described as part of one embodiment may be used in or in combination with other embodiments to produce yet another embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only.For the sake of clarity, the same elements or manufacturing steps in the different drawings have been designated with the same reference symbols, unless otherwise specified.

[0016] The term "horizontal," as used in this description, is intended to describe an orientation essentially parallel to a horizontal surface of a semiconductor substrate or structure. This could be, for example, the surface of a semiconductor wafer, die, or chip. For instance, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, with the first lateral direction X and the second lateral direction Y potentially being perpendicular to each other.

[0017] The term "vertical," as used in this description, is intended to describe an orientation that is essentially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the semiconductor wafer / chip / die's surface. For example, the extension direction Z mentioned below can be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0018] The first conductivity type is the opposite of the second conductivity type. In this description, n-doped is referred to as the "first conductivity type," while p-doped is referred to as the "second conductivity type." Alternatively, opposite doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. A dopant dose can be defined as the integral over the dopant concentration of atoms of the respective conductivity type within a given doping region in a vertical direction Z.

[0019] In the context of this description, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe the existence of a low-resistance electrical connection or current path between two regions, sections, zones, segments, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a section or part of a semiconductor device, where "low resistance" may mean that the properties of the respective contact are not substantially affected by the ohmic resistance. Furthermore, in the context of this description, the term "in contact" is intended to describe the existence of a direct physical connection between two elements of the respective power semiconductor device; e.g.,A transition between two elements that are in contact with each other cannot contain any further intermediate element or the like.

[0020] Additionally, in the context of this description, the term "electrical isolation" is used, unless otherwise specified, in its generally accepted sense and thus describes a situation where two or more components are positioned separately and there is no ohmic connection linking them. However, components that are electrically isolated from each other may still be coupled, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (for example, in the case of a junction). To give an example, two electrodes of a capacitor may be electrically isolated from each other and simultaneously mechanically and capacitively coupled, for example, by means of insulation, such as a dielectric.

[0021] Specific embodiments described in this description relate, but are not limited to, a power semiconductor device that can be used within a power converter or power supply. Thus, in one embodiment, such a power semiconductor device can be configured to carry a load current that is to be supplied to a load and / or that is provided by a power source. For example, the power semiconductor device can comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell, a monolithically integrated transistor cell, e.g., a monolithically integrated IGBT or MOSFET cell, and / or derivatives thereof. Such diode / transistor cells can be integrated within a single chip.A large number of such cells can form a cell array that is arranged within an active region of the power semiconductor device.

[0022] The term "blocking state" of a power semiconductor device can refer to conditions when the power semiconductor is in a state configured to block load current flow while an external voltage is applied. Specifically, the power semiconductor device can be configured to block forward load current flow while a forward voltage bias is applied. Conversely, the power semiconductor device can be configured to conduct forward load current in a "forward conducting state" while a forward voltage bias is applied. A transition between the forward blocking state and the forward conducting state can be controlled by a control electrode, or more specifically, by the potential of the control electrode.The electrical properties can, of course, only be valid within a predetermined operating range of external voltage and current density within the power semiconductor device. The term "forward-biased blocking state" can therefore refer to conditions in which the power semiconductor device is in a forward-biased state while a forward voltage bias is applied.

[0023] The term "power semiconductor device," as used in this description, is intended to describe a power semiconductor device on a single chip with high-voltage blocking and / or high-current carrying capacities. In other words, such a power semiconductor device is designed for high currents, typically in the range of several amps, e.g., up to several tens or hundreds of amperes, and / or high voltages, typically above 100 V, typically 300 V and above, e.g., up to at least 600 V or even more, e.g., up to at least 1.2 kV or even up to 6 kV or more, depending on the specific application.

[0024] For example, the term "power semiconductor device" as used in this description does not refer to logic semiconductor devices used, for example, for storing data, calculating data and / or other types of semiconductor-based data processing.

[0025] For example, the power semiconductor device described below can be a single semiconductor chip and can be configured to be used as a power component in a low, medium and / or high voltage application.

[0026] Fig. 1 to Fig. Figure 3 illustrates schematically and by way of example, based on sections of vertical cross-sections of a power semiconductor device being manufactured, a method for manufacturing the power semiconductor device 1 according to some embodiments.

[0027] The procedure includes provisioning, in stage 20 (see Fig. 1), of a semiconductor body 10. For example, the semiconductor body 10 is based on silicon, Si.

[0028] The semiconductor body 10 has a front face 110 with a substantially horizontal area over both an active area 1-1 and an edge termination area 1-3 of the semiconductor body 10, as shown in Fig. 1 illustrates.

[0029] The procedure also includes education, in stage 20 (see below). Fig. 1) on the front face 110, a first insulating layer 11 over both the active region 1-1 and the edge termination region 1-3. For example, the first insulating layer 11 is based on an oxide. The first insulating layer 11 can be formed by performing an oxidation processing step and / or a deposition processing step.

[0030] The procedure also includes education, in stage 20 (see below). Fig. 1) at the first insulating layer 11, a first mask layer 12. The first mask layer 12 covers the edge sealing region 1-3 at least partially and exposes the active region 1-1, e.g., at least partially or completely. For example, the first mask layer 12 defines the lateral transition between the edge sealing region 1-3 and the active region 1-2.

[0031] The procedure also includes education, in stage 22 (see below). Fig. 2A), a part of the first insulating layer 11, which covers the active area (1-1). In one embodiment, during step 22 (see Fig. 2B) also remove and / or modify the first mask layer 12 and / or replace it with another mask layer 13.

[0032] The procedure also includes education, in stage 24 (see below). Fig. 3) after the first mask layer 12 or a modified first mask layer 12 or another mask layer 13 has been opened over the marginal sealing area 1-3, at least partially subjecting the marginal sealing area 1-3 to a first implantation processing step (indicated by the bold arrow with an “I” 2 “ is marked), to form one or more doped semiconductor regions 1-31 in the edge termination region 1-3.

[0033] For example, the first implantation processing step is performed with an implantation energy of less than 500 keV, less than 200 keV, or even less than 100 keV. The actual implantation energy can be selected depending on the thickness t of the first insulating layer 11.

[0034] For example, the first implantation processing step is performed to form a variation-of-the-lateral doping (VLD) area 1-31 under the anterior surface 110 and in the marginal closure area 1-3. For example, the procedure involves modifying the first mask layer 12 to obtain a modified first mask layer 12 by forming a plurality of openings 1213 in the first mask layer 12, the openings 1213 corresponding to an intended variation-of-the-lateral doping (VLD) area 1-31. Then, the variation-of-the-lateral doping (VLD) area 1-31 can be formed during the first implantation processing step. Of course, instead of modifying the first mask layer 12, the mask layer 12 could also be replaced by another layer 13 which has the openings 1213 corresponding to the intended variation-of-the-lateral doping, VLD, area 1-31.After the first implantation processing step, a diffusion processing step can be performed to achieve a contiguous VLD area 1-31.

[0035] After diffusion processing, the VLD region 1-31 can exhibit a continuous function, e.g., a linear gradient, of doping concentration in the semiconductor body 10, starting at the interface with the active region 1-1, where the concentration is highest. Towards the outer edge of the edge termination region 1-2, the doping concentration decreases and may eventually result in essentially no increased doping concentration compared to the background doping of the semiconductor body 10. While at the interface with the active region 1-1 the doping concentration of the VLD region 1-31 is high enough to avoid being completely depleted by the space charge region during static blocking, at the outer parts of the VLD region 1-31 the space charge region during static blocking will reach the interface between the semiconductor body 10 and the first insulating layer 11.On the path from the active region 1-1 to the outer edge termination, the doping of the VLD region 1-31 can exhibit one or more regions of constant concentration (e.g., at the interface with the active region 1-1) and one or more steep steps in doping concentration, e.g., at the outer edge of the VLD region 1-31. Since the diffusion processing step may not be sufficient to completely disperse implanted dopants, a moving average of the doping concentration can be formed with a lateral width of the averaging length of, e.g., 3 times or 5 times the depth of the VLD region 1-31 in the semiconductor body 10, resulting in average dopant concentrations within the VLD region 1-31, as described above.

[0036] In one embodiment, the VLD region 1-31 can have a junction-termination-extension (JTE) configuration. While the VLD region 1-31 exhibits a gradient in doping concentration, at the JTE edge termination the doping concentration can decrease in steps and become essentially constant at one step. Alternatively, the JTE edge termination can start with a doping concentration too high to be completely depleted by the space charge region and have one or more additional steps in doping concentration that result in a completely depletable doping concentration.

[0037] With further reference to level 24, as in Fig. As shown in Figure 3, the method can further comprise the formation of another mask layer 14 before the first implantation processing step is performed, in order to at least partially cover the active area 1-1. This ensures that the active area 1-1 is not subjected to the first implantation processing step. In another embodiment, the active area 1-1 can also be subjected to the first implantation processing step, e.g., while it is covered with a structured mask.

[0038] For example, with reference to level 20, as exemplified in Fig. As shown in Figure 1, the first insulating layer 11 contains or consists of a thermally grown oxide. For example, the formation of the first insulating layer 11 does not involve a deposition processing step. For example, the semiconductor body 10 is based on silicon, Si, and the first insulating layer 11 is thermally grown silicon oxide, SiO2. During the thermal growth of SiO2, some of the originally available semiconductor material of the semiconductor body 10 is consumed, resulting in a step at the front face 110 of the semiconductor body 10. Therefore, the insulating layer 11 may be partially buried beneath the original extent of the front face 110.

[0039] For example, with reference to level 20, as exemplified in Fig. As shown in Figure 1, prior to forming 20, the first insulating layer 11, the first mask layer 12, has a thickness t of the first insulating layer 11 within the range of 50 nm to 500 nm. Furthermore, in one embodiment, the thickness t of the first insulating layer 11 is essentially constant within the entire horizontal extent (along the first and second lateral directions X and Y) of the first insulating layer 11.

[0040] Furthermore, in one embodiment the first insulating layer 11 is present, while the step of underlayment (see step 24 in Fig. 13) of the marginal sealing area 1-3 is performed with the first implantation processing step. The first insulating layer 11 can be configured to mask doping ions implanted with an implantation energy of 10 keV or less.

[0041] In one embodiment, the first insulating layer 11 can be arranged such that it abuts the front face 110 of the semiconductor body 10 or does not penetrate the semiconductor body 10. For example, the first insulating layer 11 can be arranged such that it does not extend further along the vertical direction Z than the front face 110 formed by the portion of the semiconductor body 10 in the active region 1-1. Naturally, the optional provisions take into account that the first insulating layer 11 can be based on a thermal growth processing step in which the front face 110 of the original semiconductor body 10 undergoes an oxidation processing step.

[0042] With reference to Fig. 2A and Fig. 2B may further comprise, in one embodiment, after removing (see step 22) the part of the first insulating layer 11 covering the active area 1-1, subjecting (see step 22) the active area (1-1) to a second implantation processing step (indicated by the bold arrows marked with an “I” 2 “ are marked), to form one or more doped semiconductor regions 1-11 in the active region 1-1.

[0043] The second implant processing step can be performed after the first implant processing step, or it can be performed before the first implant processing step.

[0044] Depending on how the first insulating layer removal step is performed and / or how the first mask layer 12 is modified, removed or replaced, a small gap g may remain between the one or more doped semiconductor regions 1-11 and the first insulating layer 11 (cf. Fig. 2A) or a small lateral overlap is formed between the one or more doped semiconductor regions 1-11 and the first insulating layer 11 (cf. Fig. 2B). In any case, it can be ensured that the one or more doped semiconductor regions 1-11 border or overlap the VLD region 1-31 at least after a diffusion step, as shown in Fig. 3 and Fig. 5 shown.

[0045] After diffusion, a blocking pn junction in the active region 1-1 must be in conductive contact with the VLD region 1-31. In the case of only slight over-etching of the first insulating layer 11 and strong diffusion, the final result of Fig. 2A and Fig. 2B will be only slight and indistinguishable. With a large over-etching of the insulating layer 11 and the process according to Fig. 2A can be the lateral end of the doping range 1-11 in Fig. 5 end before the full thickness of the insulating layer 11 is reached.

[0046] Before the device is further processed, e.g. by being fitted with encapsulation or the like, the (modified) first mask layer 12 or the other mask layer 13, which covers the edge termination area 1-3, can be removed. The second mask layer 14 can also be removed.

[0047] For example, see: Fig. 5. After mask removal, a passivation layer 15 can be formed over the first insulating layer 11 in the edge termination region 1-3. For example, the passivation layer 15 comprises at least one of an inorganic insulating material, a silicon nitride, a silicon oxide, an electroactive material, a semi-insulating polycrystalline silicon, a diamond-like carbon, DLC, Si-rich Si3N4, an organic insulating material, an imide, or a silicon.

[0048] With further reference to Fig. 5. In one embodiment, the method may further comprise forming a metal layer 1-12 on the semiconductor body 10. For example, the metal layer 1-12 is in direct physical contact with the semiconductor body 10 (e.g., partially or completely) where the portion of the first insulating layer 11 covering the active region (1-1) has previously been removed (see transition from step 20 to step 22, illustrated in Figure 5). Fig. 1, Fig. 2A and Fig. 2B). For example, the metal layer 1-12 forms part of a first load terminal of the power semiconductor device 1. For example, the metal layer 1-12 is in direct physical contact with a remaining part of the first insulating layer 11, e.g., the remaining part of the first insulating layer 11 that is not removed during removal stage 22. An overlapping portion of the metal layer 1-12 may extend over the first insulating layer 11. In general, the formation of the metal layer 1-12 can occur after removal stage 22 and after undergoing stage 24.

[0049] This document also introduces a power semiconductor device 1, wherein the power semiconductor device 1 was manufactured according to a method according to one of the embodiments described above.

[0050] For example, the power semiconductor device comprises a semiconductor body 10, wherein the semiconductor body has a front face with a substantially horizontal region over both an active region and an edge termination region of the semiconductor body; a first insulating layer over the edge termination region, wherein the first insulating layer is a thermally grown oxide in contact with the front face and has a thickness in the range of 50 nm to 500 nm; and below the front face in the edge termination region, a variation-of-the-lateral doping (VLD) region. Embodiments of this power semiconductor device correspond to embodiments of the method described above. Thus, reference is made above regarding embodiments of the power semiconductor device.

[0051] According to a further embodiment, a power semiconductor device comprises a semiconductor body, wherein the semiconductor body has a front face with a substantially horizontal region over both an active region and an edge termination region of the semiconductor body; a first insulating layer over the edge termination region and in contact with the front face; and below the front face in the edge termination region a doped semiconductor region, wherein the doped semiconductor region has a dopant concentration profile along a vertical direction, such that the dopant concentration at the front face has a starting value N A_0 exhibits; the dopant concentration has a maximum value N A_MAX reached, which is greater than the starting value N A_0 at a first vertical distance Z MAX from the front side; the dopant concentration along the vertical direction after the first vertical distance Z MAXcontinuously decreases and the starting value N A_0 at a second vertical distance Z MED from the front again; and (N A_MAX -N A_0 ) / N A_MAX not greater than 1 / 3.

[0052] With regard to the embodiments of the power semiconductor device 1 described above, reference is made to Fig. Reference is made to Figure 4, which schematically and exemplarily illustrates a dopant concentration profile in the power semiconductor device 1 according to one or more embodiments. The horizontal axis shows the magnitude of the dopant concentration N. A (in any unit, e.g. 1 / cm²) 3 ) in the VLD range 1-31, and the vertical axis shows the level along the vertical direction Z (in any unit, e.g. µm).

[0053] Accordingly, in one embodiment, the dopant concentration at the front face 110 under the first insulating layer 11 has the starting value NA_0 The dopant concentration reaches its maximum value N along the vertical direction Z. A_MAX (which is greater than the starting value N) A _0 is) in the first vertical distance Z MAX from the front side 110. The dopant concentration then decreases along the vertical direction Z after the first vertical distance Z. MAX continuously decreases and reaches the starting value N A_0 in the second vertical distance Z MED from the front 110 again.

[0054] In one embodiment, the dopant concentration profile has a further maximum value, wherein the further maximum value is greater or less than the maximum value N. A_MAX may be.

[0055] For example, the embodiments of the power semiconductor device described above may have a MOSFET configuration, an IGBT configuration, or a configuration derived from a MOSFET configuration or an IGBT configuration.

[0056] The above described embodiments relating to power semiconductor devices and corresponding manufacturing processes.

[0057] For example, these power semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor area or layer, e.g., the semiconductor body and its regions / zones, can be a monocrystalline Si region or layer. In other embodiments, polycrystalline or amorphous silicon can be used.

[0058] However, it is understood that the semiconductor body and its areas / zones can be made from any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP) and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name just a few.The semiconductor materials mentioned above are also referred to as "homo-junction semiconductor materials." When two different semiconductor materials are combined, a hetero-junction semiconductor material is formed. Examples of hetero-junction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe hetero-junction semiconductor materials. Si, SiC, GaAs, and GaN materials are currently the most commonly used for power semiconductor switching applications.

[0059] Spatially relative terms such as "below," "under," "lower," "above," "upper," and the like are used to simplify the description and to explain the positioning of one element relative to another. These terms are intended to encompass various orientations of the respective device in addition to those shown in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, areas, sections, etc., and are not intended to be restrictive. The same terms may refer to the same elements throughout the description.

Claims

[1] Method for manufacturing a power semiconductor device (1) comprising - Providing (20) a semiconductor body (10) wherein the semiconductor body (10) has a front face (110) with a substantially horizontal area over both an active area (1-1) and an edge termination area (1-3) of the semiconductor body (10); - Forming (20), on the front (110), a first insulating layer (11) both over the active area (1-1) and the edge termination area (1-3); - Forming (20), on the first insulating layer (11), a first mask layer (12), wherein the first mask layer (12) at least partially covers the edge termination area (1-3) and exposes the active area (1-1); and - Removing (22) part of the first insulating layer (11) covering the active area (1-1); - while the first mask layer (12) or a modified first mask layer (12) or another mask layer (13) covers the edge termination region (1-3), subjecting (24) the edge termination region (1-3) to a first implantation processing step to form one or more doped semiconductor regions (1-31) in the edge termination region (1-3). [2] Method according to claim 1, wherein the first insulating layer (11) contains or consists of a thermally grown oxide. [3] Method according to claim 1 or 2, wherein prior to forming (20) the first insulating layer (11) of the first mask layer (12), the thickness (t) of the first insulating layer (11) is within the range of 50 nm to 500 nm. [4] Method according to claim 3, wherein the thickness (t) of the first insulating layer (11) is substantially constant throughout the entire horizontal extent of the first insulating layer (11). [5] Method according to claim 3 or 4, wherein the thickness (t) of the first insulating layer (11) is present while the step of applying (24) to the edge closure area (1-3) is carried out during the first implantation processing step. [6] Method according to any of the preceding claims, wherein the first insulating layer (11) is configured to mask doping ions implanted with an implantation energy of less than 10 keV. [7] Method according to any of the preceding claims, wherein the first insulating layer (11) is adjacent to the front side (110) of the semiconductor body (10) or does not penetrate the semiconductor body (10). [8] Method according to any of the preceding claims, wherein the semiconductor body (10) is based on silicon, Si, and wherein the first insulating layer (11) is thermally grown silicon oxide, SiO2. [9] Method according to any of the preceding claims, further comprising, after removing (22) the part of the first insulating layer (11) covering the active region (1-1), subjecting (22) the active region (1-1) to a second implantation processing step to form one or more doped semiconductor regions (1-11) in the active region (1-1). [10] Method according to any of the preceding claims, wherein the first implantation processing step is performed with an implantation energy of less than 500 keV. [11] Method according to one of the preceding claims, wherein the first implantation processing step is carried out to form a variation-of-the-lateral doping, VLD, area (1-31) under the front (110) in the marginal termination area (1-3). [12] The method of claim 11, further comprising: - Modifying the first mask layer (12) to obtain a modified first mask layer (12) by forming a plurality of openings (1213) in the first mask layer (12), wherein the openings (1213) correspond to an intended variation-of-the-lateral doping, VLD, area (1-31); and - Formation of the variation-of-the-lateral doping, VLD, area (1-31) during the first implantation processing step. [13] Method according to one of the preceding claims, wherein, before the first implantation processing step is carried out, a further mask layer (14) is formed to at least partially cover the active area (1-1). [14] Method according to any of the preceding claims, further comprising removing the first mask layer (12), the modified first mask layer (12) or the other mask layer (13). [15] Method according to any of the preceding claims, wherein the first mask layer (12) defines the lateral transition between the edge closure area (1-3) and the active area (1-2). [16] Method according to one of the preceding claims, further comprising forming a passivation layer (15) over the first insulating layer (11) in the edge termination area (1-3). [17] Method according to claim 16, wherein the passivation layer (15) comprises at least one of an inorganic insulating material, a silicon nitride, a silicon oxide, an electroactive material, a semi-insulating polycrystalline silicon, a diamond-like carbon, DLC, Si-rich Si3N4, an organic insulating material, an imide or a silicon. [18] Method according to any of the preceding claims, further comprising forming a metal layer (1-12) on the semiconductor body (10), wherein the metal layer (1-12) is in direct physical contact with the semiconductor body (10), where the part of the first insulating layer (11) covering the active area (1-1) has been previously removed (22). [19] Method according to one of the preceding claims 18, wherein the metal layer (1-12) is in direct physical contact with a remaining part of the first insulating layer (11). [20] Power semiconductor device (1), wherein the power semiconductor device (1) was manufactured according to a method according to one of the preceding claims. [21] Power semiconductor device (1) comprising: - a semiconductor body (10) wherein the semiconductor body (10) has a front face (110) with a substantially horizontal area over both an active area (1-1) and an edge termination area (1-3) of the semiconductor body (10); - a first insulating layer (11) over the edge termination region (1-3), wherein the first insulating layer (11) is a thermally grown oxide in contact with the front face (110) and has a thickness (t) within the range of 50 nm to 500 nm; and - under the front (110) in the rim area (1-3) a variation-of-the-lateral doping, VLD, area (1-31). [22] Power semiconductor device (1) comprising: - a semiconductor body (10) wherein the semiconductor body (10) has a front face (110) with a substantially horizontal area over both an active area (1-1) and an edge termination area (1-3) of the semiconductor body (10); - a first insulating layer (11) over the edge termination area (1-3) and in contact with the front face (110); and - under the front face (110) in the edge termination region (1-3) a doped semiconductor region (1-31) wherein the doped semiconductor region has a dopant concentration profile along a vertical direction (Z) according to which: ◯ the dopant concentration at the front (110) a starting value (N A_0 ) exhibits; ◯ the dopant concentration has a maximum value (N A_MAX ) reached, which is greater than the starting value (N A_0 ) at a first vertical distance (Z MAX ) from the front (110); ◯ the dopant concentration along the vertical direction (Z) after the first vertical distance (Z) MAX ) decreases continuously and the initial value (N A_0 ) at a second vertical distance (Z MED ) from the front (110) again; and ◯ (NA_MAX -N A_0 ) / N A_MAX not greater than 1 / 3. [23] Power semiconductor device (1) according to any one of the preceding claims 17 to 19, wherein the power semiconductor device (1) is a diode, a MOSFET or an IGBT or a derivative of any of the aforementioned devices.

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