Semiconductor chip and method for manufacturing it

Abstract

The disclosure relates to a semiconductor chip (100) comprising: a semiconductor body (10), an insulating layer (20) and a metallization (30), wherein a conductor track (31) is formed in the metallization (30) and is arranged outside an active region (101) of the semiconductor chip (100), wherein a first contact opening (21) is formed in the insulating layer (20) under the conductor track (31), wherein the conductor track (31) is electrically connected to the semiconductor body (10) in a first contact area (41) in the first contact opening (21), the first contact opening (21) is subdivided along a longitudinal extent (110) of the conductor track (31) into a plurality of first contact opening sections (21.1-21.3), wherein the first contact area (41) is provided with a respective first interruption (51, 51.1, 51.2) between adjacent first contact opening sections (21.1-21.3).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor chip comprising a semiconductor body. BACKGROUND

[0002] In embodiments of this application, the semiconductor body is made of silicon carbide (SiC), which has a comparatively wide bandgap, e.g., compared to silicon. This can be of interest, for example, for power semiconductor devices in high-voltage and / or high-current applications. A device structure with one or more load terminals can be formed within the semiconductor body, for example, a transistor structure with a source terminal and a drain terminal. A metallization can be formed over the semiconductor body for wiring and contacting the device structure. SUMMARY

[0003] Examples of the present application are directed to an advantageous semiconductor chip.

[0004] The semiconductor chip can comprise a semiconductor body, an insulating layer over a first side of the semiconductor body, and a metallization over the insulating layer. A conductive trace can be formed in the metallization and located outside an active region of the chip. The conductive trace is connected to the semiconductor body, e.g., to an entity formed within the semiconductor body or to the semiconductor body itself, via a first contact opening formed in the underlying insulating layer. Specifically, the electrical contact can be formed via a first contact area in the first contact opening. In one embodiment, the first contact opening is subdivided into a plurality of first contact opening sections along a longitudinal extent of the conductive trace, with the insulating layer being continuous, for example, between adjacent first contact opening sections.Conversely, the first contact area can be interrupted between adjacent first contact opening sections, i.e., provided with a respective first interruption.

[0005] In other words, the first contact area beneath the conductor track does not extend continuously, but rather with initial interruptions, for example, in a dashed pattern (see below for details). These interruptions can offer advantages in manufacturing, such as structuring the metallization. The metallization, or a portion thereof, can be structured, for example, by a lift-off process, i.e., deposited onto a structured mask followed by mask removal. This can be enhanced by creating a small undercut in the insulating layer beneath the mask, such as a small undercut on a side edge of the insulating layer that is otherwise essentially flush with a corresponding side edge of the mask (see below). Fig. Figures 4a-f illustrate this. Segmenting the contact opening can improve undercut formation, for example, compared to a continuous (uninterrupted) contact opening. Segmentation or interruption can, for instance, allow better penetration of a solvent to lift the mask.

[0006] Further embodiments and features are provided in the claims and throughout the entire disclosure. The individual features are intended to be disclosed independently of any specific claim category and / or embodiment. The disclosure relates to device and apparatus aspects, but also to process and use aspects. For example, if a chip manufactured in a specific way is described, this also constitutes a disclosure of the respective manufacturing process, and vice versa. In general terms, one approach of this application is to subdivide an opening in the insulating layer into a plurality of opening sections, e.g., a contact opening under a conductor track or pad.

[0007] As discussed above, the conductive track or pad is located outside an active region, for example, in an edge termination region between the active region and a side edge of the chip. Within the active region, a device structure can be formed in the semiconductor body. The semiconductor body can be made of silicon carbide (SiC), with possible alternatives including silicon (Si), gallium nitride (GaN), or aluminum oxide (Al₂O₃). The device structure can, for example, include a first load terminal located on the first side of the semiconductor body. It can also include a second load terminal, for example, on a vertically opposite second side of the semiconductor body. The device structure can, for example, be a FET with a source terminal / region and a drain terminal region in the semiconductor body.the source region on the first side of the semiconductor body and the drain region on the second side of it.

[0008] In addition to the source region and the drain region, the device can include a body region to which a gate electrode is capacitively coupled. A drift region can also be arranged between the body region and the drain region, for example, made of the same doping type but at a lower concentration than the drain region. The source region, the drain region, and, if present, the drift region can consist of a first doping type, while the body region can consist of a second doping type. In one embodiment, the first doping type is n-type and the second doping type is p-type.

[0009] In general, the contact area connecting the metallization to the semiconductor body can be formed by a separate contact plug beneath the metallization. However, in one embodiment, the metallization itself forms the contact area, extending, for example, downwards through the contact opening to the semiconductor body. Specifically, the contact area can be formed between a bottom layer of the metallization, such as a sputter-deposited layer, and the semiconductor body (i.e., where the bottom metallization layer contacts the semiconductor body). To improve electrical contact, a highly doped contact area can be formed in the semiconductor body beneath the conductor track. Generally, the highly doped contact area in the semiconductor body can also be provided with discontinuities that, for example, coincide with discontinuities in the contact area.In one embodiment, however, the highly doped contact area extends uninterrupted, e.g. as a continuous line under the conductor track.

[0010] As discussed in more detail below, the conductor track can, for example, form a runner or be part of a runner that extends alongside and along the active area. It can extend along one or more of the chip's edges, e.g., having an L or U shape, or form a closed loop around the active area. Regardless of these details, it can be, for example, a gate runner or a source runner of the device.

[0011] In one embodiment, each first contact opening section beneath the conductor track has a length of at least 0.5 µm and / or at most 50 µm. Further lower limits can be, for example, at least 0.7 µm, 0.8 µm, 0.9 µm, 1 µm, 1.1 µm, or 1.2 µm, although larger lower limits are also conceivable, e.g., at least 2 µm. Further upper limits can be 20 µm, 10 µm, or 5 µm. Regardless of a specific value, the length can be measured along the longitudinal extent of the conductor track, e.g., along a center line of the first contact opening viewed vertically from above. More precisely, the length can be measured at the base of the respective contact opening section (where the contact area is formed).

[0012] In one embodiment, each interruption in the contact area, or conversely, each uninterrupted section of the insulating layer, has a length of at least 0.5 µm and / or at most 50 µm. Further lower limits can be, for example, at least 0.7 µm, 0.8 µm, 0.9 µm, 1 µm, 1.1 µm, or 1.2 µm, although larger lower limits are also conceivable, e.g., at least 2 µm. Further upper limits can be, for example, at most 20 µm, 10 µm, or 5 µm. Again, the length can be taken along the longitudinal extent of the conductor track, e.g., along a center line of the first contact opening as seen from a vertical top view.

[0013] In one embodiment, the first contact opening sections form a dashed pattern along at least one section of the conductor track. The "dashed pattern" can be characterized by the number of contact opening sections provided per unit length, e.g., at least five contact opening sections along a conductor track length of 100 µm. The section of the conductor track in which the dashed pattern is provided can extend further, e.g., to a length of several hundred micrometers or even to a length in the millimeter range.

[0014] Further lower limits for the number of first contact opening segments per unit length of 100 µm could be, for example, at least 10, 15, or 20. Possible upper limits could be, for example, a maximum of 100, 80, 60, or 50 first contact opening segments per 100 µm unit length. Regardless of a specific number, the "dashed pattern" can be irregular, i.e., with varying lengths of the contact opening segments and / or varying spacing between them. Alternatively, it can be regular, with the contact opening segments all having the same length and spaced equally apart.

[0015] In one embodiment, the conductor extends along a side edge of the chip, with the dashed pattern provided along at least 25% of the total length of the conductor along that side edge. As seen in a vertical top view, the conductor may extend parallel to the side edge, and the total length may be taken up to this parallel extent, for example, neglecting a curved section at a corner. In other words, the total length may be taken, for example, as long as the conductor extends as a straight line. Regardless of these details, in this embodiment, the dashed pattern may extend over a section (≥ 25%) of the total length or over the entire total length (100%).

[0016] In one embodiment, the conductor track has a curved shape at a corner of the semiconductor chip, i.e., at a transition between two adjacent edges of the chip. The dashed pattern can be provided along at least one segment of the curved shape, e.g., over a section of the curved shape or over the entire curved shape. Due to the curved shape at the corner, the area between the conductor track and the edges of the chip can be larger, and thus, for example, the respective area of ​​a mask in a lift-off process can also be larger. In this respect, the undercutting discussed above, i.e., potential solvent attack in the lift-off process, can be advantageous.

[0017] In one embodiment, the conductor track is a runner or belongs to a runner, wherein a second contact opening is formed beneath the runner. The second contact opening is arranged with a lateral offset to the first contact opening in a transverse direction, i.e., perpendicular to a longitudinal extent of the runner. The contact openings beneath the runner may, for example, be arranged parallel to each other, with their respective centerlines, for example, having a constant distance between them, as seen in a vertical top view. As discussed above, the runner may, for example, be a gate runner or a source runner, i.e., connected to a gate terminal, e.g., a gate electrode, or to a source region of a device structure formed in the active region.

[0018] In general, the segmentation of the (first) contact opening into a plurality of (first) contact opening sections refers to the longitudinal direction of the runner. Conversely, the segmentation referenced by the various contact openings (first, second, and so on) refers to the transverse direction, which is perpendicular to the longitudinal direction.

[0019] In other words, a contact area beneath the runner, having a certain width in the transverse direction, is subdivided into a plurality of adjacent contact openings (and separated from each other by a respective section of the insulating layer). As discussed above for the segmentation of the first contact opening along the longitudinal direction, segmentation in the transverse direction can improve the formation of an undercut (and a lift-off process), for example, compared to a contact opening that extends uninterrupted across the entire width of the runner. Despite the segmentation into a plurality of contact openings, the conductor track of the runner can be electrically connected across the different contact opening sections to the same entity in the semiconductor body, such as a doped region (source region) or a polysilicon structure (gate electrode).

[0020] In one embodiment, the first contact opening, which is provided with the segmented first contact area, e.g., the dashed pattern, is either the innermost or outermost contact opening under the runner. The innermost contact opening can be located closer to the active area than the other contact openings under the runner, whereas the outermost contact opening can be located closer to the side edges than the other contact openings of the runner. A region without metallization can be arranged laterally inside and / or outside the runner, so that a mask used in a lift-off process can have a comparatively large area there (and the segmentation is advantageous, see above).

[0021] In one embodiment, the second contact opening forms a second contact area with the semiconductor body, which is also segmented. In other words, a second contact opening beneath the conductor track is subdivided into a plurality of second contact opening sections along the longitudinal extent of the conductor track, as discussed above for the first contact opening. All embodiments described above for the first contact opening and first contact area are also to be disclosed with respect to the second contact opening / second contact area. For example, the second contact opening can also form a dashed pattern. The first and second contact openings can, for example, be the innermost and outermost contact openings of the runner with respect to the transverse direction.In general, a further contact opening, which may be arranged laterally between the first and second contact openings with respect to the transverse direction, may also be provided with a dashed pattern. For example, all contact openings arranged under the conductor track may be provided with a dashed pattern along its longitudinal extent.

[0022] In one embodiment, at least one additional contact opening is formed beneath the runner, positioned laterally between the first and second contact openings in the transverse direction. This additional contact opening connects the conductor track to the semiconductor body via a corresponding underlying contact area. The additional contact area beneath the runner can be continuous along the longitudinal direction of the runner, i.e., uninterrupted / unsegmented. In other words, the additional contact area / opening beneath the runner can extend as a continuous line, as seen in a vertical top view.In combination with the first and / or second contact opening, which forms a segmented contact area in the longitudinal direction, one or more additional contact openings with a respective continuous contact area along the longitudinal direction can, for example, enable an optimization of both the lift-off and the electrical contact properties.

[0023] In one embodiment, the width of each contact opening, e.g., a first, second, or additional contact opening, and / or the distance between adjacent contact openings under the runner is at least 0.5 µm and / or at most 3 µm. The width and distance are measured in the transverse direction.

[0024] As discussed above, a component, such as a transistor, can be formed in the active region. In detail, such a component can comprise a multitude of component cells arranged sequentially within the active region, spaced a certain distance apart. These component cells can, for example, be electrically connected in parallel and / or arranged with translational symmetry relative to one another (each offset by the cell spacing).

[0025] Regardless of these details, the transverse distance between adjacent contact openings under the runner in one embodiment may differ from the cell spacing in the active area by no more than + / - 80%. In other words, the distance between adjacent contact openings may be at most 80% smaller or larger than the cell spacing. Further upper limits may be, for example, 60%, 50%, 40%, 30%, or 20%; the distance may also be equal to the cell spacing. Adapting the dimensions of the runner to those in the active area may, for example, reduce differences in the lift-off behavior.

[0026] In one embodiment, a plurality of component contact openings are formed in the insulating layer in the active region, each component contact opening belonging to a respective component cell. Each component contact opening can form an electrical contact with an element of the respective component cell, e.g., a source and / or body region. The component contact openings in the active region can have their longitudinal extent in a first lateral direction, with the component cells exhibiting their translational symmetry with respect to a second lateral direction perpendicular thereto.

[0027] In one embodiment, the width of a given contact opening in the runner differs by no more than + / - 80% from a component contact opening width in the active area, with the contact opening width being measured in the transverse direction / perpendicular to the longitudinal extent. In other words, a contact opening width in the runner is at most 80% smaller or larger than a contact opening width in the active area, with further upper limits of 60%, 50%, 40%, 30%, or 20% (the width in the runner can also be equal to the width in the active area).

[0028] In one embodiment, a method for manufacturing a semiconductor chip comprises: i) Forming an insulating layer over a first side of a semiconductor body; ii) Forming a mask on the insulating layer, wherein the mask defines an opening which - is located outside an active area of ​​the semiconductor chip; and - is divided into a plurality of opening sections along a longitudinal extension; iii) Etching the opening defined by the mask into the insulating layer; iv) Deposition of at least one partial layer of a metallization on the mask and into the opening etched into the insulating layer; v) Removing the mask from the insulating layer.

[0029] The mask in step ii) can be formed, for example, by depositing and structuring a photoresist layer; the mask can, for example, be an organic layer. For example, the mask can define further openings in the active region (as well as outside the active region). The mask that defines the openings in the insulating layer is opened in step iii), i.e., where the contact with the semiconductor body is formed.

[0030] After the opening for contact formation is etched into the insulating layer in step iii), at least one partial layer of the metallization is deposited in step iv) while the mask is still in place. In other words, the at least one partial layer of the metallization can contact the semiconductor body where the insulating layer is opened, and it can cover the mask laterally. When the mask is removed in step v), the portion of the partial layer that contacts the semiconductor body at the openings remains, whereas the portion of the partial layer that covers the side is removed along with the mask.

[0031] The at least one partial layer of the metallization can, for example, be a sputter-deposited metal layer, e.g., a metal layer comprising nickel and / or aluminum. In a subsequent processing step, the partial layer can serve as a nucleation layer, e.g., for bath deposition of a further layer or layer stack, e.g., copper layer(s). Regardless of these details, the at least one partial layer deposited in step iv) can, for example, have a thickness of at least 30 nm, e.g., at least 40 nm, and / or at most 90 nm, e.g., at most 70 nm.

[0032] In one embodiment, step iii) comprises an isotropic etching step and a subsequent anisotropic etching step. The anisotropic etching step can form the contact opening, with the preceding isotropic etching step potentially creating an undercut beneath the mask, as discussed above. Both the anisotropic and the isotropic etching steps can be performed, for example, by dry etching.

[0033] In one embodiment, step v) comprises applying a solvent to the mask and the at least one partial layer. This solvent, which dissolves or detaches the mask, can better attack the mask where the undercut is formed, since the at least one partial layer can be broken up there. Because the segmented contact area / segmented opening can improve the formation of the undercut, it can also improve this lift-off process.

[0034] As mentioned above, every feature discussed with regard to the chip should also be disclosed with regard to the manufacturing process, and vice versa. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The semiconductor chip and the manufacturing process are explained in more detail below using exemplary embodiments. The individual features may also be relevant in other combinations. Fig. 1 shows a cross-sectional view of a conductor track on a semiconductor body; Fig. Two contact openings under a runner at a corner of a semiconductor chip illustrated in a vertical top view; Fig. 3 shows a vertical cross-section through a runner; Fig. 4a-f illustrate different steps for forming a contact opening and a partial layer of metallization in the contact opening; Fig. 5. A component that can be formed in an active area of ​​the chip, illustrated in a vertical cross-section; Fig. 6 summarizes some manufacturing steps in a flowchart. DETAILED DESCRIPTION

[0036] Fig. Figure 1 shows a vertical cross-section of a section of a semiconductor chip 100 and illustrates a semiconductor body 10, which in the example shown is a silicon carbide (SiC) semiconductor body 11. On a first side 10.1 of the semiconductor body 10, an insulating layer 20 is arranged, which can be, for example, a silicon oxide layer or a layer stack, e.g., comprising a PSG or a BPSG layer. A metallization 30 is formed on the insulating layer 20, the cross-section of Fig. Figure 1 shows a conductor track 31 formed in the metallization 30. The section plane lies parallel to a longitudinal direction 111 and to a vertical direction 113. In other words, the section view runs from Fig. 1 along a longitudinal extent 110 of the conductor track 31 (see BB in Fig. 2).

[0037] The conductor track 31 is electrically connected to the semiconductor body 10 by means of a first contact opening 21 etched into the insulating layer 20. Within this opening, as shown in Fig. As illustrated in Figure 1, the first contact opening 21 is not continuous along the longitudinal extent 110, but is divided into a plurality of first contact opening sections 21.1-21.3. Consequently, a first contact area 41, through which the conductor track 31 is electrically connected to the semiconductor body 10, is provided with first interruptions 51, i.e., a respective first interruption 51.1, 51.2 between adjacent first contact opening sections 21.1-21.3. Conversely, the first contact area 41 is segmented into first contact area sections 41.1-41.3.

[0038] Along the longitudinal extent 110, i.e., in the longitudinal direction 111, each first contact opening section 21.1-21.3 can have a length l1 of 0.5 µm-50 µm, e.g., approximately 3 µm in the example shown. Each interruption 51.1, 51.2 of the contact area 41 can have a length l2 of 0.5 µm-50 µm, e.g., approximately 3 µm in the example shown.

[0039] Fig. Figure 2 shows a section of the semiconductor chip 100 in a vertical top view, i.e., as seen in the vertical direction 113. The section shown is located at a corner 106 of the chip 100, where two of the side edges 105, 107 of the chip 100 are adjacent to each other. As indicated below left, the conductor track forms a runner 70. Below the runner 70, a second contact opening 22 and at least one additional contact opening 23 are formed, as shown in detail below.

[0040] The first and second contact openings 21, 22 are illustrated as hatched lines, representing a break / segmentation in the longitudinal direction. The breaks, i.e., contact opening sections (see Fig. 1), form a dashed pattern 60. For example, 5-100 contact opening sections can be provided over a conductor track length l3 of 100 µm (“unit of length”), i.e., in the example shown, about 8 contact opening sections.

[0041] Referring to a total length l4 that the conductor track 31 has along the side edge 105, the dashed pattern 60 can extend over at least 25% of the total length l4, i.e., in the example shown, over the entire total length l4. At corner 106, the conductor track 31 has a curved shape 120, with the dashed pattern 60 also provided over the curved shape 120 (which also applies to the second contact opening 22).

[0042] Fig. Figure 2 also illustrates an active area 101 of the chip 100. A semiconductor transistor device 200 is formed in the active area 101, comprising a plurality of device cells 201-203, see Figure 2. Fig. 5 for further details. Each component cell 201-203 includes a component contact opening 210, wherein these component contact openings 210 in the example shown each have a width comparable to a width of a respective contact opening 21-23 of the runner 70.

[0043] Fig. Figure 3 illustrates the width w in a vertical cross-section through the runner 70, see the section plane AA, as in Fig. 2 referenced. In general, in this disclosure, the same reference numerals denote identical elements or elements with the same function, and reference is also made to the description of the other figures. With respect to the transverse direction 112, the runner 70 is provided as a single conductor track, although separate contact areas 41-43 are formed one below the other and arranged at a distance d from each other, which is comparable to a distance between the component contact openings in the active area.

[0044] As discussed above, the second contact area 42 is also segmented, i.e., like the first contact area 41. At least one additional contact opening 23, i.e., two additional contact openings 23 in the example shown (where other numbers are also possible, as in Fig. (2 shown), is arranged between the first and second contact openings 21, 22. The contact areas 43 extend continuously there, as also shown by the continuous lines in Fig. 2 indicated.

[0045] Fig. 3 also illustrates how Fig. 1, a highly doped region 12 formed in the semiconductor body 10, which can improve the electrical contact to the semiconductor body 10. As in Fig. As illustrated in Figure 3, the highly doped area 12 extends continuously between the contact openings 21-23, which also applies to its extension in the longitudinal direction 111 under the first and second contact openings 21, 22 (see Figure 3). Fig. 1 for illustration).

[0046] Fig. Figures 4a-f illustrate some manufacturing steps for forming a contact opening and subsequent metallization or metallization partial layer deposition. Fig. 4a The highly doped region 12 was formed in the semiconductor body 10, and the insulating layer 20 was deposited on the semiconductor body 10. Furthermore, a mask 250 was formed on the insulating layer 20. The mask 250 was structured, i.e., it defines an opening 251 for a subsequent etching step.

[0047] Fig. Figure 4b illustrates an isotropic etching step 302.1 in which an undercut 25 is etched into the insulating layer 20. In a subsequent anisotropic etching step 302.2, as shown in Figure 4b, the undercut 25 is etched into the insulating layer 20. Fig. As illustrated in Figure 4c, the entire contact opening 21 is etched through the insulating layer 20.

[0048] Fig. Figure 4d illustrates a subsequent deposition 303 of a sublayer 230, which is the bottom layer of the metallization. In the opening 21, the sublayer 230 forms the contact area 41 to the semiconductor body 10. It is deposited laterally on the mask 250 to be removed together with the mask 250 in a lift-off process. The undercut 25, as shown in Fig. Figure 4d illustrates supporting a local fracture of sublayer 230, which allows for improved attack of a solvent on the resist of mask 250.

[0049] Fig. Figure 4e illustrates a situation after removal of the mask, with the partial layer 230 remaining at the bottom of the contact opening 21. The entire metallization 30 is formed in subsequent steps, see Figure 4e. Fig. 4f for illustration.

[0050] Fig. Section 5 summarizes some of the manufacturing steps in a flowchart. After forming the insulating layer 300, the mask can be formed on the insulating layer 301. Then the opening can be etched into the insulating layer 302, i.e., in an isotropic and a subsequent anisotropic etching step 302.1, 302.2 (see above). Then the partial layer can be deposited 303 before the mask is removed 304, e.g., by applying 305 a solvent.

[0051] Fig.Figure 6 shows a semiconductor transistor device 200 with a component cell 201. A source region 221 is arranged on the first side 10.1 of the semiconductor body 10, with a drain region 222 formed on the vertically opposite second side 10.2 of the semiconductor body 10. The device 200 also includes a body region 223, with a gate region 225 arranged laterally next to it in a gate groove 226. The gate region comprises a gate electrode 225.1 and a gate dielectric 225.2, through which the gate electrode 225.1 capacitively couples to the body region 223. A vertical current flow through the device 200 can be controlled by applying a voltage to the gate electrode 225.1.

[0052] The component 200 shown additionally includes a drift region 224, which is made of the same doping type but with a lower doping concentration compared to the drain region 222. In the example shown, the source region 221, the drain region 222, and the drift region 224 are n-doped, while the body region 223 is p-doped.

Claims

[1] Semiconductor chip (100), comprising: a semiconductor body (10); an insulating layer (20) over a first side (10.1) of the semiconductor body (10); a metallization (30) over the insulating layer (20); wherein a conductor track (31) is formed in the metallization (30) and is arranged outside an active area (101) of the semiconductor chip (100), wherein a first contact opening (21) is formed in the insulating layer (20) under the conductor track (31), wherein the conductor track (31) is electrically connected to the semiconductor body (10) in a first contact area (41) in the contact opening (21), wherein the first contact opening (21) is subdivided along a longitudinal extent (110) of the conductor track (31) into a plurality of first contact opening sections (21.1-21.3), wherein the first contact area (41) is provided with a respective first interruption (51, 51.1, 51.2) between adjacent first contact opening sections (21.1-21.3). [2] Semiconductor chip (100) according to claim 1, wherein each first contact opening section (21.1-21.3) along the longitudinal extent (110) of the conductor track (31) has a length (l1) of at least 0.5 µm and / or at most 50 µm. [3] Semiconductor chip (100) according to claim 1 or 2, wherein a respective first interruption (51, 51.1, 51.2) of the first contact area (41) along the longitudinal extent (110) of the conductor track (31) has a length (l2) of at least 0.5 µm and / or at most 50 µm. [4] Semiconductor chip (100) according to one of the preceding claims, wherein the first contact opening sections (21.1-21.3) form a dashed pattern (60) along at least one section of the conductor track (31), wherein at least 5 first contact opening sections (21.1-21.3) with a respective first interruption (51, 51.1, 51.2) of the contact area (41) between adjacent first contact opening sections (21.1-21.3) along a conductor track length (13) of 100 µm are provided in the dashed pattern (60). [5] Semiconductor chip (100) according to claim 4, wherein the conductor track (31) extends along a side edge (105) of the semiconductor chip (100), wherein, with reference to a total length (l4) that the conductor track (31) has along the side edge (105), the dashed pattern (60) is provided along at least 25% of the total length (l4). [6] Semiconductor chip (100) according to claim 4 or 5, wherein the conductor track (31) has a curved shape (120) in a corner (106) of the semiconductor chip (100), wherein the dashed pattern (60) is provided along at least one segment of the curved shape (120). [7] Semiconductor chip (100) according to one of the preceding claims, wherein the conductor track (31) is a runner (70) or belongs to a runner (70) extending along the active area (101), wherein a second contact opening (22) is formed in the insulating layer (20) under the runner (70), wherein the second contact opening (22) is offset laterally to the first contact opening (21) in a transverse direction (112) perpendicular to the longitudinal extent (110) of the runner (70). [8] Semiconductor chip (100) according to claim 7, wherein the first contact opening (21) is a laterally innermost or outermost contact opening of the runner (70). [9] Semiconductor chip (100) according to claim 7 or 8, wherein the runner (70) is electrically connected to the semiconductor body (10) via a second contact area (42) in the second contact opening (22), wherein the second contact opening (22) is divided into a plurality of second contact opening sections along a longitudinal extension (110) of the conductor track (31), wherein the second contact area (42) is provided with a respective second interruption between adjacent second contact opening sections. [10] Semiconductor chip (100) according to claim 8 or 9, wherein a third contact opening (23) is formed in the insulating layer (20) under the runner, wherein the third contact opening (23) is arranged laterally between the first contact opening (21) and the second contact opening (22), wherein the runner (70) is electrically connected to the semiconductor body (10) via a third contact area (43) in the third contact opening (23), wherein the third contact area (43) extends continuously along a longitudinal extent (110) of the runner (70). [11] Semiconductor chip (100) according to one of claims 7 to 10, wherein a width (w) of a respective contact opening (21, 22, 23) and / or a distance (d) between adjacent contact openings (21, 22, 23) under the runner (70), each measured in the transverse direction (112), is at least 0.5 µm and / or at most 3 µm. [12] Semiconductor chip (100) according to one of claims 7 to 11, wherein a plurality of component cells (201-203) with a cell spacing in the active area (101) are arranged successively, wherein a distance (d) between adjacent contact openings (21, 22, 23) under the runner (70) differs by no more than + / - 80 % from the cell spacing in the active area (101). [13] Semiconductor chip (100) according to claim 12, wherein a plurality of component contact openings (210) are formed in the insulating layer (20) in the active area (101), wherein each component contact opening (210) belongs to a respective component cell (201-203), wherein a width (w) of a respective contact opening (21, 22, 23) under the runner (70) differs by no more than + / -80 % from a component contact opening width in the active area (101). [14] Method for manufacturing a semiconductor chip (100), comprising: i) Forming (300) an insulating layer (20) over a first side (10.1) of a semiconductor body (10); ii) Forming (301) a mask (200) on the insulating layer (20), wherein the mask defines an opening (201) which - is located outside an active area (101) of the semiconductor chip; and - is divided into a plurality of opening sections along a longitudinal extension (110); iii) Etching (302) of the opening (201) defined by the mask (200) into the insulating layer (20); iv) Deposition (303) of at least one partial layer (230) of a metallization (30) on the mask and into the opening (201) etched into the insulating layer (20); v) Removal (304) of the mask (230) from the insulating layer (20). [15] Method according to claim 14, wherein step iii) comprises: - an isotropic etching step (302.1); and - a subsequent anisotropic etching step (302.2). [16] Method according to claim 14 or 15, wherein step v) comprises: - Applying (305) a solvent to the mask (200) and at least one partial layer (230). [17] Method according to any one of claims 14 to 16 for producing the semiconductor chip (100) according to any one of claims 1 to 13, wherein the opening etched in step iii) (201) the first contact opening (21) is, wherein the at least one sublayer (230) deposited in step iv) forms the first contact surface (41) to the semiconductor body (10).

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