Driver circuit and method for driving an electrical load

Abstract

Driver circuit for a current regulator (13) which can be coupled in series to an electrical load (14), containing a control circuit (12) for controlling the current regulator (13), which control circuit is designed to determine at least two setpoint current values ​​(SW1) of the current regulator current (IS1) of the current regulator (13) at at least two points in time in an operating phase as a function of a signal (VS1, STR) which can be tapped off at the current regulator (13), wherein the control circuit (12) is designed to determine a setting coefficient (K) as a function of the signal (VS1, STR) which can be tapped off at the current regulator (13) and to determine the setpoint current values ​​(SW1) in each case by multiplying or dividing the setting coefficient (K) and a predetermined setpoint current value (ISET).

Description

[0001] The present patent application relates to a driver circuit, a lighting arrangement and a method for driving an electrical load.

[0002] An electrical load, such as a light-emitting diode (LED), is often operated with a driver circuit that includes a control circuit and a current regulator. The current regulator is arranged in series with the electrical load and is adjusted by the control circuit.

[0003] Document US 2011 / 0062872 A1 describes a driver circuit for multiple electrical loads arranged in parallel, each with at least one LED. A calibration procedure determines the current values ​​of the current regulators. The current values ​​are kept constant during operation of the electrical loads.

[0004] Document DE 10040154 A1 deals with a neon sign in which a voltage source feeds several LEDs via a constant current source. A comparator compares the voltage across the constant current source with a setpoint.

[0005] Document US 2007 / 0080911 A1 describes a control circuit for LEDs. A DC / DC converter circuit has an output coupled to a reference potential terminal via three series circuits. Each series circuit comprises several LEDs, a transistor, and resistors. Voltages are tapped at the resistors and fed to the inputs of amplifiers, which are connected on their output side to the control terminals of the transistors. For example, one of the amplifiers controls the transistor of the first series circuit. One input of the amplifier is connected to a resistor that measures the current flowing through the first series circuit. Another input of the amplifier is connected to resistors that measure the current flowing through the second series circuit. Thus, a feedback circuit is capable of comparing the current in one series circuit with the current in another series circuit.

[0006] Document US 2011 / 0068700 A1 relates to a device for controlling multiple LEDs. A driver supply has an output coupled to a reference potential terminal via two series circuits. Each series circuit consists of several LEDs, a transistor, and a resistor. An output of a flip-flop is directly connected to a control terminal of the transistor.

[0007] Document US 2011 / 0204798 A1 illustrates a system for controlling LEDs. A power supply has an output connected to a reference potential terminal via three series circuits. Each series circuit consists of several LEDs and a current source controlled by a digital-to-analog converter (DAC). Voltages tapped from the series circuits between the LEDs and the current sources are fed to a control logic. An output of the control logic is coupled to the three current sources via the three DACs. The DACs convert the digital values ​​provided by the control logic into analog reference voltage signals, which are applied to the current sources.

[0008] Document DE 10 2008 030 365 A1 deals with a device for controlling individual light sources arranged in an array. The device comprises a current control means, a current source, a current mirroring means, and a transistor, which together form a current regulator, and a light-emitting diode. The current mirroring means performs a current range extension for the current source. A control circuit comprises a comparator, to which a voltage at the light-emitting diode is supplied, a diagnostic bus, and a controller unit. The comparator is coupled to the controller unit via the diagnostic bus. The controller unit is coupled to the current control means.

[0009] The object of the present patent application is to provide a driver circuit, a lighting arrangement and a method for driving an electrical load which have a high efficiency.

[0010] The problem is solved by the subject matter according to patent claims 1 and 15 and by the method according to patent claim 16. Further developments and refinements are the subject matter of the dependent claims.

[0011] In one embodiment, a driver circuit for a current regulator, which can be coupled in particular in series to an electrical load, contains a control circuit for controlling the current regulator. The control circuit is designed to determine at least two target current values ​​of the current regulator current of the current regulator at at least two points in time during an operating phase as a function of a signal that can be tapped from the current regulator.

[0012] In one embodiment, the at least two target current values ​​are determined such that a supply voltage assigned to the current regulator is reduced.

[0013] It is advantageous to determine the setpoint current values ​​of the current controller at at least two points in time during operation of the current controller. This allows the current controller to be controlled during operation. Different setpoint current values ​​of the current controller can be determined at the at least two points in time. The setpoint current value of the current controller is changed in such a way that it results in a decreasing supply voltage.

[0014] In one embodiment, the supply voltage drops across the electrical load and the current regulator. The supply voltage can be applied across a series circuit comprising the electrical load and the current regulator.

[0015] In one embodiment, the supply voltage is approximately the same at the at least two points in time. The control circuit is designed to perform a gradual optimization in the form of a reduction in the supply voltage over a longer period of operation. Therefore, the supply voltage preferably does not change abruptly. The control circuit has the effect that the supply voltage is lower at the later of the at least two points in time than at the earlier of the at least two points in time. The at least two points in time can be in a time period of the operating phase that follows a switch-on phase. During this time period, a voltage converter generating the supply voltage operates in a nearly steady-state state. During the switch-on phase, the supply voltage starts at 0 V.

[0016] In one embodiment, the supply voltage is approximately constant during the period of the operating phase in which the at least two points in time occur. Even with a nearly constant supply voltage, the characteristics of the electrical load can change due to temperature drift or an aging effect in the electrical load such that the supply voltage can be reduced by changing the target current value. However, the at least two points in time can also be in a period of the operating phase during which the supply voltage increases or decreases. An increase can be caused, for example, by external influences such as a change in temperature.

[0017] In one embodiment, the control circuit is designed to continuously determine the target current value of the current regulator during the operating phase. The determination takes place at at least two points in time and in the period between the at least two points in time.

[0018] In a preferred embodiment, the control circuit is designed to operate the current regulator with pulse width modulation. The operating phase comprises at least two clock cycles. A first of the at least two points in time is in a first clock cycle, and a second of the at least two points in time is in a second clock cycle of the operating phase. The at least two points in time do not lie in the same clock cycle. The target current value of the current regulator is determined in both the first and the second clock cycle. A clock cycle has a switch-on phase and a switch-off phase. The clock cycle has a period. The period can be a predetermined constant duration. The signal tapped at the current regulator is preferably tapped in the switch-on phase of the current regulator. Typically, no current regulator current flows in the switch-off phase.Preferably, the control circuit sets the target current value determined in one clock cycle on the current regulator in the following clock cycle. For example, the target current value is determined and set in at least ten clock cycles. Advantageously, the target current value of the current regulator is determined and set quasi-continuously. This allows for particularly high efficiency of the overall system.

[0019] In one embodiment, the control circuit is designed to set a constant duty cycle at which the current regulator is operated. The duty cycle can, for example, have the value 100%.

[0020] In an alternative embodiment, the control circuit is designed to determine the duty cycle at which the current regulator is operated based on the signal available at the current regulator. To keep the electrical power consumed by the electrical load constant, for example, the target current value can be reduced and the duty cycle increased accordingly.

[0021] In one embodiment, the signal available at the current regulator is a current regulator voltage, which can be tapped at a load terminal between the current regulator and the electrical load. The current regulator voltage can, for example, be dropped across the current regulator. The current regulator is connected to the electrical load via the load terminal. The current regulator voltage can be tapped between a supply voltage terminal of the current regulator and the load terminal.

[0022] Alternatively, the signal tapped at the current regulator can be a control signal of a transistor in the current regulator. The current flowing through the current regulator flows through the transistor. The transistor is designed to control the current flowing through the current regulator.

[0023] In one embodiment, the control circuit is configured to determine a setting coefficient depending on the signal available at the current regulator. Furthermore, the control circuit is configured to determine the target current value by multiplying or dividing a predetermined target current value and the setting coefficient. Thus, the deviation between the target current value and the predetermined target current value is known at any time. This information about the relative deviation can be useful, for example, for determining a duty cycle of a pulse-width modulation with which the current regulator is operated.

[0024] In a further development, the control circuit is designed to determine the duty cycle at which the current regulator is operated by dividing or multiplying a predetermined duty cycle and the setting coefficient. If the target current value results from multiplying the setting coefficient and the predetermined target current value, the duty cycle results from dividing the predetermined duty cycle by the predetermined setting coefficient. Alternatively, if the target current value is determined by dividing the predetermined target current value by the setting coefficient, the duty cycle results from multiplying the setting coefficient and the predetermined duty cycle. This ensures that the product of the target current value and the duty cycle is equal to the product of the predetermined target current value and the predetermined duty cycle.This ensures that the average load current remains constant and the brightness of the LEDs of the electrical load remains approximately constant.

[0025] In one embodiment, the control circuit comprises a window comparator. The window comparator receives the signal available at the current regulator on the input side. The window comparator has two outputs. The window comparator can determine whether the signal available at the current regulator is below a specified signal range, within the specified signal range, or above the specified signal range.

[0026] In one embodiment, the control circuit comprises an up / down counter. The up / down counter provides the adjustment coefficient on the output side. The up / down counter is coupled to the window comparator on the input side. The adjustment coefficient remains constant when the signal tapped at the current regulator is within the specified signal range. The adjustment coefficient is increased if the signal tapped at the current regulator is above the specified signal range and decreased if the signal tapped at the current regulator is below the specified signal range.

[0027] Alternatively, the setting coefficient is reduced if the signal available at the current controller is above the specified signal range and increased if the signal available at the current controller is below the specified signal range.

[0028] In one embodiment, the control circuit comprises a first functional unit coupled to the up / down counter at a first input. The adjustment coefficient is supplied to the first input of the first functional unit. The predetermined target current value, i.e., a signal representing the predetermined target current value, is supplied to a second input of the first functional unit. The target current value, i.e., a signal representing the target current value of the current regulator, can be tapped off at the output side of the first functional unit. The first functional unit can be implemented as a multiplier or divider.

[0029] In a further development, the control circuit comprises a second functional unit which is coupled to the up / down counter at a first input. The setting coefficient is fed to the first input of the second functional unit. The predetermined duty cycle, i.e. a signal representing the predetermined duty cycle, is fed to a second input of the second functional unit. The duty cycle, i.e. a signal representing the duty cycle of the current regulator, can be tapped off at the output side of the second functional unit. The current regulator is operated in accordance with the duty cycle which can be tapped off at the output side of the second functional unit. The second functional unit is provided for performing the mathematical operation which represents the inverse operation of the operation performed by the first functional unit.If the first functional unit is implemented as a multiplier, the second functional unit is designed as a divider. However, if the first functional unit is implemented as a divider, the second functional unit is designed as a multiplier.

[0030] In a further development, the control circuit comprises a signal generator whose input is coupled to the second functional unit and whose output provides a clock signal that has the duty cycle. The signal generator is designed as a pulse-width modulator.

[0031] In one embodiment, the driver circuit comprises a low-pass filter, the output of which is coupled to the second input of the second functional unit. The low-pass filter converts a digital signal representing the specified duty cycle into a digital value.

[0032] In one embodiment, the control circuit is designed to control at least one further current regulator. The further current regulator can be coupled in series to the at least one further electrical load. The control circuit is designed to determine the target current value of the at least one further current regulator as a function of a signal that can be tapped from the at least one further current regulator. The determination of at least two target current values ​​can be carried out at at least two points in time during the operating phase. Preferably, the determination is carried out at the at least two points in time during the operating phase. The control unit can thus advantageously control several current regulators and thus increase the efficiency of the entire arrangement.

[0033] In one embodiment, the control circuit is designed to adjust the duty cycles and the target current values ​​of the current regulator and of the at least one further current regulator such that a load voltage across the load and at least one further load voltage across the at least one further load have approximately the same value. If the load voltages match, the current regulator voltages dropped across the current regulator and the at least one further current regulator are also the same. The supply voltage is the sum of the load voltage and the current regulator voltage, as well as the sum of the at least one further load voltage and the at least one further current regulator voltage. The control circuit serves to dynamically balance the various electrical loads.

[0034] In one embodiment, the control voltage is designed to adjust the duty cycles and the target current values ​​of the current regulator and the at least one further current regulator such that the product of the duty cycle and the target current value corresponds to a preset value for the respective current regulator. The preset value for the product of the current regulator can be the same as the preset value for the product of the at least one further current regulator. Alternatively, the preset values ​​for the current regulator and for the at least one further current regulator can be different. Thus, it is possible to achieve different power dissipated in the various electrical loads and, for example, different brightness of LEDs in the various electrical loads.

[0035] In one embodiment, the control voltage is designed to adjust the duty cycles and the target current values ​​of the current regulator and of the at least one further current regulator such that at least one of the target current values ​​deviates from a predetermined target current value.

[0036] In one embodiment, the control voltage is designed to adjust the duty cycles and the target current values ​​of the current regulator and of the at least one further current regulator such that at least one of the duty cycles deviates from a predetermined duty cycle.

[0037] In a further embodiment, the control voltage is designed such that at least one of the duty cycles is 100%.

[0038] In one embodiment, the driver circuit comprises the current regulator. The current regulator can be implemented as a current source or current sink. The current regulator is connected to a control output of the control circuit via a control input. The driver circuit can have at least one further current regulator. A control input of the at least one further current regulator is connected to at least one further control output of the control circuit.

[0039] In a further development, the driver circuit includes the voltage converter.

[0040] In one embodiment, a lighting arrangement comprises the voltage converter. The driver circuit is coupled on the output side to a feedback input of the voltage converter.

[0041] The voltage converter can be implemented as a DC-DC converter. The voltage converter can be implemented as a step-down, step-up, or step-up / step-down converter. The supply voltage can be tapped off at a voltage converter output of the voltage converter. A series circuit comprising the current regulator and the electrical load couples the voltage converter output to a reference potential terminal. At least one further series circuit comprising the at least one further electrical load and the at least one further current regulator also couples the voltage converter output to the reference potential terminal.

[0042] In one embodiment, a semiconductor body comprises the driver circuit. The driver circuit is integrated on a first main surface of the semiconductor body. The driver circuit is implemented on a semiconductor body, for example, on exactly one semiconductor body.

[0043] In one embodiment, a lighting arrangement comprises the driver circuit and the electrical load. The electrical load comprises at least one light-emitting diode.

[0044] In one embodiment, the lighting arrangement is integrated as a backlight in a mobile communications device or a tablet computer. The lighting arrangement can be used with large screens.

[0045] In one embodiment, a method for driving an electrical load comprises tapping a signal from a current regulator arranged in series with the electrical load. At least two target current values ​​of the current regulator current of the current regulator are determined at at least two points in time during an operating phase as a function of the signal tapped from the current regulator in such a way that a supply voltage drop across the electrical load and the current regulator is reduced. The target current values ​​are set on the current regulator.

[0046] Advantageously, the setpoint current value is variable and can be adjusted depending on the signal. This allows the load voltage drop across the electrical load and / or the current regulator voltage drop across the current regulator to be reduced and efficiency to be increased.

[0047] In one embodiment, at least two values ​​of a setting coefficient are determined as a function of at least two values ​​of the signal that can be tapped at the current regulator, and the at least two target current values ​​are determined by multiplying or dividing a predetermined target current value and the at least two values ​​of the setting coefficient.

[0048] The invention is explained in more detail below using several exemplary embodiments with reference to the figures. Components or functional units with the same function or effect bear the same reference numerals. Where components or functional units are functionally equivalent, their description will not be repeated in each of the following figures. They show: Fig. 1A to 1D exemplary embodiments of a lighting arrangement with a driver circuit according to the proposed principle and Fig. 2 an exemplary embodiment of a control circuit and a current regulator according to the proposed principle.

[0049] Fig. 1A shows an exemplary embodiment of a lighting arrangement 10 according to the proposed principle. The lighting arrangement 10 comprises a driver circuit 11. The driver circuit 11 comprises a control circuit 12 and a current regulator 13, which is connected to the input side of the control circuit 12. The lighting arrangement 10 further has an electrical load 14 arranged in series with the current regulator 13. In addition, the lighting arrangement 10 comprises a voltage converter 15. A series circuit comprising the current regulator 13 and the electrical load 14 is arranged between a voltage converter output 16 and a reference potential terminal 17. The current regulator 13 is connected to the reference potential terminal 17, and the electrical load 14 is connected to the voltage converter output 16. The electrical load 14 comprises first, second, and third light-emitting diodes 18, 19, 20, which are arranged in series with one another.A feedback output of the driver circuit 11 is coupled to a feedback input 22 of the voltage converter 15.

[0050] The current regulator 13 comprises a switch 23 and a current source 24, which are arranged in series with one another. A first control output 25 of the control circuit 12 is connected to a control terminal of the current source 24. Correspondingly, a second control output 26 of the control circuit 12 is connected to a control terminal of the switch 23. A load terminal 27 is arranged between the electrical load 14 and the current regulator 13. The load terminal 27 is connected to a control input 28 of the control circuit 12. The driver circuit 11 also has a comparator 29. A reference voltage source 30 is connected to a first input of the comparator 29. A second input of the comparator 29 is coupled to the load terminal 27. Furthermore, the driver circuit 11 comprises a selection block 31, the input side of which is coupled to the load terminal 27. On the output side, the selection block 31 is connected to the second input of the comparator 29.An output of comparator 29 is connected to the feedback output.

[0051] The voltage converter 15 is implemented as a boost converter. The voltage converter 15 has a first and a second voltage converter switch 32, 33 and an inductor 34. An input of the voltage converter 15 is connected to the reference potential terminal 17 via the inductor 34 and the first voltage converter switch 32. A node between the inductor 34 and the first voltage converter switch 32 is coupled to the voltage converter output 16 via the second voltage converter switch 33. An output capacitor 35 connects the voltage converter output 16 to the reference potential terminal 17. An input capacitor 60 couples the input of the voltage converter 15 to the reference potential terminal 17.

[0052] In addition, the driver circuit 11 comprises a further current regulator 36, which is coupled on the input side to the control circuit 12. Furthermore, the lighting arrangement 10 comprises a further electrical load 37, which is arranged in series with the further current regulator 36. A series circuit comprising the further electrical load 37 and the further current regulator 36 couples the voltage converter output 16 to the reference potential connection 17. The further electrical load 37 is connected to the voltage converter output 16 and the further current regulator 36 is connected to the reference potential connection 17. The further electrical load 37 comprises further light-emitting diodes 38, 39, 40. The further current regulator 36 comprises a further switch 41 and a further current source 42, which are arranged in series with one another. A further first control output 25' of the control circuit 12 is connected to a control input of the further current source 42.Accordingly, a further second control output 26' of control circuit 12 is connected to a control input of further switch 41. A further load terminal 45 is arranged between the further electrical load 37 and the further current regulator 36. The further load terminal 45 is connected to a further input of the selection block 31. The selection block 31 is designed as a minimum detector. The further load terminal 45 is connected to a further control input 28' of control circuit 12.

[0053] The driver circuit 11 further comprises an additional current regulator 47, which is coupled on the input side to the control circuit 12. Furthermore, the lighting arrangement 10 comprises an additional electrical load 48, which is arranged in series with the additional current regulator 47. A series circuit comprising the additional electrical load 48 and the additional current regulator 47 couples the voltage converter output 16 to the reference potential terminal 17. The additional electrical load 48 comprises additional light-emitting diodes 49, 50, 51. The additional current regulator 47 comprises an additional switch 52 and an additional current source 53, which are arranged in series with one another. An additional first control output 25'' of the control circuit 12 is connected to a control input of the additional current source 53. Accordingly, an additional second control output 26'' is connected to a control input of the additional switch 52.

[0054] An additional load terminal 56 is arranged between the additional electrical load 48 and the additional current regulator 47. The additional load terminal 56 is connected to an additional input of the selection block 31. Furthermore, the additional load terminal 56 is connected to an additional control input 28" of the control circuit 12.

[0055] An input voltage VIN is fed to the input of voltage converter 15. The input voltage VIN drops across the input capacitor 60. The voltage converter 15 converts the input voltage VIN into a supply voltage VDC, which can be tapped at the voltage converter output 16. The supply voltage VDC drops between the voltage converter output 16 and the reference potential terminal 17. The supply voltage VDC thus drops across the series circuit comprising the current regulator 13 and the electrical load 14. The supply voltage VDC also drops across another series circuit comprising the further current regulator 36 and the further electrical load 37. Furthermore, the supply voltage VDC drops across the additional electrical load 48 and the additional current regulator 47.The voltage converter 15 provides a voltage converter current IDC at its voltage converter output 16, which is divided into partial currents that flow through the electrical loads 14, 37, 48.

[0056] A current regulator current IS1 flows through the electrical load 14 and the current regulator 13. The current regulator 13 sets the current regulator current IS1. Accordingly, the additional current regulator 36 sets an additional current regulator current IS2. The additional current regulator current IS2 flows through the additional electrical load 37 and the additional current regulator 36. Furthermore, the additional current regulator 47 sets an additional current regulator current IS3. The additional current regulator current IS3 flows through the additional electrical load 48 and the additional current regulator 47. Thus, the value of a voltage converter current IDC provided by the voltage converter 15 is: IDC=∑i=1NISi=IS1+IS2+IS3

[0057] A current regulator voltage VS1 is applied across current regulator 13. A further current regulator voltage VS2 is applied across current regulator 36, and an additional current regulator voltage VS3 is applied across additional current regulator 47. A load voltage VL1 is applied across electrical load 14. A further load voltage VL2 is applied across additional electrical load 37, and an additional load voltage VL3 is applied across additional electrical load 48. The following equation applies to the supply voltage VDC: VDC=VL1+VS1=VL2+VS2=VL3+VS3

[0058] The current regulator voltage VS1, the further current regulator voltage VS2, and the additional current regulator voltage VS3 are fed to the inputs of selection block 31. Selection block 31 selects the voltage at its input that has the smallest value. On the output side, selection block 31 provides the smallest voltage that is fed to it at one of its inputs. The selected signal VMIN, which can be tapped at the output of selection block 31, is fed to the second input of comparator 29. Reference voltage source 30 provides a target voltage value VMS, which is fed to the first input of comparator 29. The target voltage value VMS corresponds to the minimum voltage value required for operation by one of the three current regulators 13, 36, 47. A feedback signal SFB is provided at the output of comparator 29 and is fed to the feedback input 22 of voltage converter 15 via the feedback output of driver circuit 11.In accordance with the feedback signal SFB, a control circuit (not shown) of the voltage converter 15 controls the voltage converter 15. The comparator 29 is implemented as a comparator. Alternatively, the comparator 29 is designed as an operational amplifier, transconductance amplifier, or differential amplifier. A transconductance amplifier is usually used. If the selected signal VMIN is less than the target voltage value VMS, the voltage converter 15 is adjusted to increase the supply voltage VDC. However, if the target voltage value VMS is less than the selected signal VMIN, the voltage converter 15 is controlled to reduce the supply voltage VDC.

[0059] The current regulator voltage VS1 is supplied to the control input 28. The further current regulator voltage VS2 and the additional current regulator voltage VS3 are supplied correspondingly to the further and additional control inputs 28', 28''. The control circuit 12 has a processor. The processor can be implemented as a microprocessor or microcontroller or as an analog / digital circuit. A first setting signal ISET, which represents a predetermined target current value, is supplied to a first setting input 58 of the control circuit 12. Accordingly, a second setting signal PWM, which represents a predetermined duty cycle, is supplied to a second setting input 59 of the control circuit 12.

[0060] The control circuit 12 provides a target current value SW1 at the first control output 25, which is fed to the control input of the current source 24. Accordingly, the control circuit 12 outputs a clock signal ST1 via the second control output 26, which is fed to the control input of the switch 23. The control circuit 12 provides a further target current value SW2 at the further first control output 25', which is fed to the control input of the further current source 42. Furthermore, the control circuit 12 outputs a further clock signal ST2 via the further second control output 26', which is fed to the control input of the further switch 41.Similarly, the control circuit 12 generates an additional set current value SW3 for supply to the control input of the additional current source 53 via the additional first control output 25'' and an additional clock signal ST3 for supply to the control input of the additional switch 52 via the additional second control output 26''.

[0061] The control circuit 12 determines the target current value SW1 as a function of the current regulator voltage VS1 and the specified target current value ISET. In addition, the target current value SW1 can depend on the specified duty cycle PWM. Furthermore, the target current value SW1 can depend on the current regulator voltages VS2, VS3 of the additional current regulators 36, 47, i.e., the additional current regulator voltage VS2 and the additional current regulator voltage VS3. The same applies to the additional and additional target current values ​​SW2, SW3. The control circuit 12 sets the target current value SW1, the additional target current value SW2, and the additional target current value SW3 such that the current regulator voltages, i.e., the current regulator voltage VS1, the additional current regulator voltage VS2, and the additional current regulator voltage VS3, match.Furthermore, the control circuit 12 sets a duty cycle TV1 of the clock signal ST1, a further duty cycle TV2 of the further clock signal ST2, and an additional duty cycle TV3 of the additional clock signal ST3 such that the product of the setpoint current value and the duty cycle of the respective current controller is equal to the product of the specified setpoint current value ISET and the specified duty cycle PWM. Thus, the following applies: ISET⋅PWM=SW1⋅TV1=SW2⋅TV2=SW3⋅TV3

[0062] The control circuit 12 is designed for dynamic adjustment of the setpoint current value SW1 and the duty cycle TV1. The setpoint current value SW1, the additional setpoint current value SW2, the additional setpoint current value, as well as the duty cycle TV1, the additional duty cycle TV2, and the additional duty cycle TV3 are set such that the load voltage, the additional load voltage VL2, and the additional load voltage VL3 assume the same value.

[0063] The various loads 14, 37, and 47 may be unbalanced and require different forward voltages to achieve the same load current. If the target current values ​​SW1, SW2, and SW3 were set to the same value, the load voltage VL1, VL2, and VL3 would be highest for one of the electrical loads 14, 37, and 48. According to the Fig. 1A, the load voltage VL1 would be greater than the additional load voltage VL3, which in turn would be greater than the additional load voltage VL2. In order to achieve the lowest possible value for the supply voltage VDC, the duty cycle TV1 of the current regulator 13 is increased and the setpoint current value SW1 of the current regulator 13 is reduced. By reducing the setpoint current value SW1, the load voltage VL1 dropped across the electrical load 14 decreases. The value of the output voltage VDC can therefore also be reduced. In contrast, for the additional electrical load 37, a lower value for the additional load voltage VL2 is sufficient to achieve the load current value just mentioned. In order to operate the additional electrical load 37 with the same load voltage VL2 as the electrical load 14, the additional duty cycle TV2 is reduced and the additional setpoint current value SW2 is increased.

[0064] By feeding back the current regulator voltages VS1, VS2, VS3 via the selection block 31 and the comparator 29, the current regulator voltages VS1, VS2, VS3 assume the setpoint voltage VMS. The driver circuit 11 is configured to set all current regulator voltages VS1, VS2, VS3 to the minimum value, namely the setpoint voltage VMS. Thus, no excess voltage is dissipated in the respective current regulator when there is no electrical load. The average load current AVC is constant. The average current AVC can be calculated using the following equation: AVC=SW1⋅TV1=SW2⋅TV2=SW3⋅TV3

[0065] According to the Fig. In the example shown in Figure 1A, the setpoint voltage value VMS is 0.5 V, the specified PWM duty cycle is 50%, and the specified current value ISET is 20 mA. This results in an average current value AVC of 10 mA for all three loads 14, 37, and 47. The setpoint current value SW1 is below the specified ISET, while the further setpoint current value SW2 is above the specified ISET. Conversely, the TV1 duty cycle is above the specified PWM duty cycle, and the further TV2 duty cycle is below the specified PWM duty cycle. Since in the example according to Fig. 1A, the electrical load 14 has the highest forward voltage, the control circuit 12 automatically reduces the target current value SW1, allowing the supply voltage VDC to be lowered. The same brightness can be achieved with lower power consumption using the LEDs 18, 19, and 20.

[0066] In an alternative embodiment not shown, the lighting assembly 10 comprises more than three electrical loads and more than three current regulators. Alternatively, the lighting assembly may comprise only two electrical loads 14, 37 and two current regulators 13, 36. The additional electrical load 48 and the additional current regulator 47 may be omitted in this embodiment.

[0067] In an alternative embodiment not shown, the current regulators 13, 36, 47 are connected to the voltage converter output 16 and the electrical loads 14, 37, 48 are connected to the reference potential terminal 17.

[0068] In an alternative embodiment not shown, the voltage converter 15 is implemented as a buck or boost-to-buck converter. Alternatively, the voltage converter 15 can be implemented as a charge pump.

[0069] In a further embodiment not shown, more or fewer than the three LEDs shown as an example are used per load.

[0070] Fig. 1B shows a further exemplary embodiment of the lighting arrangement according to the proposed principle, which is a further development of the Fig. 1A. The control circuit 12 has Fig. 1B alternative process steps compared with the control circuit 12 of Fig. 1A. The control circuit 12 is designed to set at least one duty cycle to 100%. If the set current values ​​SW1, SW2, SW3 of all current regulators 13, 36, 47 were set to the same value, one of the three load voltages VL1, VL2, VL3 would be the highest. The duty cycle of the current regulator associated with this electrical load is set to 100%. In the example according to Fig. 1B, these are the electrical load 14 and the current regulator 13. The set current value SW1 of the current regulator 13, which is set to a duty cycle TV1 of 100% by the control circuit 12, is calculated according to the following equation: SW1=ISET⋅PWM

[0071] Due to the characteristics of the electrical load, in this case the electrical load 14, the setpoint current value SW1 determined in this way results in a value of 9.5 V for the load voltage VL1, for example. The current regulator voltages VS1, VS2, VS3 have the setpoint voltage value VMS of, for example, 0.5 V for all three current regulators 13, 36, 47. Since the three current regulator voltages VS1, VS2, VS3 have the same value, the load voltages VL1, VL2, VL3 also have the same value, in this example 9.5 V. This results in a value of 10 V for the supply voltage VDC. Due to the characteristics of the additional electrical load 37, the additional setpoint current value SW2 results from the additional load voltage VL2, in this example 15 mA.Based on the load voltage VL2 across the additional electrical load 47, in this example 9.5 V, and the current-voltage characteristics of the additional electrical load 47, the control circuit 12 sets the additional target current value SW3. In this example, the additional target current value SW3 is 12.5 mA. The further duty cycle TV2 and the additional duty cycle TV3 are calculated by the control circuit 12 according to the following equations: . TV2=ISET⋅PWMSW2=SW1SW2 TV3=ISET⋅PWMSW3=SW1SW3

[0072] According to Fig. 1B, the duty cycle of one of the electrical loads 14, 37, 48 is thus increased to 100%, so that one of the electrical loads 14, 37, 48 is constantly switched on. Since the peak current through the electrical load 14 is now reduced, with the average current value AVC remaining identical due to the increase in the corresponding duty cycle TV1, the load voltage VL1 in this branch is further reduced. For example, a current supplied to the voltage converter 15 in an arrangement 10 according to Fig. 1B 5% lower than a current that is in the arrangement in Fig. 1A is fed to the voltage converter 15.

[0073] In an alternative embodiment not shown, control circuit 12 sets more than one duty cycle to 100%. Control circuit 12 can also set all duty cycles TV1, TV2, and TV3 to 100%. In this case, the target current values ​​SW1, SW2, and SW3 are identical and can be calculated according to the following equation: SW1=SW2=SW3=ISET⋅PWM

[0074] This results in different values ​​for the current regulator voltages VS1, VS2, and VS3. The value of the supply voltage VDC increases slightly. Advantageously, however, such a control circuit 12 can be implemented with very little effort. Because the duty cycles TV1, TV2, and TV3 are higher than the specified PWM duty cycle, efficiency is improved.

[0075] In an alternative embodiment not shown, the lighting arrangement 10 comprises only an electrical load 14 and a current regulator 13. The further and additional electrical loads 37, 48 and the further and additional current regulators 36, 47 can be omitted in this embodiment. The duty cycle TV1 and the target current value SW1 are set as follows: TV1=100% and SW1=ISET⋅PWM

[0076] Fig. 1C shows a further exemplary embodiment of a lighting arrangement according to the proposed principle, which is a further development of the Fig. 1A and Fig. 1B. The control circuit 12 is designed to carry out a method which is a further development of the embodiments shown in Fig. 1A and Fig. 1B. The control circuit 12 is designed to set the setpoint current values ​​SW1, SW2, SW3 to the predetermined setpoint current value ISET in a first operating phase. The current regulator voltages VS1, VS2, VS3 are supplied to the control circuit 12. The lowest value of the current regulator voltages VS1, VS2, VS3 occurs at one of the three current regulators 13, 36, 47. In the Fig. In the example shown in Figure 1C, this is current regulator 13. In the current regulator 13, in a second operating phase, control circuit 12 sets the setpoint current value SW1 to the specified setpoint current value ISET and the duty cycle TV1 to the specified duty cycle PWM. The specified duty cycle PWM is 100%.

[0077] The control circuit 12 is designed to reduce the target current value SW2 of the additional current regulator 36 in the second operating phase such that the additional current regulator voltage VS2 of the additional current regulator 36 corresponds to the current regulator voltage VS1 of the current regulator 13. By controlling the voltage converter 15, the current regulator voltage VS1 is set to the target voltage value VMS in the second operating phase. Therefore, the additional current regulator voltage VS2 also assumes the target voltage value VMS. Accordingly, the control circuit 12 determines the additional target current value SW3, at which the additional current regulator voltage VS3 becomes equal to the other current regulator voltages VS1, VS2 and thus identical to the target voltage value VMS. The control circuit 12 is designed to determine the additional and additional duty cycles TV2, TV3 based on the thus determined additional target current value SW2 and the additional target current value SW3 according to the following equation: TV2=ISET⋅PWMSW2=ISET⋅100%SW2 TV3=ISET⋅PWMSW3=ISET⋅100%SW3

[0078] Consequently, the control circuit 12 sets at least one of the duty cycles, in this case the further and additional duty cycles TV2, TV3, lower than the predefined duty cycle PWM. Furthermore, the control circuit 12 sets at least one of the target current values, in this case the further and additional target current values ​​SW2, SW3, higher than the predefined target current value ISET. If, for example, the characteristics of the electrical loads 14, 37, 48 change due to temperature influences, the control circuit 12 changes at least one of the target current values ​​SW1, SW2, SW3.

[0079] The specified average current value PWM * ISET can be achieved for all three electrical loads 14, 37, and 48, whereby both the set current values ​​SW1, SW2, and SW3 as well as the duty cycles TV1, TV2, and TV3 are adjusted to reduce the supply voltage VDC. This advantageously reduces the power consumed by the current regulators 13, 36, and 47. Often, a temperature limit exists, and the current regulators are integrated on a semiconductor device or implemented using external power transistors. The lower power consumption can reduce heat dissipation requirements, allowing for a smaller package size.

[0080] Fig. 1D shows a further exemplary embodiment of a lighting arrangement according to the proposed principle, which is a further development of the Fig. 1A to 1C. The control circuit 12 has a control block 69 with an up / down counter 70, which is coupled on the input side to the load terminal 27. Furthermore, a window comparator 71 of the control block 69 couples the load terminal 27 to the up / down counter 70. The window comparator 71 has a first and a second comparator 72, 73, the outputs of which are each connected to an input of the up / down counter 70. A first input of the first comparator 72 is connected to the voltage tap node 27. A second input of the first comparator 72 is connected to a first reference voltage source 74. A first input of the second comparator 73 is connected to a second reference voltage source 75. A second input of the second comparator 73 is coupled to the load terminal 27.

[0081] The control block 69 comprises a first functional unit 76, which is connected at a first input to an output of the up / down counter 70. A second input of the first functional unit 76 is coupled to the first set input 58. An output of the first functional unit 76 is connected to the control input of the current source 24 via the first control output 25. The first functional unit 76 is implemented as a divider.

[0082] In addition, the control block 69 has a second functional unit 77, which is connected at a first input to the output of the up / down counter 70. A second input of the second functional unit 77 is coupled to the second set input 59. A low-pass filter 79, 79', 79'' is arranged between the second set input 59 and the second input of the second functional unit 77. The low-pass filter 79, 79', 79'' is n-order and is designed in the drawing as a series circuit of three individual stages 79, 79', 79'' of the filter. The low-pass filter 79 has two buffers 80, 81, a summing element 82, and a delay element 83. An output of the second functional unit 77 is connected to the control terminal of the switch 23 via the second control output 26. A signal generator 78 of the control block 69 is arranged between the output of the second functional unit 77 and the second control output 26.The second functional unit 77 is implemented as a multiplier.

[0083] The first and second functional units 76, 77 are implemented as digital circuits. The first and second functional units 76, 77 are implemented as combinational logic. Furthermore, the control block 69 includes a limiting unit 84. The limiting unit 84 is arranged between the output of the second functional unit 77 and another input of the up / down counter 70. Furthermore, the limiting unit 84 is connected on the input side to the output of the first functional unit 76.

[0084] In addition, the control circuit 12 comprises a further control block 85, which is implemented like the control block 69. The further control block 85 is connected on the input side to the further load connection 45 and on the output side to the control connections of the further current source 42 and the further switch 41. Furthermore, the control circuit 12 comprises an additional control block 86, which is connected on the input side to the additional load connection 56 and on the output side to the control inputs of the additional switch 52 and the additional current source 53. Furthermore, the control circuit 12 comprises a coordination circuit 87, which is connected on the input side to the control block 69, the further control block 85, and the additional control block 86, and on the output side to the up / down counter 70 of the three control blocks 69, 85, 86.

[0085] The first reference voltage source 74 provides an upper reference voltage VU. The second reference voltage source 75 provides a lower reference voltage VD. The range between the upper and lower reference voltages VU, VD is a predetermined signal range. The window comparator 71 thus compares the current regulator voltage VS1 with the upper reference voltage VU and the lower reference voltage VD. The result of the comparison of the current regulator voltage VS1 with the upper reference voltage VU can be tapped at the output of the first comparator 72. Accordingly, the result of the comparison of the current regulator voltage VS1 with the lower reference voltage VD is provided at the output of the second comparator 73. An adjustment coefficient K can be tapped at the output of the up / down counter 70. If the current regulator voltage VS1 is greater than the upper reference voltage VU, the up / down counter 70 counts up and the adjustment coefficient K is increased.If, however, the power source voltage VS1 is lower than the lower reference voltage VD, the up / down counter 70 counts downwards and the adjustment coefficient K is decreased. However, if the power source voltage VS1 is lower than the upper reference voltage value VU and higher than the lower reference voltage value VD, the up / down counter 70 does not change the adjustment coefficient K, and the latter remains constant. For example, the up / down counter 70 is designed to count in increments of 0.1 within the range of 0.5 to 2.0 and output the adjustment coefficient K from the range of 0.5 to 2.0 in increments of 0.1.

[0086] The target current value SW1 is determined by dividing the specified target current value ISET by the setting coefficient K. The signal generator 48 provides the clock signal ST1 with the duty cycle TV1, for which the setting coefficient K is multiplied by the specified value of the duty cycle PWM. One clock cycle of the clock signal ST1 has an on-phase in which the clock signal ST1 has the value 1, and an off-phase in which the clock signal ST1 has the value 0. The duty cycle TV1 is the duration of the on-phase divided by the period of one clock cycle. The target current value SW1 and the duty cycle TV1 are thus determined according to the following equations: SW1=ISETK and TV1=PWM⋅K

[0087] Since the first and second functional units 76, 77 perform inverse mathematical operations to each other, the resulting average current value AVC is constant. If the current regulator voltage VS1 is too high, the up / down counter 70 counts upwards, thus increasing the duty cycle TV1 and decreasing the target current value SW1. The limiting block 84 limits the up / down counter 70 such that the duty cycle TV1 does not exceed 100%. Furthermore, the block 84 can be designed to set minimum or maximum values ​​for the target current value SW1. This ensures that the target current value SW1 does not fall below a minimum target current value and does not exceed a maximum target current value. The specified target current value SW1 and the specified duty cycle PWM are implemented as digital values.

[0088] The coordination circuit 87 is configured to coordinate the control blocks 69, 85, 86. The coordination circuit 87 therefore implements the Fig. 1A to 1C, for example, the coordination circuit 87 causes the current regulator 13, 36, 47 to be set to the duty cycle 100% and how the other current regulators follow the current regulator thus set.

[0089] The up / down counter 70 controls the timing. The timing of the up / down counter 70 is synchronized with the timing of the signal generator 78. The signal generator 78 is implemented as a pulse width modulation generator. The up / down counter 70 is designed as a state machine. The up / down counter 70 exclusively makes decisions and, for example, determines a new value of the setting coefficient K when a current regulator current IS1, IS2, IS3 flows through the respective electrical load 14, 37, 48. The up / down counter 70 outputs the setting coefficient K, for example, from a set of values ​​such as 0.5 / 0.6 / 0.7 / ... / 2.0.

[0090] During an initialization phase, the setting coefficient K is set to the value 1. Thus, the up / down counter 70 outputs the setting coefficient K with the value 1. During the initialization phase, the voltage converter 15 starts and performs a control of the voltage converter 15. The control loop of the voltage converter 15 is implemented by means of the selection block 31 and the comparator 29.

[0091] In an operational phase, the following steps are repeated: - Wait until the clock signal ST1 returns the value 1 according to the switch-on phase. - In a comparison phase, the current regulator voltage VS1 is compared with the upper and lower reference voltages VU, VD before the clock signal ST1 returns to the value 0 of the off-phase. Likewise, the additional current regulator voltage VS2 and the additional current regulator voltage VS3 are compared with the upper and lower reference voltages VU, VD. A time shortly before the end of the on-phase is ideal, as the signals have settled by then. - It waits until the clock signals ST1, ST2, ST3 indicate the value 0 of the switch-off phase or, in the case of duty cycles TV1, TV2, TV3 with the value 100%, until the end of the clock cycle is reached. - If the first comparator 72 was triggered during the comparison phase, i.e., if the current regulator voltage VS1 is greater than the upper reference voltage VU during the comparison phase, the adjustment coefficient K is increased. In an alternative embodiment, the adjustment coefficient K is only increased when the first comparator 72 was triggered in a first number M of consecutive clock cycles. The first number M is greater than 1 and can be, for example, 20. - If the second comparator 73 was triggered in the comparison phase, i.e., if the current regulator voltage VS1 is less than the lower reference voltage VD in the comparison phase, the adjustment coefficient K is reduced. In the alternative embodiment, the adjustment coefficient K is only reduced when the second comparator 73 is triggered in the first number M of consecutive clock cycles. - In every nth clock cycle, an output signal provided by the coordination circuit 87 is checked. If the output signal is at the logical value 1, the adjustment coefficient K is increased. - As long as the limiting unit 84 determines that the duty cycle TV1 exceeds a predetermined maximum value for the duty cycle, the adjustment coefficient K is reduced. - As long as the limiting unit 84 determines that the duty cycle TV1 is below a predetermined minimum value for the duty cycle, the adjustment coefficient K is increased.

[0092] The steps listed above are repeated. These steps are performed not only by control block 69, but also by the additional control block 85 and the additional control block 86.

[0093] The coordination circuit 87 monitors all channels—that is, the control block 69, the further control block 85, and the additional control block 86—in parallel and is designed to maximize the duty cycle TV1, TV2, TV3 of all three control blocks 69, 85, 86. The goal is to achieve a duty cycle TV1, TV2, TV3 of 100% for at least one control block 69, 85, 86. The coordination circuit 87 is designed to operate the control blocks 69, 85, 86 such that the up / down counter 70 in the various control blocks 69, 85, 86 sets the respective adjustment coefficient K to the value 1 if none of the duty cycles TV1, TV2, TV3 of the three control blocks 69, 85, 86 reaches the predetermined maximum value of the duty cycle. The specified maximum value of the duty cycle is 100%.

[0094] Thus, the window comparator 71 must detect the exceedance of the upper reference voltage VU or the undershoot of the lower reference voltage VD for the first number M of consecutive clock cycles before the up / down counter 70 changes the adjustment coefficient K. The new value of the adjustment coefficient K is used to adjust the clock signal ST1 and the target current value SW1 in the next subsequent clock cycle.

[0095] After setting the new target current value SW1 and the new clock signal ST1, the current regulator voltage VS1 is further monitored. If the window comparator 71 determines again during a first number M of consecutive clock cycles that the current regulator voltage VS1 is greater than the upper reference voltage VU or, alternatively, less than the lower reference voltage VD in all of these clock cycles, a new target current value SW1 and a new value of the duty cycle TV1 are again provided by the clock signal ST1 at a second time, namely a time after these consecutive M clock cycles. Thus, new target current values ​​SW1 and duty cycles TV1 are calculated at a plurality of times during the operation of the driver circuit 11 and used to adjust the current regulator 13.

[0096] In an alternative embodiment (not shown), the first functional unit 76 is implemented as a multiplier and the second functional unit 77 as a divider. The up / down counter 70 is coupled to the window comparator 71 such that the adjustment coefficient K is increased when the current regulator voltage VS1 is less than the lower reference voltage VD, and the adjustment coefficient K is reduced when the current regulator voltage VS1 is higher than the upper reference voltage VU.

[0097] In an alternative embodiment, the low-pass filter 79 is configured to convert the predetermined duty cycle PWM, which is present as a digital signal, into an analog signal. The resulting analog signal is then multiplied by the current regulator current IS1. The LEDs 18, 19, 20 are driven linearly, which reduces the load voltage VL1 and increases efficiency. The first and second functional units 76, 77 are implemented as analog multiplier and divider circuits, respectively.

[0098] Fig. Figure 2 shows an exemplary embodiment of a control circuit 12 and a current regulator 13 according to the proposed principle, as used in the lighting arrangements according to Fig.1A to 1D can be used. The circuit block 69 has an output switch 100, which is arranged between the first functional unit 76 and the first control output 25. The output of the second functional unit 77 is coupled to a control terminal of the output switch 100 via the signal generator 78. The second control output 26 of the control circuit 12 is thus omitted. The driver circuit 11 comprises a sample and hold circuit 104, which couples the load terminal 27 to the selection block 31 and the control input 28. The sample and hold circuit 104 comprises a sample switch 105 and a hold capacitor 106. A control terminal of the sample and hold circuit 104 is coupled to the output of the signal generator 78.

[0099] The current regulator 13 comprises a transistor 101 and a current sensor 102, which are arranged in series with one another. The load terminal 27 is thus connected to the reference potential terminal 17 via a series circuit comprising the controlled path of the transistor 101 and the current sensor 102. The transistor 23 can thus be omitted and is replaced by a connecting line. The current sensor 102 is implemented as a resistor. The current regulator 13 has an amplifier 103, the output of which is coupled to a control terminal of the transistor 101. A first input of the amplifier 103 is coupled to the first control output 25. An output of the current sensor 102 is connected to a second input of the amplifier 103. For this purpose, a node between the transistor 101 and the current sensor 102 is connected to the second input of the amplifier 103. The current regulator 24 is implemented as a regulated current regulator. The current controller 24 has an internal control loop.The control loop includes transistor 101, current sensor 102 and amplifier 103.

[0100] The clock signal ST1 controls the output switch 100. The setpoint current value SW1 provided by the first functional unit 76 is fed via the output switch 100 to the current regulator 13 and thus to the first input of the amplifier 103. Thus, the setpoint current value SW1 is present at the first input of the amplifier 103 during the on-phases of a clock cycle of the clock signal ST1. During the off-phases of the respective clock cycle, the value 0 V is present at the first input of the amplifier 103. The amplifier 103 provides a control signal STR, which controls the transistor 101. The transistor 101 controls the current regulator current IS1 as a function of the clock signal ST1 and the setpoint current value SW1. The current source current IS1 flowing through the current sensor 102 is measured by the current sensor 102. A current signal in the form of a voltage VR is dropped across the resistor of the current sensor 102 and is fed to the second input of the amplifier 103.The control signal STR is generated based on a comparison of the set current value SW1 and the sensor signal VR. Due to the feedback loop formed by transistor 101, current sensor 102, and amplifier 103, the current source current IS1 is proportional to the set current value SW1 according to the equation IS1 = SW1 * R. Where R is the resistance of the resistor of current sensor 102.

[0101] The sample-and-hold circuit 104 is also controlled by the clock signal ST1. During the on-state phases of the clock signal ST1, the current regulator voltage VS1 is sampled and is also present at the output of the sample-and-hold circuit 104 during the off-state phases of the clock signal ST1.

[0102] The further and additional current regulators 36, 47 can also be implemented like the current regulator 13. Accordingly, the further circuit block 85 and the additional circuit block 86 can each have an output switch corresponding to the output switch 100 in the circuit block 69. Furthermore, a further and an additional sample-and-hold circuit of the driver circuit 12 is provided, analogous to the sample-and-hold circuit 104.

[0103] Current regulator 13 comprises a maximum of one power transistor, namely transistor 101. The controlled current path of a maximum of one transistor, namely transistor 101, is arranged between electrical load 14 and reference potential terminal 17. Advantageously, switch 23 can be omitted, thus reducing ohmic losses.

[0104] In an alternative embodiment, selection block 31 and control input 28 of control circuit 12 are coupled to a node between amplifier 103 and the control terminal of transistor 101. The connection is shown in dashed lines. The MAX value of the inputs, i.e., the maximum voltage value of the control signals STR of current regulators 13, 36, 47, is then formed in selection block 31. The inputs are swapped for comparators 72, 73. However, the connection of selection block 31 and control input 28 to load terminal 27 is omitted. The control signal STR is thus fed to selection block 31 and control circuit 12. Selection block 31 is implemented such that it outputs the largest of the signals present on the input side. A high value of the control signal STR signals that the supply voltage VDC is too low.The comparator 29 and the voltage converter 15 are implemented such that the supply voltage VDC is increased if the control signal STR is greater than the setpoint voltage value VMS. The control signal STR is fed to the window comparator 71. If the control signal STR is above the specified signal range, the setpoint current value SW1 is reduced. If the control signal STR is below the specified signal range, the setpoint current value SW1 is increased. List of reference symbols 10 Lighting arrangement 11 Driver circuit 12 Control circuit 13 current regulators 14 electrical load 15 voltage converters 16 Voltage converter output 17 Reference potential connection 18, 19, 20 LED 22 Feedback input 23 switches 24 Power source 25, 25', 25'' first control output 26, 26', 26'' second control output 27 Load connection 28, 28', 28'' control input 29 comparators 30 Reference voltage source 31 Selection block 32, 33 Voltage converter switch 34 Inductance 35 Output capacitor 36 additional current regulators 37 additional electrical load 38, 39, 40 LED 41 additional switches 42 additional power sources 45 additional load connection 47 additional current regulator 48 additional electrical load 49, 50, 51 LED 52 additional switches 53 additional power source 56 additional load connection 58 first set entrance 59 second setting input 60 input capacitor 69 Control block 70 Up / Down Counters 71 Window comparator 72 first comparator 73 second comparator 74 first reference voltage source 75 second reference voltage source 76 first functional unit 77 second functional unit 78 Signal generator 79, 79', 79'' low-pass filter 80, 81 buffer 82 summing element 83 Delay element 84 Boundary unit 85 additional control block 86 additional control block 87 Coordination circuit 100 output switches 101 Transistor 102 Current sensor 103 amplifiers 104 Sample and hold circuit 105 scanning switches 106 Holding capacitor IDC voltage transformer current ISET specified target current value IS1 current regulator current IS2 additional current regulator current IS3 additional current regulator current K adjustment coefficient PWM specified duty cycle SFB feedback signal STR control signal ST1 clock signal ST2 additional clock signal ST3 additional clock signal SW1 set current value SW2 additional target current value SW3 additional set current value TV1 duty cycle TV2 further duty cycle TV3 additional duty cycle VD lower reference voltage VDC supply voltage VIN input voltage VL1 load voltage VL2 additional load voltage VL3 additional load voltage VMIN selected signal VMS target voltage value VR current signal VS1 current regulator voltage VS2 additional current regulator voltage VS3 additional current regulator voltage VU upper reference voltage

Claims

[1] Driver circuit for a current regulator (13) which can be coupled in series to an electrical load (14), comprising a control circuit (12) for controlling the current regulator (13), which control circuit is designed to determine at least two setpoint current values ​​(SW1) of the current regulator current (IS1) of the current regulator (13) at at least two points in time in an operating phase as a function of a signal (VS1, STR) which can be tapped off at the current regulator (13), wherein the control circuit (12) is designed to determine a setting coefficient (K) as a function of the signal (VS1, STR) which can be tapped off at the current regulator (13) and to determine the setpoint current values ​​(SW1) in each case by multiplying or dividing the setting coefficient (K) and a predetermined setpoint current value (ISET). [2] Driver circuit according to claim 1, wherein the control circuit (12) is designed to determine the at least two desired current values ​​(SW1) of the current regulator current (IS1) at the at least two points in time in the operating phase as a function of the signal (VS1, STR) that can be tapped off at the current regulator (13) in such a way that a supply voltage (VDC) assigned to the current regulator (13) is reduced. [3] Driver circuit according to claim 1 or 2, wherein the supply voltage (VDC) drops across a series circuit comprising the electrical load (14) and the current regulator (13). [4] Driver circuit according to one of claims 1 to 3, in which the control circuit (12) is designed to operate the current regulator (13) in a pulse-width modulated manner, in which the operating phase comprises at least two clock cycles and in which the at least two points in time are in different clock cycles of the operating phase, wherein a clock signal having a duty cycle comprises the clock cycles. [5] Driver circuit according to one of claims 1 to 4, in which the control circuit (12) is designed to determine a duty cycle (TV1) with which the current regulator (13) is operated as a function of the signal (VS1, STR) which can be tapped off at the current regulator (13). [6] Driver circuit according to one of claims 1 to 5, wherein the signal which can be tapped at the current regulator (13) is a signal from a group comprising: - a current regulator voltage (VS1) which can be tapped at a load terminal (27) between the current regulator (13) and the electrical load (14), and - a control signal (STR) of a transistor (101) which sets the current regulator current (IS1) and is included in the current regulator (13). [7] Driver circuit according to one of claims 1 to 6, wherein the control circuit (12) is designed to determine a duty cycle (TV1) of the current regulator (13) by dividing or multiplying the adjustment coefficient (K) and a predetermined duty cycle (PWM). [8] Driver circuit according to one of claims 1 to 7, the control circuit (12) comprising - a window comparator (71) to which the signal (VS1, STR) available at the current regulator (13) can be fed, and - an up / down counter (70) which is coupled on the input side to the window comparator (71) and from which the setting coefficient (K) can be tapped on the output side. [9] Driver circuit according to claim 8, the control circuit (12) comprising a first functional unit (76) which is implemented as a multiplier or divider, which is coupled at a first input to the up / down counter (70), to which a signal representing a predetermined set current value (ISET) can be fed at a second input and at which a signal representing the set current value (SW1) of the current regulator (13) can be tapped off on the output side. [10] Driver circuit according to claim 9, the control circuit (12) comprising a second functional unit (77) which is designed to carry out the inverse operation compared to the operation of the first functional unit (76), which is coupled at a first input to the up / down counter (70), to which a signal representing a predetermined duty cycle (PWM) can be fed at a second input and at which a signal representing a duty cycle (TV1) of the current regulator (13) can be tapped off on the output side. [11] Driver circuit according to claim 10, comprising a low-pass filter (79) which is coupled on the output side to the second input of the second functional unit (77). [12] Driver circuit according to one of claims 1 to 11, in which the control circuit (12) is arranged to control at least one further current regulator (36, 47), which can be arranged in series with at least one further electrical load (37, 48), and is designed to determine at least two desired current values ​​(SW2, SW3) of the current regulator current (IS2, IS3) of the at least one further current regulator (36, 47) at at least two times in the operating phase as a function of a signal (VS2, VS3) which can be tapped off at the at least one further current regulator (36, 47). [13] Driver circuit according to claim 12, wherein the control circuit (12) is designed to set the duty cycles (TV1, TV2, TV3) and the setpoint current values ​​(SW1, SW2, SW3) of the current regulator (13) and of the at least one further current regulator (36, 47) such that at least one of the setpoint current values ​​(SW1, SW2, SW3) deviates from a predetermined setpoint current value (ISET). [14] Driver circuit according to claim 12 or 13, wherein the control circuit (12) is designed to set the duty cycles (TV1, TV2, TV3) and the target current values ​​(SW1, SW2, SW3) of the current regulator (13) and of the at least one further current regulator (36, 47) such that at least one of the duty cycles (TV1, TV2, TV3) deviates from a predetermined duty cycle (PWM). [15] Lighting arrangement comprising the driver circuit (11) according to one of claims 1 to 14 and - the electrical load (14) and - a voltage converter (15) with a voltage converter output (16), wherein the driver circuit (11) comprises the control circuit (12) and the current regulator (13), which is connected to the control circuit (12) on the input side, and a series circuit comprises the current regulator (13) and the electrical load (14) and is arranged between the voltage converter output (16), at which a supply voltage (VDC) can be tapped, and a reference potential connection (17). [16] A method of driving an electrical load, comprising: - tapping a signal (VS1, STR) at a current regulator (13) arranged in series with the electrical load (14), - determining at least two setpoint current values ​​(SW1) of the current regulator current (IS1) of the current regulator (13) at at least two points in time in an operating phase as a function of the signal (VS1, STR) tapped at the current regulator (13) in such a way that a supply voltage (VDC) dropping across the electrical load (14) and the current regulator (13) is reduced, wherein in each case a setting coefficient (K) is determined as a function of the signal (VS1, STR) tapped at the current regulator and in each case the setpoint current value (SW1) is determined by multiplying or dividing a predetermined setpoint current value (ISET) and the setting coefficient (K), and - Setting the target current values ​​(SW1) on the current controller (13).

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