Electronic control device

Abstract

Electronic control device comprising the following: a first electronic circuit (2) comprising several transistors for controlling currents flowing through loads, and a second electronic circuit (1) comprising a pulse generation circuit (4) for generating multiple pulses which are an input to the transistors, wherein the second electronic circuit (1) transmits the pulses to the first electronic circuit (2) using serial communication (6, 11, 7), wherein the second electronic circuit (1) comprises an edge detection circuit (5) for detecting the edges of the pulses and wherein the transmission of the pulses is carried out when the edge detection circuit (5) detects at least one edge among the edges of the pulses.

Description

Technical field

[0001] The present invention relates to electronic control devices and in particular to an electronic control device suitable for use in a device comprising an IC that controls loads and an IC that generates a pulse that is used to control the loads. background

[0002] Since various control objectives are electronically controlled, electrical actuators such as an injection system, an ignition device, a motor, a solenoid, and a relay are widely used. As disclosed, for example, in JP 2004-339977A and US 2004 / 0230347A1, an electronic control device for controlling these actuators generally comprises two types of ICs: one is a drive IC that drives the actuators (loads), and the other is a control IC that generates pulses to drive the loads.

[0003] In recent years, the increasing performance of electronic control devices has made it possible for a single driver IC to control many loads. However, this presents a challenge: as the number of signals transmitted between the driver and controller ICs grows, a large number of pins for each IC is required, necessitating a large board area for mounting each IC. This increases the cost and size of the electronic control device. To address this issue, measures are being taken to reduce the number of signals transmitted between the driver and controller ICs using the Micro Second Bus (MSB), a communication protocol used for the serial transmission of multiple pulse signals between the driver and controller ICs.JP H08 - 284 729 A relates to a control device for a fuel injection pump for diesel engines, which includes a pump-side storage element containing correction data regarding manufacturing deviations or the corresponding manufacturing tolerances for the respective fuel injection pump. A control device not located on the pump side can request this correction data, which is then transmitted via a dedicated data line. Summary of the invention: Technical problem

[0004] In serial pulse transmission using the MSB, it is necessary to shorten the serial transmission cycle to improve the timing resolution of the pulse for highly accurate control. However, because the time intervals between transmitted pulses are short, and it is impossible, for example, to send commands used for fault diagnosis of IC2 or for controlling various functions during these intervals, a problem arises: the reliability of the entire electronic control device is reduced, or the functions inherent to IC2 are limited.

[0005] Additionally, as the number of pulses to be transmitted increases, more time is required to transmit the pulses serially, and mismatches occur between the pulses generated by the control IC and the timing specifications at which the control IC drives loads, causing the problem that it becomes impossible to perform highly accurate control.

[0006] A first objective of the present invention is to reduce the number of pulses in the serial transmission between the drive IC and the control IC.

[0007] A second object of the present invention is to provide a means to ensure strict timing specifications among the pulses even when the number of pulses increases during serial transmission of the pulses between the drive IC and the control IC. Solution to the problem

[0008] The problems are solved by the features of independent claim 1. Advantageous embodiments of the invention are described in the dependent claims. Advantageous effects of the invention

[0009] According to the present invention, strict timing specifications can be ensured among the pulses even when the number of pulses increases during serial transmission of the pulses between the drive IC and the control IC. Brief description of the embodiments Fig. Figure 1 is a block diagram showing the configuration of a current control device according to a first embodiment of the present invention. Fig. Figure 2 is a time schedule for the serial transmission of a 16-bit pulse from IC1 (1) to IC (2) according to the first embodiment of the present invention. Fig. Figure 3 is a block diagram showing the configuration of a current control device according to a second embodiment of the present invention. Fig. Figure 4 is a block diagram showing the detailed configuration of an encoder (31) according to the second embodiment of the present invention. Fig. 5 is the data configuration of the DATA1 output by a setting circuit (47). Fig. Figure 6 is a time schedule for the serial transmission of a 16-bit pulse from IC1 (1) to IC (2) according to the second embodiment of the present invention. Fig. Figure 7 is a block diagram showing the detailed configuration of an encoder (31) according to the third embodiment of the present invention. Fig. 8 is a coding table for the edge signals. Fig. 9 is the data configuration of the DATA1 output by a setting circuit (77). Fig. Figure 10 is a time schedule for the serial transmission of a 16-bit pulse from IC1 (1) to IC1 (2) according to the third embodiment of the present invention. Fig. Figure 11 is a block diagram showing the configuration of a current control device according to a fourth embodiment of the present invention. Fig. Figure 12 is a block diagram showing the detailed configuration of an encoder (31) according to the fourth embodiment of the present invention. Fig. 13 is the data configuration of the DATA1 output by a setting circuit (121). Description of the embodiments

[0010] The configuration and behavior of a current control device according to a first embodiment of the present invention are described below with reference to Fig. 1 and Fig. 2 will be described. First embodiment

[0011] First, the configuration of an electronic control device according to this embodiment is described with reference to Fig. 1. will be described. Fig. Figure 1 is a block diagram showing the configuration of the current control device according to a first embodiment of the present invention.

[0012] The electronic control device comprises an IC2 (2) that drives the loads and an IC1 (1) that generates pulses used to indicate the timing at which the IC2 (2) drives the loads, and the IC1 (1) and the IC2 (2) are coupled to each other via a serial communication line So (11). The electronic control device according to this embodiment drives, for example, eight injection devices 1 to 8 that inject fuel into a multi-cylinder engine installed in a vehicle, and other four loads A1 to A4 and four loads B1 to B4, but the loads that may be driven by the electronic control device are not limited to these loads, and any load may be driven by the electronic control device as long as it is driven by a pulse.

[0013] IC1 (1) mainly comprises various digital circuits such as a pulse generation circuit (4) that generates pulses; a control unit (3) that generates a pulse width and instructions about the pulse timing specifications and various commands about IC diagnostics and the like; an edge detection circuit (5) for detecting the edges of the pulses and a serial IF1 (6) that is used for communication with IC2 (2) via the serial communication line So (11).

[0014] The control unit (3) calculates the pulse width and pulse timing instructions using inputs from various sensors, such as an intake air flow sensor for detecting intake air flow into a power engine (not shown in this embodiment), based on a control algorithm such as a fuel injection quantity calculation, and sends the pulse widths and pulse timing instructions to the pulse generation circuit (4). Additionally, the control unit (3) generates various commands, such as those required for fault diagnosis of IC2 (2), configuration changes, and the like, and sends these commands to serial IF1 (6).

[0015] The pulse generation unit (4) generates, for example, a 16-bit pulse in accordance with the pulse width and the pulse timing instructions, which is sent by the control unit (3). The pulses are transmitted via a 16-bit signal line P1 (9) to the edge detection circuit (5) and the serial IF1 (6). In this embodiment, each 16-bit pulse corresponds to eight injection devices 1 to 8, four loads A1 to A4, and four loads B1 to B4, in order from the highest bit to the lowest bit.

[0016] The edge detection circuit (5) detects the rising edge or the falling edge of each bit of the 16-bit pulses sent by the pulse generation circuit (4) and sends the time specification at which the edge is detected to the serial IF1 (6) via an edge detection signal E1 (10).

[0017] Upon receiving the timing signal sent by the edge detection circuit (5), the serial IF1 (6) converts the 16-bit pulse sent by the pulse generation circuit (4) into a serial signal and transmits the serially converted pulse to the IC2 (2) via the serial communication line So (11). Additionally, the IF1 (6) sends a command that is transmitted by the control unit (3) during a period of inactivity in the serial transmission of the pulse, when the serial IF1 (6) is not receiving an edge detection signal.

[0018] IC2 (2) includes IF2 (7), which is used for communication with IC1 (1) via the serial communication line So (11), and a driver for controlling the loads.

[0019] The serial IF2 (7) converts the serial data of the 16-bit pulse sent by IC1 (1) into parallel data and sends the 16-bit pulse to the driver (8) via a signal line P2 (12). Additionally, the serial IF2 (7) receives commands sent by IC1 (1) and performs fault diagnosis of IC2 (2) and controls the various functions, although the fault diagnosis and control are not shown in the diagram in this embodiment.

[0020] The behavior of the serial transmission of a 16-bit pulse from IC1 (1) to IC2 (2) is described with reference to Fig. 2 will be described.

[0021] Fig. Figure 2 is a time schedule for the serial transmission of a 16-bit pulse from IC1 (1) to IC (2).

[0022] This timing diagram is an example of a serial transmission of a 16-bit pulse at the time when a pulse to control an injection unit 1 among the eight injection units 1 to 8, the four loads A1 to A4 and four loads B1 to B4 changes from "0" to "1".

[0023] First, in cycle 2, the pulse P1

[15] to control the injection device 1 changes from “0” to “1”. The edge detection circuit (5) detects the rising edge of P1

[15] and outputs “1” to the edge detection signal E1 (10).

[0024] Subsequently, in cycle 3, after being notified of the edge detection by the edge detection circuit (5), serial IF1 (6) begins the serial transmission of the 16-bit pulse output from the pulse generation circuit (4). Sixteen cycles are required to transmit the 16-bit pulse, so the transmission of the last bit is completed in cycle 19.

[0025] In cycle 20, the serial IF2 (7) converts the serial data of the received 16-bit pulse into parallel data and outputs “1” to the P2

[15] .

[0026] As described above, because serial transmission begins when a pulse edge is detected, serial transmission of pulses does not occur during a time interval when no pulse changes. By utilizing these free cycles, various commands used for fault diagnosis of IC2(2) and for controlling different functions can be sent, and additional pulses can be sent redundantly to improve noise resistance. Due to the steps mentioned above, the reliability and high performance of the entire electronic control device can be improved. Second embodiment

[0027] The configuration and behavior of a current control device according to a second embodiment of the present invention are described below with reference to Fig. 3 to Fig. 6 will be described.

[0028] First, the configuration of an electronic control device according to this embodiment is described with reference to Fig. 3 will be described.

[0029] Fig. Figure 3 is a block diagram showing the configuration of the current control device according to a second embodiment. The configuration of the electronic control device according to this embodiment is the same as that of the first embodiment, except for an encoder (31) and a decoder (32), so that a detailed description of these components is omitted.

[0030] The encoder (31) performs the data conversion on a 16-bit pulse sent by a pulse generation circuit (4) using a method that will later be described using the Fig. 4 and Fig. 5 will be described, and sends the received data via a signal line DATA1 (33) to the serial IF1 (6).

[0031] Upon receiving valid data from the encoder (31), the serial IF1 (6) converts the data to serial format and transmits the serially converted data via a serial communication line So (11) to the IC2 (2). Additionally, during a free period of the serial pulse transmission, the serial IF1 (6) sends various commands, which are sent from a control unit (3) to the IC2 (2).

[0032] The serial IF2 (7) converts the serial data sent by the IC1 (1) into parallel data and sends the parallel data via a DATA2 (34) to the decoder (32). Additionally, the serial IF2 (7) receives commands sent by the IC1 (1) and performs fault diagnosis of the IC2 (2) and controls the various functions, although the fault diagnosis and control are not shown in the diagram in this embodiment.

[0033] The decoder (32) restores the 16-bit pulse to the data sent by serial IF2 (7) by performing a data conversion, which is the reverse of the conversion performed by the encoder (31), and sends the restored pulse to a driver (8) via a signal line P2 (12).

[0034] Next, the detailed configuration of the encoder (31) will be described with reference to Fig. 4 will be described. Fig. Figure 4 is a block diagram showing the detailed configuration of an encoder (31).

[0035] The encoder (31) comprises: an edge detection circuit 1 (43); an edge detection circuit 2 (42); an edge detection circuit 3 (41); an OR gate 1 (46); an OR gate 2 (45); an OR gate 3 (44) and a setting circuit (47).

[0036] The edge detection circuit 1 (43) detects the rising or falling edge of each of bits No. 0 to No. 3 of the 16-bit pulse sent by the pulse generation circuit (4) and outputs the edge detection result of each bit to the corresponding bit of an edge detection signal E1[3:0]. The OR gate 1 (46) performs a logical addition of the edge detection signal E1[3:0] and outputs the result to req1. It can be seen from the above configuration that when req1 is “1”, each of bits No. 0 to No. 3 of the 16-bit pulse sent by the pulse generation circuit (4) has a rising edge or a falling edge and the transmit request of bits No. 0 to No. 3 of the 16-bit pulse is generated.

[0037] The edge detection circuit 2 (42) detects the rising or falling edge of each of bits 4 to 7 of the 16-bit pulse sent by the pulse generation circuit (4) and outputs the detection result of each bit to the corresponding bit of an edge output signal E1[7:4]. The OR gate 2 (45) performs a logical addition of the edge detection signal E1[7:4] and outputs the result to req2. It can be seen from the above configuration that when req2 is “1”, each of bits No. 4 to No. 7 of the 16-bit pulse generated by the pulse generation circuit (4) has a rising edge or a falling edge and the transfer request of bits No. 4 to No. 7 of the 16-bit pulse is generated.

[0038] The edge detection circuit 3 (41) detects the rising or falling edge of each of bits 8 to 15 of the 16-bit pulse sent by the pulse generation circuit (4) and outputs the detection result of each bit to the corresponding bit of an edge output signal E1 [15:8]. The OR gate 3 (44) performs a logical addition of the edge detection signal E1 [15:8] and outputs the result to req3. It can be seen from the above configuration that when req3 is “1”, each of bits No. 8 to No. 15 of the 16-bit pulse generated by the pulse generation circuit (4) has a rising edge or a falling edge and the transmit request of bits No. 8 to No. 15 of the 16-bit pulse is generated.

[0039] The setting circuit (47) outputs DATA1 in accordance with the transmission request of each pulse from req1, req2, and req3. When the transmission requests from req1, req2, and req3 compete with each other, the transmission requests are selected based on their priorities. For example, the priority of req3 is higher than that of req2, and the priority of req2 is higher than that of req1. Additionally, due to the competition among the transmission requests, requests that are not selected are stored in a buffer, and each request is accepted after the previously selected transmission has finished.

[0040] Fig. Figure 5 shows the data configuration of the DATA1 output by the setting circuit (47). DATA1 includes a TAG field and a DATA field, and TAG="0" and DATA=P1 [15:8] when req3 is selected, TAG="10" and DATA=P1 [7:4] when req2 is selected, and TAG="1" and DATA=P1 [3:0] when req1 is selected.

[0041] Next, with reference to Fig. 6 a behavior is described in which a 16-bit pulse is transmitted serially from IC1 (1) to IC2 (2).

[0042] Fig. Figure 6 is a time schedule for the serial transmission of a 16-bit pulse from IC1 (1) to IC (2).

[0043] This time schedule shows an example of a serial transmission of a 16-bit pulse, in which a pulse that controls an injection unit 1 among the eight injection units 1 to 8, four loads A1 to A4 and four loads B1 to B4 changes from "0" to "1".

[0044] First, in cycle 2, a pulse P1

[15] , which controls the injection device 1, changes from "0" to "1". The edge detection circuit 3 (42) detects the rising edge of P1

[15] and outputs "1" to req3 via the OR gate 3 (44), which is the transmission request for bits 8 to 15 of the 16-bit pulse. The setting circuit (47) outputs DATA1, which consists of TAG ("0"), and DATA (P1 [15:8]), as shown in Fig. 5 is explained.

[0045] Next, in cycle 3, serial IF1 (6) receives a valid data output from the setting circuit (47) and begins serial transmission of the DATA1 output through the setting circuit (47). While 16 cycles are required to transmit the 16-bit pulse according to the first embodiment, because the pulse data transmitted serially in this case consists only of bits 8 to 15, including P1

[15] , which are necessary to be transmitted from the 16-bit pulse, 9 cycles are required to transmit bits 8 to 15, and the transmission is completed in cycle 11.

[0046] Subsequently, in cycle 12, the data received via serial IF2 (7) is decoded by the encoder (31) and “1” is the output to P2

[15] .

[0047] As described above, because a combination of pulses, including the bits to be transmitted, is selected from a 16-bit pulse and transmitted serially, the delay that occurs during serial transmission of the pulses is reduced, thus ensuring strict timing of the pulses. Additionally, during periods of inactivity in the serial transmission, when there are no transmission requirements, various commands used for fault diagnosis of IC2(2) and for controlling various functions can be sent, and further pulses can be sent redundantly to improve noise resistance.Due to the steps mentioned above, in serial transmission between the driver IC and the control IC, the transmission time of the various commands can be ensured differently from the transmission time of the pulses, so that the improvement of the reliability and high performance of the entire electronic control device can be achieved. Third embodiment

[0048] The configuration and behavior of a current control device according to a third embodiment of the present invention are described below with reference to Fig. 7 to Fig. 10. Here, the configuration of the current control device according to the third embodiment is the same as that of the second embodiment except for the internal configurations of an encoder (31) and a decoder (32), so that the detailed description of the same components is omitted.

[0049] First, the detailed configuration of the encoder (31) is described with reference to Fig. 7 will be described.

[0050] Fig. Figure 7 is a block diagram showing the detailed configuration of the encoder (31).

[0051] The encoder (31) comprises: an edge detection circuit 1 (43); an edge detection circuit 2 (42); an edge detection circuit 3f (72); an edge detection circuit 3r (71); an OR gate 1 (46); an OR gate 2 (45); an OR gate 3f (74); an OR gate 3r (73); an encoder f (76); an encoder r (75) and a setting circuit (77).

[0052] The edge detection circuit 1 (43) detects the rising or falling edge of each of bits 0 to 3 of a 16-bit pulse sent by a pulse generation circuit (4) and outputs the edge detection result of each bit to the corresponding edge output signal E1[3:0]. The OR gate 1 (46) performs a logical addition of the edge detection signal E1[3:0] and outputs the result to req1. It is evident from the configuration above that when req1 is "1", one of bits 0 to 3 of the 16-bit pulse sent by the pulse generation circuit (4) has a rising or falling edge, and the transmit request for bits 0 to 3 of the 16-bit pulse is generated.

[0053] The edge detection circuit 2 (42) detects the rising or falling edge of each of bits 4 to 7 of a 16-bit pulse sent by the pulse generation circuit (4) and outputs the detection result of each bit to the corresponding edge output signal E1[7:4]. The OR gate 2 (45) performs a logical addition of the edge detection signal E1[7:4] and outputs the result to req2. It is evident from the configuration above that when req2 is "1", one of bits 4 to 7 of the 16-bit pulse sent by the pulse generation circuit (4) has a rising or falling edge, and the transmit request for bits 4 to 7 of the 16-bit pulse is generated.

[0054] The edge detection circuit 3f (72) detects the falling edge of each of bits 8 to 15 of the 16-bit pulse sent by the pulse generation circuit (4) and outputs the detection result of each bit to the corresponding edge output signal E1f [15:8]. The OR gate 3f (74) performs a logical addition of the edge detection signal E1f [15:8] and outputs the result to req3f. It can be seen from the above configuration that when req3f is "1", one of bits 8 to 15 of the 16-bit pulse sent by the pulse generation circuit (4) has a falling edge, and the transmit request for bits 8 to 15 of the 16-bit pulse is generated.

[0055] The edge detection circuit 3r (71) detects the rising edge of each of bits 8 to 15 of the 16-bit pulse sent by the pulse generation circuit (4) and outputs the detection result of each bit to the corresponding edge output signal E1r [15:8]. The OR gate 3r (73) performs a logical addition of the edge detection signal E1r [15:8] and outputs the result to req3. It can be seen from the configuration above that when req3 is "1", one of bits 8 to 15 of the 16-bit pulse sent by the pulse generation circuit (4) has a rising edge, and the transmit request for bits 8 to 15 of the 16-bit pulse is generated.

[0056] The encoder f (76) codes E1f [15:8] and outputs the result to E2f [2:0]. Here, E1f [15:8] shows the falling edges of the pulses, each corresponding to one of the injection units 1 to 8. The falling edges are generated every eighth of a time interval during rotation at specified intervals, during which the multi-cylinder engine with the eight injection units 1 to 8 rotates 360 degrees, and do not overlap. Using this feature, for example in an input / output table in Fig. As shown in Figure 8, the 8-bit Eif [15:8] is encoded so that the 8-bit Eif [15:8] can be compressed into 3-bit data. The encoder r (75) encodes E1r [15:8] and outputs the result to E2r [2:0]. Here, E1r [15:8] shows the rising edges of the pulses corresponding to each of the injection units 1 to 8. These rising edges are generated at predetermined intervals every eighth of a time period during which the multi-cylinder engine with the eight injection units 1 to 8 rotates 360 degrees, and they do not overlap. Using this feature, for example in an input / output table in Fig. As shown in Figure 8, the 8-bit Eif [15:8] is encoded so that the 8-bit Eif [15:8] can be compressed into 3-bit data.

[0057] In this embodiment, several pulses enclosed in the same group are assigned numbers; the number of a pulse that generates an edge is determined in accordance with the input / output table in Fig. 8 is encoded into a binary number and the decoded data is transmitted.

[0058] In the case of loads that behave in synchronization with a multi-cylinder engine, such as ignition devices that ignite an air-fuel mixture, the number of bits to be transmitted can be compressed in a similar way to the above by using control pulses, provided that the edges of the control pulses do not overlap.

[0059] In other words, in this embodiment, the pulses P1 [15:8], whose edges are guaranteed not to overlap by the system, are divided into one group, and P1 [3:0] and P1 [7:4], whose edges are not guaranteed not to overlap by the system, are divided into other groups. Due to the steps mentioned above, in the group to which the pulses P1 [15:8] belong, because the combination patterns of the outputs that individual pulses generate are limited, the number of bits to be transmitted can be compressed.

[0060] The setting circuit (77) outputs DATA1 in accordance with the transmission request of each pulse from req1, req2, req3f, and req3r. When the transmission requests from reql, req2, req3f, and req3r compete with each other, the transmission requests are selected based on their priorities. For example, the priority of req3r is higher than that of req3f, the priority of req3f is higher than that of req2, and the priority of req2 is higher than that of reql. Additionally, due to the competition among the transmission requests, requests that are not selected are stored in a buffer, and each request is accepted after the previously selected transmission has finished.

[0061] Fig. Figure 9 shows the data configuration of the DATA1 output by the setting circuit (77). DATA1 includes a TAG field and a DATA field and TAG="01" and DATA=E2r [2:0] if req3 is selected, TAG="00" and DATA=E2f [2:0] if req3f is selected, TAG="101" and DATA=P1 [7:4] if req2 is selected, and TAG="100" and DATA=P1 [3:0] if req1 is selected.

[0062] Next, with reference to Fig. 10 a behavior is described in which a 16-bit pulse is transmitted serially from IC1 (1) to IC2 (2).

[0063] Fig. Figure 10 is a time schedule for the serial transmission of a 16-bit pulse from IC1 (1) to IC (2).

[0064] This time schedule shows an example of a serial transmission of a 16-bit pulse, in which a pulse controlling an injection unit 1 among the eight injection units 1 to 8, four loads A1 to A4 and four loads B1 to B4 changes from "0" to "1".

[0065] First, in cycle 2, a pulse P1

[15] , which controls the injection device 1, changes from "0" to "1". The edge detection circuit 3r (71) detects the rising edge of P1

[15] and outputs "1" to req3 via the OR gate 3 (44). This req3 is the transmission request from bit #8 to bit #15 of the 16-bit pulse. At the same time, the encoder r (75) encodes E1r [15:8] and outputs the result to E2r [2:0]. The setting circuit (77) outputs DATA1, which consists of TAG ("01"), and DATA (=E2r [2:0]), as shown in Fig. 9 is explained.

[0066] Next, in cycle 3, serial IF1 (6) receives a valid data output from the setting circuit (47) and begins serial transmission of the DATA1 output through the setting circuit (47). While 9 cycles are required to transmit the pulse data according to the second execution mode, because the pulse data transmitted serially in this case is only 3-bit data, which is compressed from bits 8 to 15 including P1

[15] of the 16-bit pulse, a shorter time is required, i.e., 6 cycles, to transmit the 3-bit data, and the transmission is completed in cycle 7.

[0067] Subsequently, in cycle 8, the data received via serial IF2 (7) is decoded by the encoder (31) and “1” is the output to P2

[15] .

[0068] As described above, because a combination of pulses, including a bit to be transmitted, is selected from a 16-bit pulse and transmitted serially, a delay that occurs during the serial transmission of the pulses is reduced, which ensures that the strict timing of the pulses is guaranteed. Fourth embodiment

[0069] The configuration and behavior of a current control device according to a fourth embodiment of the present invention are described below with reference to Fig. 11 to Fig. 13. Here, the configuration of the current control device according to the fourth embodiment is the same as that of the third embodiment except for the internal configurations of an encoder (31) and a decoder (32), so that the detailed description of the same components is omitted.

[0070] First, the configuration of the electronic control device according to this embodiment is described with reference to Fig. 11. The electronic control device according to this embodiment drives eight magnetic coils 1 to 8, four loads A1 to A4 and four loads B1 to B4. Here, a 16-bit pulse according to this embodiment corresponds to eight magnetic coils 1 to 8, four loads A1 to A4 and four loads B1 to B4 in the order of the bits from the highest bit to the lowest bit.

[0071] Next, the detailed configuration of the encoder (31) will be described with reference to Fig. 12 will be described. Fig. Figure 12 is a block diagram showing the detailed configuration of the encoder (31).

[0072] The encoder (31) comprises: an edge detection circuit 1 (43); an edge detection circuit 2 (42); an edge detection circuit 3f (72); an edge detection circuit 3r (71); an OR gate 1 (46); an OR gate 2 (45); an OR gate 3f (74); an OR gate 3r (73); an encoder r (75); and a setting circuit (121). The components of the encoder (31) according to this embodiment are the same as those of the third embodiment, except for the setting circuit (121), so a detailed description of these identical components is omitted.

[0073] The encoder r(75) encodes E1r[15:8] and outputs the result to E2r[2:0]. Here, E1r[15:8] shows the rising edges of the pulses corresponding to each of the magnetic coils 1 to 8, and these rising edges are generally configured so that they do not overlap to reduce noise. Using this feature, the 8-bit E1r[15:8] can be used according to the input / output table in Fig. 8-bit data can be compressed to 3-bit data.

[0074] The setting circuit (121) outputs DATA1 in accordance with the transmission request of each pulse from req1, req2, req3f, and req3r. When the transmission requests from req1, req2, req3f, and req3r compete with each other, the transmission requests are selected based on their priorities, with req3r having a higher priority than req3f, req3f having a higher priority than req2, and req2 having a higher priority than req1. Additionally, due to the competition among the transmission requests, requests that are not selected are stored in a buffer, and each request is accepted after the previously selected transmission has finished.

[0075] Fig.Figure 13 shows the data configuration of the DATA1 output by the setting circuit (121). DATA1 includes a TAG field and a DATA field and TAG="01" and DATA=E2r [2:0] if req3r is selected, TAG="00" and DATA=P1 [15:8] if req3f is selected, TAG="101" and DATA=P1 [7:4] if req2 is selected, and TAG="100" and DATA=P1 [3:0] if req1 is selected.

[0076] The description of a behavior in which a 16-bit pulse is serially transmitted from IC1 (1) to IC2 (2) will be omitted here, because the behavior is the same as that of the third embodiment.

[0077] As described above, because a combination of pulses, including a bit to be transmitted, is selected from a 16-bit pulse and transmitted serially after the data has been compressed, any delay that occurs during the serial transmission of the pulses is reduced, thus ensuring strict timing of the pulses. List of reference symbols 1 IC1 2 IC2 3 Control unit 4 Pulse generation circuit 5 Edge detection circuit 6 Serial IF1 7 Serial IF2 8 drivers

Claims

[1] Electronic control device comprising: a first electronic circuit (2) comprising several transistors for controlling currents flowing through loads, and a second electronic circuit (1) comprising a pulse generation circuit (4) for generating multiple pulses which are an input to the transistors, wherein the second electronic circuit (1) transmits the pulses to the first electronic circuit (2) using serial communication (6, 11, 7), wherein the second electronic circuit (1) comprises an edge detection circuit (5) for detecting the edges of the pulses and wherein the transmission of the pulses is carried out when the edge detection circuit (5) detects at least one edge among the edges of the pulses. [2] Electronic control device according to claim 1, the impulses are classified into several groups and wherein a group including the pulse whose edge is detected by the edge detection circuit (5) is selected from the pulses and transmitted. [3] Electronic control device according to claim 2, wherein the classification is carried out in such a way that pulses whose edges do not occur at the same time are classified into the same group. [4] Electronic control device according to claim 3, wherein the serial transmission of the pulses is carried out in such a way that numbers are assigned to several pulses contained in the same group and the number of a pulse whose edge has occurred is encoded into a binary number and the encoded data is transmitted. [5] Electronic control device according to claim 3, wherein the loads are fuel injection devices, each installed for the cylinders in a multi-cylinder engine installed in a vehicle. [6] Electronic control device according to claim 3, wherein the loads are fuel ignition devices, each installed for the cylinders in a multi-cylinder engine installed in a vehicle. [7] Electronic control device according to claim 2, wherein the second electronic circuit (1) comprises a setting circuit (47; 77; 121) which executes the transmissions of the different groups on the basis of predefined priorities when the transmissions compete with each other. [8] Electronic control device according to claim 1, wherein when the edge detection circuit (5) does not detect an edge among the edges of the pulses, information for the diagnosis of the first electronic circuit (2), information used for purposes other than controlling the transistors, or information that makes the pulses more redundant is transmitted.

Images